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Space_Invaders/Debug/Space_Invaders.list
Leopold Clement 9c3eee1cb8 Update geneated code
2021-07-08 08:50:14 +02:00

75468 lines
2.8 MiB
Raw Blame History

Space_Invaders.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001c8 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0001be40 080001d0 080001d0 000101d0 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00005198 0801c010 0801c010 0002c010 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080211a8 080211a8 000400dc 2**0
CONTENTS
4 .ARM 00000008 080211a8 080211a8 000311a8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 080211b0 080211b0 000400dc 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080211b0 080211b0 000311b0 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 080211b4 080211b4 000311b4 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 000000dc 20000000 080211b8 00040000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000f7b8 200000dc 08021294 000400dc 2**2
ALLOC
10 ._user_heap_stack 00000604 2000f894 08021294 0004f894 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 000400dc 2**0
CONTENTS, READONLY
12 .debug_info 000541f9 00000000 00000000 0004010c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 0000a229 00000000 00000000 00094305 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00002f70 00000000 00000000 0009e530 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00002ce0 00000000 00000000 000a14a0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0003b61e 00000000 00000000 000a4180 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00046d0e 00000000 00000000 000df79e 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0012745e 00000000 00000000 001264ac 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000053 00000000 00000000 0024d90a 2**0
CONTENTS, READONLY
20 .debug_frame 0000cd78 00000000 00000000 0024d960 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001d0 <__do_global_dtors_aux>:
80001d0: b510 push {r4, lr}
80001d2: 4c05 ldr r4, [pc, #20] ; (80001e8 <__do_global_dtors_aux+0x18>)
80001d4: 7823 ldrb r3, [r4, #0]
80001d6: b933 cbnz r3, 80001e6 <__do_global_dtors_aux+0x16>
80001d8: 4b04 ldr r3, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x1c>)
80001da: b113 cbz r3, 80001e2 <__do_global_dtors_aux+0x12>
80001dc: 4804 ldr r0, [pc, #16] ; (80001f0 <__do_global_dtors_aux+0x20>)
80001de: f3af 8000 nop.w
80001e2: 2301 movs r3, #1
80001e4: 7023 strb r3, [r4, #0]
80001e6: bd10 pop {r4, pc}
80001e8: 200000dc .word 0x200000dc
80001ec: 00000000 .word 0x00000000
80001f0: 0801bff8 .word 0x0801bff8
080001f4 <frame_dummy>:
80001f4: b508 push {r3, lr}
80001f6: 4b03 ldr r3, [pc, #12] ; (8000204 <frame_dummy+0x10>)
80001f8: b11b cbz r3, 8000202 <frame_dummy+0xe>
80001fa: 4903 ldr r1, [pc, #12] ; (8000208 <frame_dummy+0x14>)
80001fc: 4803 ldr r0, [pc, #12] ; (800020c <frame_dummy+0x18>)
80001fe: f3af 8000 nop.w
8000202: bd08 pop {r3, pc}
8000204: 00000000 .word 0x00000000
8000208: 200000e0 .word 0x200000e0
800020c: 0801bff8 .word 0x0801bff8
08000210 <memchr>:
8000210: f001 01ff and.w r1, r1, #255 ; 0xff
8000214: 2a10 cmp r2, #16
8000216: db2b blt.n 8000270 <memchr+0x60>
8000218: f010 0f07 tst.w r0, #7
800021c: d008 beq.n 8000230 <memchr+0x20>
800021e: f810 3b01 ldrb.w r3, [r0], #1
8000222: 3a01 subs r2, #1
8000224: 428b cmp r3, r1
8000226: d02d beq.n 8000284 <memchr+0x74>
8000228: f010 0f07 tst.w r0, #7
800022c: b342 cbz r2, 8000280 <memchr+0x70>
800022e: d1f6 bne.n 800021e <memchr+0xe>
8000230: b4f0 push {r4, r5, r6, r7}
8000232: ea41 2101 orr.w r1, r1, r1, lsl #8
8000236: ea41 4101 orr.w r1, r1, r1, lsl #16
800023a: f022 0407 bic.w r4, r2, #7
800023e: f07f 0700 mvns.w r7, #0
8000242: 2300 movs r3, #0
8000244: e8f0 5602 ldrd r5, r6, [r0], #8
8000248: 3c08 subs r4, #8
800024a: ea85 0501 eor.w r5, r5, r1
800024e: ea86 0601 eor.w r6, r6, r1
8000252: fa85 f547 uadd8 r5, r5, r7
8000256: faa3 f587 sel r5, r3, r7
800025a: fa86 f647 uadd8 r6, r6, r7
800025e: faa5 f687 sel r6, r5, r7
8000262: b98e cbnz r6, 8000288 <memchr+0x78>
8000264: d1ee bne.n 8000244 <memchr+0x34>
8000266: bcf0 pop {r4, r5, r6, r7}
8000268: f001 01ff and.w r1, r1, #255 ; 0xff
800026c: f002 0207 and.w r2, r2, #7
8000270: b132 cbz r2, 8000280 <memchr+0x70>
8000272: f810 3b01 ldrb.w r3, [r0], #1
8000276: 3a01 subs r2, #1
8000278: ea83 0301 eor.w r3, r3, r1
800027c: b113 cbz r3, 8000284 <memchr+0x74>
800027e: d1f8 bne.n 8000272 <memchr+0x62>
8000280: 2000 movs r0, #0
8000282: 4770 bx lr
8000284: 3801 subs r0, #1
8000286: 4770 bx lr
8000288: 2d00 cmp r5, #0
800028a: bf06 itte eq
800028c: 4635 moveq r5, r6
800028e: 3803 subeq r0, #3
8000290: 3807 subne r0, #7
8000292: f015 0f01 tst.w r5, #1
8000296: d107 bne.n 80002a8 <memchr+0x98>
8000298: 3001 adds r0, #1
800029a: f415 7f80 tst.w r5, #256 ; 0x100
800029e: bf02 ittt eq
80002a0: 3001 addeq r0, #1
80002a2: f415 3fc0 tsteq.w r5, #98304 ; 0x18000
80002a6: 3001 addeq r0, #1
80002a8: bcf0 pop {r4, r5, r6, r7}
80002aa: 3801 subs r0, #1
80002ac: 4770 bx lr
80002ae: bf00 nop
080002b0 <__aeabi_uldivmod>:
80002b0: b953 cbnz r3, 80002c8 <__aeabi_uldivmod+0x18>
80002b2: b94a cbnz r2, 80002c8 <__aeabi_uldivmod+0x18>
80002b4: 2900 cmp r1, #0
80002b6: bf08 it eq
80002b8: 2800 cmpeq r0, #0
80002ba: bf1c itt ne
80002bc: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
80002c0: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
80002c4: f000 b96e b.w 80005a4 <__aeabi_idiv0>
80002c8: f1ad 0c08 sub.w ip, sp, #8
80002cc: e96d ce04 strd ip, lr, [sp, #-16]!
80002d0: f000 f806 bl 80002e0 <__udivmoddi4>
80002d4: f8dd e004 ldr.w lr, [sp, #4]
80002d8: e9dd 2302 ldrd r2, r3, [sp, #8]
80002dc: b004 add sp, #16
80002de: 4770 bx lr
080002e0 <__udivmoddi4>:
80002e0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80002e4: 9d08 ldr r5, [sp, #32]
80002e6: 4604 mov r4, r0
80002e8: 468c mov ip, r1
80002ea: 2b00 cmp r3, #0
80002ec: f040 8083 bne.w 80003f6 <__udivmoddi4+0x116>
80002f0: 428a cmp r2, r1
80002f2: 4617 mov r7, r2
80002f4: d947 bls.n 8000386 <__udivmoddi4+0xa6>
80002f6: fab2 f282 clz r2, r2
80002fa: b142 cbz r2, 800030e <__udivmoddi4+0x2e>
80002fc: f1c2 0020 rsb r0, r2, #32
8000300: fa24 f000 lsr.w r0, r4, r0
8000304: 4091 lsls r1, r2
8000306: 4097 lsls r7, r2
8000308: ea40 0c01 orr.w ip, r0, r1
800030c: 4094 lsls r4, r2
800030e: ea4f 4817 mov.w r8, r7, lsr #16
8000312: 0c23 lsrs r3, r4, #16
8000314: fbbc f6f8 udiv r6, ip, r8
8000318: fa1f fe87 uxth.w lr, r7
800031c: fb08 c116 mls r1, r8, r6, ip
8000320: ea43 4301 orr.w r3, r3, r1, lsl #16
8000324: fb06 f10e mul.w r1, r6, lr
8000328: 4299 cmp r1, r3
800032a: d909 bls.n 8000340 <__udivmoddi4+0x60>
800032c: 18fb adds r3, r7, r3
800032e: f106 30ff add.w r0, r6, #4294967295 ; 0xffffffff
8000332: f080 8119 bcs.w 8000568 <__udivmoddi4+0x288>
8000336: 4299 cmp r1, r3
8000338: f240 8116 bls.w 8000568 <__udivmoddi4+0x288>
800033c: 3e02 subs r6, #2
800033e: 443b add r3, r7
8000340: 1a5b subs r3, r3, r1
8000342: b2a4 uxth r4, r4
8000344: fbb3 f0f8 udiv r0, r3, r8
8000348: fb08 3310 mls r3, r8, r0, r3
800034c: ea44 4403 orr.w r4, r4, r3, lsl #16
8000350: fb00 fe0e mul.w lr, r0, lr
8000354: 45a6 cmp lr, r4
8000356: d909 bls.n 800036c <__udivmoddi4+0x8c>
8000358: 193c adds r4, r7, r4
800035a: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
800035e: f080 8105 bcs.w 800056c <__udivmoddi4+0x28c>
8000362: 45a6 cmp lr, r4
8000364: f240 8102 bls.w 800056c <__udivmoddi4+0x28c>
8000368: 3802 subs r0, #2
800036a: 443c add r4, r7
800036c: ea40 4006 orr.w r0, r0, r6, lsl #16
8000370: eba4 040e sub.w r4, r4, lr
8000374: 2600 movs r6, #0
8000376: b11d cbz r5, 8000380 <__udivmoddi4+0xa0>
8000378: 40d4 lsrs r4, r2
800037a: 2300 movs r3, #0
800037c: e9c5 4300 strd r4, r3, [r5]
8000380: 4631 mov r1, r6
8000382: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000386: b902 cbnz r2, 800038a <__udivmoddi4+0xaa>
8000388: deff udf #255 ; 0xff
800038a: fab2 f282 clz r2, r2
800038e: 2a00 cmp r2, #0
8000390: d150 bne.n 8000434 <__udivmoddi4+0x154>
8000392: 1bcb subs r3, r1, r7
8000394: ea4f 4e17 mov.w lr, r7, lsr #16
8000398: fa1f f887 uxth.w r8, r7
800039c: 2601 movs r6, #1
800039e: fbb3 fcfe udiv ip, r3, lr
80003a2: 0c21 lsrs r1, r4, #16
80003a4: fb0e 331c mls r3, lr, ip, r3
80003a8: ea41 4103 orr.w r1, r1, r3, lsl #16
80003ac: fb08 f30c mul.w r3, r8, ip
80003b0: 428b cmp r3, r1
80003b2: d907 bls.n 80003c4 <__udivmoddi4+0xe4>
80003b4: 1879 adds r1, r7, r1
80003b6: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
80003ba: d202 bcs.n 80003c2 <__udivmoddi4+0xe2>
80003bc: 428b cmp r3, r1
80003be: f200 80e9 bhi.w 8000594 <__udivmoddi4+0x2b4>
80003c2: 4684 mov ip, r0
80003c4: 1ac9 subs r1, r1, r3
80003c6: b2a3 uxth r3, r4
80003c8: fbb1 f0fe udiv r0, r1, lr
80003cc: fb0e 1110 mls r1, lr, r0, r1
80003d0: ea43 4401 orr.w r4, r3, r1, lsl #16
80003d4: fb08 f800 mul.w r8, r8, r0
80003d8: 45a0 cmp r8, r4
80003da: d907 bls.n 80003ec <__udivmoddi4+0x10c>
80003dc: 193c adds r4, r7, r4
80003de: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
80003e2: d202 bcs.n 80003ea <__udivmoddi4+0x10a>
80003e4: 45a0 cmp r8, r4
80003e6: f200 80d9 bhi.w 800059c <__udivmoddi4+0x2bc>
80003ea: 4618 mov r0, r3
80003ec: eba4 0408 sub.w r4, r4, r8
80003f0: ea40 400c orr.w r0, r0, ip, lsl #16
80003f4: e7bf b.n 8000376 <__udivmoddi4+0x96>
80003f6: 428b cmp r3, r1
80003f8: d909 bls.n 800040e <__udivmoddi4+0x12e>
80003fa: 2d00 cmp r5, #0
80003fc: f000 80b1 beq.w 8000562 <__udivmoddi4+0x282>
8000400: 2600 movs r6, #0
8000402: e9c5 0100 strd r0, r1, [r5]
8000406: 4630 mov r0, r6
8000408: 4631 mov r1, r6
800040a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800040e: fab3 f683 clz r6, r3
8000412: 2e00 cmp r6, #0
8000414: d14a bne.n 80004ac <__udivmoddi4+0x1cc>
8000416: 428b cmp r3, r1
8000418: d302 bcc.n 8000420 <__udivmoddi4+0x140>
800041a: 4282 cmp r2, r0
800041c: f200 80b8 bhi.w 8000590 <__udivmoddi4+0x2b0>
8000420: 1a84 subs r4, r0, r2
8000422: eb61 0103 sbc.w r1, r1, r3
8000426: 2001 movs r0, #1
8000428: 468c mov ip, r1
800042a: 2d00 cmp r5, #0
800042c: d0a8 beq.n 8000380 <__udivmoddi4+0xa0>
800042e: e9c5 4c00 strd r4, ip, [r5]
8000432: e7a5 b.n 8000380 <__udivmoddi4+0xa0>
8000434: f1c2 0320 rsb r3, r2, #32
8000438: fa20 f603 lsr.w r6, r0, r3
800043c: 4097 lsls r7, r2
800043e: fa01 f002 lsl.w r0, r1, r2
8000442: ea4f 4e17 mov.w lr, r7, lsr #16
8000446: 40d9 lsrs r1, r3
8000448: 4330 orrs r0, r6
800044a: 0c03 lsrs r3, r0, #16
800044c: fbb1 f6fe udiv r6, r1, lr
8000450: fa1f f887 uxth.w r8, r7
8000454: fb0e 1116 mls r1, lr, r6, r1
8000458: ea43 4301 orr.w r3, r3, r1, lsl #16
800045c: fb06 f108 mul.w r1, r6, r8
8000460: 4299 cmp r1, r3
8000462: fa04 f402 lsl.w r4, r4, r2
8000466: d909 bls.n 800047c <__udivmoddi4+0x19c>
8000468: 18fb adds r3, r7, r3
800046a: f106 3cff add.w ip, r6, #4294967295 ; 0xffffffff
800046e: f080 808d bcs.w 800058c <__udivmoddi4+0x2ac>
8000472: 4299 cmp r1, r3
8000474: f240 808a bls.w 800058c <__udivmoddi4+0x2ac>
8000478: 3e02 subs r6, #2
800047a: 443b add r3, r7
800047c: 1a5b subs r3, r3, r1
800047e: b281 uxth r1, r0
8000480: fbb3 f0fe udiv r0, r3, lr
8000484: fb0e 3310 mls r3, lr, r0, r3
8000488: ea41 4103 orr.w r1, r1, r3, lsl #16
800048c: fb00 f308 mul.w r3, r0, r8
8000490: 428b cmp r3, r1
8000492: d907 bls.n 80004a4 <__udivmoddi4+0x1c4>
8000494: 1879 adds r1, r7, r1
8000496: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
800049a: d273 bcs.n 8000584 <__udivmoddi4+0x2a4>
800049c: 428b cmp r3, r1
800049e: d971 bls.n 8000584 <__udivmoddi4+0x2a4>
80004a0: 3802 subs r0, #2
80004a2: 4439 add r1, r7
80004a4: 1acb subs r3, r1, r3
80004a6: ea40 4606 orr.w r6, r0, r6, lsl #16
80004aa: e778 b.n 800039e <__udivmoddi4+0xbe>
80004ac: f1c6 0c20 rsb ip, r6, #32
80004b0: fa03 f406 lsl.w r4, r3, r6
80004b4: fa22 f30c lsr.w r3, r2, ip
80004b8: 431c orrs r4, r3
80004ba: fa20 f70c lsr.w r7, r0, ip
80004be: fa01 f306 lsl.w r3, r1, r6
80004c2: ea4f 4e14 mov.w lr, r4, lsr #16
80004c6: fa21 f10c lsr.w r1, r1, ip
80004ca: 431f orrs r7, r3
80004cc: 0c3b lsrs r3, r7, #16
80004ce: fbb1 f9fe udiv r9, r1, lr
80004d2: fa1f f884 uxth.w r8, r4
80004d6: fb0e 1119 mls r1, lr, r9, r1
80004da: ea43 4101 orr.w r1, r3, r1, lsl #16
80004de: fb09 fa08 mul.w sl, r9, r8
80004e2: 458a cmp sl, r1
80004e4: fa02 f206 lsl.w r2, r2, r6
80004e8: fa00 f306 lsl.w r3, r0, r6
80004ec: d908 bls.n 8000500 <__udivmoddi4+0x220>
80004ee: 1861 adds r1, r4, r1
80004f0: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
80004f4: d248 bcs.n 8000588 <__udivmoddi4+0x2a8>
80004f6: 458a cmp sl, r1
80004f8: d946 bls.n 8000588 <__udivmoddi4+0x2a8>
80004fa: f1a9 0902 sub.w r9, r9, #2
80004fe: 4421 add r1, r4
8000500: eba1 010a sub.w r1, r1, sl
8000504: b2bf uxth r7, r7
8000506: fbb1 f0fe udiv r0, r1, lr
800050a: fb0e 1110 mls r1, lr, r0, r1
800050e: ea47 4701 orr.w r7, r7, r1, lsl #16
8000512: fb00 f808 mul.w r8, r0, r8
8000516: 45b8 cmp r8, r7
8000518: d907 bls.n 800052a <__udivmoddi4+0x24a>
800051a: 19e7 adds r7, r4, r7
800051c: f100 31ff add.w r1, r0, #4294967295 ; 0xffffffff
8000520: d22e bcs.n 8000580 <__udivmoddi4+0x2a0>
8000522: 45b8 cmp r8, r7
8000524: d92c bls.n 8000580 <__udivmoddi4+0x2a0>
8000526: 3802 subs r0, #2
8000528: 4427 add r7, r4
800052a: ea40 4009 orr.w r0, r0, r9, lsl #16
800052e: eba7 0708 sub.w r7, r7, r8
8000532: fba0 8902 umull r8, r9, r0, r2
8000536: 454f cmp r7, r9
8000538: 46c6 mov lr, r8
800053a: 4649 mov r1, r9
800053c: d31a bcc.n 8000574 <__udivmoddi4+0x294>
800053e: d017 beq.n 8000570 <__udivmoddi4+0x290>
8000540: b15d cbz r5, 800055a <__udivmoddi4+0x27a>
8000542: ebb3 020e subs.w r2, r3, lr
8000546: eb67 0701 sbc.w r7, r7, r1
800054a: fa07 fc0c lsl.w ip, r7, ip
800054e: 40f2 lsrs r2, r6
8000550: ea4c 0202 orr.w r2, ip, r2
8000554: 40f7 lsrs r7, r6
8000556: e9c5 2700 strd r2, r7, [r5]
800055a: 2600 movs r6, #0
800055c: 4631 mov r1, r6
800055e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000562: 462e mov r6, r5
8000564: 4628 mov r0, r5
8000566: e70b b.n 8000380 <__udivmoddi4+0xa0>
8000568: 4606 mov r6, r0
800056a: e6e9 b.n 8000340 <__udivmoddi4+0x60>
800056c: 4618 mov r0, r3
800056e: e6fd b.n 800036c <__udivmoddi4+0x8c>
8000570: 4543 cmp r3, r8
8000572: d2e5 bcs.n 8000540 <__udivmoddi4+0x260>
8000574: ebb8 0e02 subs.w lr, r8, r2
8000578: eb69 0104 sbc.w r1, r9, r4
800057c: 3801 subs r0, #1
800057e: e7df b.n 8000540 <__udivmoddi4+0x260>
8000580: 4608 mov r0, r1
8000582: e7d2 b.n 800052a <__udivmoddi4+0x24a>
8000584: 4660 mov r0, ip
8000586: e78d b.n 80004a4 <__udivmoddi4+0x1c4>
8000588: 4681 mov r9, r0
800058a: e7b9 b.n 8000500 <__udivmoddi4+0x220>
800058c: 4666 mov r6, ip
800058e: e775 b.n 800047c <__udivmoddi4+0x19c>
8000590: 4630 mov r0, r6
8000592: e74a b.n 800042a <__udivmoddi4+0x14a>
8000594: f1ac 0c02 sub.w ip, ip, #2
8000598: 4439 add r1, r7
800059a: e713 b.n 80003c4 <__udivmoddi4+0xe4>
800059c: 3802 subs r0, #2
800059e: 443c add r4, r7
80005a0: e724 b.n 80003ec <__udivmoddi4+0x10c>
80005a2: bf00 nop
080005a4 <__aeabi_idiv0>:
80005a4: 4770 bx lr
80005a6: bf00 nop
080005a8 <vApplicationIdleHook>:
void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName);
void vApplicationMallocFailedHook(void);
/* USER CODE BEGIN 2 */
__weak void vApplicationIdleHook( void )
{
80005a8: b480 push {r7}
80005aa: af00 add r7, sp, #0
specified, or call vTaskDelay()). If the application makes use of the
vTaskDelete() API function (as this demo application does) then it is also
important that vApplicationIdleHook() is permitted to return to its calling
function, because it is the responsibility of the idle task to clean up
memory allocated by the kernel to any task that has since been deleted. */
}
80005ac: bf00 nop
80005ae: 46bd mov sp, r7
80005b0: f85d 7b04 ldr.w r7, [sp], #4
80005b4: 4770 bx lr
080005b6 <vApplicationStackOverflowHook>:
/* USER CODE END 2 */
/* USER CODE BEGIN 4 */
__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
{
80005b6: b480 push {r7}
80005b8: b083 sub sp, #12
80005ba: af00 add r7, sp, #0
80005bc: 6078 str r0, [r7, #4]
80005be: 6039 str r1, [r7, #0]
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
called if a stack overflow is detected. */
}
80005c0: bf00 nop
80005c2: 370c adds r7, #12
80005c4: 46bd mov sp, r7
80005c6: f85d 7b04 ldr.w r7, [sp], #4
80005ca: 4770 bx lr
080005cc <vApplicationMallocFailedHook>:
/* USER CODE END 4 */
/* USER CODE BEGIN 5 */
__weak void vApplicationMallocFailedHook(void)
{
80005cc: b480 push {r7}
80005ce: af00 add r7, sp, #0
demo application. If heap_1.c or heap_2.c are used, then the size of the
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */
}
80005d0: bf00 nop
80005d2: 46bd mov sp, r7
80005d4: f85d 7b04 ldr.w r7, [sp], #4
80005d8: 4770 bx lr
...
080005dc <vApplicationGetIdleTaskMemory>:
/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
static StaticTask_t xIdleTaskTCBBuffer;
static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
{
80005dc: b480 push {r7}
80005de: b085 sub sp, #20
80005e0: af00 add r7, sp, #0
80005e2: 60f8 str r0, [r7, #12]
80005e4: 60b9 str r1, [r7, #8]
80005e6: 607a str r2, [r7, #4]
*ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
80005e8: 68fb ldr r3, [r7, #12]
80005ea: 4a07 ldr r2, [pc, #28] ; (8000608 <vApplicationGetIdleTaskMemory+0x2c>)
80005ec: 601a str r2, [r3, #0]
*ppxIdleTaskStackBuffer = &xIdleStack[0];
80005ee: 68bb ldr r3, [r7, #8]
80005f0: 4a06 ldr r2, [pc, #24] ; (800060c <vApplicationGetIdleTaskMemory+0x30>)
80005f2: 601a str r2, [r3, #0]
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
80005f4: 687b ldr r3, [r7, #4]
80005f6: 2280 movs r2, #128 ; 0x80
80005f8: 601a str r2, [r3, #0]
/* place for user code */
}
80005fa: bf00 nop
80005fc: 3714 adds r7, #20
80005fe: 46bd mov sp, r7
8000600: f85d 7b04 ldr.w r7, [sp], #4
8000604: 4770 bx lr
8000606: bf00 nop
8000608: 200000f8 .word 0x200000f8
800060c: 20000150 .word 0x20000150
08000610 <ft5336_Init>:
* from MCU to FT5336 : ie I2C channel initialization (if required).
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval None
*/
void ft5336_Init(uint16_t DeviceAddr)
{
8000610: b580 push {r7, lr}
8000612: b082 sub sp, #8
8000614: af00 add r7, sp, #0
8000616: 4603 mov r3, r0
8000618: 80fb strh r3, [r7, #6]
/* Wait at least 200ms after power up before accessing registers
* Trsi timing (Time of starting to report point after resetting) from FT5336GQQ datasheet */
TS_IO_Delay(200);
800061a: 20c8 movs r0, #200 ; 0xc8
800061c: f002 f9cc bl 80029b8 <TS_IO_Delay>
/* Initialize I2C link if needed */
ft5336_I2C_InitializeIfRequired();
8000620: f000 fa7a bl 8000b18 <ft5336_I2C_InitializeIfRequired>
}
8000624: bf00 nop
8000626: 3708 adds r7, #8
8000628: 46bd mov sp, r7
800062a: bd80 pop {r7, pc}
0800062c <ft5336_Reset>:
* @note : Not applicable to FT5336.
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval None
*/
void ft5336_Reset(uint16_t DeviceAddr)
{
800062c: b480 push {r7}
800062e: b083 sub sp, #12
8000630: af00 add r7, sp, #0
8000632: 4603 mov r3, r0
8000634: 80fb strh r3, [r7, #6]
/* Do nothing */
/* No software reset sequence available in FT5336 IC */
}
8000636: bf00 nop
8000638: 370c adds r7, #12
800063a: 46bd mov sp, r7
800063c: f85d 7b04 ldr.w r7, [sp], #4
8000640: 4770 bx lr
08000642 <ft5336_ReadID>:
* able to read the FT5336 device ID, and verify this is a FT5336.
* @param DeviceAddr: I2C FT5336 Slave address.
* @retval The Device ID (two bytes).
*/
uint16_t ft5336_ReadID(uint16_t DeviceAddr)
{
8000642: b580 push {r7, lr}
8000644: b084 sub sp, #16
8000646: af00 add r7, sp, #0
8000648: 4603 mov r3, r0
800064a: 80fb strh r3, [r7, #6]
volatile uint8_t ucReadId = 0;
800064c: 2300 movs r3, #0
800064e: 737b strb r3, [r7, #13]
uint8_t nbReadAttempts = 0;
8000650: 2300 movs r3, #0
8000652: 73fb strb r3, [r7, #15]
uint8_t bFoundDevice = 0; /* Device not found by default */
8000654: 2300 movs r3, #0
8000656: 73bb strb r3, [r7, #14]
/* Initialize I2C link if needed */
ft5336_I2C_InitializeIfRequired();
8000658: f000 fa5e bl 8000b18 <ft5336_I2C_InitializeIfRequired>
/* At maximum 4 attempts to read ID : exit at first finding of the searched device ID */
for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++)
800065c: 2300 movs r3, #0
800065e: 73fb strb r3, [r7, #15]
8000660: e010 b.n 8000684 <ft5336_ReadID+0x42>
{
/* Read register FT5336_CHIP_ID_REG as DeviceID detection */
ucReadId = TS_IO_Read(DeviceAddr, FT5336_CHIP_ID_REG);
8000662: 88fb ldrh r3, [r7, #6]
8000664: b2db uxtb r3, r3
8000666: 21a8 movs r1, #168 ; 0xa8
8000668: 4618 mov r0, r3
800066a: f002 f987 bl 800297c <TS_IO_Read>
800066e: 4603 mov r3, r0
8000670: 737b strb r3, [r7, #13]
/* Found the searched device ID ? */
if(ucReadId == FT5336_ID_VALUE)
8000672: 7b7b ldrb r3, [r7, #13]
8000674: b2db uxtb r3, r3
8000676: 2b51 cmp r3, #81 ; 0x51
8000678: d101 bne.n 800067e <ft5336_ReadID+0x3c>
{
/* Set device as found */
bFoundDevice = 1;
800067a: 2301 movs r3, #1
800067c: 73bb strb r3, [r7, #14]
for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++)
800067e: 7bfb ldrb r3, [r7, #15]
8000680: 3301 adds r3, #1
8000682: 73fb strb r3, [r7, #15]
8000684: 7bfb ldrb r3, [r7, #15]
8000686: 2b02 cmp r3, #2
8000688: d802 bhi.n 8000690 <ft5336_ReadID+0x4e>
800068a: 7bbb ldrb r3, [r7, #14]
800068c: 2b00 cmp r3, #0
800068e: d0e8 beq.n 8000662 <ft5336_ReadID+0x20>
}
}
/* Return the device ID value */
return (ucReadId);
8000690: 7b7b ldrb r3, [r7, #13]
8000692: b2db uxtb r3, r3
8000694: b29b uxth r3, r3
}
8000696: 4618 mov r0, r3
8000698: 3710 adds r7, #16
800069a: 46bd mov sp, r7
800069c: bd80 pop {r7, pc}
0800069e <ft5336_TS_Start>:
* @brief Configures the touch Screen IC device to start detecting touches
* @param DeviceAddr: Device address on communication Bus (I2C slave address).
* @retval None.
*/
void ft5336_TS_Start(uint16_t DeviceAddr)
{
800069e: b580 push {r7, lr}
80006a0: b082 sub sp, #8
80006a2: af00 add r7, sp, #0
80006a4: 4603 mov r3, r0
80006a6: 80fb strh r3, [r7, #6]
/* Minimum static configuration of FT5336 */
FT5336_ASSERT(ft5336_TS_Configure(DeviceAddr));
80006a8: 88fb ldrh r3, [r7, #6]
80006aa: 4618 mov r0, r3
80006ac: f000 fa44 bl 8000b38 <ft5336_TS_Configure>
/* By default set FT5336 IC in Polling mode : no INT generation on FT5336 for new touch available */
/* Note TS_INT is active low */
ft5336_TS_DisableIT(DeviceAddr);
80006b0: 88fb ldrh r3, [r7, #6]
80006b2: 4618 mov r0, r3
80006b4: f000 f932 bl 800091c <ft5336_TS_DisableIT>
}
80006b8: bf00 nop
80006ba: 3708 adds r7, #8
80006bc: 46bd mov sp, r7
80006be: bd80 pop {r7, pc}
080006c0 <ft5336_TS_DetectTouch>:
* variables).
* @param DeviceAddr: Device address on communication Bus.
* @retval : Number of active touches detected (can be 0, 1 or 2).
*/
uint8_t ft5336_TS_DetectTouch(uint16_t DeviceAddr)
{
80006c0: b580 push {r7, lr}
80006c2: b084 sub sp, #16
80006c4: af00 add r7, sp, #0
80006c6: 4603 mov r3, r0
80006c8: 80fb strh r3, [r7, #6]
volatile uint8_t nbTouch = 0;
80006ca: 2300 movs r3, #0
80006cc: 73fb strb r3, [r7, #15]
/* Read register FT5336_TD_STAT_REG to check number of touches detection */
nbTouch = TS_IO_Read(DeviceAddr, FT5336_TD_STAT_REG);
80006ce: 88fb ldrh r3, [r7, #6]
80006d0: b2db uxtb r3, r3
80006d2: 2102 movs r1, #2
80006d4: 4618 mov r0, r3
80006d6: f002 f951 bl 800297c <TS_IO_Read>
80006da: 4603 mov r3, r0
80006dc: 73fb strb r3, [r7, #15]
nbTouch &= FT5336_TD_STAT_MASK;
80006de: 7bfb ldrb r3, [r7, #15]
80006e0: b2db uxtb r3, r3
80006e2: f003 030f and.w r3, r3, #15
80006e6: b2db uxtb r3, r3
80006e8: 73fb strb r3, [r7, #15]
if(nbTouch > FT5336_MAX_DETECTABLE_TOUCH)
80006ea: 7bfb ldrb r3, [r7, #15]
80006ec: b2db uxtb r3, r3
80006ee: 2b05 cmp r3, #5
80006f0: d901 bls.n 80006f6 <ft5336_TS_DetectTouch+0x36>
{
/* If invalid number of touch detected, set it to zero */
nbTouch = 0;
80006f2: 2300 movs r3, #0
80006f4: 73fb strb r3, [r7, #15]
}
/* Update ft5336 driver internal global : current number of active touches */
ft5336_handle.currActiveTouchNb = nbTouch;
80006f6: 7bfb ldrb r3, [r7, #15]
80006f8: b2da uxtb r2, r3
80006fa: 4b05 ldr r3, [pc, #20] ; (8000710 <ft5336_TS_DetectTouch+0x50>)
80006fc: 705a strb r2, [r3, #1]
/* Reset current active touch index on which to work on */
ft5336_handle.currActiveTouchIdx = 0;
80006fe: 4b04 ldr r3, [pc, #16] ; (8000710 <ft5336_TS_DetectTouch+0x50>)
8000700: 2200 movs r2, #0
8000702: 709a strb r2, [r3, #2]
return(nbTouch);
8000704: 7bfb ldrb r3, [r7, #15]
8000706: b2db uxtb r3, r3
}
8000708: 4618 mov r0, r3
800070a: 3710 adds r7, #16
800070c: 46bd mov sp, r7
800070e: bd80 pop {r7, pc}
8000710: 20000350 .word 0x20000350
08000714 <ft5336_TS_GetXY>:
* @param X: Pointer to X position value
* @param Y: Pointer to Y position value
* @retval None.
*/
void ft5336_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y)
{
8000714: b580 push {r7, lr}
8000716: b086 sub sp, #24
8000718: af00 add r7, sp, #0
800071a: 4603 mov r3, r0
800071c: 60b9 str r1, [r7, #8]
800071e: 607a str r2, [r7, #4]
8000720: 81fb strh r3, [r7, #14]
volatile uint8_t ucReadData = 0;
8000722: 2300 movs r3, #0
8000724: 74fb strb r3, [r7, #19]
static uint16_t coord;
uint8_t regAddressXLow = 0;
8000726: 2300 movs r3, #0
8000728: 75fb strb r3, [r7, #23]
uint8_t regAddressXHigh = 0;
800072a: 2300 movs r3, #0
800072c: 75bb strb r3, [r7, #22]
uint8_t regAddressYLow = 0;
800072e: 2300 movs r3, #0
8000730: 757b strb r3, [r7, #21]
uint8_t regAddressYHigh = 0;
8000732: 2300 movs r3, #0
8000734: 753b strb r3, [r7, #20]
if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb)
8000736: 4b6d ldr r3, [pc, #436] ; (80008ec <ft5336_TS_GetXY+0x1d8>)
8000738: 789a ldrb r2, [r3, #2]
800073a: 4b6c ldr r3, [pc, #432] ; (80008ec <ft5336_TS_GetXY+0x1d8>)
800073c: 785b ldrb r3, [r3, #1]
800073e: 429a cmp r2, r3
8000740: f080 80cf bcs.w 80008e2 <ft5336_TS_GetXY+0x1ce>
{
switch(ft5336_handle.currActiveTouchIdx)
8000744: 4b69 ldr r3, [pc, #420] ; (80008ec <ft5336_TS_GetXY+0x1d8>)
8000746: 789b ldrb r3, [r3, #2]
8000748: 2b09 cmp r3, #9
800074a: d871 bhi.n 8000830 <ft5336_TS_GetXY+0x11c>
800074c: a201 add r2, pc, #4 ; (adr r2, 8000754 <ft5336_TS_GetXY+0x40>)
800074e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8000752: bf00 nop
8000754: 0800077d .word 0x0800077d
8000758: 0800078f .word 0x0800078f
800075c: 080007a1 .word 0x080007a1
8000760: 080007b3 .word 0x080007b3
8000764: 080007c5 .word 0x080007c5
8000768: 080007d7 .word 0x080007d7
800076c: 080007e9 .word 0x080007e9
8000770: 080007fb .word 0x080007fb
8000774: 0800080d .word 0x0800080d
8000778: 0800081f .word 0x0800081f
{
case 0 :
regAddressXLow = FT5336_P1_XL_REG;
800077c: 2304 movs r3, #4
800077e: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P1_XH_REG;
8000780: 2303 movs r3, #3
8000782: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P1_YL_REG;
8000784: 2306 movs r3, #6
8000786: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P1_YH_REG;
8000788: 2305 movs r3, #5
800078a: 753b strb r3, [r7, #20]
break;
800078c: e051 b.n 8000832 <ft5336_TS_GetXY+0x11e>
case 1 :
regAddressXLow = FT5336_P2_XL_REG;
800078e: 230a movs r3, #10
8000790: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P2_XH_REG;
8000792: 2309 movs r3, #9
8000794: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P2_YL_REG;
8000796: 230c movs r3, #12
8000798: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P2_YH_REG;
800079a: 230b movs r3, #11
800079c: 753b strb r3, [r7, #20]
break;
800079e: e048 b.n 8000832 <ft5336_TS_GetXY+0x11e>
case 2 :
regAddressXLow = FT5336_P3_XL_REG;
80007a0: 2310 movs r3, #16
80007a2: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P3_XH_REG;
80007a4: 230f movs r3, #15
80007a6: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P3_YL_REG;
80007a8: 2312 movs r3, #18
80007aa: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P3_YH_REG;
80007ac: 2311 movs r3, #17
80007ae: 753b strb r3, [r7, #20]
break;
80007b0: e03f b.n 8000832 <ft5336_TS_GetXY+0x11e>
case 3 :
regAddressXLow = FT5336_P4_XL_REG;
80007b2: 2316 movs r3, #22
80007b4: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P4_XH_REG;
80007b6: 2315 movs r3, #21
80007b8: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P4_YL_REG;
80007ba: 2318 movs r3, #24
80007bc: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P4_YH_REG;
80007be: 2317 movs r3, #23
80007c0: 753b strb r3, [r7, #20]
break;
80007c2: e036 b.n 8000832 <ft5336_TS_GetXY+0x11e>
case 4 :
regAddressXLow = FT5336_P5_XL_REG;
80007c4: 231c movs r3, #28
80007c6: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P5_XH_REG;
80007c8: 231b movs r3, #27
80007ca: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P5_YL_REG;
80007cc: 231e movs r3, #30
80007ce: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P5_YH_REG;
80007d0: 231d movs r3, #29
80007d2: 753b strb r3, [r7, #20]
break;
80007d4: e02d b.n 8000832 <ft5336_TS_GetXY+0x11e>
case 5 :
regAddressXLow = FT5336_P6_XL_REG;
80007d6: 2322 movs r3, #34 ; 0x22
80007d8: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P6_XH_REG;
80007da: 2321 movs r3, #33 ; 0x21
80007dc: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P6_YL_REG;
80007de: 2324 movs r3, #36 ; 0x24
80007e0: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P6_YH_REG;
80007e2: 2323 movs r3, #35 ; 0x23
80007e4: 753b strb r3, [r7, #20]
break;
80007e6: e024 b.n 8000832 <ft5336_TS_GetXY+0x11e>
case 6 :
regAddressXLow = FT5336_P7_XL_REG;
80007e8: 2328 movs r3, #40 ; 0x28
80007ea: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P7_XH_REG;
80007ec: 2327 movs r3, #39 ; 0x27
80007ee: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P7_YL_REG;
80007f0: 232a movs r3, #42 ; 0x2a
80007f2: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P7_YH_REG;
80007f4: 2329 movs r3, #41 ; 0x29
80007f6: 753b strb r3, [r7, #20]
break;
80007f8: e01b b.n 8000832 <ft5336_TS_GetXY+0x11e>
case 7 :
regAddressXLow = FT5336_P8_XL_REG;
80007fa: 232e movs r3, #46 ; 0x2e
80007fc: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P8_XH_REG;
80007fe: 232d movs r3, #45 ; 0x2d
8000800: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P8_YL_REG;
8000802: 2330 movs r3, #48 ; 0x30
8000804: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P8_YH_REG;
8000806: 232f movs r3, #47 ; 0x2f
8000808: 753b strb r3, [r7, #20]
break;
800080a: e012 b.n 8000832 <ft5336_TS_GetXY+0x11e>
case 8 :
regAddressXLow = FT5336_P9_XL_REG;
800080c: 2334 movs r3, #52 ; 0x34
800080e: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P9_XH_REG;
8000810: 2333 movs r3, #51 ; 0x33
8000812: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P9_YL_REG;
8000814: 2336 movs r3, #54 ; 0x36
8000816: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P9_YH_REG;
8000818: 2335 movs r3, #53 ; 0x35
800081a: 753b strb r3, [r7, #20]
break;
800081c: e009 b.n 8000832 <ft5336_TS_GetXY+0x11e>
case 9 :
regAddressXLow = FT5336_P10_XL_REG;
800081e: 233a movs r3, #58 ; 0x3a
8000820: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P10_XH_REG;
8000822: 2339 movs r3, #57 ; 0x39
8000824: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P10_YL_REG;
8000826: 233c movs r3, #60 ; 0x3c
8000828: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P10_YH_REG;
800082a: 233b movs r3, #59 ; 0x3b
800082c: 753b strb r3, [r7, #20]
break;
800082e: e000 b.n 8000832 <ft5336_TS_GetXY+0x11e>
default :
break;
8000830: bf00 nop
} /* end switch(ft5336_handle.currActiveTouchIdx) */
/* Read low part of X position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressXLow);
8000832: 89fb ldrh r3, [r7, #14]
8000834: b2db uxtb r3, r3
8000836: 7dfa ldrb r2, [r7, #23]
8000838: 4611 mov r1, r2
800083a: 4618 mov r0, r3
800083c: f002 f89e bl 800297c <TS_IO_Read>
8000840: 4603 mov r3, r0
8000842: 74fb strb r3, [r7, #19]
coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT;
8000844: 7cfb ldrb r3, [r7, #19]
8000846: b2db uxtb r3, r3
8000848: b29a uxth r2, r3
800084a: 4b29 ldr r3, [pc, #164] ; (80008f0 <ft5336_TS_GetXY+0x1dc>)
800084c: 801a strh r2, [r3, #0]
/* Read high part of X position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh);
800084e: 89fb ldrh r3, [r7, #14]
8000850: b2db uxtb r3, r3
8000852: 7dba ldrb r2, [r7, #22]
8000854: 4611 mov r1, r2
8000856: 4618 mov r0, r3
8000858: f002 f890 bl 800297c <TS_IO_Read>
800085c: 4603 mov r3, r0
800085e: 74fb strb r3, [r7, #19]
coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8;
8000860: 7cfb ldrb r3, [r7, #19]
8000862: b2db uxtb r3, r3
8000864: 021b lsls r3, r3, #8
8000866: f403 6370 and.w r3, r3, #3840 ; 0xf00
800086a: b21a sxth r2, r3
800086c: 4b20 ldr r3, [pc, #128] ; (80008f0 <ft5336_TS_GetXY+0x1dc>)
800086e: 881b ldrh r3, [r3, #0]
8000870: b21b sxth r3, r3
8000872: 4313 orrs r3, r2
8000874: b21b sxth r3, r3
8000876: b29a uxth r2, r3
8000878: 4b1d ldr r3, [pc, #116] ; (80008f0 <ft5336_TS_GetXY+0x1dc>)
800087a: 801a strh r2, [r3, #0]
/* Send back ready X position to caller */
*X = coord;
800087c: 4b1c ldr r3, [pc, #112] ; (80008f0 <ft5336_TS_GetXY+0x1dc>)
800087e: 881a ldrh r2, [r3, #0]
8000880: 68bb ldr r3, [r7, #8]
8000882: 801a strh r2, [r3, #0]
/* Read low part of Y position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressYLow);
8000884: 89fb ldrh r3, [r7, #14]
8000886: b2db uxtb r3, r3
8000888: 7d7a ldrb r2, [r7, #21]
800088a: 4611 mov r1, r2
800088c: 4618 mov r0, r3
800088e: f002 f875 bl 800297c <TS_IO_Read>
8000892: 4603 mov r3, r0
8000894: 74fb strb r3, [r7, #19]
coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT;
8000896: 7cfb ldrb r3, [r7, #19]
8000898: b2db uxtb r3, r3
800089a: b29a uxth r2, r3
800089c: 4b14 ldr r3, [pc, #80] ; (80008f0 <ft5336_TS_GetXY+0x1dc>)
800089e: 801a strh r2, [r3, #0]
/* Read high part of Y position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressYHigh);
80008a0: 89fb ldrh r3, [r7, #14]
80008a2: b2db uxtb r3, r3
80008a4: 7d3a ldrb r2, [r7, #20]
80008a6: 4611 mov r1, r2
80008a8: 4618 mov r0, r3
80008aa: f002 f867 bl 800297c <TS_IO_Read>
80008ae: 4603 mov r3, r0
80008b0: 74fb strb r3, [r7, #19]
coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8;
80008b2: 7cfb ldrb r3, [r7, #19]
80008b4: b2db uxtb r3, r3
80008b6: 021b lsls r3, r3, #8
80008b8: f403 6370 and.w r3, r3, #3840 ; 0xf00
80008bc: b21a sxth r2, r3
80008be: 4b0c ldr r3, [pc, #48] ; (80008f0 <ft5336_TS_GetXY+0x1dc>)
80008c0: 881b ldrh r3, [r3, #0]
80008c2: b21b sxth r3, r3
80008c4: 4313 orrs r3, r2
80008c6: b21b sxth r3, r3
80008c8: b29a uxth r2, r3
80008ca: 4b09 ldr r3, [pc, #36] ; (80008f0 <ft5336_TS_GetXY+0x1dc>)
80008cc: 801a strh r2, [r3, #0]
/* Send back ready Y position to caller */
*Y = coord;
80008ce: 4b08 ldr r3, [pc, #32] ; (80008f0 <ft5336_TS_GetXY+0x1dc>)
80008d0: 881a ldrh r2, [r3, #0]
80008d2: 687b ldr r3, [r7, #4]
80008d4: 801a strh r2, [r3, #0]
ft5336_handle.currActiveTouchIdx++; /* next call will work on next touch */
80008d6: 4b05 ldr r3, [pc, #20] ; (80008ec <ft5336_TS_GetXY+0x1d8>)
80008d8: 789b ldrb r3, [r3, #2]
80008da: 3301 adds r3, #1
80008dc: b2da uxtb r2, r3
80008de: 4b03 ldr r3, [pc, #12] ; (80008ec <ft5336_TS_GetXY+0x1d8>)
80008e0: 709a strb r2, [r3, #2]
} /* of if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb) */
}
80008e2: bf00 nop
80008e4: 3718 adds r7, #24
80008e6: 46bd mov sp, r7
80008e8: bd80 pop {r7, pc}
80008ea: bf00 nop
80008ec: 20000350 .word 0x20000350
80008f0: 20000354 .word 0x20000354
080008f4 <ft5336_TS_EnableIT>:
* connected to MCU as EXTI.
* @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336).
* @retval None
*/
void ft5336_TS_EnableIT(uint16_t DeviceAddr)
{
80008f4: b580 push {r7, lr}
80008f6: b084 sub sp, #16
80008f8: af00 add r7, sp, #0
80008fa: 4603 mov r3, r0
80008fc: 80fb strh r3, [r7, #6]
uint8_t regValue = 0;
80008fe: 2300 movs r3, #0
8000900: 73fb strb r3, [r7, #15]
regValue = (FT5336_G_MODE_INTERRUPT_TRIGGER & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT;
8000902: 2301 movs r3, #1
8000904: 73fb strb r3, [r7, #15]
/* Set interrupt trigger mode in FT5336_GMODE_REG */
TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue);
8000906: 88fb ldrh r3, [r7, #6]
8000908: b2db uxtb r3, r3
800090a: 7bfa ldrb r2, [r7, #15]
800090c: 21a4 movs r1, #164 ; 0xa4
800090e: 4618 mov r0, r3
8000910: f002 f81a bl 8002948 <TS_IO_Write>
}
8000914: bf00 nop
8000916: 3710 adds r7, #16
8000918: 46bd mov sp, r7
800091a: bd80 pop {r7, pc}
0800091c <ft5336_TS_DisableIT>:
* connected to MCU as EXTI.
* @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336).
* @retval None
*/
void ft5336_TS_DisableIT(uint16_t DeviceAddr)
{
800091c: b580 push {r7, lr}
800091e: b084 sub sp, #16
8000920: af00 add r7, sp, #0
8000922: 4603 mov r3, r0
8000924: 80fb strh r3, [r7, #6]
uint8_t regValue = 0;
8000926: 2300 movs r3, #0
8000928: 73fb strb r3, [r7, #15]
regValue = (FT5336_G_MODE_INTERRUPT_POLLING & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT;
800092a: 2300 movs r3, #0
800092c: 73fb strb r3, [r7, #15]
/* Set interrupt polling mode in FT5336_GMODE_REG */
TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue);
800092e: 88fb ldrh r3, [r7, #6]
8000930: b2db uxtb r3, r3
8000932: 7bfa ldrb r2, [r7, #15]
8000934: 21a4 movs r1, #164 ; 0xa4
8000936: 4618 mov r0, r3
8000938: f002 f806 bl 8002948 <TS_IO_Write>
}
800093c: bf00 nop
800093e: 3710 adds r7, #16
8000940: 46bd mov sp, r7
8000942: bd80 pop {r7, pc}
08000944 <ft5336_TS_ITStatus>:
* @note : This feature is not applicable to FT5336.
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval TS interrupts status : always return 0 here
*/
uint8_t ft5336_TS_ITStatus(uint16_t DeviceAddr)
{
8000944: b480 push {r7}
8000946: b083 sub sp, #12
8000948: af00 add r7, sp, #0
800094a: 4603 mov r3, r0
800094c: 80fb strh r3, [r7, #6]
/* Always return 0 as feature not applicable to FT5336 */
return 0;
800094e: 2300 movs r3, #0
}
8000950: 4618 mov r0, r3
8000952: 370c adds r7, #12
8000954: 46bd mov sp, r7
8000956: f85d 7b04 ldr.w r7, [sp], #4
800095a: 4770 bx lr
0800095c <ft5336_TS_ClearIT>:
* @note : This feature is not applicable to FT5336.
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval None
*/
void ft5336_TS_ClearIT(uint16_t DeviceAddr)
{
800095c: b480 push {r7}
800095e: b083 sub sp, #12
8000960: af00 add r7, sp, #0
8000962: 4603 mov r3, r0
8000964: 80fb strh r3, [r7, #6]
/* Nothing to be done here for FT5336 */
}
8000966: bf00 nop
8000968: 370c adds r7, #12
800096a: 46bd mov sp, r7
800096c: f85d 7b04 ldr.w r7, [sp], #4
8000970: 4770 bx lr
08000972 <ft5336_TS_GetGestureID>:
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @param pGestureId : Pointer to get last touch gesture Identification.
* @retval None.
*/
void ft5336_TS_GetGestureID(uint16_t DeviceAddr, uint32_t * pGestureId)
{
8000972: b580 push {r7, lr}
8000974: b084 sub sp, #16
8000976: af00 add r7, sp, #0
8000978: 4603 mov r3, r0
800097a: 6039 str r1, [r7, #0]
800097c: 80fb strh r3, [r7, #6]
volatile uint8_t ucReadData = 0;
800097e: 2300 movs r3, #0
8000980: 73fb strb r3, [r7, #15]
ucReadData = TS_IO_Read(DeviceAddr, FT5336_GEST_ID_REG);
8000982: 88fb ldrh r3, [r7, #6]
8000984: b2db uxtb r3, r3
8000986: 2101 movs r1, #1
8000988: 4618 mov r0, r3
800098a: f001 fff7 bl 800297c <TS_IO_Read>
800098e: 4603 mov r3, r0
8000990: 73fb strb r3, [r7, #15]
* pGestureId = ucReadData;
8000992: 7bfb ldrb r3, [r7, #15]
8000994: b2db uxtb r3, r3
8000996: 461a mov r2, r3
8000998: 683b ldr r3, [r7, #0]
800099a: 601a str r2, [r3, #0]
}
800099c: bf00 nop
800099e: 3710 adds r7, #16
80009a0: 46bd mov sp, r7
80009a2: bd80 pop {r7, pc}
080009a4 <ft5336_TS_GetTouchInfo>:
void ft5336_TS_GetTouchInfo(uint16_t DeviceAddr,
uint32_t touchIdx,
uint32_t * pWeight,
uint32_t * pArea,
uint32_t * pEvent)
{
80009a4: b580 push {r7, lr}
80009a6: b086 sub sp, #24
80009a8: af00 add r7, sp, #0
80009aa: 60b9 str r1, [r7, #8]
80009ac: 607a str r2, [r7, #4]
80009ae: 603b str r3, [r7, #0]
80009b0: 4603 mov r3, r0
80009b2: 81fb strh r3, [r7, #14]
volatile uint8_t ucReadData = 0;
80009b4: 2300 movs r3, #0
80009b6: 753b strb r3, [r7, #20]
uint8_t regAddressXHigh = 0;
80009b8: 2300 movs r3, #0
80009ba: 75fb strb r3, [r7, #23]
uint8_t regAddressPWeight = 0;
80009bc: 2300 movs r3, #0
80009be: 75bb strb r3, [r7, #22]
uint8_t regAddressPMisc = 0;
80009c0: 2300 movs r3, #0
80009c2: 757b strb r3, [r7, #21]
if(touchIdx < ft5336_handle.currActiveTouchNb)
80009c4: 4b4d ldr r3, [pc, #308] ; (8000afc <ft5336_TS_GetTouchInfo+0x158>)
80009c6: 785b ldrb r3, [r3, #1]
80009c8: 461a mov r2, r3
80009ca: 68bb ldr r3, [r7, #8]
80009cc: 4293 cmp r3, r2
80009ce: f080 8090 bcs.w 8000af2 <ft5336_TS_GetTouchInfo+0x14e>
80009d2: 68bb ldr r3, [r7, #8]
80009d4: 2b09 cmp r3, #9
80009d6: d85d bhi.n 8000a94 <ft5336_TS_GetTouchInfo+0xf0>
80009d8: a201 add r2, pc, #4 ; (adr r2, 80009e0 <ft5336_TS_GetTouchInfo+0x3c>)
80009da: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80009de: bf00 nop
80009e0: 08000a09 .word 0x08000a09
80009e4: 08000a17 .word 0x08000a17
80009e8: 08000a25 .word 0x08000a25
80009ec: 08000a33 .word 0x08000a33
80009f0: 08000a41 .word 0x08000a41
80009f4: 08000a4f .word 0x08000a4f
80009f8: 08000a5d .word 0x08000a5d
80009fc: 08000a6b .word 0x08000a6b
8000a00: 08000a79 .word 0x08000a79
8000a04: 08000a87 .word 0x08000a87
{
switch(touchIdx)
{
case 0 :
regAddressXHigh = FT5336_P1_XH_REG;
8000a08: 2303 movs r3, #3
8000a0a: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P1_WEIGHT_REG;
8000a0c: 2307 movs r3, #7
8000a0e: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P1_MISC_REG;
8000a10: 2308 movs r3, #8
8000a12: 757b strb r3, [r7, #21]
break;
8000a14: e03f b.n 8000a96 <ft5336_TS_GetTouchInfo+0xf2>
case 1 :
regAddressXHigh = FT5336_P2_XH_REG;
8000a16: 2309 movs r3, #9
8000a18: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P2_WEIGHT_REG;
8000a1a: 230d movs r3, #13
8000a1c: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P2_MISC_REG;
8000a1e: 230e movs r3, #14
8000a20: 757b strb r3, [r7, #21]
break;
8000a22: e038 b.n 8000a96 <ft5336_TS_GetTouchInfo+0xf2>
case 2 :
regAddressXHigh = FT5336_P3_XH_REG;
8000a24: 230f movs r3, #15
8000a26: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P3_WEIGHT_REG;
8000a28: 2313 movs r3, #19
8000a2a: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P3_MISC_REG;
8000a2c: 2314 movs r3, #20
8000a2e: 757b strb r3, [r7, #21]
break;
8000a30: e031 b.n 8000a96 <ft5336_TS_GetTouchInfo+0xf2>
case 3 :
regAddressXHigh = FT5336_P4_XH_REG;
8000a32: 2315 movs r3, #21
8000a34: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P4_WEIGHT_REG;
8000a36: 2319 movs r3, #25
8000a38: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P4_MISC_REG;
8000a3a: 231a movs r3, #26
8000a3c: 757b strb r3, [r7, #21]
break;
8000a3e: e02a b.n 8000a96 <ft5336_TS_GetTouchInfo+0xf2>
case 4 :
regAddressXHigh = FT5336_P5_XH_REG;
8000a40: 231b movs r3, #27
8000a42: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P5_WEIGHT_REG;
8000a44: 231f movs r3, #31
8000a46: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P5_MISC_REG;
8000a48: 2320 movs r3, #32
8000a4a: 757b strb r3, [r7, #21]
break;
8000a4c: e023 b.n 8000a96 <ft5336_TS_GetTouchInfo+0xf2>
case 5 :
regAddressXHigh = FT5336_P6_XH_REG;
8000a4e: 2321 movs r3, #33 ; 0x21
8000a50: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P6_WEIGHT_REG;
8000a52: 2325 movs r3, #37 ; 0x25
8000a54: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P6_MISC_REG;
8000a56: 2326 movs r3, #38 ; 0x26
8000a58: 757b strb r3, [r7, #21]
break;
8000a5a: e01c b.n 8000a96 <ft5336_TS_GetTouchInfo+0xf2>
case 6 :
regAddressXHigh = FT5336_P7_XH_REG;
8000a5c: 2327 movs r3, #39 ; 0x27
8000a5e: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P7_WEIGHT_REG;
8000a60: 232b movs r3, #43 ; 0x2b
8000a62: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P7_MISC_REG;
8000a64: 232c movs r3, #44 ; 0x2c
8000a66: 757b strb r3, [r7, #21]
break;
8000a68: e015 b.n 8000a96 <ft5336_TS_GetTouchInfo+0xf2>
case 7 :
regAddressXHigh = FT5336_P8_XH_REG;
8000a6a: 232d movs r3, #45 ; 0x2d
8000a6c: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P8_WEIGHT_REG;
8000a6e: 2331 movs r3, #49 ; 0x31
8000a70: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P8_MISC_REG;
8000a72: 2332 movs r3, #50 ; 0x32
8000a74: 757b strb r3, [r7, #21]
break;
8000a76: e00e b.n 8000a96 <ft5336_TS_GetTouchInfo+0xf2>
case 8 :
regAddressXHigh = FT5336_P9_XH_REG;
8000a78: 2333 movs r3, #51 ; 0x33
8000a7a: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P9_WEIGHT_REG;
8000a7c: 2337 movs r3, #55 ; 0x37
8000a7e: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P9_MISC_REG;
8000a80: 2338 movs r3, #56 ; 0x38
8000a82: 757b strb r3, [r7, #21]
break;
8000a84: e007 b.n 8000a96 <ft5336_TS_GetTouchInfo+0xf2>
case 9 :
regAddressXHigh = FT5336_P10_XH_REG;
8000a86: 2339 movs r3, #57 ; 0x39
8000a88: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P10_WEIGHT_REG;
8000a8a: 233d movs r3, #61 ; 0x3d
8000a8c: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P10_MISC_REG;
8000a8e: 233e movs r3, #62 ; 0x3e
8000a90: 757b strb r3, [r7, #21]
break;
8000a92: e000 b.n 8000a96 <ft5336_TS_GetTouchInfo+0xf2>
default :
break;
8000a94: bf00 nop
} /* end switch(touchIdx) */
/* Read Event Id of touch index */
ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh);
8000a96: 89fb ldrh r3, [r7, #14]
8000a98: b2db uxtb r3, r3
8000a9a: 7dfa ldrb r2, [r7, #23]
8000a9c: 4611 mov r1, r2
8000a9e: 4618 mov r0, r3
8000aa0: f001 ff6c bl 800297c <TS_IO_Read>
8000aa4: 4603 mov r3, r0
8000aa6: 753b strb r3, [r7, #20]
* pEvent = (ucReadData & FT5336_TOUCH_EVT_FLAG_MASK) >> FT5336_TOUCH_EVT_FLAG_SHIFT;
8000aa8: 7d3b ldrb r3, [r7, #20]
8000aaa: b2db uxtb r3, r3
8000aac: 119b asrs r3, r3, #6
8000aae: f003 0203 and.w r2, r3, #3
8000ab2: 6a3b ldr r3, [r7, #32]
8000ab4: 601a str r2, [r3, #0]
/* Read weight of touch index */
ucReadData = TS_IO_Read(DeviceAddr, regAddressPWeight);
8000ab6: 89fb ldrh r3, [r7, #14]
8000ab8: b2db uxtb r3, r3
8000aba: 7dba ldrb r2, [r7, #22]
8000abc: 4611 mov r1, r2
8000abe: 4618 mov r0, r3
8000ac0: f001 ff5c bl 800297c <TS_IO_Read>
8000ac4: 4603 mov r3, r0
8000ac6: 753b strb r3, [r7, #20]
* pWeight = (ucReadData & FT5336_TOUCH_WEIGHT_MASK) >> FT5336_TOUCH_WEIGHT_SHIFT;
8000ac8: 7d3b ldrb r3, [r7, #20]
8000aca: b2db uxtb r3, r3
8000acc: 461a mov r2, r3
8000ace: 687b ldr r3, [r7, #4]
8000ad0: 601a str r2, [r3, #0]
/* Read area of touch index */
ucReadData = TS_IO_Read(DeviceAddr, regAddressPMisc);
8000ad2: 89fb ldrh r3, [r7, #14]
8000ad4: b2db uxtb r3, r3
8000ad6: 7d7a ldrb r2, [r7, #21]
8000ad8: 4611 mov r1, r2
8000ada: 4618 mov r0, r3
8000adc: f001 ff4e bl 800297c <TS_IO_Read>
8000ae0: 4603 mov r3, r0
8000ae2: 753b strb r3, [r7, #20]
* pArea = (ucReadData & FT5336_TOUCH_AREA_MASK) >> FT5336_TOUCH_AREA_SHIFT;
8000ae4: 7d3b ldrb r3, [r7, #20]
8000ae6: b2db uxtb r3, r3
8000ae8: 111b asrs r3, r3, #4
8000aea: f003 0204 and.w r2, r3, #4
8000aee: 683b ldr r3, [r7, #0]
8000af0: 601a str r2, [r3, #0]
} /* of if(touchIdx < ft5336_handle.currActiveTouchNb) */
}
8000af2: bf00 nop
8000af4: 3718 adds r7, #24
8000af6: 46bd mov sp, r7
8000af8: bd80 pop {r7, pc}
8000afa: bf00 nop
8000afc: 20000350 .word 0x20000350
08000b00 <ft5336_Get_I2C_InitializedStatus>:
* @brief Return the status of I2C was initialized or not.
* @param None.
* @retval : I2C initialization status.
*/
static uint8_t ft5336_Get_I2C_InitializedStatus(void)
{
8000b00: b480 push {r7}
8000b02: af00 add r7, sp, #0
return(ft5336_handle.i2cInitialized);
8000b04: 4b03 ldr r3, [pc, #12] ; (8000b14 <ft5336_Get_I2C_InitializedStatus+0x14>)
8000b06: 781b ldrb r3, [r3, #0]
}
8000b08: 4618 mov r0, r3
8000b0a: 46bd mov sp, r7
8000b0c: f85d 7b04 ldr.w r7, [sp], #4
8000b10: 4770 bx lr
8000b12: bf00 nop
8000b14: 20000350 .word 0x20000350
08000b18 <ft5336_I2C_InitializeIfRequired>:
* @brief I2C initialize if needed.
* @param None.
* @retval : None.
*/
static void ft5336_I2C_InitializeIfRequired(void)
{
8000b18: b580 push {r7, lr}
8000b1a: af00 add r7, sp, #0
if(ft5336_Get_I2C_InitializedStatus() == FT5336_I2C_NOT_INITIALIZED)
8000b1c: f7ff fff0 bl 8000b00 <ft5336_Get_I2C_InitializedStatus>
8000b20: 4603 mov r3, r0
8000b22: 2b00 cmp r3, #0
8000b24: d104 bne.n 8000b30 <ft5336_I2C_InitializeIfRequired+0x18>
{
/* Initialize TS IO BUS layer (I2C) */
TS_IO_Init();
8000b26: f001 ff05 bl 8002934 <TS_IO_Init>
/* Set state to initialized */
ft5336_handle.i2cInitialized = FT5336_I2C_INITIALIZED;
8000b2a: 4b02 ldr r3, [pc, #8] ; (8000b34 <ft5336_I2C_InitializeIfRequired+0x1c>)
8000b2c: 2201 movs r2, #1
8000b2e: 701a strb r2, [r3, #0]
}
}
8000b30: bf00 nop
8000b32: bd80 pop {r7, pc}
8000b34: 20000350 .word 0x20000350
08000b38 <ft5336_TS_Configure>:
* @brief Basic static configuration of TouchScreen
* @param DeviceAddr: FT5336 Device address for communication on I2C Bus.
* @retval Status FT5336_STATUS_OK or FT5336_STATUS_NOT_OK.
*/
static uint32_t ft5336_TS_Configure(uint16_t DeviceAddr)
{
8000b38: b480 push {r7}
8000b3a: b085 sub sp, #20
8000b3c: af00 add r7, sp, #0
8000b3e: 4603 mov r3, r0
8000b40: 80fb strh r3, [r7, #6]
uint32_t status = FT5336_STATUS_OK;
8000b42: 2300 movs r3, #0
8000b44: 60fb str r3, [r7, #12]
/* Nothing special to be done for FT5336 */
return(status);
8000b46: 68fb ldr r3, [r7, #12]
}
8000b48: 4618 mov r0, r3
8000b4a: 3714 adds r7, #20
8000b4c: 46bd mov sp, r7
8000b4e: f85d 7b04 ldr.w r7, [sp], #4
8000b52: 4770 bx lr
08000b54 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000b54: b5b0 push {r4, r5, r7, lr}
8000b56: b0b2 sub sp, #200 ; 0xc8
8000b58: af00 add r7, sp, #0
/* USER CODE BEGIN 1 */
static TS_StateTypeDef TS_State;
ADC_ChannelConfTypeDef sConfig = {0};
8000b5a: f107 03b8 add.w r3, r7, #184 ; 0xb8
8000b5e: 2200 movs r2, #0
8000b60: 601a str r2, [r3, #0]
8000b62: 605a str r2, [r3, #4]
8000b64: 609a str r2, [r3, #8]
8000b66: 60da str r2, [r3, #12]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000b68: 2301 movs r3, #1
8000b6a: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8000b6e: 2300 movs r3, #0
8000b70: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000b74: f003 fe0b bl 800478e <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000b78: f000 f94a bl 8000e10 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000b7c: f000 fe1a bl 80017b4 <MX_GPIO_Init>
MX_ADC3_Init();
8000b80: f000 fa3c bl 8000ffc <MX_ADC3_Init>
MX_LTDC_Init();
8000b84: f000 fb0a bl 800119c <MX_LTDC_Init>
MX_TIM1_Init();
8000b88: f000 fb9e bl 80012c8 <MX_TIM1_Init>
MX_TIM2_Init();
8000b8c: f000 fbf0 bl 8001370 <MX_TIM2_Init>
MX_TIM3_Init();
8000b90: f000 fc3c bl 800140c <MX_TIM3_Init>
MX_TIM5_Init();
8000b94: f000 fcc8 bl 8001528 <MX_TIM5_Init>
MX_TIM8_Init();
8000b98: f000 fd14 bl 80015c4 <MX_TIM8_Init>
MX_DAC_Init();
8000b9c: f000 faa2 bl 80010e4 <MX_DAC_Init>
MX_FMC_Init();
8000ba0: f000 fdba bl 8001718 <MX_FMC_Init>
MX_DMA2D_Init();
8000ba4: f000 fac8 bl 8001138 <MX_DMA2D_Init>
MX_CRC_Init();
8000ba8: f000 fa7a bl 80010a0 <MX_CRC_Init>
MX_RNG_Init();
8000bac: f000 fb78 bl 80012a0 <MX_RNG_Init>
MX_ADC1_Init();
8000bb0: f000 f9d2 bl 8000f58 <MX_ADC1_Init>
/* USER CODE BEGIN 2 */
BSP_LCD_Init();
8000bb4: f001 ff0c bl 80029d0 <BSP_LCD_Init>
BSP_LCD_LayerDefaultInit(0, LCD_FB_START_ADDRESS);
8000bb8: f04f 4140 mov.w r1, #3221225472 ; 0xc0000000
8000bbc: 2000 movs r0, #0
8000bbe: f001 ff9f bl 8002b00 <BSP_LCD_LayerDefaultInit>
BSP_LCD_LayerDefaultInit(1,
LCD_FB_START_ADDRESS + BSP_LCD_GetXSize() * BSP_LCD_GetYSize() * 4);
8000bc2: f001 ff75 bl 8002ab0 <BSP_LCD_GetXSize>
8000bc6: 4604 mov r4, r0
8000bc8: f001 ff86 bl 8002ad8 <BSP_LCD_GetYSize>
8000bcc: 4603 mov r3, r0
8000bce: fb03 f304 mul.w r3, r3, r4
8000bd2: f103 5340 add.w r3, r3, #805306368 ; 0x30000000
BSP_LCD_LayerDefaultInit(1,
8000bd6: 009b lsls r3, r3, #2
8000bd8: 4619 mov r1, r3
8000bda: 2001 movs r0, #1
8000bdc: f001 ff90 bl 8002b00 <BSP_LCD_LayerDefaultInit>
BSP_LCD_DisplayOn();
8000be0: f002 fb1c bl 800321c <BSP_LCD_DisplayOn>
BSP_LCD_SelectLayer(1);
8000be4: 2001 movs r0, #1
8000be6: f001 ffeb bl 8002bc0 <BSP_LCD_SelectLayer>
BSP_LCD_Clear(LCD_COLOR_BLACK);
8000bea: f04f 407f mov.w r0, #4278190080 ; 0xff000000
8000bee: f002 f843 bl 8002c78 <BSP_LCD_Clear>
BSP_LCD_SetFont(&Font12);
8000bf2: 4871 ldr r0, [pc, #452] ; (8000db8 <main+0x264>)
8000bf4: f002 f826 bl 8002c44 <BSP_LCD_SetFont>
BSP_LCD_SetTextColor(LCD_COLOR_BLUE);
8000bf8: 4870 ldr r0, [pc, #448] ; (8000dbc <main+0x268>)
8000bfa: f001 fff1 bl 8002be0 <BSP_LCD_SetTextColor>
BSP_LCD_SetBackColor(LCD_COLOR_BLACK);
8000bfe: f04f 407f mov.w r0, #4278190080 ; 0xff000000
8000c02: f002 f805 bl 8002c10 <BSP_LCD_SetBackColor>
BSP_TS_Init(BSP_LCD_GetXSize(), BSP_LCD_GetYSize());
8000c06: f001 ff53 bl 8002ab0 <BSP_LCD_GetXSize>
8000c0a: 4603 mov r3, r0
8000c0c: b29c uxth r4, r3
8000c0e: f001 ff63 bl 8002ad8 <BSP_LCD_GetYSize>
8000c12: 4603 mov r3, r0
8000c14: b29b uxth r3, r3
8000c16: 4619 mov r1, r3
8000c18: 4620 mov r0, r4
8000c1a: f002 fe15 bl 8003848 <BSP_TS_Init>
/* USER CODE END 2 */
/* Create the mutex(es) */
/* definition and creation of MutexLCD */
osMutexDef(MutexLCD);
8000c1e: 2300 movs r3, #0
8000c20: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
8000c24: 2300 movs r3, #0
8000c26: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
MutexLCDHandle = osMutexCreate(osMutex(MutexLCD));
8000c2a: f107 03b0 add.w r3, r7, #176 ; 0xb0
8000c2e: 4618 mov r0, r3
8000c30: f00a fed1 bl 800b9d6 <osMutexCreate>
8000c34: 4603 mov r3, r0
8000c36: 4a62 ldr r2, [pc, #392] ; (8000dc0 <main+0x26c>)
8000c38: 6013 str r3, [r2, #0]
/* start timers, add new ones, ... */
/* USER CODE END RTOS_TIMERS */
/* Create the queue(s) */
/* definition and creation of Queue_F */
osMessageQDef(Queue_F, 1, uint8_t);
8000c3a: 4b62 ldr r3, [pc, #392] ; (8000dc4 <main+0x270>)
8000c3c: f107 04a0 add.w r4, r7, #160 ; 0xa0
8000c40: cb0f ldmia r3, {r0, r1, r2, r3}
8000c42: e884 000f stmia.w r4, {r0, r1, r2, r3}
Queue_FHandle = osMessageCreate(osMessageQ(Queue_F), NULL);
8000c46: f107 03a0 add.w r3, r7, #160 ; 0xa0
8000c4a: 2100 movs r1, #0
8000c4c: 4618 mov r0, r3
8000c4e: f00b f823 bl 800bc98 <osMessageCreate>
8000c52: 4603 mov r3, r0
8000c54: 4a5c ldr r2, [pc, #368] ; (8000dc8 <main+0x274>)
8000c56: 6013 str r3, [r2, #0]
/* definition and creation of Queue_N */
osMessageQDef(Queue_N, 8, struct Missile);
8000c58: 4b5c ldr r3, [pc, #368] ; (8000dcc <main+0x278>)
8000c5a: f107 0490 add.w r4, r7, #144 ; 0x90
8000c5e: cb0f ldmia r3, {r0, r1, r2, r3}
8000c60: e884 000f stmia.w r4, {r0, r1, r2, r3}
Queue_NHandle = osMessageCreate(osMessageQ(Queue_N), NULL);
8000c64: f107 0390 add.w r3, r7, #144 ; 0x90
8000c68: 2100 movs r1, #0
8000c6a: 4618 mov r0, r3
8000c6c: f00b f814 bl 800bc98 <osMessageCreate>
8000c70: 4603 mov r3, r0
8000c72: 4a57 ldr r2, [pc, #348] ; (8000dd0 <main+0x27c>)
8000c74: 6013 str r3, [r2, #0]
/* definition and creation of Queue_J */
osMessageQDef(Queue_J, 8, uint8_t);
8000c76: 4b57 ldr r3, [pc, #348] ; (8000dd4 <main+0x280>)
8000c78: f107 0480 add.w r4, r7, #128 ; 0x80
8000c7c: cb0f ldmia r3, {r0, r1, r2, r3}
8000c7e: e884 000f stmia.w r4, {r0, r1, r2, r3}
Queue_JHandle = osMessageCreate(osMessageQ(Queue_J), NULL);
8000c82: f107 0380 add.w r3, r7, #128 ; 0x80
8000c86: 2100 movs r1, #0
8000c88: 4618 mov r0, r3
8000c8a: f00b f805 bl 800bc98 <osMessageCreate>
8000c8e: 4603 mov r3, r0
8000c90: 4a51 ldr r2, [pc, #324] ; (8000dd8 <main+0x284>)
8000c92: 6013 str r3, [r2, #0]
/* definition and creation of Queue_E */
osMessageQDef(Queue_E, 8, struct Collision);
8000c94: 4b51 ldr r3, [pc, #324] ; (8000ddc <main+0x288>)
8000c96: f107 0470 add.w r4, r7, #112 ; 0x70
8000c9a: cb0f ldmia r3, {r0, r1, r2, r3}
8000c9c: e884 000f stmia.w r4, {r0, r1, r2, r3}
Queue_EHandle = osMessageCreate(osMessageQ(Queue_E), NULL);
8000ca0: f107 0370 add.w r3, r7, #112 ; 0x70
8000ca4: 2100 movs r1, #0
8000ca6: 4618 mov r0, r3
8000ca8: f00a fff6 bl 800bc98 <osMessageCreate>
8000cac: 4603 mov r3, r0
8000cae: 4a4c ldr r2, [pc, #304] ; (8000de0 <main+0x28c>)
8000cb0: 6013 str r3, [r2, #0]
/* add queues, ... */
/* USER CODE END RTOS_QUEUES */
/* Create the thread(s) */
/* definition and creation of GameMaster */
osThreadDef(GameMaster, f_GameMaster, osPriorityNormal, 0, 128);
8000cb2: 4b4c ldr r3, [pc, #304] ; (8000de4 <main+0x290>)
8000cb4: f107 0454 add.w r4, r7, #84 ; 0x54
8000cb8: 461d mov r5, r3
8000cba: cd0f ldmia r5!, {r0, r1, r2, r3}
8000cbc: c40f stmia r4!, {r0, r1, r2, r3}
8000cbe: e895 0007 ldmia.w r5, {r0, r1, r2}
8000cc2: e884 0007 stmia.w r4, {r0, r1, r2}
GameMasterHandle = osThreadCreate(osThread(GameMaster), NULL);
8000cc6: f107 0354 add.w r3, r7, #84 ; 0x54
8000cca: 2100 movs r1, #0
8000ccc: 4618 mov r0, r3
8000cce: f00a fe22 bl 800b916 <osThreadCreate>
8000cd2: 4603 mov r3, r0
8000cd4: 4a44 ldr r2, [pc, #272] ; (8000de8 <main+0x294>)
8000cd6: 6013 str r3, [r2, #0]
/* definition and creation of Joueur_1 */
osThreadDef(Joueur_1, f_Joueur_1, osPriorityNormal, 0, 128);
8000cd8: 4b44 ldr r3, [pc, #272] ; (8000dec <main+0x298>)
8000cda: f107 0438 add.w r4, r7, #56 ; 0x38
8000cde: 461d mov r5, r3
8000ce0: cd0f ldmia r5!, {r0, r1, r2, r3}
8000ce2: c40f stmia r4!, {r0, r1, r2, r3}
8000ce4: e895 0007 ldmia.w r5, {r0, r1, r2}
8000ce8: e884 0007 stmia.w r4, {r0, r1, r2}
Joueur_1Handle = osThreadCreate(osThread(Joueur_1), NULL);
8000cec: f107 0338 add.w r3, r7, #56 ; 0x38
8000cf0: 2100 movs r1, #0
8000cf2: 4618 mov r0, r3
8000cf4: f00a fe0f bl 800b916 <osThreadCreate>
8000cf8: 4603 mov r3, r0
8000cfa: 4a3d ldr r2, [pc, #244] ; (8000df0 <main+0x29c>)
8000cfc: 6013 str r3, [r2, #0]
/* definition and creation of Block_Enemie */
osThreadDef(Block_Enemie, f_block_enemie, osPriorityIdle, 0, 128);
8000cfe: 4b3d ldr r3, [pc, #244] ; (8000df4 <main+0x2a0>)
8000d00: f107 041c add.w r4, r7, #28
8000d04: 461d mov r5, r3
8000d06: cd0f ldmia r5!, {r0, r1, r2, r3}
8000d08: c40f stmia r4!, {r0, r1, r2, r3}
8000d0a: e895 0007 ldmia.w r5, {r0, r1, r2}
8000d0e: e884 0007 stmia.w r4, {r0, r1, r2}
Block_EnemieHandle = osThreadCreate(osThread(Block_Enemie), NULL);
8000d12: f107 031c add.w r3, r7, #28
8000d16: 2100 movs r1, #0
8000d18: 4618 mov r0, r3
8000d1a: f00a fdfc bl 800b916 <osThreadCreate>
8000d1e: 4603 mov r3, r0
8000d20: 4a35 ldr r2, [pc, #212] ; (8000df8 <main+0x2a4>)
8000d22: 6013 str r3, [r2, #0]
/* definition and creation of Projectile */
osThreadDef(Projectile, f_projectile, osPriorityNormal, 0, 128);
8000d24: 4b35 ldr r3, [pc, #212] ; (8000dfc <main+0x2a8>)
8000d26: 463c mov r4, r7
8000d28: 461d mov r5, r3
8000d2a: cd0f ldmia r5!, {r0, r1, r2, r3}
8000d2c: c40f stmia r4!, {r0, r1, r2, r3}
8000d2e: e895 0007 ldmia.w r5, {r0, r1, r2}
8000d32: e884 0007 stmia.w r4, {r0, r1, r2}
ProjectileHandle = osThreadCreate(osThread(Projectile), NULL);
8000d36: 463b mov r3, r7
8000d38: 2100 movs r1, #0
8000d3a: 4618 mov r0, r3
8000d3c: f00a fdeb bl 800b916 <osThreadCreate>
8000d40: 4603 mov r3, r0
8000d42: 4a2f ldr r2, [pc, #188] ; (8000e00 <main+0x2ac>)
8000d44: 6013 str r3, [r2, #0]
/* USER CODE BEGIN RTOS_THREADS */
/* add threads, ... */
/* USER CODE END RTOS_THREADS */
/* Start scheduler */
osKernelStart();
8000d46: f00a fdcf bl 800b8e8 <osKernelStart>
// sprintf(text, "BP1 : %d", HAL_GPIO_ReadPin(BP1_GPIO_Port, BP1_Pin));
// BSP_LCD_DisplayStringAtLine(5, (uint8_t *)text);
;
sConfig.Channel = ADC_CHANNEL_7;
8000d4a: 2307 movs r3, #7
8000d4c: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
8000d50: f107 03b8 add.w r3, r7, #184 ; 0xb8
8000d54: 4619 mov r1, r3
8000d56: 482b ldr r0, [pc, #172] ; (8000e04 <main+0x2b0>)
8000d58: f003 ff14 bl 8004b84 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8000d5c: 4829 ldr r0, [pc, #164] ; (8000e04 <main+0x2b0>)
8000d5e: f003 fdab bl 80048b8 <HAL_ADC_Start>
sConfig.Channel = ADC_CHANNEL_6;
8000d62: 2306 movs r3, #6
8000d64: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
8000d68: f107 03b8 add.w r3, r7, #184 ; 0xb8
8000d6c: 4619 mov r1, r3
8000d6e: 4825 ldr r0, [pc, #148] ; (8000e04 <main+0x2b0>)
8000d70: f003 ff08 bl 8004b84 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8000d74: 4823 ldr r0, [pc, #140] ; (8000e04 <main+0x2b0>)
8000d76: f003 fd9f bl 80048b8 <HAL_ADC_Start>
sConfig.Channel = ADC_CHANNEL_8;
8000d7a: 2308 movs r3, #8
8000d7c: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
8000d80: f107 03b8 add.w r3, r7, #184 ; 0xb8
8000d84: 4619 mov r1, r3
8000d86: 481f ldr r0, [pc, #124] ; (8000e04 <main+0x2b0>)
8000d88: f003 fefc bl 8004b84 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8000d8c: 481d ldr r0, [pc, #116] ; (8000e04 <main+0x2b0>)
8000d8e: f003 fd93 bl 80048b8 <HAL_ADC_Start>
HAL_ADC_Start(&hadc1);
8000d92: 481d ldr r0, [pc, #116] ; (8000e08 <main+0x2b4>)
8000d94: f003 fd90 bl 80048b8 <HAL_ADC_Start>
BSP_TS_GetState(&TS_State);
8000d98: 481c ldr r0, [pc, #112] ; (8000e0c <main+0x2b8>)
8000d9a: f002 fd95 bl 80038c8 <BSP_TS_GetState>
if (TS_State.touchDetected)
8000d9e: 4b1b ldr r3, [pc, #108] ; (8000e0c <main+0x2b8>)
8000da0: 781b ldrb r3, [r3, #0]
8000da2: 2b00 cmp r3, #0
8000da4: d0d1 beq.n 8000d4a <main+0x1f6>
{
BSP_LCD_FillCircle(TS_State.touchX[0], TS_State.touchY[0], 4);
8000da6: 4b19 ldr r3, [pc, #100] ; (8000e0c <main+0x2b8>)
8000da8: 885b ldrh r3, [r3, #2]
8000daa: 4a18 ldr r2, [pc, #96] ; (8000e0c <main+0x2b8>)
8000dac: 8991 ldrh r1, [r2, #12]
8000dae: 2204 movs r2, #4
8000db0: 4618 mov r0, r3
8000db2: f002 f993 bl 80030dc <BSP_LCD_FillCircle>
sConfig.Channel = ADC_CHANNEL_7;
8000db6: e7c8 b.n 8000d4a <main+0x1f6>
8000db8: 2000004c .word 0x2000004c
8000dbc: ff0000ff .word 0xff0000ff
8000dc0: 20008934 .word 0x20008934
8000dc4: 0801c044 .word 0x0801c044
8000dc8: 20008ac0 .word 0x20008ac0
8000dcc: 0801c054 .word 0x0801c054
8000dd0: 20008abc .word 0x20008abc
8000dd4: 0801c064 .word 0x0801c064
8000dd8: 200088bc .word 0x200088bc
8000ddc: 0801c074 .word 0x0801c074
8000de0: 20008e68 .word 0x20008e68
8000de4: 0801c084 .word 0x0801c084
8000de8: 20008b38 .word 0x20008b38
8000dec: 0801c0a0 .word 0x0801c0a0
8000df0: 200088e4 .word 0x200088e4
8000df4: 0801c0bc .word 0x0801c0bc
8000df8: 20008ea0 .word 0x20008ea0
8000dfc: 0801c0d8 .word 0x0801c0d8
8000e00: 20008ad8 .word 0x20008ad8
8000e04: 20008a74 .word 0x20008a74
8000e08: 20008a2c .word 0x20008a2c
8000e0c: 20000358 .word 0x20000358
08000e10 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000e10: b580 push {r7, lr}
8000e12: b0b4 sub sp, #208 ; 0xd0
8000e14: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000e16: f107 03a0 add.w r3, r7, #160 ; 0xa0
8000e1a: 2230 movs r2, #48 ; 0x30
8000e1c: 2100 movs r1, #0
8000e1e: 4618 mov r0, r3
8000e20: f01a f8c8 bl 801afb4 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000e24: f107 038c add.w r3, r7, #140 ; 0x8c
8000e28: 2200 movs r2, #0
8000e2a: 601a str r2, [r3, #0]
8000e2c: 605a str r2, [r3, #4]
8000e2e: 609a str r2, [r3, #8]
8000e30: 60da str r2, [r3, #12]
8000e32: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8000e34: f107 0308 add.w r3, r7, #8
8000e38: 2284 movs r2, #132 ; 0x84
8000e3a: 2100 movs r1, #0
8000e3c: 4618 mov r0, r3
8000e3e: f01a f8b9 bl 801afb4 <memset>
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
8000e42: f007 fbc7 bl 80085d4 <HAL_PWR_EnableBkUpAccess>
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8000e46: 4b41 ldr r3, [pc, #260] ; (8000f4c <SystemClock_Config+0x13c>)
8000e48: 6c1b ldr r3, [r3, #64] ; 0x40
8000e4a: 4a40 ldr r2, [pc, #256] ; (8000f4c <SystemClock_Config+0x13c>)
8000e4c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000e50: 6413 str r3, [r2, #64] ; 0x40
8000e52: 4b3e ldr r3, [pc, #248] ; (8000f4c <SystemClock_Config+0x13c>)
8000e54: 6c1b ldr r3, [r3, #64] ; 0x40
8000e56: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000e5a: 607b str r3, [r7, #4]
8000e5c: 687b ldr r3, [r7, #4]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000e5e: 4b3c ldr r3, [pc, #240] ; (8000f50 <SystemClock_Config+0x140>)
8000e60: 681b ldr r3, [r3, #0]
8000e62: 4a3b ldr r2, [pc, #236] ; (8000f50 <SystemClock_Config+0x140>)
8000e64: f443 4340 orr.w r3, r3, #49152 ; 0xc000
8000e68: 6013 str r3, [r2, #0]
8000e6a: 4b39 ldr r3, [pc, #228] ; (8000f50 <SystemClock_Config+0x140>)
8000e6c: 681b ldr r3, [r3, #0]
8000e6e: f403 4340 and.w r3, r3, #49152 ; 0xc000
8000e72: 603b str r3, [r7, #0]
8000e74: 683b ldr r3, [r7, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000e76: 2301 movs r3, #1
8000e78: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8000e7c: f44f 3380 mov.w r3, #65536 ; 0x10000
8000e80: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000e84: 2302 movs r3, #2
8000e86: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000e8a: f44f 0380 mov.w r3, #4194304 ; 0x400000
8000e8e: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
RCC_OscInitStruct.PLL.PLLM = 25;
8000e92: 2319 movs r3, #25
8000e94: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
RCC_OscInitStruct.PLL.PLLN = 400;
8000e98: f44f 73c8 mov.w r3, #400 ; 0x190
8000e9c: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000ea0: 2302 movs r3, #2
8000ea2: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
RCC_OscInitStruct.PLL.PLLQ = 9;
8000ea6: 2309 movs r3, #9
8000ea8: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000eac: f107 03a0 add.w r3, r7, #160 ; 0xa0
8000eb0: 4618 mov r0, r3
8000eb2: f007 fbef bl 8008694 <HAL_RCC_OscConfig>
8000eb6: 4603 mov r3, r0
8000eb8: 2b00 cmp r3, #0
8000eba: d001 beq.n 8000ec0 <SystemClock_Config+0xb0>
{
Error_Handler();
8000ebc: f001 fbde bl 800267c <Error_Handler>
}
/** Activate the Over-Drive mode
*/
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
8000ec0: f007 fb98 bl 80085f4 <HAL_PWREx_EnableOverDrive>
8000ec4: 4603 mov r3, r0
8000ec6: 2b00 cmp r3, #0
8000ec8: d001 beq.n 8000ece <SystemClock_Config+0xbe>
{
Error_Handler();
8000eca: f001 fbd7 bl 800267c <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000ece: 230f movs r3, #15
8000ed0: f8c7 308c str.w r3, [r7, #140] ; 0x8c
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000ed4: 2302 movs r3, #2
8000ed6: f8c7 3090 str.w r3, [r7, #144] ; 0x90
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000eda: 2300 movs r3, #0
8000edc: f8c7 3094 str.w r3, [r7, #148] ; 0x94
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
8000ee0: f44f 53a0 mov.w r3, #5120 ; 0x1400
8000ee4: f8c7 3098 str.w r3, [r7, #152] ; 0x98
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
8000ee8: f44f 5380 mov.w r3, #4096 ; 0x1000
8000eec: f8c7 309c str.w r3, [r7, #156] ; 0x9c
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK)
8000ef0: f107 038c add.w r3, r7, #140 ; 0x8c
8000ef4: 2106 movs r1, #6
8000ef6: 4618 mov r0, r3
8000ef8: f007 fe70 bl 8008bdc <HAL_RCC_ClockConfig>
8000efc: 4603 mov r3, r0
8000efe: 2b00 cmp r3, #0
8000f00: d001 beq.n 8000f06 <SystemClock_Config+0xf6>
{
Error_Handler();
8000f02: f001 fbbb bl 800267c <Error_Handler>
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_CLK48;
8000f06: 4b13 ldr r3, [pc, #76] ; (8000f54 <SystemClock_Config+0x144>)
8000f08: 60bb str r3, [r7, #8]
PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
8000f0a: f44f 73c0 mov.w r3, #384 ; 0x180
8000f0e: 61fb str r3, [r7, #28]
PeriphClkInitStruct.PLLSAI.PLLSAIR = 5;
8000f10: 2305 movs r3, #5
8000f12: 627b str r3, [r7, #36] ; 0x24
PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2;
8000f14: 2302 movs r3, #2
8000f16: 623b str r3, [r7, #32]
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
8000f18: 2303 movs r3, #3
8000f1a: 62bb str r3, [r7, #40] ; 0x28
PeriphClkInitStruct.PLLSAIDivQ = 1;
8000f1c: 2301 movs r3, #1
8000f1e: 633b str r3, [r7, #48] ; 0x30
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8;
8000f20: f44f 3300 mov.w r3, #131072 ; 0x20000
8000f24: 637b str r3, [r7, #52] ; 0x34
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
8000f26: f04f 6300 mov.w r3, #134217728 ; 0x8000000
8000f2a: f8c7 3084 str.w r3, [r7, #132] ; 0x84
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8000f2e: f107 0308 add.w r3, r7, #8
8000f32: 4618 mov r0, r3
8000f34: f008 f846 bl 8008fc4 <HAL_RCCEx_PeriphCLKConfig>
8000f38: 4603 mov r3, r0
8000f3a: 2b00 cmp r3, #0
8000f3c: d001 beq.n 8000f42 <SystemClock_Config+0x132>
{
Error_Handler();
8000f3e: f001 fb9d bl 800267c <Error_Handler>
}
}
8000f42: bf00 nop
8000f44: 37d0 adds r7, #208 ; 0xd0
8000f46: 46bd mov sp, r7
8000f48: bd80 pop {r7, pc}
8000f4a: bf00 nop
8000f4c: 40023800 .word 0x40023800
8000f50: 40007000 .word 0x40007000
8000f54: 00200008 .word 0x00200008
08000f58 <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
8000f58: b580 push {r7, lr}
8000f5a: b084 sub sp, #16
8000f5c: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8000f5e: 463b mov r3, r7
8000f60: 2200 movs r2, #0
8000f62: 601a str r2, [r3, #0]
8000f64: 605a str r2, [r3, #4]
8000f66: 609a str r2, [r3, #8]
8000f68: 60da str r2, [r3, #12]
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc1.Instance = ADC1;
8000f6a: 4b21 ldr r3, [pc, #132] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000f6c: 4a21 ldr r2, [pc, #132] ; (8000ff4 <MX_ADC1_Init+0x9c>)
8000f6e: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
8000f70: 4b1f ldr r3, [pc, #124] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000f72: f44f 3280 mov.w r2, #65536 ; 0x10000
8000f76: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
8000f78: 4b1d ldr r3, [pc, #116] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000f7a: 2200 movs r2, #0
8000f7c: 609a str r2, [r3, #8]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000f7e: 4b1c ldr r3, [pc, #112] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000f80: 2200 movs r2, #0
8000f82: 611a str r2, [r3, #16]
hadc1.Init.ContinuousConvMode = DISABLE;
8000f84: 4b1a ldr r3, [pc, #104] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000f86: 2200 movs r2, #0
8000f88: 619a str r2, [r3, #24]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8000f8a: 4b19 ldr r3, [pc, #100] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000f8c: 2200 movs r2, #0
8000f8e: f883 2020 strb.w r2, [r3, #32]
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000f92: 4b17 ldr r3, [pc, #92] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000f94: 2200 movs r2, #0
8000f96: 62da str r2, [r3, #44] ; 0x2c
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000f98: 4b15 ldr r3, [pc, #84] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000f9a: 4a17 ldr r2, [pc, #92] ; (8000ff8 <MX_ADC1_Init+0xa0>)
8000f9c: 629a str r2, [r3, #40] ; 0x28
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000f9e: 4b14 ldr r3, [pc, #80] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000fa0: 2200 movs r2, #0
8000fa2: 60da str r2, [r3, #12]
hadc1.Init.NbrOfConversion = 1;
8000fa4: 4b12 ldr r3, [pc, #72] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000fa6: 2201 movs r2, #1
8000fa8: 61da str r2, [r3, #28]
hadc1.Init.DMAContinuousRequests = DISABLE;
8000faa: 4b11 ldr r3, [pc, #68] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000fac: 2200 movs r2, #0
8000fae: f883 2030 strb.w r2, [r3, #48] ; 0x30
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000fb2: 4b0f ldr r3, [pc, #60] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000fb4: 2201 movs r2, #1
8000fb6: 615a str r2, [r3, #20]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
8000fb8: 480d ldr r0, [pc, #52] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000fba: f003 fc39 bl 8004830 <HAL_ADC_Init>
8000fbe: 4603 mov r3, r0
8000fc0: 2b00 cmp r3, #0
8000fc2: d001 beq.n 8000fc8 <MX_ADC1_Init+0x70>
{
Error_Handler();
8000fc4: f001 fb5a bl 800267c <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_0;
8000fc8: 2300 movs r3, #0
8000fca: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000fcc: 2301 movs r3, #1
8000fce: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8000fd0: 2300 movs r3, #0
8000fd2: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000fd4: 463b mov r3, r7
8000fd6: 4619 mov r1, r3
8000fd8: 4805 ldr r0, [pc, #20] ; (8000ff0 <MX_ADC1_Init+0x98>)
8000fda: f003 fdd3 bl 8004b84 <HAL_ADC_ConfigChannel>
8000fde: 4603 mov r3, r0
8000fe0: 2b00 cmp r3, #0
8000fe2: d001 beq.n 8000fe8 <MX_ADC1_Init+0x90>
{
Error_Handler();
8000fe4: f001 fb4a bl 800267c <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8000fe8: bf00 nop
8000fea: 3710 adds r7, #16
8000fec: 46bd mov sp, r7
8000fee: bd80 pop {r7, pc}
8000ff0: 20008a2c .word 0x20008a2c
8000ff4: 40012000 .word 0x40012000
8000ff8: 0f000001 .word 0x0f000001
08000ffc <MX_ADC3_Init>:
* @brief ADC3 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC3_Init(void)
{
8000ffc: b580 push {r7, lr}
8000ffe: b084 sub sp, #16
8001000: af00 add r7, sp, #0
/* USER CODE BEGIN ADC3_Init 0 */
/* USER CODE END ADC3_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8001002: 463b mov r3, r7
8001004: 2200 movs r2, #0
8001006: 601a str r2, [r3, #0]
8001008: 605a str r2, [r3, #4]
800100a: 609a str r2, [r3, #8]
800100c: 60da str r2, [r3, #12]
/* USER CODE BEGIN ADC3_Init 1 */
/* USER CODE END ADC3_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc3.Instance = ADC3;
800100e: 4b21 ldr r3, [pc, #132] ; (8001094 <MX_ADC3_Init+0x98>)
8001010: 4a21 ldr r2, [pc, #132] ; (8001098 <MX_ADC3_Init+0x9c>)
8001012: 601a str r2, [r3, #0]
hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
8001014: 4b1f ldr r3, [pc, #124] ; (8001094 <MX_ADC3_Init+0x98>)
8001016: f44f 3280 mov.w r2, #65536 ; 0x10000
800101a: 605a str r2, [r3, #4]
hadc3.Init.Resolution = ADC_RESOLUTION_12B;
800101c: 4b1d ldr r3, [pc, #116] ; (8001094 <MX_ADC3_Init+0x98>)
800101e: 2200 movs r2, #0
8001020: 609a str r2, [r3, #8]
hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
8001022: 4b1c ldr r3, [pc, #112] ; (8001094 <MX_ADC3_Init+0x98>)
8001024: 2200 movs r2, #0
8001026: 611a str r2, [r3, #16]
hadc3.Init.ContinuousConvMode = DISABLE;
8001028: 4b1a ldr r3, [pc, #104] ; (8001094 <MX_ADC3_Init+0x98>)
800102a: 2200 movs r2, #0
800102c: 619a str r2, [r3, #24]
hadc3.Init.DiscontinuousConvMode = DISABLE;
800102e: 4b19 ldr r3, [pc, #100] ; (8001094 <MX_ADC3_Init+0x98>)
8001030: 2200 movs r2, #0
8001032: f883 2020 strb.w r2, [r3, #32]
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8001036: 4b17 ldr r3, [pc, #92] ; (8001094 <MX_ADC3_Init+0x98>)
8001038: 2200 movs r2, #0
800103a: 62da str r2, [r3, #44] ; 0x2c
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
800103c: 4b15 ldr r3, [pc, #84] ; (8001094 <MX_ADC3_Init+0x98>)
800103e: 4a17 ldr r2, [pc, #92] ; (800109c <MX_ADC3_Init+0xa0>)
8001040: 629a str r2, [r3, #40] ; 0x28
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8001042: 4b14 ldr r3, [pc, #80] ; (8001094 <MX_ADC3_Init+0x98>)
8001044: 2200 movs r2, #0
8001046: 60da str r2, [r3, #12]
hadc3.Init.NbrOfConversion = 1;
8001048: 4b12 ldr r3, [pc, #72] ; (8001094 <MX_ADC3_Init+0x98>)
800104a: 2201 movs r2, #1
800104c: 61da str r2, [r3, #28]
hadc3.Init.DMAContinuousRequests = DISABLE;
800104e: 4b11 ldr r3, [pc, #68] ; (8001094 <MX_ADC3_Init+0x98>)
8001050: 2200 movs r2, #0
8001052: f883 2030 strb.w r2, [r3, #48] ; 0x30
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8001056: 4b0f ldr r3, [pc, #60] ; (8001094 <MX_ADC3_Init+0x98>)
8001058: 2201 movs r2, #1
800105a: 615a str r2, [r3, #20]
if (HAL_ADC_Init(&hadc3) != HAL_OK)
800105c: 480d ldr r0, [pc, #52] ; (8001094 <MX_ADC3_Init+0x98>)
800105e: f003 fbe7 bl 8004830 <HAL_ADC_Init>
8001062: 4603 mov r3, r0
8001064: 2b00 cmp r3, #0
8001066: d001 beq.n 800106c <MX_ADC3_Init+0x70>
{
Error_Handler();
8001068: f001 fb08 bl 800267c <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_8;
800106c: 2308 movs r3, #8
800106e: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
8001070: 2301 movs r3, #1
8001072: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8001074: 2300 movs r3, #0
8001076: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
8001078: 463b mov r3, r7
800107a: 4619 mov r1, r3
800107c: 4805 ldr r0, [pc, #20] ; (8001094 <MX_ADC3_Init+0x98>)
800107e: f003 fd81 bl 8004b84 <HAL_ADC_ConfigChannel>
8001082: 4603 mov r3, r0
8001084: 2b00 cmp r3, #0
8001086: d001 beq.n 800108c <MX_ADC3_Init+0x90>
{
Error_Handler();
8001088: f001 faf8 bl 800267c <Error_Handler>
}
/* USER CODE BEGIN ADC3_Init 2 */
/* USER CODE END ADC3_Init 2 */
}
800108c: bf00 nop
800108e: 3710 adds r7, #16
8001090: 46bd mov sp, r7
8001092: bd80 pop {r7, pc}
8001094: 20008a74 .word 0x20008a74
8001098: 40012200 .word 0x40012200
800109c: 0f000001 .word 0x0f000001
080010a0 <MX_CRC_Init>:
* @brief CRC Initialization Function
* @param None
* @retval None
*/
static void MX_CRC_Init(void)
{
80010a0: b580 push {r7, lr}
80010a2: af00 add r7, sp, #0
/* USER CODE END CRC_Init 0 */
/* USER CODE BEGIN CRC_Init 1 */
/* USER CODE END CRC_Init 1 */
hcrc.Instance = CRC;
80010a4: 4b0d ldr r3, [pc, #52] ; (80010dc <MX_CRC_Init+0x3c>)
80010a6: 4a0e ldr r2, [pc, #56] ; (80010e0 <MX_CRC_Init+0x40>)
80010a8: 601a str r2, [r3, #0]
hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
80010aa: 4b0c ldr r3, [pc, #48] ; (80010dc <MX_CRC_Init+0x3c>)
80010ac: 2200 movs r2, #0
80010ae: 711a strb r2, [r3, #4]
hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE;
80010b0: 4b0a ldr r3, [pc, #40] ; (80010dc <MX_CRC_Init+0x3c>)
80010b2: 2200 movs r2, #0
80010b4: 715a strb r2, [r3, #5]
hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE;
80010b6: 4b09 ldr r3, [pc, #36] ; (80010dc <MX_CRC_Init+0x3c>)
80010b8: 2200 movs r2, #0
80010ba: 615a str r2, [r3, #20]
hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE;
80010bc: 4b07 ldr r3, [pc, #28] ; (80010dc <MX_CRC_Init+0x3c>)
80010be: 2200 movs r2, #0
80010c0: 619a str r2, [r3, #24]
hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
80010c2: 4b06 ldr r3, [pc, #24] ; (80010dc <MX_CRC_Init+0x3c>)
80010c4: 2201 movs r2, #1
80010c6: 621a str r2, [r3, #32]
if (HAL_CRC_Init(&hcrc) != HAL_OK)
80010c8: 4804 ldr r0, [pc, #16] ; (80010dc <MX_CRC_Init+0x3c>)
80010ca: f004 f881 bl 80051d0 <HAL_CRC_Init>
80010ce: 4603 mov r3, r0
80010d0: 2b00 cmp r3, #0
80010d2: d001 beq.n 80010d8 <MX_CRC_Init+0x38>
{
Error_Handler();
80010d4: f001 fad2 bl 800267c <Error_Handler>
}
/* USER CODE BEGIN CRC_Init 2 */
/* USER CODE END CRC_Init 2 */
}
80010d8: bf00 nop
80010da: bd80 pop {r7, pc}
80010dc: 200088c0 .word 0x200088c0
80010e0: 40023000 .word 0x40023000
080010e4 <MX_DAC_Init>:
* @brief DAC Initialization Function
* @param None
* @retval None
*/
static void MX_DAC_Init(void)
{
80010e4: b580 push {r7, lr}
80010e6: b082 sub sp, #8
80010e8: af00 add r7, sp, #0
/* USER CODE BEGIN DAC_Init 0 */
/* USER CODE END DAC_Init 0 */
DAC_ChannelConfTypeDef sConfig = {0};
80010ea: 463b mov r3, r7
80010ec: 2200 movs r2, #0
80010ee: 601a str r2, [r3, #0]
80010f0: 605a str r2, [r3, #4]
/* USER CODE BEGIN DAC_Init 1 */
/* USER CODE END DAC_Init 1 */
/** DAC Initialization
*/
hdac.Instance = DAC;
80010f2: 4b0f ldr r3, [pc, #60] ; (8001130 <MX_DAC_Init+0x4c>)
80010f4: 4a0f ldr r2, [pc, #60] ; (8001134 <MX_DAC_Init+0x50>)
80010f6: 601a str r2, [r3, #0]
if (HAL_DAC_Init(&hdac) != HAL_OK)
80010f8: 480d ldr r0, [pc, #52] ; (8001130 <MX_DAC_Init+0x4c>)
80010fa: f004 f953 bl 80053a4 <HAL_DAC_Init>
80010fe: 4603 mov r3, r0
8001100: 2b00 cmp r3, #0
8001102: d001 beq.n 8001108 <MX_DAC_Init+0x24>
{
Error_Handler();
8001104: f001 faba bl 800267c <Error_Handler>
}
/** DAC channel OUT1 config
*/
sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
8001108: 2300 movs r3, #0
800110a: 603b str r3, [r7, #0]
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
800110c: 2300 movs r3, #0
800110e: 607b str r3, [r7, #4]
if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_1) != HAL_OK)
8001110: 463b mov r3, r7
8001112: 2200 movs r2, #0
8001114: 4619 mov r1, r3
8001116: 4806 ldr r0, [pc, #24] ; (8001130 <MX_DAC_Init+0x4c>)
8001118: f004 f9ca bl 80054b0 <HAL_DAC_ConfigChannel>
800111c: 4603 mov r3, r0
800111e: 2b00 cmp r3, #0
8001120: d001 beq.n 8001126 <MX_DAC_Init+0x42>
{
Error_Handler();
8001122: f001 faab bl 800267c <Error_Handler>
}
/* USER CODE BEGIN DAC_Init 2 */
/* USER CODE END DAC_Init 2 */
}
8001126: bf00 nop
8001128: 3708 adds r7, #8
800112a: 46bd mov sp, r7
800112c: bd80 pop {r7, pc}
800112e: bf00 nop
8001130: 20008ac4 .word 0x20008ac4
8001134: 40007400 .word 0x40007400
08001138 <MX_DMA2D_Init>:
* @brief DMA2D Initialization Function
* @param None
* @retval None
*/
static void MX_DMA2D_Init(void)
{
8001138: b580 push {r7, lr}
800113a: af00 add r7, sp, #0
/* USER CODE END DMA2D_Init 0 */
/* USER CODE BEGIN DMA2D_Init 1 */
/* USER CODE END DMA2D_Init 1 */
hdma2d.Instance = DMA2D;
800113c: 4b15 ldr r3, [pc, #84] ; (8001194 <MX_DMA2D_Init+0x5c>)
800113e: 4a16 ldr r2, [pc, #88] ; (8001198 <MX_DMA2D_Init+0x60>)
8001140: 601a str r2, [r3, #0]
hdma2d.Init.Mode = DMA2D_M2M;
8001142: 4b14 ldr r3, [pc, #80] ; (8001194 <MX_DMA2D_Init+0x5c>)
8001144: 2200 movs r2, #0
8001146: 605a str r2, [r3, #4]
hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
8001148: 4b12 ldr r3, [pc, #72] ; (8001194 <MX_DMA2D_Init+0x5c>)
800114a: 2200 movs r2, #0
800114c: 609a str r2, [r3, #8]
hdma2d.Init.OutputOffset = 0;
800114e: 4b11 ldr r3, [pc, #68] ; (8001194 <MX_DMA2D_Init+0x5c>)
8001150: 2200 movs r2, #0
8001152: 60da str r2, [r3, #12]
hdma2d.LayerCfg[1].InputOffset = 0;
8001154: 4b0f ldr r3, [pc, #60] ; (8001194 <MX_DMA2D_Init+0x5c>)
8001156: 2200 movs r2, #0
8001158: 629a str r2, [r3, #40] ; 0x28
hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
800115a: 4b0e ldr r3, [pc, #56] ; (8001194 <MX_DMA2D_Init+0x5c>)
800115c: 2200 movs r2, #0
800115e: 62da str r2, [r3, #44] ; 0x2c
hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
8001160: 4b0c ldr r3, [pc, #48] ; (8001194 <MX_DMA2D_Init+0x5c>)
8001162: 2200 movs r2, #0
8001164: 631a str r2, [r3, #48] ; 0x30
hdma2d.LayerCfg[1].InputAlpha = 0;
8001166: 4b0b ldr r3, [pc, #44] ; (8001194 <MX_DMA2D_Init+0x5c>)
8001168: 2200 movs r2, #0
800116a: 635a str r2, [r3, #52] ; 0x34
if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
800116c: 4809 ldr r0, [pc, #36] ; (8001194 <MX_DMA2D_Init+0x5c>)
800116e: f004 fbb7 bl 80058e0 <HAL_DMA2D_Init>
8001172: 4603 mov r3, r0
8001174: 2b00 cmp r3, #0
8001176: d001 beq.n 800117c <MX_DMA2D_Init+0x44>
{
Error_Handler();
8001178: f001 fa80 bl 800267c <Error_Handler>
}
if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
800117c: 2101 movs r1, #1
800117e: 4805 ldr r0, [pc, #20] ; (8001194 <MX_DMA2D_Init+0x5c>)
8001180: f004 fd0c bl 8005b9c <HAL_DMA2D_ConfigLayer>
8001184: 4603 mov r3, r0
8001186: 2b00 cmp r3, #0
8001188: d001 beq.n 800118e <MX_DMA2D_Init+0x56>
{
Error_Handler();
800118a: f001 fa77 bl 800267c <Error_Handler>
}
/* USER CODE BEGIN DMA2D_Init 2 */
/* USER CODE END DMA2D_Init 2 */
}
800118e: bf00 nop
8001190: bd80 pop {r7, pc}
8001192: bf00 nop
8001194: 20008b3c .word 0x20008b3c
8001198: 4002b000 .word 0x4002b000
0800119c <MX_LTDC_Init>:
* @brief LTDC Initialization Function
* @param None
* @retval None
*/
static void MX_LTDC_Init(void)
{
800119c: b580 push {r7, lr}
800119e: b08e sub sp, #56 ; 0x38
80011a0: af00 add r7, sp, #0
/* USER CODE BEGIN LTDC_Init 0 */
/* USER CODE END LTDC_Init 0 */
LTDC_LayerCfgTypeDef pLayerCfg = {0};
80011a2: 1d3b adds r3, r7, #4
80011a4: 2234 movs r2, #52 ; 0x34
80011a6: 2100 movs r1, #0
80011a8: 4618 mov r0, r3
80011aa: f019 ff03 bl 801afb4 <memset>
/* USER CODE BEGIN LTDC_Init 1 */
/* USER CODE END LTDC_Init 1 */
hltdc.Instance = LTDC;
80011ae: 4b3a ldr r3, [pc, #232] ; (8001298 <MX_LTDC_Init+0xfc>)
80011b0: 4a3a ldr r2, [pc, #232] ; (800129c <MX_LTDC_Init+0x100>)
80011b2: 601a str r2, [r3, #0]
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
80011b4: 4b38 ldr r3, [pc, #224] ; (8001298 <MX_LTDC_Init+0xfc>)
80011b6: 2200 movs r2, #0
80011b8: 605a str r2, [r3, #4]
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
80011ba: 4b37 ldr r3, [pc, #220] ; (8001298 <MX_LTDC_Init+0xfc>)
80011bc: 2200 movs r2, #0
80011be: 609a str r2, [r3, #8]
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
80011c0: 4b35 ldr r3, [pc, #212] ; (8001298 <MX_LTDC_Init+0xfc>)
80011c2: 2200 movs r2, #0
80011c4: 60da str r2, [r3, #12]
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
80011c6: 4b34 ldr r3, [pc, #208] ; (8001298 <MX_LTDC_Init+0xfc>)
80011c8: 2200 movs r2, #0
80011ca: 611a str r2, [r3, #16]
hltdc.Init.HorizontalSync = 40;
80011cc: 4b32 ldr r3, [pc, #200] ; (8001298 <MX_LTDC_Init+0xfc>)
80011ce: 2228 movs r2, #40 ; 0x28
80011d0: 615a str r2, [r3, #20]
hltdc.Init.VerticalSync = 9;
80011d2: 4b31 ldr r3, [pc, #196] ; (8001298 <MX_LTDC_Init+0xfc>)
80011d4: 2209 movs r2, #9
80011d6: 619a str r2, [r3, #24]
hltdc.Init.AccumulatedHBP = 53;
80011d8: 4b2f ldr r3, [pc, #188] ; (8001298 <MX_LTDC_Init+0xfc>)
80011da: 2235 movs r2, #53 ; 0x35
80011dc: 61da str r2, [r3, #28]
hltdc.Init.AccumulatedVBP = 11;
80011de: 4b2e ldr r3, [pc, #184] ; (8001298 <MX_LTDC_Init+0xfc>)
80011e0: 220b movs r2, #11
80011e2: 621a str r2, [r3, #32]
hltdc.Init.AccumulatedActiveW = 533;
80011e4: 4b2c ldr r3, [pc, #176] ; (8001298 <MX_LTDC_Init+0xfc>)
80011e6: f240 2215 movw r2, #533 ; 0x215
80011ea: 625a str r2, [r3, #36] ; 0x24
hltdc.Init.AccumulatedActiveH = 283;
80011ec: 4b2a ldr r3, [pc, #168] ; (8001298 <MX_LTDC_Init+0xfc>)
80011ee: f240 121b movw r2, #283 ; 0x11b
80011f2: 629a str r2, [r3, #40] ; 0x28
hltdc.Init.TotalWidth = 565;
80011f4: 4b28 ldr r3, [pc, #160] ; (8001298 <MX_LTDC_Init+0xfc>)
80011f6: f240 2235 movw r2, #565 ; 0x235
80011fa: 62da str r2, [r3, #44] ; 0x2c
hltdc.Init.TotalHeigh = 285;
80011fc: 4b26 ldr r3, [pc, #152] ; (8001298 <MX_LTDC_Init+0xfc>)
80011fe: f240 121d movw r2, #285 ; 0x11d
8001202: 631a str r2, [r3, #48] ; 0x30
hltdc.Init.Backcolor.Blue = 0;
8001204: 4b24 ldr r3, [pc, #144] ; (8001298 <MX_LTDC_Init+0xfc>)
8001206: 2200 movs r2, #0
8001208: f883 2034 strb.w r2, [r3, #52] ; 0x34
hltdc.Init.Backcolor.Green = 0;
800120c: 4b22 ldr r3, [pc, #136] ; (8001298 <MX_LTDC_Init+0xfc>)
800120e: 2200 movs r2, #0
8001210: f883 2035 strb.w r2, [r3, #53] ; 0x35
hltdc.Init.Backcolor.Red = 0;
8001214: 4b20 ldr r3, [pc, #128] ; (8001298 <MX_LTDC_Init+0xfc>)
8001216: 2200 movs r2, #0
8001218: f883 2036 strb.w r2, [r3, #54] ; 0x36
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
800121c: 481e ldr r0, [pc, #120] ; (8001298 <MX_LTDC_Init+0xfc>)
800121e: f006 fe61 bl 8007ee4 <HAL_LTDC_Init>
8001222: 4603 mov r3, r0
8001224: 2b00 cmp r3, #0
8001226: d001 beq.n 800122c <MX_LTDC_Init+0x90>
{
Error_Handler();
8001228: f001 fa28 bl 800267c <Error_Handler>
}
pLayerCfg.WindowX0 = 0;
800122c: 2300 movs r3, #0
800122e: 607b str r3, [r7, #4]
pLayerCfg.WindowX1 = 480;
8001230: f44f 73f0 mov.w r3, #480 ; 0x1e0
8001234: 60bb str r3, [r7, #8]
pLayerCfg.WindowY0 = 0;
8001236: 2300 movs r3, #0
8001238: 60fb str r3, [r7, #12]
pLayerCfg.WindowY1 = 272;
800123a: f44f 7388 mov.w r3, #272 ; 0x110
800123e: 613b str r3, [r7, #16]
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565;
8001240: 2302 movs r3, #2
8001242: 617b str r3, [r7, #20]
pLayerCfg.Alpha = 255;
8001244: 23ff movs r3, #255 ; 0xff
8001246: 61bb str r3, [r7, #24]
pLayerCfg.Alpha0 = 0;
8001248: 2300 movs r3, #0
800124a: 61fb str r3, [r7, #28]
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
800124c: f44f 63c0 mov.w r3, #1536 ; 0x600
8001250: 623b str r3, [r7, #32]
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
8001252: 2307 movs r3, #7
8001254: 627b str r3, [r7, #36] ; 0x24
pLayerCfg.FBStartAdress = 0xC0000000;
8001256: f04f 4340 mov.w r3, #3221225472 ; 0xc0000000
800125a: 62bb str r3, [r7, #40] ; 0x28
pLayerCfg.ImageWidth = 480;
800125c: f44f 73f0 mov.w r3, #480 ; 0x1e0
8001260: 62fb str r3, [r7, #44] ; 0x2c
pLayerCfg.ImageHeight = 272;
8001262: f44f 7388 mov.w r3, #272 ; 0x110
8001266: 633b str r3, [r7, #48] ; 0x30
pLayerCfg.Backcolor.Blue = 0;
8001268: 2300 movs r3, #0
800126a: f887 3034 strb.w r3, [r7, #52] ; 0x34
pLayerCfg.Backcolor.Green = 0;
800126e: 2300 movs r3, #0
8001270: f887 3035 strb.w r3, [r7, #53] ; 0x35
pLayerCfg.Backcolor.Red = 0;
8001274: 2300 movs r3, #0
8001276: f887 3036 strb.w r3, [r7, #54] ; 0x36
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
800127a: 1d3b adds r3, r7, #4
800127c: 2200 movs r2, #0
800127e: 4619 mov r1, r3
8001280: 4805 ldr r0, [pc, #20] ; (8001298 <MX_LTDC_Init+0xfc>)
8001282: f006 ffc1 bl 8008208 <HAL_LTDC_ConfigLayer>
8001286: 4603 mov r3, r0
8001288: 2b00 cmp r3, #0
800128a: d001 beq.n 8001290 <MX_LTDC_Init+0xf4>
{
Error_Handler();
800128c: f001 f9f6 bl 800267c <Error_Handler>
}
/* USER CODE BEGIN LTDC_Init 2 */
/* USER CODE END LTDC_Init 2 */
}
8001290: bf00 nop
8001292: 3738 adds r7, #56 ; 0x38
8001294: 46bd mov sp, r7
8001296: bd80 pop {r7, pc}
8001298: 20008984 .word 0x20008984
800129c: 40016800 .word 0x40016800
080012a0 <MX_RNG_Init>:
* @brief RNG Initialization Function
* @param None
* @retval None
*/
static void MX_RNG_Init(void)
{
80012a0: b580 push {r7, lr}
80012a2: af00 add r7, sp, #0
/* USER CODE END RNG_Init 0 */
/* USER CODE BEGIN RNG_Init 1 */
/* USER CODE END RNG_Init 1 */
hrng.Instance = RNG;
80012a4: 4b06 ldr r3, [pc, #24] ; (80012c0 <MX_RNG_Init+0x20>)
80012a6: 4a07 ldr r2, [pc, #28] ; (80012c4 <MX_RNG_Init+0x24>)
80012a8: 601a str r2, [r3, #0]
if (HAL_RNG_Init(&hrng) != HAL_OK)
80012aa: 4805 ldr r0, [pc, #20] ; (80012c0 <MX_RNG_Init+0x20>)
80012ac: f008 fa7a bl 80097a4 <HAL_RNG_Init>
80012b0: 4603 mov r3, r0
80012b2: 2b00 cmp r3, #0
80012b4: d001 beq.n 80012ba <MX_RNG_Init+0x1a>
{
Error_Handler();
80012b6: f001 f9e1 bl 800267c <Error_Handler>
}
/* USER CODE BEGIN RNG_Init 2 */
/* USER CODE END RNG_Init 2 */
}
80012ba: bf00 nop
80012bc: bd80 pop {r7, pc}
80012be: bf00 nop
80012c0: 20008b28 .word 0x20008b28
80012c4: 50060800 .word 0x50060800
080012c8 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
80012c8: b580 push {r7, lr}
80012ca: b088 sub sp, #32
80012cc: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80012ce: f107 0310 add.w r3, r7, #16
80012d2: 2200 movs r2, #0
80012d4: 601a str r2, [r3, #0]
80012d6: 605a str r2, [r3, #4]
80012d8: 609a str r2, [r3, #8]
80012da: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80012dc: 1d3b adds r3, r7, #4
80012de: 2200 movs r2, #0
80012e0: 601a str r2, [r3, #0]
80012e2: 605a str r2, [r3, #4]
80012e4: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
80012e6: 4b20 ldr r3, [pc, #128] ; (8001368 <MX_TIM1_Init+0xa0>)
80012e8: 4a20 ldr r2, [pc, #128] ; (800136c <MX_TIM1_Init+0xa4>)
80012ea: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
80012ec: 4b1e ldr r3, [pc, #120] ; (8001368 <MX_TIM1_Init+0xa0>)
80012ee: 2200 movs r2, #0
80012f0: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
80012f2: 4b1d ldr r3, [pc, #116] ; (8001368 <MX_TIM1_Init+0xa0>)
80012f4: 2200 movs r2, #0
80012f6: 609a str r2, [r3, #8]
htim1.Init.Period = 65535;
80012f8: 4b1b ldr r3, [pc, #108] ; (8001368 <MX_TIM1_Init+0xa0>)
80012fa: f64f 72ff movw r2, #65535 ; 0xffff
80012fe: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001300: 4b19 ldr r3, [pc, #100] ; (8001368 <MX_TIM1_Init+0xa0>)
8001302: 2200 movs r2, #0
8001304: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
8001306: 4b18 ldr r3, [pc, #96] ; (8001368 <MX_TIM1_Init+0xa0>)
8001308: 2200 movs r2, #0
800130a: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800130c: 4b16 ldr r3, [pc, #88] ; (8001368 <MX_TIM1_Init+0xa0>)
800130e: 2200 movs r2, #0
8001310: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
8001312: 4815 ldr r0, [pc, #84] ; (8001368 <MX_TIM1_Init+0xa0>)
8001314: f008 fb3e bl 8009994 <HAL_TIM_Base_Init>
8001318: 4603 mov r3, r0
800131a: 2b00 cmp r3, #0
800131c: d001 beq.n 8001322 <MX_TIM1_Init+0x5a>
{
Error_Handler();
800131e: f001 f9ad bl 800267c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001322: f44f 5380 mov.w r3, #4096 ; 0x1000
8001326: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8001328: f107 0310 add.w r3, r7, #16
800132c: 4619 mov r1, r3
800132e: 480e ldr r0, [pc, #56] ; (8001368 <MX_TIM1_Init+0xa0>)
8001330: f008 fe90 bl 800a054 <HAL_TIM_ConfigClockSource>
8001334: 4603 mov r3, r0
8001336: 2b00 cmp r3, #0
8001338: d001 beq.n 800133e <MX_TIM1_Init+0x76>
{
Error_Handler();
800133a: f001 f99f bl 800267c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800133e: 2300 movs r3, #0
8001340: 607b str r3, [r7, #4]
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
8001342: 2300 movs r3, #0
8001344: 60bb str r3, [r7, #8]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001346: 2300 movs r3, #0
8001348: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
800134a: 1d3b adds r3, r7, #4
800134c: 4619 mov r1, r3
800134e: 4806 ldr r0, [pc, #24] ; (8001368 <MX_TIM1_Init+0xa0>)
8001350: f009 fbd8 bl 800ab04 <HAL_TIMEx_MasterConfigSynchronization>
8001354: 4603 mov r3, r0
8001356: 2b00 cmp r3, #0
8001358: d001 beq.n 800135e <MX_TIM1_Init+0x96>
{
Error_Handler();
800135a: f001 f98f bl 800267c <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
}
800135e: bf00 nop
8001360: 3720 adds r7, #32
8001362: 46bd mov sp, r7
8001364: bd80 pop {r7, pc}
8001366: bf00 nop
8001368: 20008adc .word 0x20008adc
800136c: 40010000 .word 0x40010000
08001370 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
8001370: b580 push {r7, lr}
8001372: b088 sub sp, #32
8001374: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8001376: f107 0310 add.w r3, r7, #16
800137a: 2200 movs r2, #0
800137c: 601a str r2, [r3, #0]
800137e: 605a str r2, [r3, #4]
8001380: 609a str r2, [r3, #8]
8001382: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8001384: 1d3b adds r3, r7, #4
8001386: 2200 movs r2, #0
8001388: 601a str r2, [r3, #0]
800138a: 605a str r2, [r3, #4]
800138c: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
800138e: 4b1e ldr r3, [pc, #120] ; (8001408 <MX_TIM2_Init+0x98>)
8001390: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
8001394: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
8001396: 4b1c ldr r3, [pc, #112] ; (8001408 <MX_TIM2_Init+0x98>)
8001398: 2200 movs r2, #0
800139a: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
800139c: 4b1a ldr r3, [pc, #104] ; (8001408 <MX_TIM2_Init+0x98>)
800139e: 2200 movs r2, #0
80013a0: 609a str r2, [r3, #8]
htim2.Init.Period = 4294967295;
80013a2: 4b19 ldr r3, [pc, #100] ; (8001408 <MX_TIM2_Init+0x98>)
80013a4: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
80013a8: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80013aa: 4b17 ldr r3, [pc, #92] ; (8001408 <MX_TIM2_Init+0x98>)
80013ac: 2200 movs r2, #0
80013ae: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80013b0: 4b15 ldr r3, [pc, #84] ; (8001408 <MX_TIM2_Init+0x98>)
80013b2: 2200 movs r2, #0
80013b4: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
80013b6: 4814 ldr r0, [pc, #80] ; (8001408 <MX_TIM2_Init+0x98>)
80013b8: f008 faec bl 8009994 <HAL_TIM_Base_Init>
80013bc: 4603 mov r3, r0
80013be: 2b00 cmp r3, #0
80013c0: d001 beq.n 80013c6 <MX_TIM2_Init+0x56>
{
Error_Handler();
80013c2: f001 f95b bl 800267c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80013c6: f44f 5380 mov.w r3, #4096 ; 0x1000
80013ca: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
80013cc: f107 0310 add.w r3, r7, #16
80013d0: 4619 mov r1, r3
80013d2: 480d ldr r0, [pc, #52] ; (8001408 <MX_TIM2_Init+0x98>)
80013d4: f008 fe3e bl 800a054 <HAL_TIM_ConfigClockSource>
80013d8: 4603 mov r3, r0
80013da: 2b00 cmp r3, #0
80013dc: d001 beq.n 80013e2 <MX_TIM2_Init+0x72>
{
Error_Handler();
80013de: f001 f94d bl 800267c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80013e2: 2300 movs r3, #0
80013e4: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80013e6: 2300 movs r3, #0
80013e8: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
80013ea: 1d3b adds r3, r7, #4
80013ec: 4619 mov r1, r3
80013ee: 4806 ldr r0, [pc, #24] ; (8001408 <MX_TIM2_Init+0x98>)
80013f0: f009 fb88 bl 800ab04 <HAL_TIMEx_MasterConfigSynchronization>
80013f4: 4603 mov r3, r0
80013f6: 2b00 cmp r3, #0
80013f8: d001 beq.n 80013fe <MX_TIM2_Init+0x8e>
{
Error_Handler();
80013fa: f001 f93f bl 800267c <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
}
80013fe: bf00 nop
8001400: 3720 adds r7, #32
8001402: 46bd mov sp, r7
8001404: bd80 pop {r7, pc}
8001406: bf00 nop
8001408: 20008e1c .word 0x20008e1c
0800140c <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
800140c: b580 push {r7, lr}
800140e: b094 sub sp, #80 ; 0x50
8001410: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8001412: f107 0340 add.w r3, r7, #64 ; 0x40
8001416: 2200 movs r2, #0
8001418: 601a str r2, [r3, #0]
800141a: 605a str r2, [r3, #4]
800141c: 609a str r2, [r3, #8]
800141e: 60da str r2, [r3, #12]
TIM_SlaveConfigTypeDef sSlaveConfig = {0};
8001420: f107 032c add.w r3, r7, #44 ; 0x2c
8001424: 2200 movs r2, #0
8001426: 601a str r2, [r3, #0]
8001428: 605a str r2, [r3, #4]
800142a: 609a str r2, [r3, #8]
800142c: 60da str r2, [r3, #12]
800142e: 611a str r2, [r3, #16]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8001430: f107 0320 add.w r3, r7, #32
8001434: 2200 movs r2, #0
8001436: 601a str r2, [r3, #0]
8001438: 605a str r2, [r3, #4]
800143a: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
800143c: 1d3b adds r3, r7, #4
800143e: 2200 movs r2, #0
8001440: 601a str r2, [r3, #0]
8001442: 605a str r2, [r3, #4]
8001444: 609a str r2, [r3, #8]
8001446: 60da str r2, [r3, #12]
8001448: 611a str r2, [r3, #16]
800144a: 615a str r2, [r3, #20]
800144c: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
800144e: 4b34 ldr r3, [pc, #208] ; (8001520 <MX_TIM3_Init+0x114>)
8001450: 4a34 ldr r2, [pc, #208] ; (8001524 <MX_TIM3_Init+0x118>)
8001452: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 0;
8001454: 4b32 ldr r3, [pc, #200] ; (8001520 <MX_TIM3_Init+0x114>)
8001456: 2200 movs r2, #0
8001458: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
800145a: 4b31 ldr r3, [pc, #196] ; (8001520 <MX_TIM3_Init+0x114>)
800145c: 2200 movs r2, #0
800145e: 609a str r2, [r3, #8]
htim3.Init.Period = 65535;
8001460: 4b2f ldr r3, [pc, #188] ; (8001520 <MX_TIM3_Init+0x114>)
8001462: f64f 72ff movw r2, #65535 ; 0xffff
8001466: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001468: 4b2d ldr r3, [pc, #180] ; (8001520 <MX_TIM3_Init+0x114>)
800146a: 2200 movs r2, #0
800146c: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800146e: 4b2c ldr r3, [pc, #176] ; (8001520 <MX_TIM3_Init+0x114>)
8001470: 2200 movs r2, #0
8001472: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
8001474: 482a ldr r0, [pc, #168] ; (8001520 <MX_TIM3_Init+0x114>)
8001476: f008 fa8d bl 8009994 <HAL_TIM_Base_Init>
800147a: 4603 mov r3, r0
800147c: 2b00 cmp r3, #0
800147e: d001 beq.n 8001484 <MX_TIM3_Init+0x78>
{
Error_Handler();
8001480: f001 f8fc bl 800267c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001484: f44f 5380 mov.w r3, #4096 ; 0x1000
8001488: 643b str r3, [r7, #64] ; 0x40
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
800148a: f107 0340 add.w r3, r7, #64 ; 0x40
800148e: 4619 mov r1, r3
8001490: 4823 ldr r0, [pc, #140] ; (8001520 <MX_TIM3_Init+0x114>)
8001492: f008 fddf bl 800a054 <HAL_TIM_ConfigClockSource>
8001496: 4603 mov r3, r0
8001498: 2b00 cmp r3, #0
800149a: d001 beq.n 80014a0 <MX_TIM3_Init+0x94>
{
Error_Handler();
800149c: f001 f8ee bl 800267c <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
80014a0: 481f ldr r0, [pc, #124] ; (8001520 <MX_TIM3_Init+0x114>)
80014a2: f008 fb47 bl 8009b34 <HAL_TIM_PWM_Init>
80014a6: 4603 mov r3, r0
80014a8: 2b00 cmp r3, #0
80014aa: d001 beq.n 80014b0 <MX_TIM3_Init+0xa4>
{
Error_Handler();
80014ac: f001 f8e6 bl 800267c <Error_Handler>
}
sSlaveConfig.SlaveMode = TIM_SLAVEMODE_DISABLE;
80014b0: 2300 movs r3, #0
80014b2: 62fb str r3, [r7, #44] ; 0x2c
sSlaveConfig.InputTrigger = TIM_TS_ITR0;
80014b4: 2300 movs r3, #0
80014b6: 633b str r3, [r7, #48] ; 0x30
if (HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig) != HAL_OK)
80014b8: f107 032c add.w r3, r7, #44 ; 0x2c
80014bc: 4619 mov r1, r3
80014be: 4818 ldr r0, [pc, #96] ; (8001520 <MX_TIM3_Init+0x114>)
80014c0: f008 fe8e bl 800a1e0 <HAL_TIM_SlaveConfigSynchro>
80014c4: 4603 mov r3, r0
80014c6: 2b00 cmp r3, #0
80014c8: d001 beq.n 80014ce <MX_TIM3_Init+0xc2>
{
Error_Handler();
80014ca: f001 f8d7 bl 800267c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80014ce: 2300 movs r3, #0
80014d0: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80014d2: 2300 movs r3, #0
80014d4: 62bb str r3, [r7, #40] ; 0x28
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
80014d6: f107 0320 add.w r3, r7, #32
80014da: 4619 mov r1, r3
80014dc: 4810 ldr r0, [pc, #64] ; (8001520 <MX_TIM3_Init+0x114>)
80014de: f009 fb11 bl 800ab04 <HAL_TIMEx_MasterConfigSynchronization>
80014e2: 4603 mov r3, r0
80014e4: 2b00 cmp r3, #0
80014e6: d001 beq.n 80014ec <MX_TIM3_Init+0xe0>
{
Error_Handler();
80014e8: f001 f8c8 bl 800267c <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
80014ec: 2360 movs r3, #96 ; 0x60
80014ee: 607b str r3, [r7, #4]
sConfigOC.Pulse = 0;
80014f0: 2300 movs r3, #0
80014f2: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80014f4: 2300 movs r3, #0
80014f6: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
80014f8: 2300 movs r3, #0
80014fa: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
80014fc: 1d3b adds r3, r7, #4
80014fe: 2200 movs r2, #0
8001500: 4619 mov r1, r3
8001502: 4807 ldr r0, [pc, #28] ; (8001520 <MX_TIM3_Init+0x114>)
8001504: f008 fc96 bl 8009e34 <HAL_TIM_PWM_ConfigChannel>
8001508: 4603 mov r3, r0
800150a: 2b00 cmp r3, #0
800150c: d001 beq.n 8001512 <MX_TIM3_Init+0x106>
{
Error_Handler();
800150e: f001 f8b5 bl 800267c <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
8001512: 4803 ldr r0, [pc, #12] ; (8001520 <MX_TIM3_Init+0x114>)
8001514: f002 fea4 bl 8004260 <HAL_TIM_MspPostInit>
}
8001518: bf00 nop
800151a: 3750 adds r7, #80 ; 0x50
800151c: 46bd mov sp, r7
800151e: bd80 pop {r7, pc}
8001520: 20008938 .word 0x20008938
8001524: 40000400 .word 0x40000400
08001528 <MX_TIM5_Init>:
* @brief TIM5 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM5_Init(void)
{
8001528: b580 push {r7, lr}
800152a: b088 sub sp, #32
800152c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM5_Init 0 */
/* USER CODE END TIM5_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800152e: f107 0310 add.w r3, r7, #16
8001532: 2200 movs r2, #0
8001534: 601a str r2, [r3, #0]
8001536: 605a str r2, [r3, #4]
8001538: 609a str r2, [r3, #8]
800153a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
800153c: 1d3b adds r3, r7, #4
800153e: 2200 movs r2, #0
8001540: 601a str r2, [r3, #0]
8001542: 605a str r2, [r3, #4]
8001544: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM5_Init 1 */
/* USER CODE END TIM5_Init 1 */
htim5.Instance = TIM5;
8001546: 4b1d ldr r3, [pc, #116] ; (80015bc <MX_TIM5_Init+0x94>)
8001548: 4a1d ldr r2, [pc, #116] ; (80015c0 <MX_TIM5_Init+0x98>)
800154a: 601a str r2, [r3, #0]
htim5.Init.Prescaler = 0;
800154c: 4b1b ldr r3, [pc, #108] ; (80015bc <MX_TIM5_Init+0x94>)
800154e: 2200 movs r2, #0
8001550: 605a str r2, [r3, #4]
htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
8001552: 4b1a ldr r3, [pc, #104] ; (80015bc <MX_TIM5_Init+0x94>)
8001554: 2200 movs r2, #0
8001556: 609a str r2, [r3, #8]
htim5.Init.Period = 4294967295;
8001558: 4b18 ldr r3, [pc, #96] ; (80015bc <MX_TIM5_Init+0x94>)
800155a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800155e: 60da str r2, [r3, #12]
htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001560: 4b16 ldr r3, [pc, #88] ; (80015bc <MX_TIM5_Init+0x94>)
8001562: 2200 movs r2, #0
8001564: 611a str r2, [r3, #16]
htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001566: 4b15 ldr r3, [pc, #84] ; (80015bc <MX_TIM5_Init+0x94>)
8001568: 2200 movs r2, #0
800156a: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim5) != HAL_OK)
800156c: 4813 ldr r0, [pc, #76] ; (80015bc <MX_TIM5_Init+0x94>)
800156e: f008 fa11 bl 8009994 <HAL_TIM_Base_Init>
8001572: 4603 mov r3, r0
8001574: 2b00 cmp r3, #0
8001576: d001 beq.n 800157c <MX_TIM5_Init+0x54>
{
Error_Handler();
8001578: f001 f880 bl 800267c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
800157c: f44f 5380 mov.w r3, #4096 ; 0x1000
8001580: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK)
8001582: f107 0310 add.w r3, r7, #16
8001586: 4619 mov r1, r3
8001588: 480c ldr r0, [pc, #48] ; (80015bc <MX_TIM5_Init+0x94>)
800158a: f008 fd63 bl 800a054 <HAL_TIM_ConfigClockSource>
800158e: 4603 mov r3, r0
8001590: 2b00 cmp r3, #0
8001592: d001 beq.n 8001598 <MX_TIM5_Init+0x70>
{
Error_Handler();
8001594: f001 f872 bl 800267c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001598: 2300 movs r3, #0
800159a: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800159c: 2300 movs r3, #0
800159e: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
80015a0: 1d3b adds r3, r7, #4
80015a2: 4619 mov r1, r3
80015a4: 4805 ldr r0, [pc, #20] ; (80015bc <MX_TIM5_Init+0x94>)
80015a6: f009 faad bl 800ab04 <HAL_TIMEx_MasterConfigSynchronization>
80015aa: 4603 mov r3, r0
80015ac: 2b00 cmp r3, #0
80015ae: d001 beq.n 80015b4 <MX_TIM5_Init+0x8c>
{
Error_Handler();
80015b0: f001 f864 bl 800267c <Error_Handler>
}
/* USER CODE BEGIN TIM5_Init 2 */
/* USER CODE END TIM5_Init 2 */
}
80015b4: bf00 nop
80015b6: 3720 adds r7, #32
80015b8: 46bd mov sp, r7
80015ba: bd80 pop {r7, pc}
80015bc: 200088e8 .word 0x200088e8
80015c0: 40000c00 .word 0x40000c00
080015c4 <MX_TIM8_Init>:
* @brief TIM8 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM8_Init(void)
{
80015c4: b580 push {r7, lr}
80015c6: b09a sub sp, #104 ; 0x68
80015c8: af00 add r7, sp, #0
/* USER CODE BEGIN TIM8_Init 0 */
/* USER CODE END TIM8_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80015ca: f107 0358 add.w r3, r7, #88 ; 0x58
80015ce: 2200 movs r2, #0
80015d0: 601a str r2, [r3, #0]
80015d2: 605a str r2, [r3, #4]
80015d4: 609a str r2, [r3, #8]
80015d6: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80015d8: f107 034c add.w r3, r7, #76 ; 0x4c
80015dc: 2200 movs r2, #0
80015de: 601a str r2, [r3, #0]
80015e0: 605a str r2, [r3, #4]
80015e2: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
80015e4: f107 0330 add.w r3, r7, #48 ; 0x30
80015e8: 2200 movs r2, #0
80015ea: 601a str r2, [r3, #0]
80015ec: 605a str r2, [r3, #4]
80015ee: 609a str r2, [r3, #8]
80015f0: 60da str r2, [r3, #12]
80015f2: 611a str r2, [r3, #16]
80015f4: 615a str r2, [r3, #20]
80015f6: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
80015f8: 1d3b adds r3, r7, #4
80015fa: 222c movs r2, #44 ; 0x2c
80015fc: 2100 movs r1, #0
80015fe: 4618 mov r0, r3
8001600: f019 fcd8 bl 801afb4 <memset>
/* USER CODE BEGIN TIM8_Init 1 */
/* USER CODE END TIM8_Init 1 */
htim8.Instance = TIM8;
8001604: 4b42 ldr r3, [pc, #264] ; (8001710 <MX_TIM8_Init+0x14c>)
8001606: 4a43 ldr r2, [pc, #268] ; (8001714 <MX_TIM8_Init+0x150>)
8001608: 601a str r2, [r3, #0]
htim8.Init.Prescaler = 0;
800160a: 4b41 ldr r3, [pc, #260] ; (8001710 <MX_TIM8_Init+0x14c>)
800160c: 2200 movs r2, #0
800160e: 605a str r2, [r3, #4]
htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
8001610: 4b3f ldr r3, [pc, #252] ; (8001710 <MX_TIM8_Init+0x14c>)
8001612: 2200 movs r2, #0
8001614: 609a str r2, [r3, #8]
htim8.Init.Period = 65535;
8001616: 4b3e ldr r3, [pc, #248] ; (8001710 <MX_TIM8_Init+0x14c>)
8001618: f64f 72ff movw r2, #65535 ; 0xffff
800161c: 60da str r2, [r3, #12]
htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
800161e: 4b3c ldr r3, [pc, #240] ; (8001710 <MX_TIM8_Init+0x14c>)
8001620: 2200 movs r2, #0
8001622: 611a str r2, [r3, #16]
htim8.Init.RepetitionCounter = 0;
8001624: 4b3a ldr r3, [pc, #232] ; (8001710 <MX_TIM8_Init+0x14c>)
8001626: 2200 movs r2, #0
8001628: 615a str r2, [r3, #20]
htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800162a: 4b39 ldr r3, [pc, #228] ; (8001710 <MX_TIM8_Init+0x14c>)
800162c: 2200 movs r2, #0
800162e: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
8001630: 4837 ldr r0, [pc, #220] ; (8001710 <MX_TIM8_Init+0x14c>)
8001632: f008 f9af bl 8009994 <HAL_TIM_Base_Init>
8001636: 4603 mov r3, r0
8001638: 2b00 cmp r3, #0
800163a: d001 beq.n 8001640 <MX_TIM8_Init+0x7c>
{
Error_Handler();
800163c: f001 f81e bl 800267c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001640: f44f 5380 mov.w r3, #4096 ; 0x1000
8001644: 65bb str r3, [r7, #88] ; 0x58
if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
8001646: f107 0358 add.w r3, r7, #88 ; 0x58
800164a: 4619 mov r1, r3
800164c: 4830 ldr r0, [pc, #192] ; (8001710 <MX_TIM8_Init+0x14c>)
800164e: f008 fd01 bl 800a054 <HAL_TIM_ConfigClockSource>
8001652: 4603 mov r3, r0
8001654: 2b00 cmp r3, #0
8001656: d001 beq.n 800165c <MX_TIM8_Init+0x98>
{
Error_Handler();
8001658: f001 f810 bl 800267c <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim8) != HAL_OK)
800165c: 482c ldr r0, [pc, #176] ; (8001710 <MX_TIM8_Init+0x14c>)
800165e: f008 fa69 bl 8009b34 <HAL_TIM_PWM_Init>
8001662: 4603 mov r3, r0
8001664: 2b00 cmp r3, #0
8001666: d001 beq.n 800166c <MX_TIM8_Init+0xa8>
{
Error_Handler();
8001668: f001 f808 bl 800267c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800166c: 2300 movs r3, #0
800166e: 64fb str r3, [r7, #76] ; 0x4c
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
8001670: 2300 movs r3, #0
8001672: 653b str r3, [r7, #80] ; 0x50
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001674: 2300 movs r3, #0
8001676: 657b str r3, [r7, #84] ; 0x54
if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
8001678: f107 034c add.w r3, r7, #76 ; 0x4c
800167c: 4619 mov r1, r3
800167e: 4824 ldr r0, [pc, #144] ; (8001710 <MX_TIM8_Init+0x14c>)
8001680: f009 fa40 bl 800ab04 <HAL_TIMEx_MasterConfigSynchronization>
8001684: 4603 mov r3, r0
8001686: 2b00 cmp r3, #0
8001688: d001 beq.n 800168e <MX_TIM8_Init+0xca>
{
Error_Handler();
800168a: f000 fff7 bl 800267c <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800168e: 2360 movs r3, #96 ; 0x60
8001690: 633b str r3, [r7, #48] ; 0x30
sConfigOC.Pulse = 0;
8001692: 2300 movs r3, #0
8001694: 637b str r3, [r7, #52] ; 0x34
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8001696: 2300 movs r3, #0
8001698: 63bb str r3, [r7, #56] ; 0x38
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
800169a: 2300 movs r3, #0
800169c: 643b str r3, [r7, #64] ; 0x40
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
800169e: 2300 movs r3, #0
80016a0: 647b str r3, [r7, #68] ; 0x44
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
80016a2: 2300 movs r3, #0
80016a4: 64bb str r3, [r7, #72] ; 0x48
if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
80016a6: f107 0330 add.w r3, r7, #48 ; 0x30
80016aa: 220c movs r2, #12
80016ac: 4619 mov r1, r3
80016ae: 4818 ldr r0, [pc, #96] ; (8001710 <MX_TIM8_Init+0x14c>)
80016b0: f008 fbc0 bl 8009e34 <HAL_TIM_PWM_ConfigChannel>
80016b4: 4603 mov r3, r0
80016b6: 2b00 cmp r3, #0
80016b8: d001 beq.n 80016be <MX_TIM8_Init+0xfa>
{
Error_Handler();
80016ba: f000 ffdf bl 800267c <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
80016be: 2300 movs r3, #0
80016c0: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
80016c2: 2300 movs r3, #0
80016c4: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
80016c6: 2300 movs r3, #0
80016c8: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.DeadTime = 0;
80016ca: 2300 movs r3, #0
80016cc: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
80016ce: 2300 movs r3, #0
80016d0: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
80016d2: f44f 5300 mov.w r3, #8192 ; 0x2000
80016d6: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.BreakFilter = 0;
80016d8: 2300 movs r3, #0
80016da: 61fb str r3, [r7, #28]
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
80016dc: 2300 movs r3, #0
80016de: 623b str r3, [r7, #32]
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
80016e0: f04f 7300 mov.w r3, #33554432 ; 0x2000000
80016e4: 627b str r3, [r7, #36] ; 0x24
sBreakDeadTimeConfig.Break2Filter = 0;
80016e6: 2300 movs r3, #0
80016e8: 62bb str r3, [r7, #40] ; 0x28
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
80016ea: 2300 movs r3, #0
80016ec: 62fb str r3, [r7, #44] ; 0x2c
if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK)
80016ee: 1d3b adds r3, r7, #4
80016f0: 4619 mov r1, r3
80016f2: 4807 ldr r0, [pc, #28] ; (8001710 <MX_TIM8_Init+0x14c>)
80016f4: f009 fa94 bl 800ac20 <HAL_TIMEx_ConfigBreakDeadTime>
80016f8: 4603 mov r3, r0
80016fa: 2b00 cmp r3, #0
80016fc: d001 beq.n 8001702 <MX_TIM8_Init+0x13e>
{
Error_Handler();
80016fe: f000 ffbd bl 800267c <Error_Handler>
}
/* USER CODE BEGIN TIM8_Init 2 */
/* USER CODE END TIM8_Init 2 */
HAL_TIM_MspPostInit(&htim8);
8001702: 4803 ldr r0, [pc, #12] ; (8001710 <MX_TIM8_Init+0x14c>)
8001704: f002 fdac bl 8004260 <HAL_TIM_MspPostInit>
}
8001708: bf00 nop
800170a: 3768 adds r7, #104 ; 0x68
800170c: 46bd mov sp, r7
800170e: bd80 pop {r7, pc}
8001710: 20008870 .word 0x20008870
8001714: 40010400 .word 0x40010400
08001718 <MX_FMC_Init>:
/* FMC initialization function */
static void MX_FMC_Init(void)
{
8001718: b580 push {r7, lr}
800171a: b088 sub sp, #32
800171c: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_Init 0 */
/* USER CODE END FMC_Init 0 */
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
800171e: 1d3b adds r3, r7, #4
8001720: 2200 movs r2, #0
8001722: 601a str r2, [r3, #0]
8001724: 605a str r2, [r3, #4]
8001726: 609a str r2, [r3, #8]
8001728: 60da str r2, [r3, #12]
800172a: 611a str r2, [r3, #16]
800172c: 615a str r2, [r3, #20]
800172e: 619a str r2, [r3, #24]
/* USER CODE END FMC_Init 1 */
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1.Instance = FMC_SDRAM_DEVICE;
8001730: 4b1e ldr r3, [pc, #120] ; (80017ac <MX_FMC_Init+0x94>)
8001732: 4a1f ldr r2, [pc, #124] ; (80017b0 <MX_FMC_Init+0x98>)
8001734: 601a str r2, [r3, #0]
/* hsdram1.Init */
hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
8001736: 4b1d ldr r3, [pc, #116] ; (80017ac <MX_FMC_Init+0x94>)
8001738: 2200 movs r2, #0
800173a: 605a str r2, [r3, #4]
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
800173c: 4b1b ldr r3, [pc, #108] ; (80017ac <MX_FMC_Init+0x94>)
800173e: 2200 movs r2, #0
8001740: 609a str r2, [r3, #8]
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
8001742: 4b1a ldr r3, [pc, #104] ; (80017ac <MX_FMC_Init+0x94>)
8001744: 2204 movs r2, #4
8001746: 60da str r2, [r3, #12]
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
8001748: 4b18 ldr r3, [pc, #96] ; (80017ac <MX_FMC_Init+0x94>)
800174a: 2210 movs r2, #16
800174c: 611a str r2, [r3, #16]
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
800174e: 4b17 ldr r3, [pc, #92] ; (80017ac <MX_FMC_Init+0x94>)
8001750: 2240 movs r2, #64 ; 0x40
8001752: 615a str r2, [r3, #20]
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1;
8001754: 4b15 ldr r3, [pc, #84] ; (80017ac <MX_FMC_Init+0x94>)
8001756: 2280 movs r2, #128 ; 0x80
8001758: 619a str r2, [r3, #24]
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
800175a: 4b14 ldr r3, [pc, #80] ; (80017ac <MX_FMC_Init+0x94>)
800175c: 2200 movs r2, #0
800175e: 61da str r2, [r3, #28]
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE;
8001760: 4b12 ldr r3, [pc, #72] ; (80017ac <MX_FMC_Init+0x94>)
8001762: 2200 movs r2, #0
8001764: 621a str r2, [r3, #32]
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
8001766: 4b11 ldr r3, [pc, #68] ; (80017ac <MX_FMC_Init+0x94>)
8001768: 2200 movs r2, #0
800176a: 625a str r2, [r3, #36] ; 0x24
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
800176c: 4b0f ldr r3, [pc, #60] ; (80017ac <MX_FMC_Init+0x94>)
800176e: 2200 movs r2, #0
8001770: 629a str r2, [r3, #40] ; 0x28
/* SdramTiming */
SdramTiming.LoadToActiveDelay = 16;
8001772: 2310 movs r3, #16
8001774: 607b str r3, [r7, #4]
SdramTiming.ExitSelfRefreshDelay = 16;
8001776: 2310 movs r3, #16
8001778: 60bb str r3, [r7, #8]
SdramTiming.SelfRefreshTime = 16;
800177a: 2310 movs r3, #16
800177c: 60fb str r3, [r7, #12]
SdramTiming.RowCycleDelay = 16;
800177e: 2310 movs r3, #16
8001780: 613b str r3, [r7, #16]
SdramTiming.WriteRecoveryTime = 16;
8001782: 2310 movs r3, #16
8001784: 617b str r3, [r7, #20]
SdramTiming.RPDelay = 16;
8001786: 2310 movs r3, #16
8001788: 61bb str r3, [r7, #24]
SdramTiming.RCDDelay = 16;
800178a: 2310 movs r3, #16
800178c: 61fb str r3, [r7, #28]
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
800178e: 1d3b adds r3, r7, #4
8001790: 4619 mov r1, r3
8001792: 4806 ldr r0, [pc, #24] ; (80017ac <MX_FMC_Init+0x94>)
8001794: f008 f87f bl 8009896 <HAL_SDRAM_Init>
8001798: 4603 mov r3, r0
800179a: 2b00 cmp r3, #0
800179c: d001 beq.n 80017a2 <MX_FMC_Init+0x8a>
{
Error_Handler( );
800179e: f000 ff6d bl 800267c <Error_Handler>
}
/* USER CODE BEGIN FMC_Init 2 */
/* USER CODE END FMC_Init 2 */
}
80017a2: bf00 nop
80017a4: 3720 adds r7, #32
80017a6: 46bd mov sp, r7
80017a8: bd80 pop {r7, pc}
80017aa: bf00 nop
80017ac: 20008e6c .word 0x20008e6c
80017b0: a0000140 .word 0xa0000140
080017b4 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80017b4: b580 push {r7, lr}
80017b6: b090 sub sp, #64 ; 0x40
80017b8: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80017ba: f107 032c add.w r3, r7, #44 ; 0x2c
80017be: 2200 movs r2, #0
80017c0: 601a str r2, [r3, #0]
80017c2: 605a str r2, [r3, #4]
80017c4: 609a str r2, [r3, #8]
80017c6: 60da str r2, [r3, #12]
80017c8: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
80017ca: 4baf ldr r3, [pc, #700] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80017cc: 6b1b ldr r3, [r3, #48] ; 0x30
80017ce: 4aae ldr r2, [pc, #696] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80017d0: f043 0310 orr.w r3, r3, #16
80017d4: 6313 str r3, [r2, #48] ; 0x30
80017d6: 4bac ldr r3, [pc, #688] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80017d8: 6b1b ldr r3, [r3, #48] ; 0x30
80017da: f003 0310 and.w r3, r3, #16
80017de: 62bb str r3, [r7, #40] ; 0x28
80017e0: 6abb ldr r3, [r7, #40] ; 0x28
__HAL_RCC_GPIOG_CLK_ENABLE();
80017e2: 4ba9 ldr r3, [pc, #676] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80017e4: 6b1b ldr r3, [r3, #48] ; 0x30
80017e6: 4aa8 ldr r2, [pc, #672] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80017e8: f043 0340 orr.w r3, r3, #64 ; 0x40
80017ec: 6313 str r3, [r2, #48] ; 0x30
80017ee: 4ba6 ldr r3, [pc, #664] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80017f0: 6b1b ldr r3, [r3, #48] ; 0x30
80017f2: f003 0340 and.w r3, r3, #64 ; 0x40
80017f6: 627b str r3, [r7, #36] ; 0x24
80017f8: 6a7b ldr r3, [r7, #36] ; 0x24
__HAL_RCC_GPIOB_CLK_ENABLE();
80017fa: 4ba3 ldr r3, [pc, #652] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80017fc: 6b1b ldr r3, [r3, #48] ; 0x30
80017fe: 4aa2 ldr r2, [pc, #648] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001800: f043 0302 orr.w r3, r3, #2
8001804: 6313 str r3, [r2, #48] ; 0x30
8001806: 4ba0 ldr r3, [pc, #640] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001808: 6b1b ldr r3, [r3, #48] ; 0x30
800180a: f003 0302 and.w r3, r3, #2
800180e: 623b str r3, [r7, #32]
8001810: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001812: 4b9d ldr r3, [pc, #628] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001814: 6b1b ldr r3, [r3, #48] ; 0x30
8001816: 4a9c ldr r2, [pc, #624] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001818: f043 0301 orr.w r3, r3, #1
800181c: 6313 str r3, [r2, #48] ; 0x30
800181e: 4b9a ldr r3, [pc, #616] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001820: 6b1b ldr r3, [r3, #48] ; 0x30
8001822: f003 0301 and.w r3, r3, #1
8001826: 61fb str r3, [r7, #28]
8001828: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOJ_CLK_ENABLE();
800182a: 4b97 ldr r3, [pc, #604] ; (8001a88 <MX_GPIO_Init+0x2d4>)
800182c: 6b1b ldr r3, [r3, #48] ; 0x30
800182e: 4a96 ldr r2, [pc, #600] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001830: f443 7300 orr.w r3, r3, #512 ; 0x200
8001834: 6313 str r3, [r2, #48] ; 0x30
8001836: 4b94 ldr r3, [pc, #592] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001838: 6b1b ldr r3, [r3, #48] ; 0x30
800183a: f403 7300 and.w r3, r3, #512 ; 0x200
800183e: 61bb str r3, [r7, #24]
8001840: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOD_CLK_ENABLE();
8001842: 4b91 ldr r3, [pc, #580] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001844: 6b1b ldr r3, [r3, #48] ; 0x30
8001846: 4a90 ldr r2, [pc, #576] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001848: f043 0308 orr.w r3, r3, #8
800184c: 6313 str r3, [r2, #48] ; 0x30
800184e: 4b8e ldr r3, [pc, #568] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001850: 6b1b ldr r3, [r3, #48] ; 0x30
8001852: f003 0308 and.w r3, r3, #8
8001856: 617b str r3, [r7, #20]
8001858: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOI_CLK_ENABLE();
800185a: 4b8b ldr r3, [pc, #556] ; (8001a88 <MX_GPIO_Init+0x2d4>)
800185c: 6b1b ldr r3, [r3, #48] ; 0x30
800185e: 4a8a ldr r2, [pc, #552] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001860: f443 7380 orr.w r3, r3, #256 ; 0x100
8001864: 6313 str r3, [r2, #48] ; 0x30
8001866: 4b88 ldr r3, [pc, #544] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001868: 6b1b ldr r3, [r3, #48] ; 0x30
800186a: f403 7380 and.w r3, r3, #256 ; 0x100
800186e: 613b str r3, [r7, #16]
8001870: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOK_CLK_ENABLE();
8001872: 4b85 ldr r3, [pc, #532] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001874: 6b1b ldr r3, [r3, #48] ; 0x30
8001876: 4a84 ldr r2, [pc, #528] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001878: f443 6380 orr.w r3, r3, #1024 ; 0x400
800187c: 6313 str r3, [r2, #48] ; 0x30
800187e: 4b82 ldr r3, [pc, #520] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001880: 6b1b ldr r3, [r3, #48] ; 0x30
8001882: f403 6380 and.w r3, r3, #1024 ; 0x400
8001886: 60fb str r3, [r7, #12]
8001888: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOC_CLK_ENABLE();
800188a: 4b7f ldr r3, [pc, #508] ; (8001a88 <MX_GPIO_Init+0x2d4>)
800188c: 6b1b ldr r3, [r3, #48] ; 0x30
800188e: 4a7e ldr r2, [pc, #504] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001890: f043 0304 orr.w r3, r3, #4
8001894: 6313 str r3, [r2, #48] ; 0x30
8001896: 4b7c ldr r3, [pc, #496] ; (8001a88 <MX_GPIO_Init+0x2d4>)
8001898: 6b1b ldr r3, [r3, #48] ; 0x30
800189a: f003 0304 and.w r3, r3, #4
800189e: 60bb str r3, [r7, #8]
80018a0: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOF_CLK_ENABLE();
80018a2: 4b79 ldr r3, [pc, #484] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80018a4: 6b1b ldr r3, [r3, #48] ; 0x30
80018a6: 4a78 ldr r2, [pc, #480] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80018a8: f043 0320 orr.w r3, r3, #32
80018ac: 6313 str r3, [r2, #48] ; 0x30
80018ae: 4b76 ldr r3, [pc, #472] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80018b0: 6b1b ldr r3, [r3, #48] ; 0x30
80018b2: f003 0320 and.w r3, r3, #32
80018b6: 607b str r3, [r7, #4]
80018b8: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOH_CLK_ENABLE();
80018ba: 4b73 ldr r3, [pc, #460] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80018bc: 6b1b ldr r3, [r3, #48] ; 0x30
80018be: 4a72 ldr r2, [pc, #456] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80018c0: f043 0380 orr.w r3, r3, #128 ; 0x80
80018c4: 6313 str r3, [r2, #48] ; 0x30
80018c6: 4b70 ldr r3, [pc, #448] ; (8001a88 <MX_GPIO_Init+0x2d4>)
80018c8: 6b1b ldr r3, [r3, #48] ; 0x30
80018ca: f003 0380 and.w r3, r3, #128 ; 0x80
80018ce: 603b str r3, [r7, #0]
80018d0: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, LED14_Pin|LED15_Pin, GPIO_PIN_RESET);
80018d2: 2200 movs r2, #0
80018d4: 2160 movs r1, #96 ; 0x60
80018d6: 486d ldr r0, [pc, #436] ; (8001a8c <MX_GPIO_Init+0x2d8>)
80018d8: f005 fdbe bl 8007458 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(OTG_FS_PowerSwitchOn_GPIO_Port, OTG_FS_PowerSwitchOn_Pin, GPIO_PIN_SET);
80018dc: 2201 movs r2, #1
80018de: 2120 movs r1, #32
80018e0: 486b ldr r0, [pc, #428] ; (8001a90 <MX_GPIO_Init+0x2dc>)
80018e2: f005 fdb9 bl 8007458 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED16_GPIO_Port, LED16_Pin, GPIO_PIN_RESET);
80018e6: 2200 movs r2, #0
80018e8: 2108 movs r1, #8
80018ea: 4869 ldr r0, [pc, #420] ; (8001a90 <MX_GPIO_Init+0x2dc>)
80018ec: f005 fdb4 bl 8007458 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET);
80018f0: 2200 movs r2, #0
80018f2: 2108 movs r1, #8
80018f4: 4867 ldr r0, [pc, #412] ; (8001a94 <MX_GPIO_Init+0x2e0>)
80018f6: f005 fdaf bl 8007458 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_Port, LCD_BL_CTRL_Pin, GPIO_PIN_SET);
80018fa: 2201 movs r2, #1
80018fc: 2108 movs r1, #8
80018fe: 4866 ldr r0, [pc, #408] ; (8001a98 <MX_GPIO_Init+0x2e4>)
8001900: f005 fdaa bl 8007458 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LCD_DISP_GPIO_Port, LCD_DISP_Pin, GPIO_PIN_SET);
8001904: 2201 movs r2, #1
8001906: f44f 5180 mov.w r1, #4096 ; 0x1000
800190a: 4862 ldr r0, [pc, #392] ; (8001a94 <MX_GPIO_Init+0x2e0>)
800190c: f005 fda4 bl 8007458 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOH, LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin
8001910: 2200 movs r2, #0
8001912: f645 6140 movw r1, #24128 ; 0x5e40
8001916: 4861 ldr r0, [pc, #388] ; (8001a9c <MX_GPIO_Init+0x2e8>)
8001918: f005 fd9e bl 8007458 <HAL_GPIO_WritePin>
|LED2_Pin|LED18_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(EXT_RST_GPIO_Port, EXT_RST_Pin, GPIO_PIN_RESET);
800191c: 2200 movs r2, #0
800191e: 2108 movs r1, #8
8001920: 485f ldr r0, [pc, #380] ; (8001aa0 <MX_GPIO_Init+0x2ec>)
8001922: f005 fd99 bl 8007458 <HAL_GPIO_WritePin>
/*Configure GPIO pin : PE3 */
GPIO_InitStruct.Pin = GPIO_PIN_3;
8001926: 2308 movs r3, #8
8001928: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800192a: 2300 movs r3, #0
800192c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
800192e: 2300 movs r3, #0
8001930: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8001932: f107 032c add.w r3, r7, #44 ; 0x2c
8001936: 4619 mov r1, r3
8001938: 4854 ldr r0, [pc, #336] ; (8001a8c <MX_GPIO_Init+0x2d8>)
800193a: f005 fbe1 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : ARDUINO_SCL_D15_Pin ARDUINO_SDA_D14_Pin */
GPIO_InitStruct.Pin = ARDUINO_SCL_D15_Pin|ARDUINO_SDA_D14_Pin;
800193e: f44f 7340 mov.w r3, #768 ; 0x300
8001942: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8001944: 2312 movs r3, #18
8001946: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_PULLUP;
8001948: 2301 movs r3, #1
800194a: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800194c: 2300 movs r3, #0
800194e: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
8001950: 2304 movs r3, #4
8001952: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001954: f107 032c add.w r3, r7, #44 ; 0x2c
8001958: 4619 mov r1, r3
800195a: 4852 ldr r0, [pc, #328] ; (8001aa4 <MX_GPIO_Init+0x2f0>)
800195c: f005 fbd0 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : ULPI_D7_Pin ULPI_D6_Pin ULPI_D5_Pin ULPI_D2_Pin
ULPI_D1_Pin ULPI_D4_Pin */
GPIO_InitStruct.Pin = ULPI_D7_Pin|ULPI_D6_Pin|ULPI_D5_Pin|ULPI_D2_Pin
8001960: f643 0323 movw r3, #14371 ; 0x3823
8001964: 62fb str r3, [r7, #44] ; 0x2c
|ULPI_D1_Pin|ULPI_D4_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001966: 2302 movs r3, #2
8001968: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
800196a: 2300 movs r3, #0
800196c: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800196e: 2303 movs r3, #3
8001970: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001972: 230a movs r3, #10
8001974: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001976: f107 032c add.w r3, r7, #44 ; 0x2c
800197a: 4619 mov r1, r3
800197c: 4849 ldr r0, [pc, #292] ; (8001aa4 <MX_GPIO_Init+0x2f0>)
800197e: f005 fbbf bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : BP2_Pin BP1_Pin */
GPIO_InitStruct.Pin = BP2_Pin|BP1_Pin;
8001982: f44f 4301 mov.w r3, #33024 ; 0x8100
8001986: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001988: 2300 movs r3, #0
800198a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
800198c: 2300 movs r3, #0
800198e: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001990: f107 032c add.w r3, r7, #44 ; 0x2c
8001994: 4619 mov r1, r3
8001996: 4844 ldr r0, [pc, #272] ; (8001aa8 <MX_GPIO_Init+0x2f4>)
8001998: f005 fbb2 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : LED14_Pin LED15_Pin */
GPIO_InitStruct.Pin = LED14_Pin|LED15_Pin;
800199c: 2360 movs r3, #96 ; 0x60
800199e: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80019a0: 2301 movs r3, #1
80019a2: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
80019a4: 2300 movs r3, #0
80019a6: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80019a8: 2300 movs r3, #0
80019aa: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
80019ac: f107 032c add.w r3, r7, #44 ; 0x2c
80019b0: 4619 mov r1, r3
80019b2: 4836 ldr r0, [pc, #216] ; (8001a8c <MX_GPIO_Init+0x2d8>)
80019b4: f005 fba4 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : VCP_RX_Pin */
GPIO_InitStruct.Pin = VCP_RX_Pin;
80019b8: 2380 movs r3, #128 ; 0x80
80019ba: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80019bc: 2302 movs r3, #2
80019be: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
80019c0: 2300 movs r3, #0
80019c2: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80019c4: 2300 movs r3, #0
80019c6: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
80019c8: 2307 movs r3, #7
80019ca: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(VCP_RX_GPIO_Port, &GPIO_InitStruct);
80019cc: f107 032c add.w r3, r7, #44 ; 0x2c
80019d0: 4619 mov r1, r3
80019d2: 4834 ldr r0, [pc, #208] ; (8001aa4 <MX_GPIO_Init+0x2f0>)
80019d4: f005 fb94 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : OTG_FS_VBUS_Pin */
GPIO_InitStruct.Pin = OTG_FS_VBUS_Pin;
80019d8: f44f 5380 mov.w r3, #4096 ; 0x1000
80019dc: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80019de: 2300 movs r3, #0
80019e0: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
80019e2: 2300 movs r3, #0
80019e4: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);
80019e6: f107 032c add.w r3, r7, #44 ; 0x2c
80019ea: 4619 mov r1, r3
80019ec: 482f ldr r0, [pc, #188] ; (8001aac <MX_GPIO_Init+0x2f8>)
80019ee: f005 fb87 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : Audio_INT_Pin */
GPIO_InitStruct.Pin = Audio_INT_Pin;
80019f2: 2340 movs r3, #64 ; 0x40
80019f4: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
80019f6: 4b2e ldr r3, [pc, #184] ; (8001ab0 <MX_GPIO_Init+0x2fc>)
80019f8: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
80019fa: 2300 movs r3, #0
80019fc: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(Audio_INT_GPIO_Port, &GPIO_InitStruct);
80019fe: f107 032c add.w r3, r7, #44 ; 0x2c
8001a02: 4619 mov r1, r3
8001a04: 4822 ldr r0, [pc, #136] ; (8001a90 <MX_GPIO_Init+0x2dc>)
8001a06: f005 fb7b bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : OTG_FS_PowerSwitchOn_Pin LED16_Pin */
GPIO_InitStruct.Pin = OTG_FS_PowerSwitchOn_Pin|LED16_Pin;
8001a0a: 2328 movs r3, #40 ; 0x28
8001a0c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001a0e: 2301 movs r3, #1
8001a10: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a12: 2300 movs r3, #0
8001a14: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001a16: 2300 movs r3, #0
8001a18: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8001a1a: f107 032c add.w r3, r7, #44 ; 0x2c
8001a1e: 4619 mov r1, r3
8001a20: 481b ldr r0, [pc, #108] ; (8001a90 <MX_GPIO_Init+0x2dc>)
8001a22: f005 fb6d bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : LED3_Pin LCD_DISP_Pin */
GPIO_InitStruct.Pin = LED3_Pin|LCD_DISP_Pin;
8001a26: f241 0308 movw r3, #4104 ; 0x1008
8001a2a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001a2c: 2301 movs r3, #1
8001a2e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a30: 2300 movs r3, #0
8001a32: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001a34: 2300 movs r3, #0
8001a36: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8001a38: f107 032c add.w r3, r7, #44 ; 0x2c
8001a3c: 4619 mov r1, r3
8001a3e: 4815 ldr r0, [pc, #84] ; (8001a94 <MX_GPIO_Init+0x2e0>)
8001a40: f005 fb5e bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : uSD_Detect_Pin */
GPIO_InitStruct.Pin = uSD_Detect_Pin;
8001a44: f44f 5300 mov.w r3, #8192 ; 0x2000
8001a48: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001a4a: 2300 movs r3, #0
8001a4c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a4e: 2300 movs r3, #0
8001a50: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(uSD_Detect_GPIO_Port, &GPIO_InitStruct);
8001a52: f107 032c add.w r3, r7, #44 ; 0x2c
8001a56: 4619 mov r1, r3
8001a58: 4816 ldr r0, [pc, #88] ; (8001ab4 <MX_GPIO_Init+0x300>)
8001a5a: f005 fb51 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_BL_CTRL_Pin */
GPIO_InitStruct.Pin = LCD_BL_CTRL_Pin;
8001a5e: 2308 movs r3, #8
8001a60: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001a62: 2301 movs r3, #1
8001a64: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a66: 2300 movs r3, #0
8001a68: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001a6a: 2300 movs r3, #0
8001a6c: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(LCD_BL_CTRL_GPIO_Port, &GPIO_InitStruct);
8001a6e: f107 032c add.w r3, r7, #44 ; 0x2c
8001a72: 4619 mov r1, r3
8001a74: 4808 ldr r0, [pc, #32] ; (8001a98 <MX_GPIO_Init+0x2e4>)
8001a76: f005 fb43 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : OTG_FS_OverCurrent_Pin */
GPIO_InitStruct.Pin = OTG_FS_OverCurrent_Pin;
8001a7a: 2310 movs r3, #16
8001a7c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001a7e: 2300 movs r3, #0
8001a80: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a82: 2300 movs r3, #0
8001a84: 637b str r3, [r7, #52] ; 0x34
8001a86: e017 b.n 8001ab8 <MX_GPIO_Init+0x304>
8001a88: 40023800 .word 0x40023800
8001a8c: 40021000 .word 0x40021000
8001a90: 40020c00 .word 0x40020c00
8001a94: 40022000 .word 0x40022000
8001a98: 40022800 .word 0x40022800
8001a9c: 40021c00 .word 0x40021c00
8001aa0: 40021800 .word 0x40021800
8001aa4: 40020400 .word 0x40020400
8001aa8: 40020000 .word 0x40020000
8001aac: 40022400 .word 0x40022400
8001ab0: 10120000 .word 0x10120000
8001ab4: 40020800 .word 0x40020800
HAL_GPIO_Init(OTG_FS_OverCurrent_GPIO_Port, &GPIO_InitStruct);
8001ab8: f107 032c add.w r3, r7, #44 ; 0x2c
8001abc: 4619 mov r1, r3
8001abe: 4876 ldr r0, [pc, #472] ; (8001c98 <MX_GPIO_Init+0x4e4>)
8001ac0: f005 fb1e bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : TP3_Pin NC2_Pin */
GPIO_InitStruct.Pin = TP3_Pin|NC2_Pin;
8001ac4: f248 0304 movw r3, #32772 ; 0x8004
8001ac8: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001aca: 2300 movs r3, #0
8001acc: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ace: 2300 movs r3, #0
8001ad0: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001ad2: f107 032c add.w r3, r7, #44 ; 0x2c
8001ad6: 4619 mov r1, r3
8001ad8: 4870 ldr r0, [pc, #448] ; (8001c9c <MX_GPIO_Init+0x4e8>)
8001ada: f005 fb11 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : ARDUINO_SCK_D13_Pin */
GPIO_InitStruct.Pin = ARDUINO_SCK_D13_Pin;
8001ade: 2302 movs r3, #2
8001ae0: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001ae2: 2302 movs r3, #2
8001ae4: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ae6: 2300 movs r3, #0
8001ae8: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001aea: 2300 movs r3, #0
8001aec: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8001aee: 2305 movs r3, #5
8001af0: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(ARDUINO_SCK_D13_GPIO_Port, &GPIO_InitStruct);
8001af2: f107 032c add.w r3, r7, #44 ; 0x2c
8001af6: 4619 mov r1, r3
8001af8: 4869 ldr r0, [pc, #420] ; (8001ca0 <MX_GPIO_Init+0x4ec>)
8001afa: f005 fb01 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : LED13_Pin LED17_Pin LED11_Pin LED12_Pin
LED2_Pin LED18_Pin */
GPIO_InitStruct.Pin = LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin
8001afe: f645 6340 movw r3, #24128 ; 0x5e40
8001b02: 62fb str r3, [r7, #44] ; 0x2c
|LED2_Pin|LED18_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001b04: 2301 movs r3, #1
8001b06: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b08: 2300 movs r3, #0
8001b0a: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001b0c: 2300 movs r3, #0
8001b0e: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001b10: f107 032c add.w r3, r7, #44 ; 0x2c
8001b14: 4619 mov r1, r3
8001b16: 4861 ldr r0, [pc, #388] ; (8001c9c <MX_GPIO_Init+0x4e8>)
8001b18: f005 faf2 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : PI0 */
GPIO_InitStruct.Pin = GPIO_PIN_0;
8001b1c: 2301 movs r3, #1
8001b1e: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001b20: 2302 movs r3, #2
8001b22: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b24: 2300 movs r3, #0
8001b26: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001b28: 2303 movs r3, #3
8001b2a: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8001b2c: 2305 movs r3, #5
8001b2e: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8001b30: f107 032c add.w r3, r7, #44 ; 0x2c
8001b34: 4619 mov r1, r3
8001b36: 485a ldr r0, [pc, #360] ; (8001ca0 <MX_GPIO_Init+0x4ec>)
8001b38: f005 fae2 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : VCP_TX_Pin */
GPIO_InitStruct.Pin = VCP_TX_Pin;
8001b3c: f44f 7300 mov.w r3, #512 ; 0x200
8001b40: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001b42: 2302 movs r3, #2
8001b44: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b46: 2300 movs r3, #0
8001b48: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001b4a: 2300 movs r3, #0
8001b4c: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8001b4e: 2307 movs r3, #7
8001b50: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(VCP_TX_GPIO_Port, &GPIO_InitStruct);
8001b52: f107 032c add.w r3, r7, #44 ; 0x2c
8001b56: 4619 mov r1, r3
8001b58: 4852 ldr r0, [pc, #328] ; (8001ca4 <MX_GPIO_Init+0x4f0>)
8001b5a: f005 fad1 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_INT_Pin */
GPIO_InitStruct.Pin = LCD_INT_Pin;
8001b5e: f44f 5300 mov.w r3, #8192 ; 0x2000
8001b62: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
8001b64: 4b50 ldr r3, [pc, #320] ; (8001ca8 <MX_GPIO_Init+0x4f4>)
8001b66: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b68: 2300 movs r3, #0
8001b6a: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(LCD_INT_GPIO_Port, &GPIO_InitStruct);
8001b6c: f107 032c add.w r3, r7, #44 ; 0x2c
8001b70: 4619 mov r1, r3
8001b72: 484b ldr r0, [pc, #300] ; (8001ca0 <MX_GPIO_Init+0x4ec>)
8001b74: f005 fac4 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : PC7 PC6 */
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6;
8001b78: 23c0 movs r3, #192 ; 0xc0
8001b7a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001b7c: 2302 movs r3, #2
8001b7e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b80: 2300 movs r3, #0
8001b82: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001b84: 2303 movs r3, #3
8001b86: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
8001b88: 2308 movs r3, #8
8001b8a: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001b8c: f107 032c add.w r3, r7, #44 ; 0x2c
8001b90: 4619 mov r1, r3
8001b92: 4846 ldr r0, [pc, #280] ; (8001cac <MX_GPIO_Init+0x4f8>)
8001b94: f005 fab4 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : ULPI_NXT_Pin */
GPIO_InitStruct.Pin = ULPI_NXT_Pin;
8001b98: 2310 movs r3, #16
8001b9a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001b9c: 2302 movs r3, #2
8001b9e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ba0: 2300 movs r3, #0
8001ba2: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001ba4: 2303 movs r3, #3
8001ba6: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001ba8: 230a movs r3, #10
8001baa: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(ULPI_NXT_GPIO_Port, &GPIO_InitStruct);
8001bac: f107 032c add.w r3, r7, #44 ; 0x2c
8001bb0: 4619 mov r1, r3
8001bb2: 483a ldr r0, [pc, #232] ; (8001c9c <MX_GPIO_Init+0x4e8>)
8001bb4: f005 faa4 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : BP_JOYSTICK_Pin RMII_RXER_Pin */
GPIO_InitStruct.Pin = BP_JOYSTICK_Pin|RMII_RXER_Pin;
8001bb8: 2384 movs r3, #132 ; 0x84
8001bba: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001bbc: 2300 movs r3, #0
8001bbe: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bc0: 2300 movs r3, #0
8001bc2: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8001bc4: f107 032c add.w r3, r7, #44 ; 0x2c
8001bc8: 4619 mov r1, r3
8001bca: 4839 ldr r0, [pc, #228] ; (8001cb0 <MX_GPIO_Init+0x4fc>)
8001bcc: f005 fa98 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : PF7 */
GPIO_InitStruct.Pin = GPIO_PIN_7;
8001bd0: 2380 movs r3, #128 ; 0x80
8001bd2: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001bd4: 2302 movs r3, #2
8001bd6: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bd8: 2300 movs r3, #0
8001bda: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001bdc: 2303 movs r3, #3
8001bde: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF8_UART7;
8001be0: 2308 movs r3, #8
8001be2: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8001be4: f107 032c add.w r3, r7, #44 ; 0x2c
8001be8: 4619 mov r1, r3
8001bea: 4832 ldr r0, [pc, #200] ; (8001cb4 <MX_GPIO_Init+0x500>)
8001bec: f005 fa88 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : ULPI_STP_Pin ULPI_DIR_Pin */
GPIO_InitStruct.Pin = ULPI_STP_Pin|ULPI_DIR_Pin;
8001bf0: 2305 movs r3, #5
8001bf2: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001bf4: 2302 movs r3, #2
8001bf6: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bf8: 2300 movs r3, #0
8001bfa: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001bfc: 2303 movs r3, #3
8001bfe: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001c00: 230a movs r3, #10
8001c02: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001c04: f107 032c add.w r3, r7, #44 ; 0x2c
8001c08: 4619 mov r1, r3
8001c0a: 4828 ldr r0, [pc, #160] ; (8001cac <MX_GPIO_Init+0x4f8>)
8001c0c: f005 fa78 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pin : EXT_RST_Pin */
GPIO_InitStruct.Pin = EXT_RST_Pin;
8001c10: 2308 movs r3, #8
8001c12: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001c14: 2301 movs r3, #1
8001c16: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c18: 2300 movs r3, #0
8001c1a: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001c1c: 2300 movs r3, #0
8001c1e: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(EXT_RST_GPIO_Port, &GPIO_InitStruct);
8001c20: f107 032c add.w r3, r7, #44 ; 0x2c
8001c24: 4619 mov r1, r3
8001c26: 4822 ldr r0, [pc, #136] ; (8001cb0 <MX_GPIO_Init+0x4fc>)
8001c28: f005 fa6a bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : LCD_SCL_Pin LCD_SDA_Pin */
GPIO_InitStruct.Pin = LCD_SCL_Pin|LCD_SDA_Pin;
8001c2c: f44f 73c0 mov.w r3, #384 ; 0x180
8001c30: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8001c32: 2312 movs r3, #18
8001c34: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_PULLUP;
8001c36: 2301 movs r3, #1
8001c38: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001c3a: 2303 movs r3, #3
8001c3c: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8001c3e: 2304 movs r3, #4
8001c40: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001c42: f107 032c add.w r3, r7, #44 ; 0x2c
8001c46: 4619 mov r1, r3
8001c48: 4814 ldr r0, [pc, #80] ; (8001c9c <MX_GPIO_Init+0x4e8>)
8001c4a: f005 fa59 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : ULPI_CLK_Pin ULPI_D0_Pin */
GPIO_InitStruct.Pin = ULPI_CLK_Pin|ULPI_D0_Pin;
8001c4e: 2328 movs r3, #40 ; 0x28
8001c50: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001c52: 2302 movs r3, #2
8001c54: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c56: 2300 movs r3, #0
8001c58: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001c5a: 2303 movs r3, #3
8001c5c: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001c5e: 230a movs r3, #10
8001c60: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001c62: f107 032c add.w r3, r7, #44 ; 0x2c
8001c66: 4619 mov r1, r3
8001c68: 480e ldr r0, [pc, #56] ; (8001ca4 <MX_GPIO_Init+0x4f0>)
8001c6a: f005 fa49 bl 8007100 <HAL_GPIO_Init>
/*Configure GPIO pins : PB14 PB15 */
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
8001c6e: f44f 4340 mov.w r3, #49152 ; 0xc000
8001c72: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001c74: 2302 movs r3, #2
8001c76: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c78: 2300 movs r3, #0
8001c7a: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001c7c: 2303 movs r3, #3
8001c7e: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8001c80: 2305 movs r3, #5
8001c82: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001c84: f107 032c add.w r3, r7, #44 ; 0x2c
8001c88: 4619 mov r1, r3
8001c8a: 480b ldr r0, [pc, #44] ; (8001cb8 <MX_GPIO_Init+0x504>)
8001c8c: f005 fa38 bl 8007100 <HAL_GPIO_Init>
}
8001c90: bf00 nop
8001c92: 3740 adds r7, #64 ; 0x40
8001c94: 46bd mov sp, r7
8001c96: bd80 pop {r7, pc}
8001c98: 40020c00 .word 0x40020c00
8001c9c: 40021c00 .word 0x40021c00
8001ca0: 40022000 .word 0x40022000
8001ca4: 40020000 .word 0x40020000
8001ca8: 10120000 .word 0x10120000
8001cac: 40020800 .word 0x40020800
8001cb0: 40021800 .word 0x40021800
8001cb4: 40021400 .word 0x40021400
8001cb8: 40020400 .word 0x40020400
08001cbc <repopulate_ennemie_list>:
//socket socket_udp = udp_new();
return 0;
}
void repopulate_ennemie_list(uint8_t wave)
{
8001cbc: b590 push {r4, r7, lr}
8001cbe: b087 sub sp, #28
8001cc0: af00 add r7, sp, #0
8001cc2: 4603 mov r3, r0
8001cc4: 71fb strb r3, [r7, #7]
int idx1;
int idx2;
uint32_t nombre_aleatoire;
if (HAL_RNG_GenerateRandomNumber(&hrng, &nombre_aleatoire) != HAL_OK)
8001cc6: f107 030c add.w r3, r7, #12
8001cca: 4619 mov r1, r3
8001ccc: 4870 ldr r0, [pc, #448] ; (8001e90 <repopulate_ennemie_list+0x1d4>)
8001cce: f007 fd93 bl 80097f8 <HAL_RNG_GenerateRandomNumber>
8001cd2: 4603 mov r3, r0
8001cd4: 2b00 cmp r3, #0
8001cd6: d002 beq.n 8001cde <repopulate_ennemie_list+0x22>
{
nombre_aleatoire = 0xFFFFFFFF;
8001cd8: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8001cdc: 60fb str r3, [r7, #12]
}
for (idx1 = 0; idx1 < 8; idx1++)
8001cde: 2300 movs r3, #0
8001ce0: 617b str r3, [r7, #20]
8001ce2: e0cb b.n 8001e7c <repopulate_ennemie_list+0x1c0>
{
for (idx2 = 0; idx2 < 3; idx2++)
8001ce4: 2300 movs r3, #0
8001ce6: 613b str r3, [r7, #16]
8001ce8: e0c1 b.n 8001e6e <repopulate_ennemie_list+0x1b2>
{
Table_ennemie[idx1][idx2].x = (2 * idx1 + 1) * monstre_width;
8001cea: 697b ldr r3, [r7, #20]
8001cec: 005b lsls r3, r3, #1
8001cee: 3301 adds r3, #1
8001cf0: 2214 movs r2, #20
8001cf2: fb02 f303 mul.w r3, r2, r3
8001cf6: 461c mov r4, r3
8001cf8: 4866 ldr r0, [pc, #408] ; (8001e94 <repopulate_ennemie_list+0x1d8>)
8001cfa: 693a ldr r2, [r7, #16]
8001cfc: 6979 ldr r1, [r7, #20]
8001cfe: 4613 mov r3, r2
8001d00: 00db lsls r3, r3, #3
8001d02: 1a9b subs r3, r3, r2
8001d04: 009b lsls r3, r3, #2
8001d06: 2254 movs r2, #84 ; 0x54
8001d08: fb02 f201 mul.w r2, r2, r1
8001d0c: 4413 add r3, r2
8001d0e: 4403 add r3, r0
8001d10: 601c str r4, [r3, #0]
Table_ennemie[idx1][idx2].y = (2 * idx1 + 1) * monstre_height;
8001d12: 697b ldr r3, [r7, #20]
8001d14: 005b lsls r3, r3, #1
8001d16: 3301 adds r3, #1
8001d18: 2214 movs r2, #20
8001d1a: fb02 f303 mul.w r3, r2, r3
8001d1e: 461c mov r4, r3
8001d20: 485c ldr r0, [pc, #368] ; (8001e94 <repopulate_ennemie_list+0x1d8>)
8001d22: 693a ldr r2, [r7, #16]
8001d24: 6979 ldr r1, [r7, #20]
8001d26: 4613 mov r3, r2
8001d28: 00db lsls r3, r3, #3
8001d2a: 1a9b subs r3, r3, r2
8001d2c: 009b lsls r3, r3, #2
8001d2e: 2254 movs r2, #84 ; 0x54
8001d30: fb02 f201 mul.w r2, r2, r1
8001d34: 4413 add r3, r2
8001d36: 4403 add r3, r0
8001d38: 3304 adds r3, #4
8001d3a: 601c str r4, [r3, #0]
Table_ennemie[idx1][idx2].health = wave / 2 + 1;
8001d3c: 79fb ldrb r3, [r7, #7]
8001d3e: 085b lsrs r3, r3, #1
8001d40: b2db uxtb r3, r3
8001d42: 3301 adds r3, #1
8001d44: b2db uxtb r3, r3
8001d46: b25c sxtb r4, r3
8001d48: 4852 ldr r0, [pc, #328] ; (8001e94 <repopulate_ennemie_list+0x1d8>)
8001d4a: 693a ldr r2, [r7, #16]
8001d4c: 6979 ldr r1, [r7, #20]
8001d4e: 4613 mov r3, r2
8001d50: 00db lsls r3, r3, #3
8001d52: 1a9b subs r3, r3, r2
8001d54: 009b lsls r3, r3, #2
8001d56: 2254 movs r2, #84 ; 0x54
8001d58: fb02 f201 mul.w r2, r2, r1
8001d5c: 4413 add r3, r2
8001d5e: 4403 add r3, r0
8001d60: 3308 adds r3, #8
8001d62: 4622 mov r2, r4
8001d64: 701a strb r2, [r3, #0]
Table_ennemie[idx1][idx2].missile.x = 0;
8001d66: 484b ldr r0, [pc, #300] ; (8001e94 <repopulate_ennemie_list+0x1d8>)
8001d68: 693a ldr r2, [r7, #16]
8001d6a: 6979 ldr r1, [r7, #20]
8001d6c: 4613 mov r3, r2
8001d6e: 00db lsls r3, r3, #3
8001d70: 1a9b subs r3, r3, r2
8001d72: 009b lsls r3, r3, #2
8001d74: 2254 movs r2, #84 ; 0x54
8001d76: fb02 f201 mul.w r2, r2, r1
8001d7a: 4413 add r3, r2
8001d7c: 4403 add r3, r0
8001d7e: 330c adds r3, #12
8001d80: 2200 movs r2, #0
8001d82: 801a strh r2, [r3, #0]
Table_ennemie[idx1][idx2].missile.y = 0;
8001d84: 4843 ldr r0, [pc, #268] ; (8001e94 <repopulate_ennemie_list+0x1d8>)
8001d86: 693a ldr r2, [r7, #16]
8001d88: 6979 ldr r1, [r7, #20]
8001d8a: 4613 mov r3, r2
8001d8c: 00db lsls r3, r3, #3
8001d8e: 1a9b subs r3, r3, r2
8001d90: 009b lsls r3, r3, #2
8001d92: 2254 movs r2, #84 ; 0x54
8001d94: fb02 f201 mul.w r2, r2, r1
8001d98: 4413 add r3, r2
8001d9a: 4403 add r3, r0
8001d9c: 330e adds r3, #14
8001d9e: 2200 movs r2, #0
8001da0: 801a strh r2, [r3, #0]
Table_ennemie[idx1][idx2].missile.dx = 1;
8001da2: 483c ldr r0, [pc, #240] ; (8001e94 <repopulate_ennemie_list+0x1d8>)
8001da4: 693a ldr r2, [r7, #16]
8001da6: 6979 ldr r1, [r7, #20]
8001da8: 4613 mov r3, r2
8001daa: 00db lsls r3, r3, #3
8001dac: 1a9b subs r3, r3, r2
8001dae: 009b lsls r3, r3, #2
8001db0: 2254 movs r2, #84 ; 0x54
8001db2: fb02 f201 mul.w r2, r2, r1
8001db6: 4413 add r3, r2
8001db8: 4403 add r3, r0
8001dba: 3310 adds r3, #16
8001dbc: 2201 movs r2, #1
8001dbe: 701a strb r2, [r3, #0]
Table_ennemie[idx1][idx2].missile.dy = 0;
8001dc0: 4834 ldr r0, [pc, #208] ; (8001e94 <repopulate_ennemie_list+0x1d8>)
8001dc2: 693a ldr r2, [r7, #16]
8001dc4: 6979 ldr r1, [r7, #20]
8001dc6: 4613 mov r3, r2
8001dc8: 00db lsls r3, r3, #3
8001dca: 1a9b subs r3, r3, r2
8001dcc: 009b lsls r3, r3, #2
8001dce: 2254 movs r2, #84 ; 0x54
8001dd0: fb02 f201 mul.w r2, r2, r1
8001dd4: 4413 add r3, r2
8001dd6: 4403 add r3, r0
8001dd8: 3311 adds r3, #17
8001dda: 2200 movs r2, #0
8001ddc: 701a strb r2, [r3, #0]
Table_ennemie[idx1][idx2].missile.equipe = 0;
8001dde: 482d ldr r0, [pc, #180] ; (8001e94 <repopulate_ennemie_list+0x1d8>)
8001de0: 693a ldr r2, [r7, #16]
8001de2: 6979 ldr r1, [r7, #20]
8001de4: 4613 mov r3, r2
8001de6: 00db lsls r3, r3, #3
8001de8: 1a9b subs r3, r3, r2
8001dea: 009b lsls r3, r3, #2
8001dec: 2254 movs r2, #84 ; 0x54
8001dee: fb02 f201 mul.w r2, r2, r1
8001df2: 4413 add r3, r2
8001df4: 4403 add r3, r0
8001df6: 3312 adds r3, #18
8001df8: 2200 movs r2, #0
8001dfa: 701a strb r2, [r3, #0]
Table_ennemie[idx1][idx2].missile.damage = 1;
8001dfc: 4825 ldr r0, [pc, #148] ; (8001e94 <repopulate_ennemie_list+0x1d8>)
8001dfe: 693a ldr r2, [r7, #16]
8001e00: 6979 ldr r1, [r7, #20]
8001e02: 4613 mov r3, r2
8001e04: 00db lsls r3, r3, #3
8001e06: 1a9b subs r3, r3, r2
8001e08: 009b lsls r3, r3, #2
8001e0a: 2254 movs r2, #84 ; 0x54
8001e0c: fb02 f201 mul.w r2, r2, r1
8001e10: 4413 add r3, r2
8001e12: 4403 add r3, r0
8001e14: 3318 adds r3, #24
8001e16: 2201 movs r2, #1
8001e18: 701a strb r2, [r3, #0]
Table_ennemie[idx1][idx2].missile.valide = 1;
8001e1a: 481e ldr r0, [pc, #120] ; (8001e94 <repopulate_ennemie_list+0x1d8>)
8001e1c: 693a ldr r2, [r7, #16]
8001e1e: 6979 ldr r1, [r7, #20]
8001e20: 4613 mov r3, r2
8001e22: 00db lsls r3, r3, #3
8001e24: 1a9b subs r3, r3, r2
8001e26: 009b lsls r3, r3, #2
8001e28: 2254 movs r2, #84 ; 0x54
8001e2a: fb02 f201 mul.w r2, r2, r1
8001e2e: 4413 add r3, r2
8001e30: 4403 add r3, r0
8001e32: 3319 adds r3, #25
8001e34: 2201 movs r2, #1
8001e36: 701a strb r2, [r3, #0]
if ((nombre_aleatoire >> (idx1 * 8 + idx2)) && 1)
8001e38: 68fa ldr r2, [r7, #12]
8001e3a: 697b ldr r3, [r7, #20]
8001e3c: 00d9 lsls r1, r3, #3
8001e3e: 693b ldr r3, [r7, #16]
8001e40: 440b add r3, r1
8001e42: fa22 f303 lsr.w r3, r2, r3
8001e46: 2b00 cmp r3, #0
8001e48: d00e beq.n 8001e68 <repopulate_ennemie_list+0x1ac>
Table_ennemie[idx1][idx2].health = 0;
8001e4a: 4812 ldr r0, [pc, #72] ; (8001e94 <repopulate_ennemie_list+0x1d8>)
8001e4c: 693a ldr r2, [r7, #16]
8001e4e: 6979 ldr r1, [r7, #20]
8001e50: 4613 mov r3, r2
8001e52: 00db lsls r3, r3, #3
8001e54: 1a9b subs r3, r3, r2
8001e56: 009b lsls r3, r3, #2
8001e58: 2254 movs r2, #84 ; 0x54
8001e5a: fb02 f201 mul.w r2, r2, r1
8001e5e: 4413 add r3, r2
8001e60: 4403 add r3, r0
8001e62: 3308 adds r3, #8
8001e64: 2200 movs r2, #0
8001e66: 701a strb r2, [r3, #0]
for (idx2 = 0; idx2 < 3; idx2++)
8001e68: 693b ldr r3, [r7, #16]
8001e6a: 3301 adds r3, #1
8001e6c: 613b str r3, [r7, #16]
8001e6e: 693b ldr r3, [r7, #16]
8001e70: 2b02 cmp r3, #2
8001e72: f77f af3a ble.w 8001cea <repopulate_ennemie_list+0x2e>
for (idx1 = 0; idx1 < 8; idx1++)
8001e76: 697b ldr r3, [r7, #20]
8001e78: 3301 adds r3, #1
8001e7a: 617b str r3, [r7, #20]
8001e7c: 697b ldr r3, [r7, #20]
8001e7e: 2b07 cmp r3, #7
8001e80: f77f af30 ble.w 8001ce4 <repopulate_ennemie_list+0x28>
}
}
}
8001e84: bf00 nop
8001e86: bf00 nop
8001e88: 371c adds r7, #28
8001e8a: 46bd mov sp, r7
8001e8c: bd90 pop {r4, r7, pc}
8001e8e: bf00 nop
8001e90: 20008b28 .word 0x20008b28
8001e94: 20008b7c .word 0x20008b7c
08001e98 <lcd_plot_rect>:
* @brief Encapsulation du tracer d'un rectangle
* @param pos_x
* @retval None
*/
void lcd_plot_rect(uint16_t pos_x, uint16_t pos_y, uint16_t taille_x, uint16_t taille_y, uint32_t color)
{
8001e98: b590 push {r4, r7, lr}
8001e9a: b083 sub sp, #12
8001e9c: af00 add r7, sp, #0
8001e9e: 4604 mov r4, r0
8001ea0: 4608 mov r0, r1
8001ea2: 4611 mov r1, r2
8001ea4: 461a mov r2, r3
8001ea6: 4623 mov r3, r4
8001ea8: 80fb strh r3, [r7, #6]
8001eaa: 4603 mov r3, r0
8001eac: 80bb strh r3, [r7, #4]
8001eae: 460b mov r3, r1
8001eb0: 807b strh r3, [r7, #2]
8001eb2: 4613 mov r3, r2
8001eb4: 803b strh r3, [r7, #0]
while (xSemaphoreTake(MutexLCDHandle, (TickType_t)10) != pdPASS)
8001eb6: bf00 nop
8001eb8: 4b0e ldr r3, [pc, #56] ; (8001ef4 <lcd_plot_rect+0x5c>)
8001eba: 681b ldr r3, [r3, #0]
8001ebc: 210a movs r1, #10
8001ebe: 4618 mov r0, r3
8001ec0: f00a fda8 bl 800ca14 <xQueueSemaphoreTake>
8001ec4: 4603 mov r3, r0
8001ec6: 2b01 cmp r3, #1
8001ec8: d1f6 bne.n 8001eb8 <lcd_plot_rect+0x20>
;
BSP_LCD_SetTextColor(color);
8001eca: 69b8 ldr r0, [r7, #24]
8001ecc: f000 fe88 bl 8002be0 <BSP_LCD_SetTextColor>
BSP_LCD_FillRect(pos_x, pos_y, taille_x, taille_y);
8001ed0: 883b ldrh r3, [r7, #0]
8001ed2: 887a ldrh r2, [r7, #2]
8001ed4: 88b9 ldrh r1, [r7, #4]
8001ed6: 88f8 ldrh r0, [r7, #6]
8001ed8: f001 f886 bl 8002fe8 <BSP_LCD_FillRect>
xSemaphoreGive(MutexLCDHandle);
8001edc: 4b05 ldr r3, [pc, #20] ; (8001ef4 <lcd_plot_rect+0x5c>)
8001ede: 6818 ldr r0, [r3, #0]
8001ee0: 2300 movs r3, #0
8001ee2: 2200 movs r2, #0
8001ee4: 2100 movs r1, #0
8001ee6: f00a fa73 bl 800c3d0 <xQueueGenericSend>
}
8001eea: bf00 nop
8001eec: 370c adds r7, #12
8001eee: 46bd mov sp, r7
8001ef0: bd90 pop {r4, r7, pc}
8001ef2: bf00 nop
8001ef4: 20008934 .word 0x20008934
08001ef8 <colision_missile>:
uint8_t colision_missile(uint16_t m_pos_x, uint16_t m_pos_y, uint16_t o_pos_x, uint16_t o_pos_y, uint16_t o_taille_x, uint16_t o_taille_y)
{
8001ef8: b490 push {r4, r7}
8001efa: b082 sub sp, #8
8001efc: af00 add r7, sp, #0
8001efe: 4604 mov r4, r0
8001f00: 4608 mov r0, r1
8001f02: 4611 mov r1, r2
8001f04: 461a mov r2, r3
8001f06: 4623 mov r3, r4
8001f08: 80fb strh r3, [r7, #6]
8001f0a: 4603 mov r3, r0
8001f0c: 80bb strh r3, [r7, #4]
8001f0e: 460b mov r3, r1
8001f10: 807b strh r3, [r7, #2]
8001f12: 4613 mov r3, r2
8001f14: 803b strh r3, [r7, #0]
return ((m_pos_x > o_pos_x) & (m_pos_x < o_pos_x + o_taille_x) & (m_pos_y > o_pos_y) & (m_pos_y < o_pos_y + o_taille_y));
8001f16: 88fa ldrh r2, [r7, #6]
8001f18: 887b ldrh r3, [r7, #2]
8001f1a: 429a cmp r2, r3
8001f1c: bf8c ite hi
8001f1e: 2301 movhi r3, #1
8001f20: 2300 movls r3, #0
8001f22: b2da uxtb r2, r3
8001f24: 88f9 ldrh r1, [r7, #6]
8001f26: 8878 ldrh r0, [r7, #2]
8001f28: 8a3b ldrh r3, [r7, #16]
8001f2a: 4403 add r3, r0
8001f2c: 4299 cmp r1, r3
8001f2e: bfb4 ite lt
8001f30: 2301 movlt r3, #1
8001f32: 2300 movge r3, #0
8001f34: b2db uxtb r3, r3
8001f36: 4013 ands r3, r2
8001f38: b2db uxtb r3, r3
8001f3a: b25a sxtb r2, r3
8001f3c: 88b9 ldrh r1, [r7, #4]
8001f3e: 883b ldrh r3, [r7, #0]
8001f40: 4299 cmp r1, r3
8001f42: bf8c ite hi
8001f44: 2301 movhi r3, #1
8001f46: 2300 movls r3, #0
8001f48: b2db uxtb r3, r3
8001f4a: b25b sxtb r3, r3
8001f4c: 4013 ands r3, r2
8001f4e: b25a sxtb r2, r3
8001f50: 88b9 ldrh r1, [r7, #4]
8001f52: 8838 ldrh r0, [r7, #0]
8001f54: 8abb ldrh r3, [r7, #20]
8001f56: 4403 add r3, r0
8001f58: 4299 cmp r1, r3
8001f5a: bfb4 ite lt
8001f5c: 2301 movlt r3, #1
8001f5e: 2300 movge r3, #0
8001f60: b2db uxtb r3, r3
8001f62: b25b sxtb r3, r3
8001f64: 4013 ands r3, r2
8001f66: b25b sxtb r3, r3
8001f68: b2db uxtb r3, r3
}
8001f6a: 4618 mov r0, r3
8001f6c: 3708 adds r7, #8
8001f6e: 46bd mov sp, r7
8001f70: bc90 pop {r4, r7}
8001f72: 4770 bx lr
08001f74 <f_GameMaster>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_f_GameMaster */
void f_GameMaster(void const * argument)
{
8001f74: b580 push {r7, lr}
8001f76: b086 sub sp, #24
8001f78: af00 add r7, sp, #0
8001f7a: 6078 str r0, [r7, #4]
/* init code for LWIP */
MX_LWIP_Init();
8001f7c: f009 f816 bl 800afac <MX_LWIP_Init>
/* USER CODE BEGIN 5 */
TickType_t xLastWakeTime;
const TickType_t xPeriodeTache = 100 / portTICK_PERIOD_MS;
8001f80: 2364 movs r3, #100 ; 0x64
8001f82: 613b str r3, [r7, #16]
// Si la variable end est à 1, le jeu s'arrete.
uint8_t end = 0;
8001f84: 2300 movs r3, #0
8001f86: 73fb strb r3, [r7, #15]
uint8_t wave = 0;
8001f88: 2300 movs r3, #0
8001f8a: 75fb strb r3, [r7, #23]
repopulate_ennemie_list(wave);
8001f8c: 7dfb ldrb r3, [r7, #23]
8001f8e: 4618 mov r0, r3
8001f90: f7ff fe94 bl 8001cbc <repopulate_ennemie_list>
/* Infinite loop */
for (;;)
{
while (xQueueReceive(Queue_FHandle, &end, (TickType_t)10) != pdPASS)
8001f94: bf00 nop
8001f96: 4b14 ldr r3, [pc, #80] ; (8001fe8 <f_GameMaster+0x74>)
8001f98: 681b ldr r3, [r3, #0]
8001f9a: f107 010f add.w r1, r7, #15
8001f9e: 220a movs r2, #10
8001fa0: 4618 mov r0, r3
8001fa2: f00a fc51 bl 800c848 <xQueueReceive>
8001fa6: 4603 mov r3, r0
8001fa8: 2b01 cmp r3, #1
8001faa: d1f4 bne.n 8001f96 <f_GameMaster+0x22>
; // Tant qu'il n'y a pas de nouveau message
if (end == 1)
8001fac: 7bfb ldrb r3, [r7, #15]
8001fae: 2b01 cmp r3, #1
8001fb0: d10e bne.n 8001fd0 <f_GameMaster+0x5c>
{
vTaskDelete(Block_EnemieHandle);
8001fb2: 4b0e ldr r3, [pc, #56] ; (8001fec <f_GameMaster+0x78>)
8001fb4: 681b ldr r3, [r3, #0]
8001fb6: 4618 mov r0, r3
8001fb8: f00b f994 bl 800d2e4 <vTaskDelete>
vTaskDelete(ProjectileHandle);
8001fbc: 4b0c ldr r3, [pc, #48] ; (8001ff0 <f_GameMaster+0x7c>)
8001fbe: 681b ldr r3, [r3, #0]
8001fc0: 4618 mov r0, r3
8001fc2: f00b f98f bl 800d2e4 <vTaskDelete>
vTaskDelete(Joueur_1Handle);
8001fc6: 4b0b ldr r3, [pc, #44] ; (8001ff4 <f_GameMaster+0x80>)
8001fc8: 681b ldr r3, [r3, #0]
8001fca: 4618 mov r0, r3
8001fcc: f00b f98a bl 800d2e4 <vTaskDelete>
//TODO L'affichage de l'écran de fin et des scores
}
if (end == 0)
8001fd0: 7bfb ldrb r3, [r7, #15]
8001fd2: 2b00 cmp r3, #0
8001fd4: d1de bne.n 8001f94 <f_GameMaster+0x20>
{
wave++;
8001fd6: 7dfb ldrb r3, [r7, #23]
8001fd8: 3301 adds r3, #1
8001fda: 75fb strb r3, [r7, #23]
repopulate_ennemie_list(wave);
8001fdc: 7dfb ldrb r3, [r7, #23]
8001fde: 4618 mov r0, r3
8001fe0: f7ff fe6c bl 8001cbc <repopulate_ennemie_list>
while (xQueueReceive(Queue_FHandle, &end, (TickType_t)10) != pdPASS)
8001fe4: e7d6 b.n 8001f94 <f_GameMaster+0x20>
8001fe6: bf00 nop
8001fe8: 20008ac0 .word 0x20008ac0
8001fec: 20008ea0 .word 0x20008ea0
8001ff0: 20008ad8 .word 0x20008ad8
8001ff4: 200088e4 .word 0x200088e4
08001ff8 <f_Joueur_1>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_f_Joueur_1 */
void f_Joueur_1(void const * argument)
{
8001ff8: b590 push {r4, r7, lr}
8001ffa: b09b sub sp, #108 ; 0x6c
8001ffc: af02 add r7, sp, #8
8001ffe: 6078 str r0, [r7, #4]
/* USER CODE BEGIN f_Joueur_1 */
TickType_t xLastWakeTime;
const TickType_t xPeriodeTache = 100 / portTICK_PERIOD_MS;
8002000: 2364 movs r3, #100 ; 0x64
8002002: 65fb str r3, [r7, #92] ; 0x5c
uint32_t joystick_h, joystick_v;
uint8_t stop = 1;
8002004: 2301 movs r3, #1
8002006: f887 303f strb.w r3, [r7, #63] ; 0x3f
struct Missile missile;
ADC_ChannelConfTypeDef sConfig3 = {0};
800200a: f107 031c add.w r3, r7, #28
800200e: 2200 movs r2, #0
8002010: 601a str r2, [r3, #0]
8002012: 605a str r2, [r3, #4]
8002014: 609a str r2, [r3, #8]
8002016: 60da str r2, [r3, #12]
sConfig3.Rank = ADC_REGULAR_RANK_1;
8002018: 2301 movs r3, #1
800201a: 623b str r3, [r7, #32]
sConfig3.SamplingTime = ADC_SAMPLETIME_3CYCLES;
800201c: 2300 movs r3, #0
800201e: 627b str r3, [r7, #36] ; 0x24
sConfig3.Channel = ADC_CHANNEL_8;
8002020: 2308 movs r3, #8
8002022: 61fb str r3, [r7, #28]
HAL_ADC_ConfigChannel(&hadc3, &sConfig3);
8002024: f107 031c add.w r3, r7, #28
8002028: 4619 mov r1, r3
800202a: 4878 ldr r0, [pc, #480] ; (800220c <f_Joueur_1+0x214>)
800202c: f002 fdaa bl 8004b84 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8002030: 4876 ldr r0, [pc, #472] ; (800220c <f_Joueur_1+0x214>)
8002032: f002 fc41 bl 80048b8 <HAL_ADC_Start>
ADC_ChannelConfTypeDef sConfig1 = {0};
8002036: f107 030c add.w r3, r7, #12
800203a: 2200 movs r2, #0
800203c: 601a str r2, [r3, #0]
800203e: 605a str r2, [r3, #4]
8002040: 609a str r2, [r3, #8]
8002042: 60da str r2, [r3, #12]
sConfig1.Rank = ADC_REGULAR_RANK_1;
8002044: 2301 movs r3, #1
8002046: 613b str r3, [r7, #16]
sConfig1.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8002048: 2300 movs r3, #0
800204a: 617b str r3, [r7, #20]
sConfig1.Channel = ADC_CHANNEL_0;
800204c: 2300 movs r3, #0
800204e: 60fb str r3, [r7, #12]
HAL_ADC_ConfigChannel(&hadc1, &sConfig1);
8002050: f107 030c add.w r3, r7, #12
8002054: 4619 mov r1, r3
8002056: 486e ldr r0, [pc, #440] ; (8002210 <f_Joueur_1+0x218>)
8002058: f002 fd94 bl 8004b84 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc1);
800205c: 486c ldr r0, [pc, #432] ; (8002210 <f_Joueur_1+0x218>)
800205e: f002 fc2b bl 80048b8 <HAL_ADC_Start>
// Paramètre de l'écran pour la reprouductibilité
uint32_t LCD_HEIGHT = BSP_LCD_GetXSize();
8002062: f000 fd25 bl 8002ab0 <BSP_LCD_GetXSize>
8002066: 65b8 str r0, [r7, #88] ; 0x58
uint32_t LCD_WIDTH = BSP_LCD_GetYSize();
8002068: f000 fd36 bl 8002ad8 <BSP_LCD_GetYSize>
800206c: 6578 str r0, [r7, #84] ; 0x54
const uint32_t seuil_joystick = 200;
800206e: 23c8 movs r3, #200 ; 0xc8
8002070: 653b str r3, [r7, #80] ; 0x50
const uint32_t centre_joystick = 2048;
8002072: f44f 6300 mov.w r3, #2048 ; 0x800
8002076: 64fb str r3, [r7, #76] ; 0x4c
/* Infinite loop */
for (;;)
{
lcd_plot_rect(joueur.x, joueur.y, joueur_width, joueur_height, Couleur_vide);
8002078: 4b66 ldr r3, [pc, #408] ; (8002214 <f_Joueur_1+0x21c>)
800207a: 681b ldr r3, [r3, #0]
800207c: b298 uxth r0, r3
800207e: 4b65 ldr r3, [pc, #404] ; (8002214 <f_Joueur_1+0x21c>)
8002080: 685b ldr r3, [r3, #4]
8002082: b299 uxth r1, r3
8002084: 2214 movs r2, #20
8002086: 2414 movs r4, #20
8002088: f04f 437f mov.w r3, #4278190080 ; 0xff000000
800208c: 9300 str r3, [sp, #0]
800208e: 4623 mov r3, r4
8002090: f7ff ff02 bl 8001e98 <lcd_plot_rect>
// BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp)
HAL_ADC_ConfigChannel(&hadc3, &sConfig3);
8002094: f107 031c add.w r3, r7, #28
8002098: 4619 mov r1, r3
800209a: 485c ldr r0, [pc, #368] ; (800220c <f_Joueur_1+0x214>)
800209c: f002 fd72 bl 8004b84 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
80020a0: 485a ldr r0, [pc, #360] ; (800220c <f_Joueur_1+0x214>)
80020a2: f002 fc09 bl 80048b8 <HAL_ADC_Start>
while (HAL_ADC_PollForConversion(&hadc3, 100) != HAL_OK)
80020a6: bf00 nop
80020a8: 2164 movs r1, #100 ; 0x64
80020aa: 4858 ldr r0, [pc, #352] ; (800220c <f_Joueur_1+0x214>)
80020ac: f002 fcd2 bl 8004a54 <HAL_ADC_PollForConversion>
80020b0: 4603 mov r3, r0
80020b2: 2b00 cmp r3, #0
80020b4: d1f8 bne.n 80020a8 <f_Joueur_1+0xb0>
;
joystick_h = HAL_ADC_GetValue(&hadc3);
80020b6: 4855 ldr r0, [pc, #340] ; (800220c <f_Joueur_1+0x214>)
80020b8: f002 fd57 bl 8004b6a <HAL_ADC_GetValue>
80020bc: 64b8 str r0, [r7, #72] ; 0x48
HAL_ADC_ConfigChannel(&hadc1, &sConfig1);
80020be: f107 030c add.w r3, r7, #12
80020c2: 4619 mov r1, r3
80020c4: 4852 ldr r0, [pc, #328] ; (8002210 <f_Joueur_1+0x218>)
80020c6: f002 fd5d bl 8004b84 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc1);
80020ca: 4851 ldr r0, [pc, #324] ; (8002210 <f_Joueur_1+0x218>)
80020cc: f002 fbf4 bl 80048b8 <HAL_ADC_Start>
while (HAL_ADC_PollForConversion(&hadc1, 100) != HAL_OK)
80020d0: bf00 nop
80020d2: 2164 movs r1, #100 ; 0x64
80020d4: 484e ldr r0, [pc, #312] ; (8002210 <f_Joueur_1+0x218>)
80020d6: f002 fcbd bl 8004a54 <HAL_ADC_PollForConversion>
80020da: 4603 mov r3, r0
80020dc: 2b00 cmp r3, #0
80020de: d1f8 bne.n 80020d2 <f_Joueur_1+0xda>
;
joystick_v = HAL_ADC_GetValue(&hadc1);
80020e0: 484b ldr r0, [pc, #300] ; (8002210 <f_Joueur_1+0x218>)
80020e2: f002 fd42 bl 8004b6a <HAL_ADC_GetValue>
80020e6: 6478 str r0, [r7, #68] ; 0x44
if ((joueur.y < LCD_WIDTH - joueur_width - joueur.dy) && (joystick_h < centre_joystick - seuil_joystick))
80020e8: 4b4a ldr r3, [pc, #296] ; (8002214 <f_Joueur_1+0x21c>)
80020ea: 685a ldr r2, [r3, #4]
80020ec: 2314 movs r3, #20
80020ee: 4619 mov r1, r3
80020f0: 6d7b ldr r3, [r7, #84] ; 0x54
80020f2: 1a5b subs r3, r3, r1
80020f4: 4947 ldr r1, [pc, #284] ; (8002214 <f_Joueur_1+0x21c>)
80020f6: f991 1009 ldrsb.w r1, [r1, #9]
80020fa: 1a5b subs r3, r3, r1
80020fc: 429a cmp r2, r3
80020fe: d20d bcs.n 800211c <f_Joueur_1+0x124>
8002100: 6cfa ldr r2, [r7, #76] ; 0x4c
8002102: 6d3b ldr r3, [r7, #80] ; 0x50
8002104: 1ad3 subs r3, r2, r3
8002106: 6cba ldr r2, [r7, #72] ; 0x48
8002108: 429a cmp r2, r3
800210a: d207 bcs.n 800211c <f_Joueur_1+0x124>
joueur.y += joueur.dy;
800210c: 4b41 ldr r3, [pc, #260] ; (8002214 <f_Joueur_1+0x21c>)
800210e: 685b ldr r3, [r3, #4]
8002110: 4a40 ldr r2, [pc, #256] ; (8002214 <f_Joueur_1+0x21c>)
8002112: f992 2009 ldrsb.w r2, [r2, #9]
8002116: 4413 add r3, r2
8002118: 4a3e ldr r2, [pc, #248] ; (8002214 <f_Joueur_1+0x21c>)
800211a: 6053 str r3, [r2, #4]
if ((joueur.y > joueur.dy) && (joystick_h > centre_joystick + seuil_joystick))
800211c: 4b3d ldr r3, [pc, #244] ; (8002214 <f_Joueur_1+0x21c>)
800211e: 685b ldr r3, [r3, #4]
8002120: 4a3c ldr r2, [pc, #240] ; (8002214 <f_Joueur_1+0x21c>)
8002122: f992 2009 ldrsb.w r2, [r2, #9]
8002126: 4293 cmp r3, r2
8002128: d90d bls.n 8002146 <f_Joueur_1+0x14e>
800212a: 6cfa ldr r2, [r7, #76] ; 0x4c
800212c: 6d3b ldr r3, [r7, #80] ; 0x50
800212e: 4413 add r3, r2
8002130: 6cba ldr r2, [r7, #72] ; 0x48
8002132: 429a cmp r2, r3
8002134: d907 bls.n 8002146 <f_Joueur_1+0x14e>
joueur.y -= joueur.dy;
8002136: 4b37 ldr r3, [pc, #220] ; (8002214 <f_Joueur_1+0x21c>)
8002138: 685b ldr r3, [r3, #4]
800213a: 4a36 ldr r2, [pc, #216] ; (8002214 <f_Joueur_1+0x21c>)
800213c: f992 2009 ldrsb.w r2, [r2, #9]
8002140: 1a9b subs r3, r3, r2
8002142: 4a34 ldr r2, [pc, #208] ; (8002214 <f_Joueur_1+0x21c>)
8002144: 6053 str r3, [r2, #4]
if ((joueur.x < LCD_HEIGHT - joueur_height - joueur.dx) && (joystick_v < centre_joystick - seuil_joystick))
8002146: 4b33 ldr r3, [pc, #204] ; (8002214 <f_Joueur_1+0x21c>)
8002148: 681a ldr r2, [r3, #0]
800214a: 2314 movs r3, #20
800214c: 4619 mov r1, r3
800214e: 6dbb ldr r3, [r7, #88] ; 0x58
8002150: 1a5b subs r3, r3, r1
8002152: 4930 ldr r1, [pc, #192] ; (8002214 <f_Joueur_1+0x21c>)
8002154: f991 1008 ldrsb.w r1, [r1, #8]
8002158: 1a5b subs r3, r3, r1
800215a: 429a cmp r2, r3
800215c: d20d bcs.n 800217a <f_Joueur_1+0x182>
800215e: 6cfa ldr r2, [r7, #76] ; 0x4c
8002160: 6d3b ldr r3, [r7, #80] ; 0x50
8002162: 1ad3 subs r3, r2, r3
8002164: 6c7a ldr r2, [r7, #68] ; 0x44
8002166: 429a cmp r2, r3
8002168: d207 bcs.n 800217a <f_Joueur_1+0x182>
joueur.x += joueur.dx;
800216a: 4b2a ldr r3, [pc, #168] ; (8002214 <f_Joueur_1+0x21c>)
800216c: 681b ldr r3, [r3, #0]
800216e: 4a29 ldr r2, [pc, #164] ; (8002214 <f_Joueur_1+0x21c>)
8002170: f992 2008 ldrsb.w r2, [r2, #8]
8002174: 4413 add r3, r2
8002176: 4a27 ldr r2, [pc, #156] ; (8002214 <f_Joueur_1+0x21c>)
8002178: 6013 str r3, [r2, #0]
if ((joueur.x > joueur.dx) && (joystick_v > centre_joystick + seuil_joystick))
800217a: 4b26 ldr r3, [pc, #152] ; (8002214 <f_Joueur_1+0x21c>)
800217c: 681b ldr r3, [r3, #0]
800217e: 4a25 ldr r2, [pc, #148] ; (8002214 <f_Joueur_1+0x21c>)
8002180: f992 2008 ldrsb.w r2, [r2, #8]
8002184: 4293 cmp r3, r2
8002186: d90d bls.n 80021a4 <f_Joueur_1+0x1ac>
8002188: 6cfa ldr r2, [r7, #76] ; 0x4c
800218a: 6d3b ldr r3, [r7, #80] ; 0x50
800218c: 4413 add r3, r2
800218e: 6c7a ldr r2, [r7, #68] ; 0x44
8002190: 429a cmp r2, r3
8002192: d907 bls.n 80021a4 <f_Joueur_1+0x1ac>
joueur.x -= joueur.dx;
8002194: 4b1f ldr r3, [pc, #124] ; (8002214 <f_Joueur_1+0x21c>)
8002196: 681b ldr r3, [r3, #0]
8002198: 4a1e ldr r2, [pc, #120] ; (8002214 <f_Joueur_1+0x21c>)
800219a: f992 2008 ldrsb.w r2, [r2, #8]
800219e: 1a9b subs r3, r3, r2
80021a0: 4a1c ldr r2, [pc, #112] ; (8002214 <f_Joueur_1+0x21c>)
80021a2: 6013 str r3, [r2, #0]
lcd_plot_rect(joueur.x, joueur.y, joueur_width, joueur_height, Couleur_joueur);
80021a4: 4b1b ldr r3, [pc, #108] ; (8002214 <f_Joueur_1+0x21c>)
80021a6: 681b ldr r3, [r3, #0]
80021a8: b298 uxth r0, r3
80021aa: 4b1a ldr r3, [pc, #104] ; (8002214 <f_Joueur_1+0x21c>)
80021ac: 685b ldr r3, [r3, #4]
80021ae: b299 uxth r1, r3
80021b0: 2214 movs r2, #20
80021b2: 2414 movs r4, #20
80021b4: f46f 037f mvn.w r3, #16711680 ; 0xff0000
80021b8: 9300 str r3, [sp, #0]
80021ba: 4623 mov r3, r4
80021bc: f7ff fe6c bl 8001e98 <lcd_plot_rect>
if (xQueueReceive(Queue_JHandle, &missile, 0) == pdPASS)
80021c0: 4b15 ldr r3, [pc, #84] ; (8002218 <f_Joueur_1+0x220>)
80021c2: 681b ldr r3, [r3, #0]
80021c4: f107 012c add.w r1, r7, #44 ; 0x2c
80021c8: 2200 movs r2, #0
80021ca: 4618 mov r0, r3
80021cc: f00a fb3c bl 800c848 <xQueueReceive>
80021d0: 4603 mov r3, r0
80021d2: 2b01 cmp r3, #1
80021d4: d107 bne.n 80021e6 <f_Joueur_1+0x1ee>
joueur.health = joueur.health - missile.damage;
80021d6: 4b0f ldr r3, [pc, #60] ; (8002214 <f_Joueur_1+0x21c>)
80021d8: 7a9a ldrb r2, [r3, #10]
80021da: f897 3038 ldrb.w r3, [r7, #56] ; 0x38
80021de: 1ad3 subs r3, r2, r3
80021e0: b2da uxtb r2, r3
80021e2: 4b0c ldr r3, [pc, #48] ; (8002214 <f_Joueur_1+0x21c>)
80021e4: 729a strb r2, [r3, #10]
// On envoie 1 si le joueur est mort et on envoie 0 si les enemis sont tous morts
if (joueur.health == 0)
80021e6: 4b0b ldr r3, [pc, #44] ; (8002214 <f_Joueur_1+0x21c>)
80021e8: 7a9b ldrb r3, [r3, #10]
80021ea: 2b00 cmp r3, #0
80021ec: d107 bne.n 80021fe <f_Joueur_1+0x206>
xQueueSend(Queue_FHandle, &stop, 0);
80021ee: 4b0b ldr r3, [pc, #44] ; (800221c <f_Joueur_1+0x224>)
80021f0: 6818 ldr r0, [r3, #0]
80021f2: f107 013f add.w r1, r7, #63 ; 0x3f
80021f6: 2300 movs r3, #0
80021f8: 2200 movs r2, #0
80021fa: f00a f8e9 bl 800c3d0 <xQueueGenericSend>
// TODO La condition sur une entrée analogique pour envoyer un missile
// struct Missile missile = {joueur.x, joueur.y,joueur.missile.dx, joueur.missile.dy, 1, joueur.missile.color, joueur.missile.damage};
// xQueueSend(Queue_NHandle,&missile,0);
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
80021fe: f107 0340 add.w r3, r7, #64 ; 0x40
8002202: 6df9 ldr r1, [r7, #92] ; 0x5c
8002204: 4618 mov r0, r3
8002206: f00b f8ff bl 800d408 <vTaskDelayUntil>
lcd_plot_rect(joueur.x, joueur.y, joueur_width, joueur_height, Couleur_vide);
800220a: e735 b.n 8002078 <f_Joueur_1+0x80>
800220c: 20008a74 .word 0x20008a74
8002210: 20008a2c .word 0x20008a2c
8002214: 20000028 .word 0x20000028
8002218: 200088bc .word 0x200088bc
800221c: 20008ac0 .word 0x20008ac0
08002220 <f_block_enemie>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_f_block_enemie */
void f_block_enemie(void const * argument)
{
8002220: b590 push {r4, r7, lr}
8002222: b093 sub sp, #76 ; 0x4c
8002224: af02 add r7, sp, #8
8002226: 6078 str r0, [r7, #4]
/* USER CODE BEGIN f_block_enemie */
TickType_t xLastWakeTime;
const TickType_t xPeriodeTache = 500 / portTICK_PERIOD_MS; // Toute les demi secondes
8002228: f44f 73fa mov.w r3, #500 ; 0x1f4
800222c: 62bb str r3, [r7, #40] ; 0x28
uint8_t end = 0;
800222e: 2300 movs r3, #0
8002230: 77fb strb r3, [r7, #31]
uint8_t nombre_monstre;
struct Collision collision;
uint8_t deplacement = 1;
8002232: 2301 movs r3, #1
8002234: f887 3027 strb.w r3, [r7, #39] ; 0x27
struct Missile missile = {0,0,0,0,0,0,0,0};
8002238: f107 030c add.w r3, r7, #12
800223c: 2200 movs r2, #0
800223e: 601a str r2, [r3, #0]
8002240: 605a str r2, [r3, #4]
8002242: 609a str r2, [r3, #8]
8002244: 60da str r2, [r3, #12]
/* Infinite loop */
for (;;)
{
while (xQueueReceive(Queue_EHandle, &collision, 0) == pdPASS)
8002246: e025 b.n 8002294 <f_block_enemie+0x74>
{
Table_ennemie[collision.idx1][collision.idx2].health -= collision.damage;
8002248: 7f3b ldrb r3, [r7, #28]
800224a: 4618 mov r0, r3
800224c: 7f7b ldrb r3, [r7, #29]
800224e: 461a mov r2, r3
8002250: 4963 ldr r1, [pc, #396] ; (80023e0 <f_block_enemie+0x1c0>)
8002252: 4613 mov r3, r2
8002254: 00db lsls r3, r3, #3
8002256: 1a9b subs r3, r3, r2
8002258: 009b lsls r3, r3, #2
800225a: 2254 movs r2, #84 ; 0x54
800225c: fb02 f200 mul.w r2, r2, r0
8002260: 4413 add r3, r2
8002262: 440b add r3, r1
8002264: 3308 adds r3, #8
8002266: f993 3000 ldrsb.w r3, [r3]
800226a: b2da uxtb r2, r3
800226c: 7fbb ldrb r3, [r7, #30]
800226e: 1ad3 subs r3, r2, r3
8002270: b2db uxtb r3, r3
8002272: 7f3a ldrb r2, [r7, #28]
8002274: 4614 mov r4, r2
8002276: 7f7a ldrb r2, [r7, #29]
8002278: b258 sxtb r0, r3
800227a: 4959 ldr r1, [pc, #356] ; (80023e0 <f_block_enemie+0x1c0>)
800227c: 4613 mov r3, r2
800227e: 00db lsls r3, r3, #3
8002280: 1a9b subs r3, r3, r2
8002282: 009b lsls r3, r3, #2
8002284: 2254 movs r2, #84 ; 0x54
8002286: fb02 f204 mul.w r2, r2, r4
800228a: 4413 add r3, r2
800228c: 440b add r3, r1
800228e: 3308 adds r3, #8
8002290: 4602 mov r2, r0
8002292: 701a strb r2, [r3, #0]
while (xQueueReceive(Queue_EHandle, &collision, 0) == pdPASS)
8002294: 4b53 ldr r3, [pc, #332] ; (80023e4 <f_block_enemie+0x1c4>)
8002296: 681b ldr r3, [r3, #0]
8002298: f107 011c add.w r1, r7, #28
800229c: 2200 movs r2, #0
800229e: 4618 mov r0, r3
80022a0: f00a fad2 bl 800c848 <xQueueReceive>
80022a4: 4603 mov r3, r0
80022a6: 2b01 cmp r3, #1
80022a8: d0ce beq.n 8002248 <f_block_enemie+0x28>
}
for (int idx1 = 0; idx1 < 8; idx1++)
80022aa: 2300 movs r3, #0
80022ac: 63bb str r3, [r7, #56] ; 0x38
80022ae: e030 b.n 8002312 <f_block_enemie+0xf2>
{
for (int idx2 = 0; idx2 < 3; idx2++)
80022b0: 2300 movs r3, #0
80022b2: 637b str r3, [r7, #52] ; 0x34
80022b4: e027 b.n 8002306 <f_block_enemie+0xe6>
{
lcd_plot_rect(Table_ennemie[idx1][idx2].x, Table_ennemie[idx1][idx2].y, monstre_width, monstre_height, Couleur_vide);
80022b6: 484a ldr r0, [pc, #296] ; (80023e0 <f_block_enemie+0x1c0>)
80022b8: 6b7a ldr r2, [r7, #52] ; 0x34
80022ba: 6bb9 ldr r1, [r7, #56] ; 0x38
80022bc: 4613 mov r3, r2
80022be: 00db lsls r3, r3, #3
80022c0: 1a9b subs r3, r3, r2
80022c2: 009b lsls r3, r3, #2
80022c4: 2254 movs r2, #84 ; 0x54
80022c6: fb02 f201 mul.w r2, r2, r1
80022ca: 4413 add r3, r2
80022cc: 4403 add r3, r0
80022ce: 681b ldr r3, [r3, #0]
80022d0: b298 uxth r0, r3
80022d2: 4c43 ldr r4, [pc, #268] ; (80023e0 <f_block_enemie+0x1c0>)
80022d4: 6b7a ldr r2, [r7, #52] ; 0x34
80022d6: 6bb9 ldr r1, [r7, #56] ; 0x38
80022d8: 4613 mov r3, r2
80022da: 00db lsls r3, r3, #3
80022dc: 1a9b subs r3, r3, r2
80022de: 009b lsls r3, r3, #2
80022e0: 2254 movs r2, #84 ; 0x54
80022e2: fb02 f201 mul.w r2, r2, r1
80022e6: 4413 add r3, r2
80022e8: 4423 add r3, r4
80022ea: 3304 adds r3, #4
80022ec: 681b ldr r3, [r3, #0]
80022ee: b299 uxth r1, r3
80022f0: 2214 movs r2, #20
80022f2: 2414 movs r4, #20
80022f4: f04f 437f mov.w r3, #4278190080 ; 0xff000000
80022f8: 9300 str r3, [sp, #0]
80022fa: 4623 mov r3, r4
80022fc: f7ff fdcc bl 8001e98 <lcd_plot_rect>
for (int idx2 = 0; idx2 < 3; idx2++)
8002300: 6b7b ldr r3, [r7, #52] ; 0x34
8002302: 3301 adds r3, #1
8002304: 637b str r3, [r7, #52] ; 0x34
8002306: 6b7b ldr r3, [r7, #52] ; 0x34
8002308: 2b02 cmp r3, #2
800230a: ddd4 ble.n 80022b6 <f_block_enemie+0x96>
for (int idx1 = 0; idx1 < 8; idx1++)
800230c: 6bbb ldr r3, [r7, #56] ; 0x38
800230e: 3301 adds r3, #1
8002310: 63bb str r3, [r7, #56] ; 0x38
8002312: 6bbb ldr r3, [r7, #56] ; 0x38
8002314: 2b07 cmp r3, #7
8002316: ddcb ble.n 80022b0 <f_block_enemie+0x90>
}
}
// TODO déplacement des ennemies
nombre_monstre = 0;
8002318: 2300 movs r3, #0
800231a: f887 303f strb.w r3, [r7, #63] ; 0x3f
for (int idx1 = 0; idx1 < 8; idx1++)
800231e: 2300 movs r3, #0
8002320: 633b str r3, [r7, #48] ; 0x30
8002322: e046 b.n 80023b2 <f_block_enemie+0x192>
{
for (int idx2 = 0; idx2 < 3; idx2++)
8002324: 2300 movs r3, #0
8002326: 62fb str r3, [r7, #44] ; 0x2c
8002328: e03d b.n 80023a6 <f_block_enemie+0x186>
{
if (Table_ennemie[idx1][idx2].health > 0)
800232a: 482d ldr r0, [pc, #180] ; (80023e0 <f_block_enemie+0x1c0>)
800232c: 6afa ldr r2, [r7, #44] ; 0x2c
800232e: 6b39 ldr r1, [r7, #48] ; 0x30
8002330: 4613 mov r3, r2
8002332: 00db lsls r3, r3, #3
8002334: 1a9b subs r3, r3, r2
8002336: 009b lsls r3, r3, #2
8002338: 2254 movs r2, #84 ; 0x54
800233a: fb02 f201 mul.w r2, r2, r1
800233e: 4413 add r3, r2
8002340: 4403 add r3, r0
8002342: 3308 adds r3, #8
8002344: f993 3000 ldrsb.w r3, [r3]
8002348: 2b00 cmp r3, #0
800234a: dd29 ble.n 80023a0 <f_block_enemie+0x180>
{
nombre_monstre++;
800234c: f897 303f ldrb.w r3, [r7, #63] ; 0x3f
8002350: 3301 adds r3, #1
8002352: f887 303f strb.w r3, [r7, #63] ; 0x3f
lcd_plot_rect(Table_ennemie[idx1][idx2].x, Table_ennemie[idx1][idx2].y, monstre_width, monstre_height, Couleur_monstre);
8002356: 4822 ldr r0, [pc, #136] ; (80023e0 <f_block_enemie+0x1c0>)
8002358: 6afa ldr r2, [r7, #44] ; 0x2c
800235a: 6b39 ldr r1, [r7, #48] ; 0x30
800235c: 4613 mov r3, r2
800235e: 00db lsls r3, r3, #3
8002360: 1a9b subs r3, r3, r2
8002362: 009b lsls r3, r3, #2
8002364: 2254 movs r2, #84 ; 0x54
8002366: fb02 f201 mul.w r2, r2, r1
800236a: 4413 add r3, r2
800236c: 4403 add r3, r0
800236e: 681b ldr r3, [r3, #0]
8002370: b298 uxth r0, r3
8002372: 4c1b ldr r4, [pc, #108] ; (80023e0 <f_block_enemie+0x1c0>)
8002374: 6afa ldr r2, [r7, #44] ; 0x2c
8002376: 6b39 ldr r1, [r7, #48] ; 0x30
8002378: 4613 mov r3, r2
800237a: 00db lsls r3, r3, #3
800237c: 1a9b subs r3, r3, r2
800237e: 009b lsls r3, r3, #2
8002380: 2254 movs r2, #84 ; 0x54
8002382: fb02 f201 mul.w r2, r2, r1
8002386: 4413 add r3, r2
8002388: 4423 add r3, r4
800238a: 3304 adds r3, #4
800238c: 681b ldr r3, [r3, #0]
800238e: b299 uxth r1, r3
8002390: 2214 movs r2, #20
8002392: 2414 movs r4, #20
8002394: f46f 037f mvn.w r3, #16711680 ; 0xff0000
8002398: 9300 str r3, [sp, #0]
800239a: 4623 mov r3, r4
800239c: f7ff fd7c bl 8001e98 <lcd_plot_rect>
for (int idx2 = 0; idx2 < 3; idx2++)
80023a0: 6afb ldr r3, [r7, #44] ; 0x2c
80023a2: 3301 adds r3, #1
80023a4: 62fb str r3, [r7, #44] ; 0x2c
80023a6: 6afb ldr r3, [r7, #44] ; 0x2c
80023a8: 2b02 cmp r3, #2
80023aa: ddbe ble.n 800232a <f_block_enemie+0x10a>
for (int idx1 = 0; idx1 < 8; idx1++)
80023ac: 6b3b ldr r3, [r7, #48] ; 0x30
80023ae: 3301 adds r3, #1
80023b0: 633b str r3, [r7, #48] ; 0x30
80023b2: 6b3b ldr r3, [r7, #48] ; 0x30
80023b4: 2b07 cmp r3, #7
80023b6: ddb5 ble.n 8002324 <f_block_enemie+0x104>
}
}
}
if (nombre_monstre)
80023b8: f897 303f ldrb.w r3, [r7, #63] ; 0x3f
80023bc: 2b00 cmp r3, #0
80023be: d007 beq.n 80023d0 <f_block_enemie+0x1b0>
xQueueSend(Queue_FHandle, &end, 0);
80023c0: 4b09 ldr r3, [pc, #36] ; (80023e8 <f_block_enemie+0x1c8>)
80023c2: 6818 ldr r0, [r3, #0]
80023c4: f107 011f add.w r1, r7, #31
80023c8: 2300 movs r3, #0
80023ca: 2200 movs r2, #0
80023cc: f00a f800 bl 800c3d0 <xQueueGenericSend>
list_monsters[i].x = list_monsters[i].x + deplacement * 2;
}
}
deplacement = -1;
*/
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
80023d0: f107 0320 add.w r3, r7, #32
80023d4: 6ab9 ldr r1, [r7, #40] ; 0x28
80023d6: 4618 mov r0, r3
80023d8: f00b f816 bl 800d408 <vTaskDelayUntil>
while (xQueueReceive(Queue_EHandle, &collision, 0) == pdPASS)
80023dc: e75a b.n 8002294 <f_block_enemie+0x74>
80023de: bf00 nop
80023e0: 20008b7c .word 0x20008b7c
80023e4: 20008e68 .word 0x20008e68
80023e8: 20008ac0 .word 0x20008ac0
080023ec <f_projectile>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_f_projectile */
void f_projectile(void const * argument)
{
80023ec: b5f0 push {r4, r5, r6, r7, lr}
80023ee: b097 sub sp, #92 ; 0x5c
80023f0: af02 add r7, sp, #8
80023f2: 6078 str r0, [r7, #4]
/* USER CODE BEGIN f_projectile */
TickType_t xLastWakeTime;
const TickType_t xPeriodeTache = 200 / portTICK_PERIOD_MS; // Toutes les 200 ms
80023f4: 23c8 movs r3, #200 ; 0xc8
80023f6: 643b str r3, [r7, #64] ; 0x40
const int TAILLE_LISTE_MISSILE = 25;
80023f8: 2319 movs r3, #25
80023fa: 63fb str r3, [r7, #60] ; 0x3c
/* Infinite loop */
struct Missile liste_missile[TAILLE_LISTE_MISSILE];
80023fc: 6bfb ldr r3, [r7, #60] ; 0x3c
80023fe: 3b01 subs r3, #1
8002400: 63bb str r3, [r7, #56] ; 0x38
8002402: 6bfb ldr r3, [r7, #60] ; 0x3c
8002404: 4618 mov r0, r3
8002406: f04f 0100 mov.w r1, #0
800240a: f04f 0200 mov.w r2, #0
800240e: f04f 0300 mov.w r3, #0
8002412: 01cb lsls r3, r1, #7
8002414: ea43 6350 orr.w r3, r3, r0, lsr #25
8002418: 01c2 lsls r2, r0, #7
800241a: 6bfb ldr r3, [r7, #60] ; 0x3c
800241c: 4618 mov r0, r3
800241e: f04f 0100 mov.w r1, #0
8002422: f04f 0200 mov.w r2, #0
8002426: f04f 0300 mov.w r3, #0
800242a: 01cb lsls r3, r1, #7
800242c: ea43 6350 orr.w r3, r3, r0, lsr #25
8002430: 01c2 lsls r2, r0, #7
8002432: 6bfb ldr r3, [r7, #60] ; 0x3c
8002434: 011b lsls r3, r3, #4
8002436: 3307 adds r3, #7
8002438: 08db lsrs r3, r3, #3
800243a: 00db lsls r3, r3, #3
800243c: ebad 0d03 sub.w sp, sp, r3
8002440: ab02 add r3, sp, #8
8002442: 3303 adds r3, #3
8002444: 089b lsrs r3, r3, #2
8002446: 009b lsls r3, r3, #2
8002448: 637b str r3, [r7, #52] ; 0x34
struct Missile missile = {70, 70, 1, 0, 0, LCD_COLOR_WHITE, 1, 1};
800244a: 4b7e ldr r3, [pc, #504] ; (8002644 <f_projectile+0x258>)
800244c: f107 040c add.w r4, r7, #12
8002450: cb0f ldmia r3, {r0, r1, r2, r3}
8002452: e884 000f stmia.w r4, {r0, r1, r2, r3}
uint8_t indice = 1;
8002456: 2301 movs r3, #1
8002458: f887 3033 strb.w r3, [r7, #51] ; 0x33
liste_missile[0] = missile;
800245c: 6b7b ldr r3, [r7, #52] ; 0x34
800245e: 461c mov r4, r3
8002460: f107 030c add.w r3, r7, #12
8002464: cb0f ldmia r3, {r0, r1, r2, r3}
8002466: e884 000f stmia.w r4, {r0, r1, r2, r3}
uint32_t new_x;
uint32_t new_y;
// Paramètre de l'écran pour la reprouductibilité
uint32_t LCD_HEIGHT = BSP_LCD_GetXSize();
800246a: f000 fb21 bl 8002ab0 <BSP_LCD_GetXSize>
800246e: 62f8 str r0, [r7, #44] ; 0x2c
uint32_t LCD_WIDTH = BSP_LCD_GetYSize();
8002470: f000 fb32 bl 8002ad8 <BSP_LCD_GetYSize>
8002474: 62b8 str r0, [r7, #40] ; 0x28
for (;;)
{
for (int idx_missile = 0; idx_missile < TAILLE_LISTE_MISSILE; idx_missile++)
8002476: 2300 movs r3, #0
8002478: 647b str r3, [r7, #68] ; 0x44
800247a: e0d6 b.n 800262a <f_projectile+0x23e>
{
if (liste_missile[idx_missile].valide)
800247c: 6b7a ldr r2, [r7, #52] ; 0x34
800247e: 6c7b ldr r3, [r7, #68] ; 0x44
8002480: 011b lsls r3, r3, #4
8002482: 4413 add r3, r2
8002484: 330d adds r3, #13
8002486: 781b ldrb r3, [r3, #0]
8002488: 2b00 cmp r3, #0
800248a: f000 80cb beq.w 8002624 <f_projectile+0x238>
{
new_x = liste_missile[idx_missile].x + liste_missile[idx_missile].dx;
800248e: 6b7a ldr r2, [r7, #52] ; 0x34
8002490: 6c7b ldr r3, [r7, #68] ; 0x44
8002492: 011b lsls r3, r3, #4
8002494: 4413 add r3, r2
8002496: 881b ldrh r3, [r3, #0]
8002498: 4619 mov r1, r3
800249a: 6b7a ldr r2, [r7, #52] ; 0x34
800249c: 6c7b ldr r3, [r7, #68] ; 0x44
800249e: 011b lsls r3, r3, #4
80024a0: 4413 add r3, r2
80024a2: 3304 adds r3, #4
80024a4: f993 3000 ldrsb.w r3, [r3]
80024a8: 440b add r3, r1
80024aa: 627b str r3, [r7, #36] ; 0x24
new_y = liste_missile[idx_missile].y + liste_missile[idx_missile].dy;
80024ac: 6b7a ldr r2, [r7, #52] ; 0x34
80024ae: 6c7b ldr r3, [r7, #68] ; 0x44
80024b0: 011b lsls r3, r3, #4
80024b2: 4413 add r3, r2
80024b4: 3302 adds r3, #2
80024b6: 881b ldrh r3, [r3, #0]
80024b8: 4619 mov r1, r3
80024ba: 6b7a ldr r2, [r7, #52] ; 0x34
80024bc: 6c7b ldr r3, [r7, #68] ; 0x44
80024be: 011b lsls r3, r3, #4
80024c0: 4413 add r3, r2
80024c2: 3305 adds r3, #5
80024c4: f993 3000 ldrsb.w r3, [r3]
80024c8: 440b add r3, r1
80024ca: 623b str r3, [r7, #32]
if ((new_x < 0) | (new_x > LCD_WIDTH) | (new_y < 0) | (new_y > LCD_HEIGHT))
80024cc: 6a7a ldr r2, [r7, #36] ; 0x24
80024ce: 6abb ldr r3, [r7, #40] ; 0x28
80024d0: 429a cmp r2, r3
80024d2: bf8c ite hi
80024d4: 2301 movhi r3, #1
80024d6: 2300 movls r3, #0
80024d8: b2da uxtb r2, r3
80024da: 6a39 ldr r1, [r7, #32]
80024dc: 6afb ldr r3, [r7, #44] ; 0x2c
80024de: 4299 cmp r1, r3
80024e0: bf8c ite hi
80024e2: 2301 movhi r3, #1
80024e4: 2300 movls r3, #0
80024e6: b2db uxtb r3, r3
80024e8: 4313 orrs r3, r2
80024ea: b2db uxtb r3, r3
80024ec: 2b00 cmp r3, #0
80024ee: d006 beq.n 80024fe <f_projectile+0x112>
liste_missile[idx_missile].valide = 0;
80024f0: 6b7a ldr r2, [r7, #52] ; 0x34
80024f2: 6c7b ldr r3, [r7, #68] ; 0x44
80024f4: 011b lsls r3, r3, #4
80024f6: 4413 add r3, r2
80024f8: 330d adds r3, #13
80024fa: 2200 movs r2, #0
80024fc: 701a strb r2, [r3, #0]
if ((liste_missile[idx_missile].equipe == 0) & colision_missile(new_x, new_y, joueur.x, joueur.y, joueur_width, joueur_height))
80024fe: 6b7a ldr r2, [r7, #52] ; 0x34
8002500: 6c7b ldr r3, [r7, #68] ; 0x44
8002502: 011b lsls r3, r3, #4
8002504: 4413 add r3, r2
8002506: 3306 adds r3, #6
8002508: 781b ldrb r3, [r3, #0]
800250a: 2b00 cmp r3, #0
800250c: bf0c ite eq
800250e: 2301 moveq r3, #1
8002510: 2300 movne r3, #0
8002512: b2db uxtb r3, r3
8002514: 461e mov r6, r3
8002516: 6a7b ldr r3, [r7, #36] ; 0x24
8002518: b298 uxth r0, r3
800251a: 6a3b ldr r3, [r7, #32]
800251c: b299 uxth r1, r3
800251e: 4b4a ldr r3, [pc, #296] ; (8002648 <f_projectile+0x25c>)
8002520: 681b ldr r3, [r3, #0]
8002522: b29a uxth r2, r3
8002524: 4b48 ldr r3, [pc, #288] ; (8002648 <f_projectile+0x25c>)
8002526: 685b ldr r3, [r3, #4]
8002528: b29b uxth r3, r3
800252a: 2414 movs r4, #20
800252c: 2514 movs r5, #20
800252e: 9501 str r5, [sp, #4]
8002530: 9400 str r4, [sp, #0]
8002532: f7ff fce1 bl 8001ef8 <colision_missile>
8002536: 4603 mov r3, r0
8002538: 4033 ands r3, r6
800253a: 2b00 cmp r3, #0
800253c: d010 beq.n 8002560 <f_projectile+0x174>
{ //TODO condition de choc avec le joueur
xQueueSend(Queue_JHandle, &liste_missile[idx_missile], 0);
800253e: 4b43 ldr r3, [pc, #268] ; (800264c <f_projectile+0x260>)
8002540: 6818 ldr r0, [r3, #0]
8002542: 6c7b ldr r3, [r7, #68] ; 0x44
8002544: 011b lsls r3, r3, #4
8002546: 6b7a ldr r2, [r7, #52] ; 0x34
8002548: 18d1 adds r1, r2, r3
800254a: 2300 movs r3, #0
800254c: 2200 movs r2, #0
800254e: f009 ff3f bl 800c3d0 <xQueueGenericSend>
liste_missile[idx_missile].valide = 0;
8002552: 6b7a ldr r2, [r7, #52] ; 0x34
8002554: 6c7b ldr r3, [r7, #68] ; 0x44
8002556: 011b lsls r3, r3, #4
8002558: 4413 add r3, r2
800255a: 330d adds r3, #13
800255c: 2200 movs r2, #0
800255e: 701a strb r2, [r3, #0]
}
if (liste_missile[idx_missile].equipe == 1)
8002560: 6b7a ldr r2, [r7, #52] ; 0x34
8002562: 6c7b ldr r3, [r7, #68] ; 0x44
8002564: 011b lsls r3, r3, #4
8002566: 4413 add r3, r2
8002568: 3306 adds r3, #6
800256a: 781b ldrb r3, [r3, #0]
800256c: 2b01 cmp r3, #1
800256e: d159 bne.n 8002624 <f_projectile+0x238>
{
for (int idx_mechant_1 = 0; idx_mechant_1 < 8; idx_mechant_1++)
8002570: 2300 movs r3, #0
8002572: 64bb str r3, [r7, #72] ; 0x48
8002574: e053 b.n 800261e <f_projectile+0x232>
{
for (int idx_mechant_2 = 0; idx_mechant_2 < 3; idx_mechant_2++)
8002576: 2300 movs r3, #0
8002578: 64fb str r3, [r7, #76] ; 0x4c
800257a: e04a b.n 8002612 <f_projectile+0x226>
{
if (colision_missile(new_x, new_y, Table_ennemie[idx_mechant_1][idx_mechant_2].x, Table_ennemie[idx_mechant_1][idx_mechant_2].y, monstre_width, monstre_height))
800257c: 6a7b ldr r3, [r7, #36] ; 0x24
800257e: b298 uxth r0, r3
8002580: 6a3b ldr r3, [r7, #32]
8002582: b29c uxth r4, r3
8002584: 4d32 ldr r5, [pc, #200] ; (8002650 <f_projectile+0x264>)
8002586: 6cfa ldr r2, [r7, #76] ; 0x4c
8002588: 6cb9 ldr r1, [r7, #72] ; 0x48
800258a: 4613 mov r3, r2
800258c: 00db lsls r3, r3, #3
800258e: 1a9b subs r3, r3, r2
8002590: 009b lsls r3, r3, #2
8002592: 2254 movs r2, #84 ; 0x54
8002594: fb02 f201 mul.w r2, r2, r1
8002598: 4413 add r3, r2
800259a: 442b add r3, r5
800259c: 681b ldr r3, [r3, #0]
800259e: b29d uxth r5, r3
80025a0: 4e2b ldr r6, [pc, #172] ; (8002650 <f_projectile+0x264>)
80025a2: 6cfa ldr r2, [r7, #76] ; 0x4c
80025a4: 6cb9 ldr r1, [r7, #72] ; 0x48
80025a6: 4613 mov r3, r2
80025a8: 00db lsls r3, r3, #3
80025aa: 1a9b subs r3, r3, r2
80025ac: 009b lsls r3, r3, #2
80025ae: 2254 movs r2, #84 ; 0x54
80025b0: fb02 f201 mul.w r2, r2, r1
80025b4: 4413 add r3, r2
80025b6: 4433 add r3, r6
80025b8: 3304 adds r3, #4
80025ba: 681b ldr r3, [r3, #0]
80025bc: b29b uxth r3, r3
80025be: 2214 movs r2, #20
80025c0: 2114 movs r1, #20
80025c2: 9101 str r1, [sp, #4]
80025c4: 9200 str r2, [sp, #0]
80025c6: 462a mov r2, r5
80025c8: 4621 mov r1, r4
80025ca: f7ff fc95 bl 8001ef8 <colision_missile>
80025ce: 4603 mov r3, r0
80025d0: 2b00 cmp r3, #0
80025d2: d01b beq.n 800260c <f_projectile+0x220>
{
struct Collision collision = {idx_mechant_1, idx_mechant_2, liste_missile[idx_missile].damage};
80025d4: 6cbb ldr r3, [r7, #72] ; 0x48
80025d6: b2db uxtb r3, r3
80025d8: 723b strb r3, [r7, #8]
80025da: 6cfb ldr r3, [r7, #76] ; 0x4c
80025dc: b2db uxtb r3, r3
80025de: 727b strb r3, [r7, #9]
80025e0: 6b7a ldr r2, [r7, #52] ; 0x34
80025e2: 6c7b ldr r3, [r7, #68] ; 0x44
80025e4: 011b lsls r3, r3, #4
80025e6: 4413 add r3, r2
80025e8: 330c adds r3, #12
80025ea: 781b ldrb r3, [r3, #0]
80025ec: 72bb strb r3, [r7, #10]
xQueueSend(Queue_EHandle, (void *)&collision, 0);
80025ee: 4b19 ldr r3, [pc, #100] ; (8002654 <f_projectile+0x268>)
80025f0: 6818 ldr r0, [r3, #0]
80025f2: f107 0108 add.w r1, r7, #8
80025f6: 2300 movs r3, #0
80025f8: 2200 movs r2, #0
80025fa: f009 fee9 bl 800c3d0 <xQueueGenericSend>
liste_missile[idx_missile].valide = 0;
80025fe: 6b7a ldr r2, [r7, #52] ; 0x34
8002600: 6c7b ldr r3, [r7, #68] ; 0x44
8002602: 011b lsls r3, r3, #4
8002604: 4413 add r3, r2
8002606: 330d adds r3, #13
8002608: 2200 movs r2, #0
800260a: 701a strb r2, [r3, #0]
for (int idx_mechant_2 = 0; idx_mechant_2 < 3; idx_mechant_2++)
800260c: 6cfb ldr r3, [r7, #76] ; 0x4c
800260e: 3301 adds r3, #1
8002610: 64fb str r3, [r7, #76] ; 0x4c
8002612: 6cfb ldr r3, [r7, #76] ; 0x4c
8002614: 2b02 cmp r3, #2
8002616: ddb1 ble.n 800257c <f_projectile+0x190>
for (int idx_mechant_1 = 0; idx_mechant_1 < 8; idx_mechant_1++)
8002618: 6cbb ldr r3, [r7, #72] ; 0x48
800261a: 3301 adds r3, #1
800261c: 64bb str r3, [r7, #72] ; 0x48
800261e: 6cbb ldr r3, [r7, #72] ; 0x48
8002620: 2b07 cmp r3, #7
8002622: dda8 ble.n 8002576 <f_projectile+0x18a>
for (int idx_missile = 0; idx_missile < TAILLE_LISTE_MISSILE; idx_missile++)
8002624: 6c7b ldr r3, [r7, #68] ; 0x44
8002626: 3301 adds r3, #1
8002628: 647b str r3, [r7, #68] ; 0x44
800262a: 6c7a ldr r2, [r7, #68] ; 0x44
800262c: 6bfb ldr r3, [r7, #60] ; 0x3c
800262e: 429a cmp r2, r3
8002630: f6ff af24 blt.w 800247c <f_projectile+0x90>
}
}
}
*/
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
8002634: f107 031c add.w r3, r7, #28
8002638: 6c39 ldr r1, [r7, #64] ; 0x40
800263a: 4618 mov r0, r3
800263c: f00a fee4 bl 800d408 <vTaskDelayUntil>
for (int idx_missile = 0; idx_missile < TAILLE_LISTE_MISSILE; idx_missile++)
8002640: e719 b.n 8002476 <f_projectile+0x8a>
8002642: bf00 nop
8002644: 0801c0f4 .word 0x0801c0f4
8002648: 20000028 .word 0x20000028
800264c: 200088bc .word 0x200088bc
8002650: 20008b7c .word 0x20008b7c
8002654: 20008e68 .word 0x20008e68
08002658 <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8002658: b580 push {r7, lr}
800265a: b082 sub sp, #8
800265c: af00 add r7, sp, #0
800265e: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM6) {
8002660: 687b ldr r3, [r7, #4]
8002662: 681b ldr r3, [r3, #0]
8002664: 4a04 ldr r2, [pc, #16] ; (8002678 <HAL_TIM_PeriodElapsedCallback+0x20>)
8002666: 4293 cmp r3, r2
8002668: d101 bne.n 800266e <HAL_TIM_PeriodElapsedCallback+0x16>
HAL_IncTick();
800266a: f002 f89d bl 80047a8 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
800266e: bf00 nop
8002670: 3708 adds r7, #8
8002672: 46bd mov sp, r7
8002674: bd80 pop {r7, pc}
8002676: bf00 nop
8002678: 40001000 .word 0x40001000
0800267c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
800267c: b480 push {r7}
800267e: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8002680: b672 cpsid i
}
8002682: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8002684: e7fe b.n 8002684 <Error_Handler+0x8>
...
08002688 <I2Cx_MspInit>:
* @brief Initializes I2C MSP.
* @param i2c_handler : I2C handler
* @retval None
*/
static void I2Cx_MspInit(I2C_HandleTypeDef *i2c_handler)
{
8002688: b580 push {r7, lr}
800268a: b08c sub sp, #48 ; 0x30
800268c: af00 add r7, sp, #0
800268e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef gpio_init_structure;
if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler))
8002690: 687b ldr r3, [r7, #4]
8002692: 4a51 ldr r2, [pc, #324] ; (80027d8 <I2Cx_MspInit+0x150>)
8002694: 4293 cmp r3, r2
8002696: d14d bne.n 8002734 <I2Cx_MspInit+0xac>
{
/* AUDIO and LCD I2C MSP init */
/*** Configure the GPIOs ***/
/* Enable GPIO clock */
DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
8002698: 4b50 ldr r3, [pc, #320] ; (80027dc <I2Cx_MspInit+0x154>)
800269a: 6b1b ldr r3, [r3, #48] ; 0x30
800269c: 4a4f ldr r2, [pc, #316] ; (80027dc <I2Cx_MspInit+0x154>)
800269e: f043 0380 orr.w r3, r3, #128 ; 0x80
80026a2: 6313 str r3, [r2, #48] ; 0x30
80026a4: 4b4d ldr r3, [pc, #308] ; (80027dc <I2Cx_MspInit+0x154>)
80026a6: 6b1b ldr r3, [r3, #48] ; 0x30
80026a8: f003 0380 and.w r3, r3, #128 ; 0x80
80026ac: 61bb str r3, [r7, #24]
80026ae: 69bb ldr r3, [r7, #24]
/* Configure I2C Tx as alternate function */
gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SCL_PIN;
80026b0: 2380 movs r3, #128 ; 0x80
80026b2: 61fb str r3, [r7, #28]
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
80026b4: 2312 movs r3, #18
80026b6: 623b str r3, [r7, #32]
gpio_init_structure.Pull = GPIO_NOPULL;
80026b8: 2300 movs r3, #0
80026ba: 627b str r3, [r7, #36] ; 0x24
gpio_init_structure.Speed = GPIO_SPEED_FAST;
80026bc: 2302 movs r3, #2
80026be: 62bb str r3, [r7, #40] ; 0x28
gpio_init_structure.Alternate = DISCOVERY_AUDIO_I2Cx_SCL_SDA_AF;
80026c0: 2304 movs r3, #4
80026c2: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
80026c4: f107 031c add.w r3, r7, #28
80026c8: 4619 mov r1, r3
80026ca: 4845 ldr r0, [pc, #276] ; (80027e0 <I2Cx_MspInit+0x158>)
80026cc: f004 fd18 bl 8007100 <HAL_GPIO_Init>
/* Configure I2C Rx as alternate function */
gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SDA_PIN;
80026d0: f44f 7380 mov.w r3, #256 ; 0x100
80026d4: 61fb str r3, [r7, #28]
HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
80026d6: f107 031c add.w r3, r7, #28
80026da: 4619 mov r1, r3
80026dc: 4840 ldr r0, [pc, #256] ; (80027e0 <I2Cx_MspInit+0x158>)
80026de: f004 fd0f bl 8007100 <HAL_GPIO_Init>
/*** Configure the I2C peripheral ***/
/* Enable I2C clock */
DISCOVERY_AUDIO_I2Cx_CLK_ENABLE();
80026e2: 4b3e ldr r3, [pc, #248] ; (80027dc <I2Cx_MspInit+0x154>)
80026e4: 6c1b ldr r3, [r3, #64] ; 0x40
80026e6: 4a3d ldr r2, [pc, #244] ; (80027dc <I2Cx_MspInit+0x154>)
80026e8: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
80026ec: 6413 str r3, [r2, #64] ; 0x40
80026ee: 4b3b ldr r3, [pc, #236] ; (80027dc <I2Cx_MspInit+0x154>)
80026f0: 6c1b ldr r3, [r3, #64] ; 0x40
80026f2: f403 0300 and.w r3, r3, #8388608 ; 0x800000
80026f6: 617b str r3, [r7, #20]
80026f8: 697b ldr r3, [r7, #20]
/* Force the I2C peripheral clock reset */
DISCOVERY_AUDIO_I2Cx_FORCE_RESET();
80026fa: 4b38 ldr r3, [pc, #224] ; (80027dc <I2Cx_MspInit+0x154>)
80026fc: 6a1b ldr r3, [r3, #32]
80026fe: 4a37 ldr r2, [pc, #220] ; (80027dc <I2Cx_MspInit+0x154>)
8002700: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8002704: 6213 str r3, [r2, #32]
/* Release the I2C peripheral clock reset */
DISCOVERY_AUDIO_I2Cx_RELEASE_RESET();
8002706: 4b35 ldr r3, [pc, #212] ; (80027dc <I2Cx_MspInit+0x154>)
8002708: 6a1b ldr r3, [r3, #32]
800270a: 4a34 ldr r2, [pc, #208] ; (80027dc <I2Cx_MspInit+0x154>)
800270c: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
8002710: 6213 str r3, [r2, #32]
/* Enable and set I2Cx Interrupt to a lower priority */
HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_EV_IRQn, 0x0F, 0);
8002712: 2200 movs r2, #0
8002714: 210f movs r1, #15
8002716: 2048 movs r0, #72 ; 0x48
8002718: f002 fd30 bl 800517c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_EV_IRQn);
800271c: 2048 movs r0, #72 ; 0x48
800271e: f002 fd49 bl 80051b4 <HAL_NVIC_EnableIRQ>
/* Enable and set I2Cx Interrupt to a lower priority */
HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_ER_IRQn, 0x0F, 0);
8002722: 2200 movs r2, #0
8002724: 210f movs r1, #15
8002726: 2049 movs r0, #73 ; 0x49
8002728: f002 fd28 bl 800517c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_ER_IRQn);
800272c: 2049 movs r0, #73 ; 0x49
800272e: f002 fd41 bl 80051b4 <HAL_NVIC_EnableIRQ>
/* Enable and set I2Cx Interrupt to a lower priority */
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0);
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn);
}
}
8002732: e04d b.n 80027d0 <I2Cx_MspInit+0x148>
DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
8002734: 4b29 ldr r3, [pc, #164] ; (80027dc <I2Cx_MspInit+0x154>)
8002736: 6b1b ldr r3, [r3, #48] ; 0x30
8002738: 4a28 ldr r2, [pc, #160] ; (80027dc <I2Cx_MspInit+0x154>)
800273a: f043 0302 orr.w r3, r3, #2
800273e: 6313 str r3, [r2, #48] ; 0x30
8002740: 4b26 ldr r3, [pc, #152] ; (80027dc <I2Cx_MspInit+0x154>)
8002742: 6b1b ldr r3, [r3, #48] ; 0x30
8002744: f003 0302 and.w r3, r3, #2
8002748: 613b str r3, [r7, #16]
800274a: 693b ldr r3, [r7, #16]
gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SCL_PIN;
800274c: f44f 7380 mov.w r3, #256 ; 0x100
8002750: 61fb str r3, [r7, #28]
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
8002752: 2312 movs r3, #18
8002754: 623b str r3, [r7, #32]
gpio_init_structure.Pull = GPIO_NOPULL;
8002756: 2300 movs r3, #0
8002758: 627b str r3, [r7, #36] ; 0x24
gpio_init_structure.Speed = GPIO_SPEED_FAST;
800275a: 2302 movs r3, #2
800275c: 62bb str r3, [r7, #40] ; 0x28
gpio_init_structure.Alternate = DISCOVERY_EXT_I2Cx_SCL_SDA_AF;
800275e: 2304 movs r3, #4
8002760: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
8002762: f107 031c add.w r3, r7, #28
8002766: 4619 mov r1, r3
8002768: 481e ldr r0, [pc, #120] ; (80027e4 <I2Cx_MspInit+0x15c>)
800276a: f004 fcc9 bl 8007100 <HAL_GPIO_Init>
gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SDA_PIN;
800276e: f44f 7300 mov.w r3, #512 ; 0x200
8002772: 61fb str r3, [r7, #28]
HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
8002774: f107 031c add.w r3, r7, #28
8002778: 4619 mov r1, r3
800277a: 481a ldr r0, [pc, #104] ; (80027e4 <I2Cx_MspInit+0x15c>)
800277c: f004 fcc0 bl 8007100 <HAL_GPIO_Init>
DISCOVERY_EXT_I2Cx_CLK_ENABLE();
8002780: 4b16 ldr r3, [pc, #88] ; (80027dc <I2Cx_MspInit+0x154>)
8002782: 6c1b ldr r3, [r3, #64] ; 0x40
8002784: 4a15 ldr r2, [pc, #84] ; (80027dc <I2Cx_MspInit+0x154>)
8002786: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
800278a: 6413 str r3, [r2, #64] ; 0x40
800278c: 4b13 ldr r3, [pc, #76] ; (80027dc <I2Cx_MspInit+0x154>)
800278e: 6c1b ldr r3, [r3, #64] ; 0x40
8002790: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8002794: 60fb str r3, [r7, #12]
8002796: 68fb ldr r3, [r7, #12]
DISCOVERY_EXT_I2Cx_FORCE_RESET();
8002798: 4b10 ldr r3, [pc, #64] ; (80027dc <I2Cx_MspInit+0x154>)
800279a: 6a1b ldr r3, [r3, #32]
800279c: 4a0f ldr r2, [pc, #60] ; (80027dc <I2Cx_MspInit+0x154>)
800279e: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
80027a2: 6213 str r3, [r2, #32]
DISCOVERY_EXT_I2Cx_RELEASE_RESET();
80027a4: 4b0d ldr r3, [pc, #52] ; (80027dc <I2Cx_MspInit+0x154>)
80027a6: 6a1b ldr r3, [r3, #32]
80027a8: 4a0c ldr r2, [pc, #48] ; (80027dc <I2Cx_MspInit+0x154>)
80027aa: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
80027ae: 6213 str r3, [r2, #32]
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_EV_IRQn, 0x0F, 0);
80027b0: 2200 movs r2, #0
80027b2: 210f movs r1, #15
80027b4: 201f movs r0, #31
80027b6: f002 fce1 bl 800517c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_EV_IRQn);
80027ba: 201f movs r0, #31
80027bc: f002 fcfa bl 80051b4 <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0);
80027c0: 2200 movs r2, #0
80027c2: 210f movs r1, #15
80027c4: 2020 movs r0, #32
80027c6: f002 fcd9 bl 800517c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn);
80027ca: 2020 movs r0, #32
80027cc: f002 fcf2 bl 80051b4 <HAL_NVIC_EnableIRQ>
}
80027d0: bf00 nop
80027d2: 3730 adds r7, #48 ; 0x30
80027d4: 46bd mov sp, r7
80027d6: bd80 pop {r7, pc}
80027d8: 20000384 .word 0x20000384
80027dc: 40023800 .word 0x40023800
80027e0: 40021c00 .word 0x40021c00
80027e4: 40020400 .word 0x40020400
080027e8 <I2Cx_Init>:
* @brief Initializes I2C HAL.
* @param i2c_handler : I2C handler
* @retval None
*/
static void I2Cx_Init(I2C_HandleTypeDef *i2c_handler)
{
80027e8: b580 push {r7, lr}
80027ea: b082 sub sp, #8
80027ec: af00 add r7, sp, #0
80027ee: 6078 str r0, [r7, #4]
if(HAL_I2C_GetState(i2c_handler) == HAL_I2C_STATE_RESET)
80027f0: 6878 ldr r0, [r7, #4]
80027f2: f005 f94d bl 8007a90 <HAL_I2C_GetState>
80027f6: 4603 mov r3, r0
80027f8: 2b00 cmp r3, #0
80027fa: d125 bne.n 8002848 <I2Cx_Init+0x60>
{
if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler))
80027fc: 687b ldr r3, [r7, #4]
80027fe: 4a14 ldr r2, [pc, #80] ; (8002850 <I2Cx_Init+0x68>)
8002800: 4293 cmp r3, r2
8002802: d103 bne.n 800280c <I2Cx_Init+0x24>
{
/* Audio and LCD I2C configuration */
i2c_handler->Instance = DISCOVERY_AUDIO_I2Cx;
8002804: 687b ldr r3, [r7, #4]
8002806: 4a13 ldr r2, [pc, #76] ; (8002854 <I2Cx_Init+0x6c>)
8002808: 601a str r2, [r3, #0]
800280a: e002 b.n 8002812 <I2Cx_Init+0x2a>
}
else
{
/* External, camera and Arduino connector I2C configuration */
i2c_handler->Instance = DISCOVERY_EXT_I2Cx;
800280c: 687b ldr r3, [r7, #4]
800280e: 4a12 ldr r2, [pc, #72] ; (8002858 <I2Cx_Init+0x70>)
8002810: 601a str r2, [r3, #0]
}
i2c_handler->Init.Timing = DISCOVERY_I2Cx_TIMING;
8002812: 687b ldr r3, [r7, #4]
8002814: 4a11 ldr r2, [pc, #68] ; (800285c <I2Cx_Init+0x74>)
8002816: 605a str r2, [r3, #4]
i2c_handler->Init.OwnAddress1 = 0;
8002818: 687b ldr r3, [r7, #4]
800281a: 2200 movs r2, #0
800281c: 609a str r2, [r3, #8]
i2c_handler->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
800281e: 687b ldr r3, [r7, #4]
8002820: 2201 movs r2, #1
8002822: 60da str r2, [r3, #12]
i2c_handler->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
8002824: 687b ldr r3, [r7, #4]
8002826: 2200 movs r2, #0
8002828: 611a str r2, [r3, #16]
i2c_handler->Init.OwnAddress2 = 0;
800282a: 687b ldr r3, [r7, #4]
800282c: 2200 movs r2, #0
800282e: 615a str r2, [r3, #20]
i2c_handler->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8002830: 687b ldr r3, [r7, #4]
8002832: 2200 movs r2, #0
8002834: 61da str r2, [r3, #28]
i2c_handler->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8002836: 687b ldr r3, [r7, #4]
8002838: 2200 movs r2, #0
800283a: 621a str r2, [r3, #32]
/* Init the I2C */
I2Cx_MspInit(i2c_handler);
800283c: 6878 ldr r0, [r7, #4]
800283e: f7ff ff23 bl 8002688 <I2Cx_MspInit>
HAL_I2C_Init(i2c_handler);
8002842: 6878 ldr r0, [r7, #4]
8002844: f004 fe22 bl 800748c <HAL_I2C_Init>
}
}
8002848: bf00 nop
800284a: 3708 adds r7, #8
800284c: 46bd mov sp, r7
800284e: bd80 pop {r7, pc}
8002850: 20000384 .word 0x20000384
8002854: 40005c00 .word 0x40005c00
8002858: 40005400 .word 0x40005400
800285c: 40912732 .word 0x40912732
08002860 <I2Cx_ReadMultiple>:
uint8_t Addr,
uint16_t Reg,
uint16_t MemAddress,
uint8_t *Buffer,
uint16_t Length)
{
8002860: b580 push {r7, lr}
8002862: b08a sub sp, #40 ; 0x28
8002864: af04 add r7, sp, #16
8002866: 60f8 str r0, [r7, #12]
8002868: 4608 mov r0, r1
800286a: 4611 mov r1, r2
800286c: 461a mov r2, r3
800286e: 4603 mov r3, r0
8002870: 72fb strb r3, [r7, #11]
8002872: 460b mov r3, r1
8002874: 813b strh r3, [r7, #8]
8002876: 4613 mov r3, r2
8002878: 80fb strh r3, [r7, #6]
HAL_StatusTypeDef status = HAL_OK;
800287a: 2300 movs r3, #0
800287c: 75fb strb r3, [r7, #23]
status = HAL_I2C_Mem_Read(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
800287e: 7afb ldrb r3, [r7, #11]
8002880: b299 uxth r1, r3
8002882: 88f8 ldrh r0, [r7, #6]
8002884: 893a ldrh r2, [r7, #8]
8002886: f44f 737a mov.w r3, #1000 ; 0x3e8
800288a: 9302 str r3, [sp, #8]
800288c: 8cbb ldrh r3, [r7, #36] ; 0x24
800288e: 9301 str r3, [sp, #4]
8002890: 6a3b ldr r3, [r7, #32]
8002892: 9300 str r3, [sp, #0]
8002894: 4603 mov r3, r0
8002896: 68f8 ldr r0, [r7, #12]
8002898: f004 ffe0 bl 800785c <HAL_I2C_Mem_Read>
800289c: 4603 mov r3, r0
800289e: 75fb strb r3, [r7, #23]
/* Check the communication status */
if(status != HAL_OK)
80028a0: 7dfb ldrb r3, [r7, #23]
80028a2: 2b00 cmp r3, #0
80028a4: d004 beq.n 80028b0 <I2Cx_ReadMultiple+0x50>
{
/* I2C error occurred */
I2Cx_Error(i2c_handler, Addr);
80028a6: 7afb ldrb r3, [r7, #11]
80028a8: 4619 mov r1, r3
80028aa: 68f8 ldr r0, [r7, #12]
80028ac: f000 f832 bl 8002914 <I2Cx_Error>
}
return status;
80028b0: 7dfb ldrb r3, [r7, #23]
}
80028b2: 4618 mov r0, r3
80028b4: 3718 adds r7, #24
80028b6: 46bd mov sp, r7
80028b8: bd80 pop {r7, pc}
080028ba <I2Cx_WriteMultiple>:
uint8_t Addr,
uint16_t Reg,
uint16_t MemAddress,
uint8_t *Buffer,
uint16_t Length)
{
80028ba: b580 push {r7, lr}
80028bc: b08a sub sp, #40 ; 0x28
80028be: af04 add r7, sp, #16
80028c0: 60f8 str r0, [r7, #12]
80028c2: 4608 mov r0, r1
80028c4: 4611 mov r1, r2
80028c6: 461a mov r2, r3
80028c8: 4603 mov r3, r0
80028ca: 72fb strb r3, [r7, #11]
80028cc: 460b mov r3, r1
80028ce: 813b strh r3, [r7, #8]
80028d0: 4613 mov r3, r2
80028d2: 80fb strh r3, [r7, #6]
HAL_StatusTypeDef status = HAL_OK;
80028d4: 2300 movs r3, #0
80028d6: 75fb strb r3, [r7, #23]
status = HAL_I2C_Mem_Write(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
80028d8: 7afb ldrb r3, [r7, #11]
80028da: b299 uxth r1, r3
80028dc: 88f8 ldrh r0, [r7, #6]
80028de: 893a ldrh r2, [r7, #8]
80028e0: f44f 737a mov.w r3, #1000 ; 0x3e8
80028e4: 9302 str r3, [sp, #8]
80028e6: 8cbb ldrh r3, [r7, #36] ; 0x24
80028e8: 9301 str r3, [sp, #4]
80028ea: 6a3b ldr r3, [r7, #32]
80028ec: 9300 str r3, [sp, #0]
80028ee: 4603 mov r3, r0
80028f0: 68f8 ldr r0, [r7, #12]
80028f2: f004 fe9f bl 8007634 <HAL_I2C_Mem_Write>
80028f6: 4603 mov r3, r0
80028f8: 75fb strb r3, [r7, #23]
/* Check the communication status */
if(status != HAL_OK)
80028fa: 7dfb ldrb r3, [r7, #23]
80028fc: 2b00 cmp r3, #0
80028fe: d004 beq.n 800290a <I2Cx_WriteMultiple+0x50>
{
/* Re-Initiaize the I2C Bus */
I2Cx_Error(i2c_handler, Addr);
8002900: 7afb ldrb r3, [r7, #11]
8002902: 4619 mov r1, r3
8002904: 68f8 ldr r0, [r7, #12]
8002906: f000 f805 bl 8002914 <I2Cx_Error>
}
return status;
800290a: 7dfb ldrb r3, [r7, #23]
}
800290c: 4618 mov r0, r3
800290e: 3718 adds r7, #24
8002910: 46bd mov sp, r7
8002912: bd80 pop {r7, pc}
08002914 <I2Cx_Error>:
* @param i2c_handler : I2C handler
* @param Addr: I2C Address
* @retval None
*/
static void I2Cx_Error(I2C_HandleTypeDef *i2c_handler, uint8_t Addr)
{
8002914: b580 push {r7, lr}
8002916: b082 sub sp, #8
8002918: af00 add r7, sp, #0
800291a: 6078 str r0, [r7, #4]
800291c: 460b mov r3, r1
800291e: 70fb strb r3, [r7, #3]
/* De-initialize the I2C communication bus */
HAL_I2C_DeInit(i2c_handler);
8002920: 6878 ldr r0, [r7, #4]
8002922: f004 fe43 bl 80075ac <HAL_I2C_DeInit>
/* Re-Initialize the I2C communication bus */
I2Cx_Init(i2c_handler);
8002926: 6878 ldr r0, [r7, #4]
8002928: f7ff ff5e bl 80027e8 <I2Cx_Init>
}
800292c: bf00 nop
800292e: 3708 adds r7, #8
8002930: 46bd mov sp, r7
8002932: bd80 pop {r7, pc}
08002934 <TS_IO_Init>:
/**
* @brief Initializes Touchscreen low level.
* @retval None
*/
void TS_IO_Init(void)
{
8002934: b580 push {r7, lr}
8002936: af00 add r7, sp, #0
I2Cx_Init(&hI2cAudioHandler);
8002938: 4802 ldr r0, [pc, #8] ; (8002944 <TS_IO_Init+0x10>)
800293a: f7ff ff55 bl 80027e8 <I2Cx_Init>
}
800293e: bf00 nop
8002940: bd80 pop {r7, pc}
8002942: bf00 nop
8002944: 20000384 .word 0x20000384
08002948 <TS_IO_Write>:
* @param Reg: Reg address
* @param Value: Data to be written
* @retval None
*/
void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
{
8002948: b580 push {r7, lr}
800294a: b084 sub sp, #16
800294c: af02 add r7, sp, #8
800294e: 4603 mov r3, r0
8002950: 71fb strb r3, [r7, #7]
8002952: 460b mov r3, r1
8002954: 71bb strb r3, [r7, #6]
8002956: 4613 mov r3, r2
8002958: 717b strb r3, [r7, #5]
I2Cx_WriteMultiple(&hI2cAudioHandler, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT,(uint8_t*)&Value, 1);
800295a: 79bb ldrb r3, [r7, #6]
800295c: b29a uxth r2, r3
800295e: 79f9 ldrb r1, [r7, #7]
8002960: 2301 movs r3, #1
8002962: 9301 str r3, [sp, #4]
8002964: 1d7b adds r3, r7, #5
8002966: 9300 str r3, [sp, #0]
8002968: 2301 movs r3, #1
800296a: 4803 ldr r0, [pc, #12] ; (8002978 <TS_IO_Write+0x30>)
800296c: f7ff ffa5 bl 80028ba <I2Cx_WriteMultiple>
}
8002970: bf00 nop
8002972: 3708 adds r7, #8
8002974: 46bd mov sp, r7
8002976: bd80 pop {r7, pc}
8002978: 20000384 .word 0x20000384
0800297c <TS_IO_Read>:
* @param Addr: I2C address
* @param Reg: Reg address
* @retval Data to be read
*/
uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg)
{
800297c: b580 push {r7, lr}
800297e: b086 sub sp, #24
8002980: af02 add r7, sp, #8
8002982: 4603 mov r3, r0
8002984: 460a mov r2, r1
8002986: 71fb strb r3, [r7, #7]
8002988: 4613 mov r3, r2
800298a: 71bb strb r3, [r7, #6]
uint8_t read_value = 0;
800298c: 2300 movs r3, #0
800298e: 73fb strb r3, [r7, #15]
I2Cx_ReadMultiple(&hI2cAudioHandler, Addr, Reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)&read_value, 1);
8002990: 79bb ldrb r3, [r7, #6]
8002992: b29a uxth r2, r3
8002994: 79f9 ldrb r1, [r7, #7]
8002996: 2301 movs r3, #1
8002998: 9301 str r3, [sp, #4]
800299a: f107 030f add.w r3, r7, #15
800299e: 9300 str r3, [sp, #0]
80029a0: 2301 movs r3, #1
80029a2: 4804 ldr r0, [pc, #16] ; (80029b4 <TS_IO_Read+0x38>)
80029a4: f7ff ff5c bl 8002860 <I2Cx_ReadMultiple>
return read_value;
80029a8: 7bfb ldrb r3, [r7, #15]
}
80029aa: 4618 mov r0, r3
80029ac: 3710 adds r7, #16
80029ae: 46bd mov sp, r7
80029b0: bd80 pop {r7, pc}
80029b2: bf00 nop
80029b4: 20000384 .word 0x20000384
080029b8 <TS_IO_Delay>:
* @brief TS delay
* @param Delay: Delay in ms
* @retval None
*/
void TS_IO_Delay(uint32_t Delay)
{
80029b8: b580 push {r7, lr}
80029ba: b082 sub sp, #8
80029bc: af00 add r7, sp, #0
80029be: 6078 str r0, [r7, #4]
HAL_Delay(Delay);
80029c0: 6878 ldr r0, [r7, #4]
80029c2: f001 ff11 bl 80047e8 <HAL_Delay>
}
80029c6: bf00 nop
80029c8: 3708 adds r7, #8
80029ca: 46bd mov sp, r7
80029cc: bd80 pop {r7, pc}
...
080029d0 <BSP_LCD_Init>:
/**
* @brief Initializes the LCD.
* @retval LCD state
*/
uint8_t BSP_LCD_Init(void)
{
80029d0: b580 push {r7, lr}
80029d2: af00 add r7, sp, #0
/* Select the used LCD */
/* The RK043FN48H LCD 480x272 is selected */
/* Timing Configuration */
hLtdcHandler.Init.HorizontalSync = (RK043FN48H_HSYNC - 1);
80029d4: 4b31 ldr r3, [pc, #196] ; (8002a9c <BSP_LCD_Init+0xcc>)
80029d6: 2228 movs r2, #40 ; 0x28
80029d8: 615a str r2, [r3, #20]
hLtdcHandler.Init.VerticalSync = (RK043FN48H_VSYNC - 1);
80029da: 4b30 ldr r3, [pc, #192] ; (8002a9c <BSP_LCD_Init+0xcc>)
80029dc: 2209 movs r2, #9
80029de: 619a str r2, [r3, #24]
hLtdcHandler.Init.AccumulatedHBP = (RK043FN48H_HSYNC + RK043FN48H_HBP - 1);
80029e0: 4b2e ldr r3, [pc, #184] ; (8002a9c <BSP_LCD_Init+0xcc>)
80029e2: 2235 movs r2, #53 ; 0x35
80029e4: 61da str r2, [r3, #28]
hLtdcHandler.Init.AccumulatedVBP = (RK043FN48H_VSYNC + RK043FN48H_VBP - 1);
80029e6: 4b2d ldr r3, [pc, #180] ; (8002a9c <BSP_LCD_Init+0xcc>)
80029e8: 220b movs r2, #11
80029ea: 621a str r2, [r3, #32]
hLtdcHandler.Init.AccumulatedActiveH = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP - 1);
80029ec: 4b2b ldr r3, [pc, #172] ; (8002a9c <BSP_LCD_Init+0xcc>)
80029ee: f240 121b movw r2, #283 ; 0x11b
80029f2: 629a str r2, [r3, #40] ; 0x28
hLtdcHandler.Init.AccumulatedActiveW = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP - 1);
80029f4: 4b29 ldr r3, [pc, #164] ; (8002a9c <BSP_LCD_Init+0xcc>)
80029f6: f240 2215 movw r2, #533 ; 0x215
80029fa: 625a str r2, [r3, #36] ; 0x24
hLtdcHandler.Init.TotalHeigh = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP + RK043FN48H_VFP - 1);
80029fc: 4b27 ldr r3, [pc, #156] ; (8002a9c <BSP_LCD_Init+0xcc>)
80029fe: f240 121d movw r2, #285 ; 0x11d
8002a02: 631a str r2, [r3, #48] ; 0x30
hLtdcHandler.Init.TotalWidth = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP + RK043FN48H_HFP - 1);
8002a04: 4b25 ldr r3, [pc, #148] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a06: f240 2235 movw r2, #565 ; 0x235
8002a0a: 62da str r2, [r3, #44] ; 0x2c
/* LCD clock configuration */
BSP_LCD_ClockConfig(&hLtdcHandler, NULL);
8002a0c: 2100 movs r1, #0
8002a0e: 4823 ldr r0, [pc, #140] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a10: f000 fcfc bl 800340c <BSP_LCD_ClockConfig>
/* Initialize the LCD pixel width and pixel height */
hLtdcHandler.LayerCfg->ImageWidth = RK043FN48H_WIDTH;
8002a14: 4b21 ldr r3, [pc, #132] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a16: f44f 72f0 mov.w r2, #480 ; 0x1e0
8002a1a: 661a str r2, [r3, #96] ; 0x60
hLtdcHandler.LayerCfg->ImageHeight = RK043FN48H_HEIGHT;
8002a1c: 4b1f ldr r3, [pc, #124] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a1e: f44f 7288 mov.w r2, #272 ; 0x110
8002a22: 665a str r2, [r3, #100] ; 0x64
/* Background value */
hLtdcHandler.Init.Backcolor.Blue = 0;
8002a24: 4b1d ldr r3, [pc, #116] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a26: 2200 movs r2, #0
8002a28: f883 2034 strb.w r2, [r3, #52] ; 0x34
hLtdcHandler.Init.Backcolor.Green = 0;
8002a2c: 4b1b ldr r3, [pc, #108] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a2e: 2200 movs r2, #0
8002a30: f883 2035 strb.w r2, [r3, #53] ; 0x35
hLtdcHandler.Init.Backcolor.Red = 0;
8002a34: 4b19 ldr r3, [pc, #100] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a36: 2200 movs r2, #0
8002a38: f883 2036 strb.w r2, [r3, #54] ; 0x36
/* Polarity */
hLtdcHandler.Init.HSPolarity = LTDC_HSPOLARITY_AL;
8002a3c: 4b17 ldr r3, [pc, #92] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a3e: 2200 movs r2, #0
8002a40: 605a str r2, [r3, #4]
hLtdcHandler.Init.VSPolarity = LTDC_VSPOLARITY_AL;
8002a42: 4b16 ldr r3, [pc, #88] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a44: 2200 movs r2, #0
8002a46: 609a str r2, [r3, #8]
hLtdcHandler.Init.DEPolarity = LTDC_DEPOLARITY_AL;
8002a48: 4b14 ldr r3, [pc, #80] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a4a: 2200 movs r2, #0
8002a4c: 60da str r2, [r3, #12]
hLtdcHandler.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
8002a4e: 4b13 ldr r3, [pc, #76] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a50: 2200 movs r2, #0
8002a52: 611a str r2, [r3, #16]
hLtdcHandler.Instance = LTDC;
8002a54: 4b11 ldr r3, [pc, #68] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a56: 4a12 ldr r2, [pc, #72] ; (8002aa0 <BSP_LCD_Init+0xd0>)
8002a58: 601a str r2, [r3, #0]
if(HAL_LTDC_GetState(&hLtdcHandler) == HAL_LTDC_STATE_RESET)
8002a5a: 4810 ldr r0, [pc, #64] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a5c: f005 fc12 bl 8008284 <HAL_LTDC_GetState>
8002a60: 4603 mov r3, r0
8002a62: 2b00 cmp r3, #0
8002a64: d103 bne.n 8002a6e <BSP_LCD_Init+0x9e>
{
/* Initialize the LCD Msp: this __weak function can be rewritten by the application */
BSP_LCD_MspInit(&hLtdcHandler, NULL);
8002a66: 2100 movs r1, #0
8002a68: 480c ldr r0, [pc, #48] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a6a: f000 fbf5 bl 8003258 <BSP_LCD_MspInit>
}
HAL_LTDC_Init(&hLtdcHandler);
8002a6e: 480b ldr r0, [pc, #44] ; (8002a9c <BSP_LCD_Init+0xcc>)
8002a70: f005 fa38 bl 8007ee4 <HAL_LTDC_Init>
/* Assert display enable LCD_DISP pin */
HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET);
8002a74: 2201 movs r2, #1
8002a76: f44f 5180 mov.w r1, #4096 ; 0x1000
8002a7a: 480a ldr r0, [pc, #40] ; (8002aa4 <BSP_LCD_Init+0xd4>)
8002a7c: f004 fcec bl 8007458 <HAL_GPIO_WritePin>
/* Assert backlight LCD_BL_CTRL pin */
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET);
8002a80: 2201 movs r2, #1
8002a82: 2108 movs r1, #8
8002a84: 4808 ldr r0, [pc, #32] ; (8002aa8 <BSP_LCD_Init+0xd8>)
8002a86: f004 fce7 bl 8007458 <HAL_GPIO_WritePin>
#if !defined(DATA_IN_ExtSDRAM)
/* Initialize the SDRAM */
BSP_SDRAM_Init();
8002a8a: f000 fd27 bl 80034dc <BSP_SDRAM_Init>
#endif
/* Initialize the font */
BSP_LCD_SetFont(&LCD_DEFAULT_FONT);
8002a8e: 4807 ldr r0, [pc, #28] ; (8002aac <BSP_LCD_Init+0xdc>)
8002a90: f000 f8d8 bl 8002c44 <BSP_LCD_SetFont>
return LCD_OK;
8002a94: 2300 movs r3, #0
}
8002a96: 4618 mov r0, r3
8002a98: bd80 pop {r7, pc}
8002a9a: bf00 nop
8002a9c: 20008ea4 .word 0x20008ea4
8002aa0: 40016800 .word 0x40016800
8002aa4: 40022000 .word 0x40022000
8002aa8: 40022800 .word 0x40022800
8002aac: 20000044 .word 0x20000044
08002ab0 <BSP_LCD_GetXSize>:
/**
* @brief Gets the LCD X size.
* @retval Used LCD X size
*/
uint32_t BSP_LCD_GetXSize(void)
{
8002ab0: b480 push {r7}
8002ab2: af00 add r7, sp, #0
return hLtdcHandler.LayerCfg[ActiveLayer].ImageWidth;
8002ab4: 4b06 ldr r3, [pc, #24] ; (8002ad0 <BSP_LCD_GetXSize+0x20>)
8002ab6: 681b ldr r3, [r3, #0]
8002ab8: 4a06 ldr r2, [pc, #24] ; (8002ad4 <BSP_LCD_GetXSize+0x24>)
8002aba: 2134 movs r1, #52 ; 0x34
8002abc: fb01 f303 mul.w r3, r1, r3
8002ac0: 4413 add r3, r2
8002ac2: 3360 adds r3, #96 ; 0x60
8002ac4: 681b ldr r3, [r3, #0]
}
8002ac6: 4618 mov r0, r3
8002ac8: 46bd mov sp, r7
8002aca: f85d 7b04 ldr.w r7, [sp], #4
8002ace: 4770 bx lr
8002ad0: 20000410 .word 0x20000410
8002ad4: 20008ea4 .word 0x20008ea4
08002ad8 <BSP_LCD_GetYSize>:
/**
* @brief Gets the LCD Y size.
* @retval Used LCD Y size
*/
uint32_t BSP_LCD_GetYSize(void)
{
8002ad8: b480 push {r7}
8002ada: af00 add r7, sp, #0
return hLtdcHandler.LayerCfg[ActiveLayer].ImageHeight;
8002adc: 4b06 ldr r3, [pc, #24] ; (8002af8 <BSP_LCD_GetYSize+0x20>)
8002ade: 681b ldr r3, [r3, #0]
8002ae0: 4a06 ldr r2, [pc, #24] ; (8002afc <BSP_LCD_GetYSize+0x24>)
8002ae2: 2134 movs r1, #52 ; 0x34
8002ae4: fb01 f303 mul.w r3, r1, r3
8002ae8: 4413 add r3, r2
8002aea: 3364 adds r3, #100 ; 0x64
8002aec: 681b ldr r3, [r3, #0]
}
8002aee: 4618 mov r0, r3
8002af0: 46bd mov sp, r7
8002af2: f85d 7b04 ldr.w r7, [sp], #4
8002af6: 4770 bx lr
8002af8: 20000410 .word 0x20000410
8002afc: 20008ea4 .word 0x20008ea4
08002b00 <BSP_LCD_LayerDefaultInit>:
* @param LayerIndex: Layer foreground or background
* @param FB_Address: Layer frame buffer
* @retval None
*/
void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FB_Address)
{
8002b00: b580 push {r7, lr}
8002b02: b090 sub sp, #64 ; 0x40
8002b04: af00 add r7, sp, #0
8002b06: 4603 mov r3, r0
8002b08: 6039 str r1, [r7, #0]
8002b0a: 80fb strh r3, [r7, #6]
LCD_LayerCfgTypeDef layer_cfg;
/* Layer Init */
layer_cfg.WindowX0 = 0;
8002b0c: 2300 movs r3, #0
8002b0e: 60fb str r3, [r7, #12]
layer_cfg.WindowX1 = BSP_LCD_GetXSize();
8002b10: f7ff ffce bl 8002ab0 <BSP_LCD_GetXSize>
8002b14: 4603 mov r3, r0
8002b16: 613b str r3, [r7, #16]
layer_cfg.WindowY0 = 0;
8002b18: 2300 movs r3, #0
8002b1a: 617b str r3, [r7, #20]
layer_cfg.WindowY1 = BSP_LCD_GetYSize();
8002b1c: f7ff ffdc bl 8002ad8 <BSP_LCD_GetYSize>
8002b20: 4603 mov r3, r0
8002b22: 61bb str r3, [r7, #24]
layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
8002b24: 2300 movs r3, #0
8002b26: 61fb str r3, [r7, #28]
layer_cfg.FBStartAdress = FB_Address;
8002b28: 683b ldr r3, [r7, #0]
8002b2a: 633b str r3, [r7, #48] ; 0x30
layer_cfg.Alpha = 255;
8002b2c: 23ff movs r3, #255 ; 0xff
8002b2e: 623b str r3, [r7, #32]
layer_cfg.Alpha0 = 0;
8002b30: 2300 movs r3, #0
8002b32: 627b str r3, [r7, #36] ; 0x24
layer_cfg.Backcolor.Blue = 0;
8002b34: 2300 movs r3, #0
8002b36: f887 303c strb.w r3, [r7, #60] ; 0x3c
layer_cfg.Backcolor.Green = 0;
8002b3a: 2300 movs r3, #0
8002b3c: f887 303d strb.w r3, [r7, #61] ; 0x3d
layer_cfg.Backcolor.Red = 0;
8002b40: 2300 movs r3, #0
8002b42: f887 303e strb.w r3, [r7, #62] ; 0x3e
layer_cfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
8002b46: f44f 63c0 mov.w r3, #1536 ; 0x600
8002b4a: 62bb str r3, [r7, #40] ; 0x28
layer_cfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
8002b4c: 2307 movs r3, #7
8002b4e: 62fb str r3, [r7, #44] ; 0x2c
layer_cfg.ImageWidth = BSP_LCD_GetXSize();
8002b50: f7ff ffae bl 8002ab0 <BSP_LCD_GetXSize>
8002b54: 4603 mov r3, r0
8002b56: 637b str r3, [r7, #52] ; 0x34
layer_cfg.ImageHeight = BSP_LCD_GetYSize();
8002b58: f7ff ffbe bl 8002ad8 <BSP_LCD_GetYSize>
8002b5c: 4603 mov r3, r0
8002b5e: 63bb str r3, [r7, #56] ; 0x38
HAL_LTDC_ConfigLayer(&hLtdcHandler, &layer_cfg, LayerIndex);
8002b60: 88fa ldrh r2, [r7, #6]
8002b62: f107 030c add.w r3, r7, #12
8002b66: 4619 mov r1, r3
8002b68: 4812 ldr r0, [pc, #72] ; (8002bb4 <BSP_LCD_LayerDefaultInit+0xb4>)
8002b6a: f005 fb4d bl 8008208 <HAL_LTDC_ConfigLayer>
DrawProp[LayerIndex].BackColor = LCD_COLOR_WHITE;
8002b6e: 88fa ldrh r2, [r7, #6]
8002b70: 4911 ldr r1, [pc, #68] ; (8002bb8 <BSP_LCD_LayerDefaultInit+0xb8>)
8002b72: 4613 mov r3, r2
8002b74: 005b lsls r3, r3, #1
8002b76: 4413 add r3, r2
8002b78: 009b lsls r3, r3, #2
8002b7a: 440b add r3, r1
8002b7c: 3304 adds r3, #4
8002b7e: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
8002b82: 601a str r2, [r3, #0]
DrawProp[LayerIndex].pFont = &Font24;
8002b84: 88fa ldrh r2, [r7, #6]
8002b86: 490c ldr r1, [pc, #48] ; (8002bb8 <BSP_LCD_LayerDefaultInit+0xb8>)
8002b88: 4613 mov r3, r2
8002b8a: 005b lsls r3, r3, #1
8002b8c: 4413 add r3, r2
8002b8e: 009b lsls r3, r3, #2
8002b90: 440b add r3, r1
8002b92: 3308 adds r3, #8
8002b94: 4a09 ldr r2, [pc, #36] ; (8002bbc <BSP_LCD_LayerDefaultInit+0xbc>)
8002b96: 601a str r2, [r3, #0]
DrawProp[LayerIndex].TextColor = LCD_COLOR_BLACK;
8002b98: 88fa ldrh r2, [r7, #6]
8002b9a: 4907 ldr r1, [pc, #28] ; (8002bb8 <BSP_LCD_LayerDefaultInit+0xb8>)
8002b9c: 4613 mov r3, r2
8002b9e: 005b lsls r3, r3, #1
8002ba0: 4413 add r3, r2
8002ba2: 009b lsls r3, r3, #2
8002ba4: 440b add r3, r1
8002ba6: f04f 427f mov.w r2, #4278190080 ; 0xff000000
8002baa: 601a str r2, [r3, #0]
}
8002bac: bf00 nop
8002bae: 3740 adds r7, #64 ; 0x40
8002bb0: 46bd mov sp, r7
8002bb2: bd80 pop {r7, pc}
8002bb4: 20008ea4 .word 0x20008ea4
8002bb8: 20000414 .word 0x20000414
8002bbc: 20000044 .word 0x20000044
08002bc0 <BSP_LCD_SelectLayer>:
* @brief Selects the LCD Layer.
* @param LayerIndex: Layer foreground or background
* @retval None
*/
void BSP_LCD_SelectLayer(uint32_t LayerIndex)
{
8002bc0: b480 push {r7}
8002bc2: b083 sub sp, #12
8002bc4: af00 add r7, sp, #0
8002bc6: 6078 str r0, [r7, #4]
ActiveLayer = LayerIndex;
8002bc8: 4a04 ldr r2, [pc, #16] ; (8002bdc <BSP_LCD_SelectLayer+0x1c>)
8002bca: 687b ldr r3, [r7, #4]
8002bcc: 6013 str r3, [r2, #0]
}
8002bce: bf00 nop
8002bd0: 370c adds r7, #12
8002bd2: 46bd mov sp, r7
8002bd4: f85d 7b04 ldr.w r7, [sp], #4
8002bd8: 4770 bx lr
8002bda: bf00 nop
8002bdc: 20000410 .word 0x20000410
08002be0 <BSP_LCD_SetTextColor>:
* @brief Sets the LCD text color.
* @param Color: Text color code ARGB(8-8-8-8)
* @retval None
*/
void BSP_LCD_SetTextColor(uint32_t Color)
{
8002be0: b480 push {r7}
8002be2: b083 sub sp, #12
8002be4: af00 add r7, sp, #0
8002be6: 6078 str r0, [r7, #4]
DrawProp[ActiveLayer].TextColor = Color;
8002be8: 4b07 ldr r3, [pc, #28] ; (8002c08 <BSP_LCD_SetTextColor+0x28>)
8002bea: 681a ldr r2, [r3, #0]
8002bec: 4907 ldr r1, [pc, #28] ; (8002c0c <BSP_LCD_SetTextColor+0x2c>)
8002bee: 4613 mov r3, r2
8002bf0: 005b lsls r3, r3, #1
8002bf2: 4413 add r3, r2
8002bf4: 009b lsls r3, r3, #2
8002bf6: 440b add r3, r1
8002bf8: 687a ldr r2, [r7, #4]
8002bfa: 601a str r2, [r3, #0]
}
8002bfc: bf00 nop
8002bfe: 370c adds r7, #12
8002c00: 46bd mov sp, r7
8002c02: f85d 7b04 ldr.w r7, [sp], #4
8002c06: 4770 bx lr
8002c08: 20000410 .word 0x20000410
8002c0c: 20000414 .word 0x20000414
08002c10 <BSP_LCD_SetBackColor>:
* @brief Sets the LCD background color.
* @param Color: Layer background color code ARGB(8-8-8-8)
* @retval None
*/
void BSP_LCD_SetBackColor(uint32_t Color)
{
8002c10: b480 push {r7}
8002c12: b083 sub sp, #12
8002c14: af00 add r7, sp, #0
8002c16: 6078 str r0, [r7, #4]
DrawProp[ActiveLayer].BackColor = Color;
8002c18: 4b08 ldr r3, [pc, #32] ; (8002c3c <BSP_LCD_SetBackColor+0x2c>)
8002c1a: 681a ldr r2, [r3, #0]
8002c1c: 4908 ldr r1, [pc, #32] ; (8002c40 <BSP_LCD_SetBackColor+0x30>)
8002c1e: 4613 mov r3, r2
8002c20: 005b lsls r3, r3, #1
8002c22: 4413 add r3, r2
8002c24: 009b lsls r3, r3, #2
8002c26: 440b add r3, r1
8002c28: 3304 adds r3, #4
8002c2a: 687a ldr r2, [r7, #4]
8002c2c: 601a str r2, [r3, #0]
}
8002c2e: bf00 nop
8002c30: 370c adds r7, #12
8002c32: 46bd mov sp, r7
8002c34: f85d 7b04 ldr.w r7, [sp], #4
8002c38: 4770 bx lr
8002c3a: bf00 nop
8002c3c: 20000410 .word 0x20000410
8002c40: 20000414 .word 0x20000414
08002c44 <BSP_LCD_SetFont>:
* @brief Sets the LCD text font.
* @param fonts: Layer font to be used
* @retval None
*/
void BSP_LCD_SetFont(sFONT *fonts)
{
8002c44: b480 push {r7}
8002c46: b083 sub sp, #12
8002c48: af00 add r7, sp, #0
8002c4a: 6078 str r0, [r7, #4]
DrawProp[ActiveLayer].pFont = fonts;
8002c4c: 4b08 ldr r3, [pc, #32] ; (8002c70 <BSP_LCD_SetFont+0x2c>)
8002c4e: 681a ldr r2, [r3, #0]
8002c50: 4908 ldr r1, [pc, #32] ; (8002c74 <BSP_LCD_SetFont+0x30>)
8002c52: 4613 mov r3, r2
8002c54: 005b lsls r3, r3, #1
8002c56: 4413 add r3, r2
8002c58: 009b lsls r3, r3, #2
8002c5a: 440b add r3, r1
8002c5c: 3308 adds r3, #8
8002c5e: 687a ldr r2, [r7, #4]
8002c60: 601a str r2, [r3, #0]
}
8002c62: bf00 nop
8002c64: 370c adds r7, #12
8002c66: 46bd mov sp, r7
8002c68: f85d 7b04 ldr.w r7, [sp], #4
8002c6c: 4770 bx lr
8002c6e: bf00 nop
8002c70: 20000410 .word 0x20000410
8002c74: 20000414 .word 0x20000414
08002c78 <BSP_LCD_Clear>:
* @brief Clears the hole LCD.
* @param Color: Color of the background
* @retval None
*/
void BSP_LCD_Clear(uint32_t Color)
{
8002c78: b5f0 push {r4, r5, r6, r7, lr}
8002c7a: b085 sub sp, #20
8002c7c: af02 add r7, sp, #8
8002c7e: 6078 str r0, [r7, #4]
/* Clear the LCD */
LL_FillBuffer(ActiveLayer, (uint32_t *)(hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress), BSP_LCD_GetXSize(), BSP_LCD_GetYSize(), 0, Color);
8002c80: 4b0f ldr r3, [pc, #60] ; (8002cc0 <BSP_LCD_Clear+0x48>)
8002c82: 681c ldr r4, [r3, #0]
8002c84: 4b0e ldr r3, [pc, #56] ; (8002cc0 <BSP_LCD_Clear+0x48>)
8002c86: 681b ldr r3, [r3, #0]
8002c88: 4a0e ldr r2, [pc, #56] ; (8002cc4 <BSP_LCD_Clear+0x4c>)
8002c8a: 2134 movs r1, #52 ; 0x34
8002c8c: fb01 f303 mul.w r3, r1, r3
8002c90: 4413 add r3, r2
8002c92: 335c adds r3, #92 ; 0x5c
8002c94: 681b ldr r3, [r3, #0]
8002c96: 461e mov r6, r3
8002c98: f7ff ff0a bl 8002ab0 <BSP_LCD_GetXSize>
8002c9c: 4605 mov r5, r0
8002c9e: f7ff ff1b bl 8002ad8 <BSP_LCD_GetYSize>
8002ca2: 4602 mov r2, r0
8002ca4: 687b ldr r3, [r7, #4]
8002ca6: 9301 str r3, [sp, #4]
8002ca8: 2300 movs r3, #0
8002caa: 9300 str r3, [sp, #0]
8002cac: 4613 mov r3, r2
8002cae: 462a mov r2, r5
8002cb0: 4631 mov r1, r6
8002cb2: 4620 mov r0, r4
8002cb4: f000 fbc6 bl 8003444 <LL_FillBuffer>
}
8002cb8: bf00 nop
8002cba: 370c adds r7, #12
8002cbc: 46bd mov sp, r7
8002cbe: bdf0 pop {r4, r5, r6, r7, pc}
8002cc0: 20000410 .word 0x20000410
8002cc4: 20008ea4 .word 0x20008ea4
08002cc8 <BSP_LCD_DrawHLine>:
* @param Ypos: Y position
* @param Length: Line length
* @retval None
*/
void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length)
{
8002cc8: b5b0 push {r4, r5, r7, lr}
8002cca: b086 sub sp, #24
8002ccc: af02 add r7, sp, #8
8002cce: 4603 mov r3, r0
8002cd0: 80fb strh r3, [r7, #6]
8002cd2: 460b mov r3, r1
8002cd4: 80bb strh r3, [r7, #4]
8002cd6: 4613 mov r3, r2
8002cd8: 807b strh r3, [r7, #2]
uint32_t Xaddress = 0;
8002cda: 2300 movs r3, #0
8002cdc: 60fb str r3, [r7, #12]
/* Get the line address */
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
8002cde: 4b26 ldr r3, [pc, #152] ; (8002d78 <BSP_LCD_DrawHLine+0xb0>)
8002ce0: 681b ldr r3, [r3, #0]
8002ce2: 4a26 ldr r2, [pc, #152] ; (8002d7c <BSP_LCD_DrawHLine+0xb4>)
8002ce4: 2134 movs r1, #52 ; 0x34
8002ce6: fb01 f303 mul.w r3, r1, r3
8002cea: 4413 add r3, r2
8002cec: 3348 adds r3, #72 ; 0x48
8002cee: 681b ldr r3, [r3, #0]
8002cf0: 2b02 cmp r3, #2
8002cf2: d114 bne.n 8002d1e <BSP_LCD_DrawHLine+0x56>
{ /* RGB565 format */
Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos);
8002cf4: 4b20 ldr r3, [pc, #128] ; (8002d78 <BSP_LCD_DrawHLine+0xb0>)
8002cf6: 681b ldr r3, [r3, #0]
8002cf8: 4a20 ldr r2, [pc, #128] ; (8002d7c <BSP_LCD_DrawHLine+0xb4>)
8002cfa: 2134 movs r1, #52 ; 0x34
8002cfc: fb01 f303 mul.w r3, r1, r3
8002d00: 4413 add r3, r2
8002d02: 335c adds r3, #92 ; 0x5c
8002d04: 681c ldr r4, [r3, #0]
8002d06: f7ff fed3 bl 8002ab0 <BSP_LCD_GetXSize>
8002d0a: 4602 mov r2, r0
8002d0c: 88bb ldrh r3, [r7, #4]
8002d0e: fb03 f202 mul.w r2, r3, r2
8002d12: 88fb ldrh r3, [r7, #6]
8002d14: 4413 add r3, r2
8002d16: 005b lsls r3, r3, #1
8002d18: 4423 add r3, r4
8002d1a: 60fb str r3, [r7, #12]
8002d1c: e013 b.n 8002d46 <BSP_LCD_DrawHLine+0x7e>
}
else
{ /* ARGB8888 format */
Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);
8002d1e: 4b16 ldr r3, [pc, #88] ; (8002d78 <BSP_LCD_DrawHLine+0xb0>)
8002d20: 681b ldr r3, [r3, #0]
8002d22: 4a16 ldr r2, [pc, #88] ; (8002d7c <BSP_LCD_DrawHLine+0xb4>)
8002d24: 2134 movs r1, #52 ; 0x34
8002d26: fb01 f303 mul.w r3, r1, r3
8002d2a: 4413 add r3, r2
8002d2c: 335c adds r3, #92 ; 0x5c
8002d2e: 681c ldr r4, [r3, #0]
8002d30: f7ff febe bl 8002ab0 <BSP_LCD_GetXSize>
8002d34: 4602 mov r2, r0
8002d36: 88bb ldrh r3, [r7, #4]
8002d38: fb03 f202 mul.w r2, r3, r2
8002d3c: 88fb ldrh r3, [r7, #6]
8002d3e: 4413 add r3, r2
8002d40: 009b lsls r3, r3, #2
8002d42: 4423 add r3, r4
8002d44: 60fb str r3, [r7, #12]
}
/* Write line */
LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, Length, 1, 0, DrawProp[ActiveLayer].TextColor);
8002d46: 4b0c ldr r3, [pc, #48] ; (8002d78 <BSP_LCD_DrawHLine+0xb0>)
8002d48: 6818 ldr r0, [r3, #0]
8002d4a: 68f9 ldr r1, [r7, #12]
8002d4c: 887c ldrh r4, [r7, #2]
8002d4e: 4b0a ldr r3, [pc, #40] ; (8002d78 <BSP_LCD_DrawHLine+0xb0>)
8002d50: 681a ldr r2, [r3, #0]
8002d52: 4d0b ldr r5, [pc, #44] ; (8002d80 <BSP_LCD_DrawHLine+0xb8>)
8002d54: 4613 mov r3, r2
8002d56: 005b lsls r3, r3, #1
8002d58: 4413 add r3, r2
8002d5a: 009b lsls r3, r3, #2
8002d5c: 442b add r3, r5
8002d5e: 681b ldr r3, [r3, #0]
8002d60: 9301 str r3, [sp, #4]
8002d62: 2300 movs r3, #0
8002d64: 9300 str r3, [sp, #0]
8002d66: 2301 movs r3, #1
8002d68: 4622 mov r2, r4
8002d6a: f000 fb6b bl 8003444 <LL_FillBuffer>
}
8002d6e: bf00 nop
8002d70: 3710 adds r7, #16
8002d72: 46bd mov sp, r7
8002d74: bdb0 pop {r4, r5, r7, pc}
8002d76: bf00 nop
8002d78: 20000410 .word 0x20000410
8002d7c: 20008ea4 .word 0x20008ea4
8002d80: 20000414 .word 0x20000414
08002d84 <BSP_LCD_DrawCircle>:
* @param Ypos: Y position
* @param Radius: Circle radius
* @retval None
*/
void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
{
8002d84: b590 push {r4, r7, lr}
8002d86: b087 sub sp, #28
8002d88: af00 add r7, sp, #0
8002d8a: 4603 mov r3, r0
8002d8c: 80fb strh r3, [r7, #6]
8002d8e: 460b mov r3, r1
8002d90: 80bb strh r3, [r7, #4]
8002d92: 4613 mov r3, r2
8002d94: 807b strh r3, [r7, #2]
int32_t decision; /* Decision Variable */
uint32_t current_x; /* Current X Value */
uint32_t current_y; /* Current Y Value */
decision = 3 - (Radius << 1);
8002d96: 887b ldrh r3, [r7, #2]
8002d98: 005b lsls r3, r3, #1
8002d9a: f1c3 0303 rsb r3, r3, #3
8002d9e: 617b str r3, [r7, #20]
current_x = 0;
8002da0: 2300 movs r3, #0
8002da2: 613b str r3, [r7, #16]
current_y = Radius;
8002da4: 887b ldrh r3, [r7, #2]
8002da6: 60fb str r3, [r7, #12]
while (current_x <= current_y)
8002da8: e0c7 b.n 8002f3a <BSP_LCD_DrawCircle+0x1b6>
{
BSP_LCD_DrawPixel((Xpos + current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor);
8002daa: 693b ldr r3, [r7, #16]
8002dac: b29a uxth r2, r3
8002dae: 88fb ldrh r3, [r7, #6]
8002db0: 4413 add r3, r2
8002db2: b298 uxth r0, r3
8002db4: 68fb ldr r3, [r7, #12]
8002db6: b29b uxth r3, r3
8002db8: 88ba ldrh r2, [r7, #4]
8002dba: 1ad3 subs r3, r2, r3
8002dbc: b299 uxth r1, r3
8002dbe: 4b64 ldr r3, [pc, #400] ; (8002f50 <BSP_LCD_DrawCircle+0x1cc>)
8002dc0: 681a ldr r2, [r3, #0]
8002dc2: 4c64 ldr r4, [pc, #400] ; (8002f54 <BSP_LCD_DrawCircle+0x1d0>)
8002dc4: 4613 mov r3, r2
8002dc6: 005b lsls r3, r3, #1
8002dc8: 4413 add r3, r2
8002dca: 009b lsls r3, r3, #2
8002dcc: 4423 add r3, r4
8002dce: 681b ldr r3, [r3, #0]
8002dd0: 461a mov r2, r3
8002dd2: f000 f8c1 bl 8002f58 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor);
8002dd6: 693b ldr r3, [r7, #16]
8002dd8: b29b uxth r3, r3
8002dda: 88fa ldrh r2, [r7, #6]
8002ddc: 1ad3 subs r3, r2, r3
8002dde: b298 uxth r0, r3
8002de0: 68fb ldr r3, [r7, #12]
8002de2: b29b uxth r3, r3
8002de4: 88ba ldrh r2, [r7, #4]
8002de6: 1ad3 subs r3, r2, r3
8002de8: b299 uxth r1, r3
8002dea: 4b59 ldr r3, [pc, #356] ; (8002f50 <BSP_LCD_DrawCircle+0x1cc>)
8002dec: 681a ldr r2, [r3, #0]
8002dee: 4c59 ldr r4, [pc, #356] ; (8002f54 <BSP_LCD_DrawCircle+0x1d0>)
8002df0: 4613 mov r3, r2
8002df2: 005b lsls r3, r3, #1
8002df4: 4413 add r3, r2
8002df6: 009b lsls r3, r3, #2
8002df8: 4423 add r3, r4
8002dfa: 681b ldr r3, [r3, #0]
8002dfc: 461a mov r2, r3
8002dfe: f000 f8ab bl 8002f58 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos + current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor);
8002e02: 68fb ldr r3, [r7, #12]
8002e04: b29a uxth r2, r3
8002e06: 88fb ldrh r3, [r7, #6]
8002e08: 4413 add r3, r2
8002e0a: b298 uxth r0, r3
8002e0c: 693b ldr r3, [r7, #16]
8002e0e: b29b uxth r3, r3
8002e10: 88ba ldrh r2, [r7, #4]
8002e12: 1ad3 subs r3, r2, r3
8002e14: b299 uxth r1, r3
8002e16: 4b4e ldr r3, [pc, #312] ; (8002f50 <BSP_LCD_DrawCircle+0x1cc>)
8002e18: 681a ldr r2, [r3, #0]
8002e1a: 4c4e ldr r4, [pc, #312] ; (8002f54 <BSP_LCD_DrawCircle+0x1d0>)
8002e1c: 4613 mov r3, r2
8002e1e: 005b lsls r3, r3, #1
8002e20: 4413 add r3, r2
8002e22: 009b lsls r3, r3, #2
8002e24: 4423 add r3, r4
8002e26: 681b ldr r3, [r3, #0]
8002e28: 461a mov r2, r3
8002e2a: f000 f895 bl 8002f58 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor);
8002e2e: 68fb ldr r3, [r7, #12]
8002e30: b29b uxth r3, r3
8002e32: 88fa ldrh r2, [r7, #6]
8002e34: 1ad3 subs r3, r2, r3
8002e36: b298 uxth r0, r3
8002e38: 693b ldr r3, [r7, #16]
8002e3a: b29b uxth r3, r3
8002e3c: 88ba ldrh r2, [r7, #4]
8002e3e: 1ad3 subs r3, r2, r3
8002e40: b299 uxth r1, r3
8002e42: 4b43 ldr r3, [pc, #268] ; (8002f50 <BSP_LCD_DrawCircle+0x1cc>)
8002e44: 681a ldr r2, [r3, #0]
8002e46: 4c43 ldr r4, [pc, #268] ; (8002f54 <BSP_LCD_DrawCircle+0x1d0>)
8002e48: 4613 mov r3, r2
8002e4a: 005b lsls r3, r3, #1
8002e4c: 4413 add r3, r2
8002e4e: 009b lsls r3, r3, #2
8002e50: 4423 add r3, r4
8002e52: 681b ldr r3, [r3, #0]
8002e54: 461a mov r2, r3
8002e56: f000 f87f bl 8002f58 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos + current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor);
8002e5a: 693b ldr r3, [r7, #16]
8002e5c: b29a uxth r2, r3
8002e5e: 88fb ldrh r3, [r7, #6]
8002e60: 4413 add r3, r2
8002e62: b298 uxth r0, r3
8002e64: 68fb ldr r3, [r7, #12]
8002e66: b29a uxth r2, r3
8002e68: 88bb ldrh r3, [r7, #4]
8002e6a: 4413 add r3, r2
8002e6c: b299 uxth r1, r3
8002e6e: 4b38 ldr r3, [pc, #224] ; (8002f50 <BSP_LCD_DrawCircle+0x1cc>)
8002e70: 681a ldr r2, [r3, #0]
8002e72: 4c38 ldr r4, [pc, #224] ; (8002f54 <BSP_LCD_DrawCircle+0x1d0>)
8002e74: 4613 mov r3, r2
8002e76: 005b lsls r3, r3, #1
8002e78: 4413 add r3, r2
8002e7a: 009b lsls r3, r3, #2
8002e7c: 4423 add r3, r4
8002e7e: 681b ldr r3, [r3, #0]
8002e80: 461a mov r2, r3
8002e82: f000 f869 bl 8002f58 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor);
8002e86: 693b ldr r3, [r7, #16]
8002e88: b29b uxth r3, r3
8002e8a: 88fa ldrh r2, [r7, #6]
8002e8c: 1ad3 subs r3, r2, r3
8002e8e: b298 uxth r0, r3
8002e90: 68fb ldr r3, [r7, #12]
8002e92: b29a uxth r2, r3
8002e94: 88bb ldrh r3, [r7, #4]
8002e96: 4413 add r3, r2
8002e98: b299 uxth r1, r3
8002e9a: 4b2d ldr r3, [pc, #180] ; (8002f50 <BSP_LCD_DrawCircle+0x1cc>)
8002e9c: 681a ldr r2, [r3, #0]
8002e9e: 4c2d ldr r4, [pc, #180] ; (8002f54 <BSP_LCD_DrawCircle+0x1d0>)
8002ea0: 4613 mov r3, r2
8002ea2: 005b lsls r3, r3, #1
8002ea4: 4413 add r3, r2
8002ea6: 009b lsls r3, r3, #2
8002ea8: 4423 add r3, r4
8002eaa: 681b ldr r3, [r3, #0]
8002eac: 461a mov r2, r3
8002eae: f000 f853 bl 8002f58 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos + current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor);
8002eb2: 68fb ldr r3, [r7, #12]
8002eb4: b29a uxth r2, r3
8002eb6: 88fb ldrh r3, [r7, #6]
8002eb8: 4413 add r3, r2
8002eba: b298 uxth r0, r3
8002ebc: 693b ldr r3, [r7, #16]
8002ebe: b29a uxth r2, r3
8002ec0: 88bb ldrh r3, [r7, #4]
8002ec2: 4413 add r3, r2
8002ec4: b299 uxth r1, r3
8002ec6: 4b22 ldr r3, [pc, #136] ; (8002f50 <BSP_LCD_DrawCircle+0x1cc>)
8002ec8: 681a ldr r2, [r3, #0]
8002eca: 4c22 ldr r4, [pc, #136] ; (8002f54 <BSP_LCD_DrawCircle+0x1d0>)
8002ecc: 4613 mov r3, r2
8002ece: 005b lsls r3, r3, #1
8002ed0: 4413 add r3, r2
8002ed2: 009b lsls r3, r3, #2
8002ed4: 4423 add r3, r4
8002ed6: 681b ldr r3, [r3, #0]
8002ed8: 461a mov r2, r3
8002eda: f000 f83d bl 8002f58 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor);
8002ede: 68fb ldr r3, [r7, #12]
8002ee0: b29b uxth r3, r3
8002ee2: 88fa ldrh r2, [r7, #6]
8002ee4: 1ad3 subs r3, r2, r3
8002ee6: b298 uxth r0, r3
8002ee8: 693b ldr r3, [r7, #16]
8002eea: b29a uxth r2, r3
8002eec: 88bb ldrh r3, [r7, #4]
8002eee: 4413 add r3, r2
8002ef0: b299 uxth r1, r3
8002ef2: 4b17 ldr r3, [pc, #92] ; (8002f50 <BSP_LCD_DrawCircle+0x1cc>)
8002ef4: 681a ldr r2, [r3, #0]
8002ef6: 4c17 ldr r4, [pc, #92] ; (8002f54 <BSP_LCD_DrawCircle+0x1d0>)
8002ef8: 4613 mov r3, r2
8002efa: 005b lsls r3, r3, #1
8002efc: 4413 add r3, r2
8002efe: 009b lsls r3, r3, #2
8002f00: 4423 add r3, r4
8002f02: 681b ldr r3, [r3, #0]
8002f04: 461a mov r2, r3
8002f06: f000 f827 bl 8002f58 <BSP_LCD_DrawPixel>
if (decision < 0)
8002f0a: 697b ldr r3, [r7, #20]
8002f0c: 2b00 cmp r3, #0
8002f0e: da06 bge.n 8002f1e <BSP_LCD_DrawCircle+0x19a>
{
decision += (current_x << 2) + 6;
8002f10: 693b ldr r3, [r7, #16]
8002f12: 009a lsls r2, r3, #2
8002f14: 697b ldr r3, [r7, #20]
8002f16: 4413 add r3, r2
8002f18: 3306 adds r3, #6
8002f1a: 617b str r3, [r7, #20]
8002f1c: e00a b.n 8002f34 <BSP_LCD_DrawCircle+0x1b0>
}
else
{
decision += ((current_x - current_y) << 2) + 10;
8002f1e: 693a ldr r2, [r7, #16]
8002f20: 68fb ldr r3, [r7, #12]
8002f22: 1ad3 subs r3, r2, r3
8002f24: 009a lsls r2, r3, #2
8002f26: 697b ldr r3, [r7, #20]
8002f28: 4413 add r3, r2
8002f2a: 330a adds r3, #10
8002f2c: 617b str r3, [r7, #20]
current_y--;
8002f2e: 68fb ldr r3, [r7, #12]
8002f30: 3b01 subs r3, #1
8002f32: 60fb str r3, [r7, #12]
}
current_x++;
8002f34: 693b ldr r3, [r7, #16]
8002f36: 3301 adds r3, #1
8002f38: 613b str r3, [r7, #16]
while (current_x <= current_y)
8002f3a: 693a ldr r2, [r7, #16]
8002f3c: 68fb ldr r3, [r7, #12]
8002f3e: 429a cmp r2, r3
8002f40: f67f af33 bls.w 8002daa <BSP_LCD_DrawCircle+0x26>
}
}
8002f44: bf00 nop
8002f46: bf00 nop
8002f48: 371c adds r7, #28
8002f4a: 46bd mov sp, r7
8002f4c: bd90 pop {r4, r7, pc}
8002f4e: bf00 nop
8002f50: 20000410 .word 0x20000410
8002f54: 20000414 .word 0x20000414
08002f58 <BSP_LCD_DrawPixel>:
* @param Ypos: Y position
* @param RGB_Code: Pixel color in ARGB mode (8-8-8-8)
* @retval None
*/
void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t RGB_Code)
{
8002f58: b5b0 push {r4, r5, r7, lr}
8002f5a: b082 sub sp, #8
8002f5c: af00 add r7, sp, #0
8002f5e: 4603 mov r3, r0
8002f60: 603a str r2, [r7, #0]
8002f62: 80fb strh r3, [r7, #6]
8002f64: 460b mov r3, r1
8002f66: 80bb strh r3, [r7, #4]
/* Write data value to all SDRAM memory */
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
8002f68: 4b1d ldr r3, [pc, #116] ; (8002fe0 <BSP_LCD_DrawPixel+0x88>)
8002f6a: 681b ldr r3, [r3, #0]
8002f6c: 4a1d ldr r2, [pc, #116] ; (8002fe4 <BSP_LCD_DrawPixel+0x8c>)
8002f6e: 2134 movs r1, #52 ; 0x34
8002f70: fb01 f303 mul.w r3, r1, r3
8002f74: 4413 add r3, r2
8002f76: 3348 adds r3, #72 ; 0x48
8002f78: 681b ldr r3, [r3, #0]
8002f7a: 2b02 cmp r3, #2
8002f7c: d116 bne.n 8002fac <BSP_LCD_DrawPixel+0x54>
{ /* RGB565 format */
*(__IO uint16_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos))) = (uint16_t)RGB_Code;
8002f7e: 4b18 ldr r3, [pc, #96] ; (8002fe0 <BSP_LCD_DrawPixel+0x88>)
8002f80: 681b ldr r3, [r3, #0]
8002f82: 4a18 ldr r2, [pc, #96] ; (8002fe4 <BSP_LCD_DrawPixel+0x8c>)
8002f84: 2134 movs r1, #52 ; 0x34
8002f86: fb01 f303 mul.w r3, r1, r3
8002f8a: 4413 add r3, r2
8002f8c: 335c adds r3, #92 ; 0x5c
8002f8e: 681c ldr r4, [r3, #0]
8002f90: 88bd ldrh r5, [r7, #4]
8002f92: f7ff fd8d bl 8002ab0 <BSP_LCD_GetXSize>
8002f96: 4603 mov r3, r0
8002f98: fb03 f205 mul.w r2, r3, r5
8002f9c: 88fb ldrh r3, [r7, #6]
8002f9e: 4413 add r3, r2
8002fa0: 005b lsls r3, r3, #1
8002fa2: 4423 add r3, r4
8002fa4: 683a ldr r2, [r7, #0]
8002fa6: b292 uxth r2, r2
8002fa8: 801a strh r2, [r3, #0]
}
else
{ /* ARGB8888 format */
*(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code;
}
}
8002faa: e015 b.n 8002fd8 <BSP_LCD_DrawPixel+0x80>
*(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code;
8002fac: 4b0c ldr r3, [pc, #48] ; (8002fe0 <BSP_LCD_DrawPixel+0x88>)
8002fae: 681b ldr r3, [r3, #0]
8002fb0: 4a0c ldr r2, [pc, #48] ; (8002fe4 <BSP_LCD_DrawPixel+0x8c>)
8002fb2: 2134 movs r1, #52 ; 0x34
8002fb4: fb01 f303 mul.w r3, r1, r3
8002fb8: 4413 add r3, r2
8002fba: 335c adds r3, #92 ; 0x5c
8002fbc: 681c ldr r4, [r3, #0]
8002fbe: 88bd ldrh r5, [r7, #4]
8002fc0: f7ff fd76 bl 8002ab0 <BSP_LCD_GetXSize>
8002fc4: 4603 mov r3, r0
8002fc6: fb03 f205 mul.w r2, r3, r5
8002fca: 88fb ldrh r3, [r7, #6]
8002fcc: 4413 add r3, r2
8002fce: 009b lsls r3, r3, #2
8002fd0: 4423 add r3, r4
8002fd2: 461a mov r2, r3
8002fd4: 683b ldr r3, [r7, #0]
8002fd6: 6013 str r3, [r2, #0]
}
8002fd8: bf00 nop
8002fda: 3708 adds r7, #8
8002fdc: 46bd mov sp, r7
8002fde: bdb0 pop {r4, r5, r7, pc}
8002fe0: 20000410 .word 0x20000410
8002fe4: 20008ea4 .word 0x20008ea4
08002fe8 <BSP_LCD_FillRect>:
* @param Width: Rectangle width
* @param Height: Rectangle height
* @retval None
*/
void BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
{
8002fe8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8002fec: b086 sub sp, #24
8002fee: af02 add r7, sp, #8
8002ff0: 4604 mov r4, r0
8002ff2: 4608 mov r0, r1
8002ff4: 4611 mov r1, r2
8002ff6: 461a mov r2, r3
8002ff8: 4623 mov r3, r4
8002ffa: 80fb strh r3, [r7, #6]
8002ffc: 4603 mov r3, r0
8002ffe: 80bb strh r3, [r7, #4]
8003000: 460b mov r3, r1
8003002: 807b strh r3, [r7, #2]
8003004: 4613 mov r3, r2
8003006: 803b strh r3, [r7, #0]
uint32_t x_address = 0;
8003008: 2300 movs r3, #0
800300a: 60fb str r3, [r7, #12]
/* Set the text color */
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
800300c: 4b30 ldr r3, [pc, #192] ; (80030d0 <BSP_LCD_FillRect+0xe8>)
800300e: 681a ldr r2, [r3, #0]
8003010: 4930 ldr r1, [pc, #192] ; (80030d4 <BSP_LCD_FillRect+0xec>)
8003012: 4613 mov r3, r2
8003014: 005b lsls r3, r3, #1
8003016: 4413 add r3, r2
8003018: 009b lsls r3, r3, #2
800301a: 440b add r3, r1
800301c: 681b ldr r3, [r3, #0]
800301e: 4618 mov r0, r3
8003020: f7ff fdde bl 8002be0 <BSP_LCD_SetTextColor>
/* Get the rectangle start address */
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
8003024: 4b2a ldr r3, [pc, #168] ; (80030d0 <BSP_LCD_FillRect+0xe8>)
8003026: 681b ldr r3, [r3, #0]
8003028: 4a2b ldr r2, [pc, #172] ; (80030d8 <BSP_LCD_FillRect+0xf0>)
800302a: 2134 movs r1, #52 ; 0x34
800302c: fb01 f303 mul.w r3, r1, r3
8003030: 4413 add r3, r2
8003032: 3348 adds r3, #72 ; 0x48
8003034: 681b ldr r3, [r3, #0]
8003036: 2b02 cmp r3, #2
8003038: d114 bne.n 8003064 <BSP_LCD_FillRect+0x7c>
{ /* RGB565 format */
x_address = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos);
800303a: 4b25 ldr r3, [pc, #148] ; (80030d0 <BSP_LCD_FillRect+0xe8>)
800303c: 681b ldr r3, [r3, #0]
800303e: 4a26 ldr r2, [pc, #152] ; (80030d8 <BSP_LCD_FillRect+0xf0>)
8003040: 2134 movs r1, #52 ; 0x34
8003042: fb01 f303 mul.w r3, r1, r3
8003046: 4413 add r3, r2
8003048: 335c adds r3, #92 ; 0x5c
800304a: 681c ldr r4, [r3, #0]
800304c: f7ff fd30 bl 8002ab0 <BSP_LCD_GetXSize>
8003050: 4602 mov r2, r0
8003052: 88bb ldrh r3, [r7, #4]
8003054: fb03 f202 mul.w r2, r3, r2
8003058: 88fb ldrh r3, [r7, #6]
800305a: 4413 add r3, r2
800305c: 005b lsls r3, r3, #1
800305e: 4423 add r3, r4
8003060: 60fb str r3, [r7, #12]
8003062: e013 b.n 800308c <BSP_LCD_FillRect+0xa4>
}
else
{ /* ARGB8888 format */
x_address = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);
8003064: 4b1a ldr r3, [pc, #104] ; (80030d0 <BSP_LCD_FillRect+0xe8>)
8003066: 681b ldr r3, [r3, #0]
8003068: 4a1b ldr r2, [pc, #108] ; (80030d8 <BSP_LCD_FillRect+0xf0>)
800306a: 2134 movs r1, #52 ; 0x34
800306c: fb01 f303 mul.w r3, r1, r3
8003070: 4413 add r3, r2
8003072: 335c adds r3, #92 ; 0x5c
8003074: 681c ldr r4, [r3, #0]
8003076: f7ff fd1b bl 8002ab0 <BSP_LCD_GetXSize>
800307a: 4602 mov r2, r0
800307c: 88bb ldrh r3, [r7, #4]
800307e: fb03 f202 mul.w r2, r3, r2
8003082: 88fb ldrh r3, [r7, #6]
8003084: 4413 add r3, r2
8003086: 009b lsls r3, r3, #2
8003088: 4423 add r3, r4
800308a: 60fb str r3, [r7, #12]
}
/* Fill the rectangle */
LL_FillBuffer(ActiveLayer, (uint32_t *)x_address, Width, Height, (BSP_LCD_GetXSize() - Width), DrawProp[ActiveLayer].TextColor);
800308c: 4b10 ldr r3, [pc, #64] ; (80030d0 <BSP_LCD_FillRect+0xe8>)
800308e: 681c ldr r4, [r3, #0]
8003090: 68fd ldr r5, [r7, #12]
8003092: 887e ldrh r6, [r7, #2]
8003094: f8b7 8000 ldrh.w r8, [r7]
8003098: f7ff fd0a bl 8002ab0 <BSP_LCD_GetXSize>
800309c: 4602 mov r2, r0
800309e: 887b ldrh r3, [r7, #2]
80030a0: 1ad1 subs r1, r2, r3
80030a2: 4b0b ldr r3, [pc, #44] ; (80030d0 <BSP_LCD_FillRect+0xe8>)
80030a4: 681a ldr r2, [r3, #0]
80030a6: 480b ldr r0, [pc, #44] ; (80030d4 <BSP_LCD_FillRect+0xec>)
80030a8: 4613 mov r3, r2
80030aa: 005b lsls r3, r3, #1
80030ac: 4413 add r3, r2
80030ae: 009b lsls r3, r3, #2
80030b0: 4403 add r3, r0
80030b2: 681b ldr r3, [r3, #0]
80030b4: 9301 str r3, [sp, #4]
80030b6: 9100 str r1, [sp, #0]
80030b8: 4643 mov r3, r8
80030ba: 4632 mov r2, r6
80030bc: 4629 mov r1, r5
80030be: 4620 mov r0, r4
80030c0: f000 f9c0 bl 8003444 <LL_FillBuffer>
}
80030c4: bf00 nop
80030c6: 3710 adds r7, #16
80030c8: 46bd mov sp, r7
80030ca: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
80030ce: bf00 nop
80030d0: 20000410 .word 0x20000410
80030d4: 20000414 .word 0x20000414
80030d8: 20008ea4 .word 0x20008ea4
080030dc <BSP_LCD_FillCircle>:
* @param Ypos: Y position
* @param Radius: Circle radius
* @retval None
*/
void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
{
80030dc: b580 push {r7, lr}
80030de: b086 sub sp, #24
80030e0: af00 add r7, sp, #0
80030e2: 4603 mov r3, r0
80030e4: 80fb strh r3, [r7, #6]
80030e6: 460b mov r3, r1
80030e8: 80bb strh r3, [r7, #4]
80030ea: 4613 mov r3, r2
80030ec: 807b strh r3, [r7, #2]
int32_t decision; /* Decision Variable */
uint32_t current_x; /* Current X Value */
uint32_t current_y; /* Current Y Value */
decision = 3 - (Radius << 1);
80030ee: 887b ldrh r3, [r7, #2]
80030f0: 005b lsls r3, r3, #1
80030f2: f1c3 0303 rsb r3, r3, #3
80030f6: 617b str r3, [r7, #20]
current_x = 0;
80030f8: 2300 movs r3, #0
80030fa: 613b str r3, [r7, #16]
current_y = Radius;
80030fc: 887b ldrh r3, [r7, #2]
80030fe: 60fb str r3, [r7, #12]
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
8003100: 4b44 ldr r3, [pc, #272] ; (8003214 <BSP_LCD_FillCircle+0x138>)
8003102: 681a ldr r2, [r3, #0]
8003104: 4944 ldr r1, [pc, #272] ; (8003218 <BSP_LCD_FillCircle+0x13c>)
8003106: 4613 mov r3, r2
8003108: 005b lsls r3, r3, #1
800310a: 4413 add r3, r2
800310c: 009b lsls r3, r3, #2
800310e: 440b add r3, r1
8003110: 681b ldr r3, [r3, #0]
8003112: 4618 mov r0, r3
8003114: f7ff fd64 bl 8002be0 <BSP_LCD_SetTextColor>
while (current_x <= current_y)
8003118: e061 b.n 80031de <BSP_LCD_FillCircle+0x102>
{
if(current_y > 0)
800311a: 68fb ldr r3, [r7, #12]
800311c: 2b00 cmp r3, #0
800311e: d021 beq.n 8003164 <BSP_LCD_FillCircle+0x88>
{
BSP_LCD_DrawHLine(Xpos - current_y, Ypos + current_x, 2*current_y);
8003120: 68fb ldr r3, [r7, #12]
8003122: b29b uxth r3, r3
8003124: 88fa ldrh r2, [r7, #6]
8003126: 1ad3 subs r3, r2, r3
8003128: b298 uxth r0, r3
800312a: 693b ldr r3, [r7, #16]
800312c: b29a uxth r2, r3
800312e: 88bb ldrh r3, [r7, #4]
8003130: 4413 add r3, r2
8003132: b299 uxth r1, r3
8003134: 68fb ldr r3, [r7, #12]
8003136: b29b uxth r3, r3
8003138: 005b lsls r3, r3, #1
800313a: b29b uxth r3, r3
800313c: 461a mov r2, r3
800313e: f7ff fdc3 bl 8002cc8 <BSP_LCD_DrawHLine>
BSP_LCD_DrawHLine(Xpos - current_y, Ypos - current_x, 2*current_y);
8003142: 68fb ldr r3, [r7, #12]
8003144: b29b uxth r3, r3
8003146: 88fa ldrh r2, [r7, #6]
8003148: 1ad3 subs r3, r2, r3
800314a: b298 uxth r0, r3
800314c: 693b ldr r3, [r7, #16]
800314e: b29b uxth r3, r3
8003150: 88ba ldrh r2, [r7, #4]
8003152: 1ad3 subs r3, r2, r3
8003154: b299 uxth r1, r3
8003156: 68fb ldr r3, [r7, #12]
8003158: b29b uxth r3, r3
800315a: 005b lsls r3, r3, #1
800315c: b29b uxth r3, r3
800315e: 461a mov r2, r3
8003160: f7ff fdb2 bl 8002cc8 <BSP_LCD_DrawHLine>
}
if(current_x > 0)
8003164: 693b ldr r3, [r7, #16]
8003166: 2b00 cmp r3, #0
8003168: d021 beq.n 80031ae <BSP_LCD_FillCircle+0xd2>
{
BSP_LCD_DrawHLine(Xpos - current_x, Ypos - current_y, 2*current_x);
800316a: 693b ldr r3, [r7, #16]
800316c: b29b uxth r3, r3
800316e: 88fa ldrh r2, [r7, #6]
8003170: 1ad3 subs r3, r2, r3
8003172: b298 uxth r0, r3
8003174: 68fb ldr r3, [r7, #12]
8003176: b29b uxth r3, r3
8003178: 88ba ldrh r2, [r7, #4]
800317a: 1ad3 subs r3, r2, r3
800317c: b299 uxth r1, r3
800317e: 693b ldr r3, [r7, #16]
8003180: b29b uxth r3, r3
8003182: 005b lsls r3, r3, #1
8003184: b29b uxth r3, r3
8003186: 461a mov r2, r3
8003188: f7ff fd9e bl 8002cc8 <BSP_LCD_DrawHLine>
BSP_LCD_DrawHLine(Xpos - current_x, Ypos + current_y, 2*current_x);
800318c: 693b ldr r3, [r7, #16]
800318e: b29b uxth r3, r3
8003190: 88fa ldrh r2, [r7, #6]
8003192: 1ad3 subs r3, r2, r3
8003194: b298 uxth r0, r3
8003196: 68fb ldr r3, [r7, #12]
8003198: b29a uxth r2, r3
800319a: 88bb ldrh r3, [r7, #4]
800319c: 4413 add r3, r2
800319e: b299 uxth r1, r3
80031a0: 693b ldr r3, [r7, #16]
80031a2: b29b uxth r3, r3
80031a4: 005b lsls r3, r3, #1
80031a6: b29b uxth r3, r3
80031a8: 461a mov r2, r3
80031aa: f7ff fd8d bl 8002cc8 <BSP_LCD_DrawHLine>
}
if (decision < 0)
80031ae: 697b ldr r3, [r7, #20]
80031b0: 2b00 cmp r3, #0
80031b2: da06 bge.n 80031c2 <BSP_LCD_FillCircle+0xe6>
{
decision += (current_x << 2) + 6;
80031b4: 693b ldr r3, [r7, #16]
80031b6: 009a lsls r2, r3, #2
80031b8: 697b ldr r3, [r7, #20]
80031ba: 4413 add r3, r2
80031bc: 3306 adds r3, #6
80031be: 617b str r3, [r7, #20]
80031c0: e00a b.n 80031d8 <BSP_LCD_FillCircle+0xfc>
}
else
{
decision += ((current_x - current_y) << 2) + 10;
80031c2: 693a ldr r2, [r7, #16]
80031c4: 68fb ldr r3, [r7, #12]
80031c6: 1ad3 subs r3, r2, r3
80031c8: 009a lsls r2, r3, #2
80031ca: 697b ldr r3, [r7, #20]
80031cc: 4413 add r3, r2
80031ce: 330a adds r3, #10
80031d0: 617b str r3, [r7, #20]
current_y--;
80031d2: 68fb ldr r3, [r7, #12]
80031d4: 3b01 subs r3, #1
80031d6: 60fb str r3, [r7, #12]
}
current_x++;
80031d8: 693b ldr r3, [r7, #16]
80031da: 3301 adds r3, #1
80031dc: 613b str r3, [r7, #16]
while (current_x <= current_y)
80031de: 693a ldr r2, [r7, #16]
80031e0: 68fb ldr r3, [r7, #12]
80031e2: 429a cmp r2, r3
80031e4: d999 bls.n 800311a <BSP_LCD_FillCircle+0x3e>
}
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
80031e6: 4b0b ldr r3, [pc, #44] ; (8003214 <BSP_LCD_FillCircle+0x138>)
80031e8: 681a ldr r2, [r3, #0]
80031ea: 490b ldr r1, [pc, #44] ; (8003218 <BSP_LCD_FillCircle+0x13c>)
80031ec: 4613 mov r3, r2
80031ee: 005b lsls r3, r3, #1
80031f0: 4413 add r3, r2
80031f2: 009b lsls r3, r3, #2
80031f4: 440b add r3, r1
80031f6: 681b ldr r3, [r3, #0]
80031f8: 4618 mov r0, r3
80031fa: f7ff fcf1 bl 8002be0 <BSP_LCD_SetTextColor>
BSP_LCD_DrawCircle(Xpos, Ypos, Radius);
80031fe: 887a ldrh r2, [r7, #2]
8003200: 88b9 ldrh r1, [r7, #4]
8003202: 88fb ldrh r3, [r7, #6]
8003204: 4618 mov r0, r3
8003206: f7ff fdbd bl 8002d84 <BSP_LCD_DrawCircle>
}
800320a: bf00 nop
800320c: 3718 adds r7, #24
800320e: 46bd mov sp, r7
8003210: bd80 pop {r7, pc}
8003212: bf00 nop
8003214: 20000410 .word 0x20000410
8003218: 20000414 .word 0x20000414
0800321c <BSP_LCD_DisplayOn>:
/**
* @brief Enables the display.
* @retval None
*/
void BSP_LCD_DisplayOn(void)
{
800321c: b580 push {r7, lr}
800321e: af00 add r7, sp, #0
/* Display On */
__HAL_LTDC_ENABLE(&hLtdcHandler);
8003220: 4b0a ldr r3, [pc, #40] ; (800324c <BSP_LCD_DisplayOn+0x30>)
8003222: 681b ldr r3, [r3, #0]
8003224: 699a ldr r2, [r3, #24]
8003226: 4b09 ldr r3, [pc, #36] ; (800324c <BSP_LCD_DisplayOn+0x30>)
8003228: 681b ldr r3, [r3, #0]
800322a: f042 0201 orr.w r2, r2, #1
800322e: 619a str r2, [r3, #24]
HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET); /* Assert LCD_DISP pin */
8003230: 2201 movs r2, #1
8003232: f44f 5180 mov.w r1, #4096 ; 0x1000
8003236: 4806 ldr r0, [pc, #24] ; (8003250 <BSP_LCD_DisplayOn+0x34>)
8003238: f004 f90e bl 8007458 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET); /* Assert LCD_BL_CTRL pin */
800323c: 2201 movs r2, #1
800323e: 2108 movs r1, #8
8003240: 4804 ldr r0, [pc, #16] ; (8003254 <BSP_LCD_DisplayOn+0x38>)
8003242: f004 f909 bl 8007458 <HAL_GPIO_WritePin>
}
8003246: bf00 nop
8003248: bd80 pop {r7, pc}
800324a: bf00 nop
800324c: 20008ea4 .word 0x20008ea4
8003250: 40022000 .word 0x40022000
8003254: 40022800 .word 0x40022800
08003258 <BSP_LCD_MspInit>:
* @param hltdc: LTDC handle
* @param Params
* @retval None
*/
__weak void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params)
{
8003258: b580 push {r7, lr}
800325a: b090 sub sp, #64 ; 0x40
800325c: af00 add r7, sp, #0
800325e: 6078 str r0, [r7, #4]
8003260: 6039 str r1, [r7, #0]
GPIO_InitTypeDef gpio_init_structure;
/* Enable the LTDC and DMA2D clocks */
__HAL_RCC_LTDC_CLK_ENABLE();
8003262: 4b64 ldr r3, [pc, #400] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003264: 6c5b ldr r3, [r3, #68] ; 0x44
8003266: 4a63 ldr r2, [pc, #396] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003268: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
800326c: 6453 str r3, [r2, #68] ; 0x44
800326e: 4b61 ldr r3, [pc, #388] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003270: 6c5b ldr r3, [r3, #68] ; 0x44
8003272: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8003276: 62bb str r3, [r7, #40] ; 0x28
8003278: 6abb ldr r3, [r7, #40] ; 0x28
__HAL_RCC_DMA2D_CLK_ENABLE();
800327a: 4b5e ldr r3, [pc, #376] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
800327c: 6b1b ldr r3, [r3, #48] ; 0x30
800327e: 4a5d ldr r2, [pc, #372] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003280: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8003284: 6313 str r3, [r2, #48] ; 0x30
8003286: 4b5b ldr r3, [pc, #364] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003288: 6b1b ldr r3, [r3, #48] ; 0x30
800328a: f403 0300 and.w r3, r3, #8388608 ; 0x800000
800328e: 627b str r3, [r7, #36] ; 0x24
8003290: 6a7b ldr r3, [r7, #36] ; 0x24
/* Enable GPIOs clock */
__HAL_RCC_GPIOE_CLK_ENABLE();
8003292: 4b58 ldr r3, [pc, #352] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003294: 6b1b ldr r3, [r3, #48] ; 0x30
8003296: 4a57 ldr r2, [pc, #348] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003298: f043 0310 orr.w r3, r3, #16
800329c: 6313 str r3, [r2, #48] ; 0x30
800329e: 4b55 ldr r3, [pc, #340] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
80032a0: 6b1b ldr r3, [r3, #48] ; 0x30
80032a2: f003 0310 and.w r3, r3, #16
80032a6: 623b str r3, [r7, #32]
80032a8: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOG_CLK_ENABLE();
80032aa: 4b52 ldr r3, [pc, #328] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
80032ac: 6b1b ldr r3, [r3, #48] ; 0x30
80032ae: 4a51 ldr r2, [pc, #324] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
80032b0: f043 0340 orr.w r3, r3, #64 ; 0x40
80032b4: 6313 str r3, [r2, #48] ; 0x30
80032b6: 4b4f ldr r3, [pc, #316] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
80032b8: 6b1b ldr r3, [r3, #48] ; 0x30
80032ba: f003 0340 and.w r3, r3, #64 ; 0x40
80032be: 61fb str r3, [r7, #28]
80032c0: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOI_CLK_ENABLE();
80032c2: 4b4c ldr r3, [pc, #304] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
80032c4: 6b1b ldr r3, [r3, #48] ; 0x30
80032c6: 4a4b ldr r2, [pc, #300] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
80032c8: f443 7380 orr.w r3, r3, #256 ; 0x100
80032cc: 6313 str r3, [r2, #48] ; 0x30
80032ce: 4b49 ldr r3, [pc, #292] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
80032d0: 6b1b ldr r3, [r3, #48] ; 0x30
80032d2: f403 7380 and.w r3, r3, #256 ; 0x100
80032d6: 61bb str r3, [r7, #24]
80032d8: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOJ_CLK_ENABLE();
80032da: 4b46 ldr r3, [pc, #280] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
80032dc: 6b1b ldr r3, [r3, #48] ; 0x30
80032de: 4a45 ldr r2, [pc, #276] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
80032e0: f443 7300 orr.w r3, r3, #512 ; 0x200
80032e4: 6313 str r3, [r2, #48] ; 0x30
80032e6: 4b43 ldr r3, [pc, #268] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
80032e8: 6b1b ldr r3, [r3, #48] ; 0x30
80032ea: f403 7300 and.w r3, r3, #512 ; 0x200
80032ee: 617b str r3, [r7, #20]
80032f0: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOK_CLK_ENABLE();
80032f2: 4b40 ldr r3, [pc, #256] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
80032f4: 6b1b ldr r3, [r3, #48] ; 0x30
80032f6: 4a3f ldr r2, [pc, #252] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
80032f8: f443 6380 orr.w r3, r3, #1024 ; 0x400
80032fc: 6313 str r3, [r2, #48] ; 0x30
80032fe: 4b3d ldr r3, [pc, #244] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003300: 6b1b ldr r3, [r3, #48] ; 0x30
8003302: f403 6380 and.w r3, r3, #1024 ; 0x400
8003306: 613b str r3, [r7, #16]
8003308: 693b ldr r3, [r7, #16]
LCD_DISP_GPIO_CLK_ENABLE();
800330a: 4b3a ldr r3, [pc, #232] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
800330c: 6b1b ldr r3, [r3, #48] ; 0x30
800330e: 4a39 ldr r2, [pc, #228] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003310: f443 7380 orr.w r3, r3, #256 ; 0x100
8003314: 6313 str r3, [r2, #48] ; 0x30
8003316: 4b37 ldr r3, [pc, #220] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003318: 6b1b ldr r3, [r3, #48] ; 0x30
800331a: f403 7380 and.w r3, r3, #256 ; 0x100
800331e: 60fb str r3, [r7, #12]
8003320: 68fb ldr r3, [r7, #12]
LCD_BL_CTRL_GPIO_CLK_ENABLE();
8003322: 4b34 ldr r3, [pc, #208] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003324: 6b1b ldr r3, [r3, #48] ; 0x30
8003326: 4a33 ldr r2, [pc, #204] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003328: f443 6380 orr.w r3, r3, #1024 ; 0x400
800332c: 6313 str r3, [r2, #48] ; 0x30
800332e: 4b31 ldr r3, [pc, #196] ; (80033f4 <BSP_LCD_MspInit+0x19c>)
8003330: 6b1b ldr r3, [r3, #48] ; 0x30
8003332: f403 6380 and.w r3, r3, #1024 ; 0x400
8003336: 60bb str r3, [r7, #8]
8003338: 68bb ldr r3, [r7, #8]
/*** LTDC Pins configuration ***/
/* GPIOE configuration */
gpio_init_structure.Pin = GPIO_PIN_4;
800333a: 2310 movs r3, #16
800333c: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
800333e: 2302 movs r3, #2
8003340: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Pull = GPIO_NOPULL;
8003342: 2300 movs r3, #0
8003344: 637b str r3, [r7, #52] ; 0x34
gpio_init_structure.Speed = GPIO_SPEED_FAST;
8003346: 2302 movs r3, #2
8003348: 63bb str r3, [r7, #56] ; 0x38
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
800334a: 230e movs r3, #14
800334c: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
800334e: f107 032c add.w r3, r7, #44 ; 0x2c
8003352: 4619 mov r1, r3
8003354: 4828 ldr r0, [pc, #160] ; (80033f8 <BSP_LCD_MspInit+0x1a0>)
8003356: f003 fed3 bl 8007100 <HAL_GPIO_Init>
/* GPIOG configuration */
gpio_init_structure.Pin = GPIO_PIN_12;
800335a: f44f 5380 mov.w r3, #4096 ; 0x1000
800335e: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
8003360: 2302 movs r3, #2
8003362: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF9_LTDC;
8003364: 2309 movs r3, #9
8003366: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
8003368: f107 032c add.w r3, r7, #44 ; 0x2c
800336c: 4619 mov r1, r3
800336e: 4823 ldr r0, [pc, #140] ; (80033fc <BSP_LCD_MspInit+0x1a4>)
8003370: f003 fec6 bl 8007100 <HAL_GPIO_Init>
/* GPIOI LTDC alternate configuration */
gpio_init_structure.Pin = GPIO_PIN_9 | GPIO_PIN_10 | \
8003374: f44f 4366 mov.w r3, #58880 ; 0xe600
8003378: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
800337a: 2302 movs r3, #2
800337c: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
800337e: 230e movs r3, #14
8003380: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOI, &gpio_init_structure);
8003382: f107 032c add.w r3, r7, #44 ; 0x2c
8003386: 4619 mov r1, r3
8003388: 481d ldr r0, [pc, #116] ; (8003400 <BSP_LCD_MspInit+0x1a8>)
800338a: f003 feb9 bl 8007100 <HAL_GPIO_Init>
/* GPIOJ configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \
800338e: f64e 73ff movw r3, #61439 ; 0xefff
8003392: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \
GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
8003394: 2302 movs r3, #2
8003396: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
8003398: 230e movs r3, #14
800339a: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOJ, &gpio_init_structure);
800339c: f107 032c add.w r3, r7, #44 ; 0x2c
80033a0: 4619 mov r1, r3
80033a2: 4818 ldr r0, [pc, #96] ; (8003404 <BSP_LCD_MspInit+0x1ac>)
80033a4: f003 feac bl 8007100 <HAL_GPIO_Init>
/* GPIOK configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | \
80033a8: 23f7 movs r3, #247 ; 0xf7
80033aa: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
80033ac: 2302 movs r3, #2
80033ae: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
80033b0: 230e movs r3, #14
80033b2: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOK, &gpio_init_structure);
80033b4: f107 032c add.w r3, r7, #44 ; 0x2c
80033b8: 4619 mov r1, r3
80033ba: 4813 ldr r0, [pc, #76] ; (8003408 <BSP_LCD_MspInit+0x1b0>)
80033bc: f003 fea0 bl 8007100 <HAL_GPIO_Init>
/* LCD_DISP GPIO configuration */
gpio_init_structure.Pin = LCD_DISP_PIN; /* LCD_DISP pin has to be manually controlled */
80033c0: f44f 5380 mov.w r3, #4096 ; 0x1000
80033c4: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
80033c6: 2301 movs r3, #1
80033c8: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(LCD_DISP_GPIO_PORT, &gpio_init_structure);
80033ca: f107 032c add.w r3, r7, #44 ; 0x2c
80033ce: 4619 mov r1, r3
80033d0: 480b ldr r0, [pc, #44] ; (8003400 <BSP_LCD_MspInit+0x1a8>)
80033d2: f003 fe95 bl 8007100 <HAL_GPIO_Init>
/* LCD_BL_CTRL GPIO configuration */
gpio_init_structure.Pin = LCD_BL_CTRL_PIN; /* LCD_BL_CTRL pin has to be manually controlled */
80033d6: 2308 movs r3, #8
80033d8: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
80033da: 2301 movs r3, #1
80033dc: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(LCD_BL_CTRL_GPIO_PORT, &gpio_init_structure);
80033de: f107 032c add.w r3, r7, #44 ; 0x2c
80033e2: 4619 mov r1, r3
80033e4: 4808 ldr r0, [pc, #32] ; (8003408 <BSP_LCD_MspInit+0x1b0>)
80033e6: f003 fe8b bl 8007100 <HAL_GPIO_Init>
}
80033ea: bf00 nop
80033ec: 3740 adds r7, #64 ; 0x40
80033ee: 46bd mov sp, r7
80033f0: bd80 pop {r7, pc}
80033f2: bf00 nop
80033f4: 40023800 .word 0x40023800
80033f8: 40021000 .word 0x40021000
80033fc: 40021800 .word 0x40021800
8003400: 40022000 .word 0x40022000
8003404: 40022400 .word 0x40022400
8003408: 40022800 .word 0x40022800
0800340c <BSP_LCD_ClockConfig>:
* @note This API is called by BSP_LCD_Init()
* Being __weak it can be overwritten by the application
* @retval None
*/
__weak void BSP_LCD_ClockConfig(LTDC_HandleTypeDef *hltdc, void *Params)
{
800340c: b580 push {r7, lr}
800340e: b082 sub sp, #8
8003410: af00 add r7, sp, #0
8003412: 6078 str r0, [r7, #4]
8003414: 6039 str r1, [r7, #0]
/* RK043FN48H LCD clock configuration */
/* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz */
/* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz */
/* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz */
periph_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
8003416: 4b0a ldr r3, [pc, #40] ; (8003440 <BSP_LCD_ClockConfig+0x34>)
8003418: 2208 movs r2, #8
800341a: 601a str r2, [r3, #0]
periph_clk_init_struct.PLLSAI.PLLSAIN = 192;
800341c: 4b08 ldr r3, [pc, #32] ; (8003440 <BSP_LCD_ClockConfig+0x34>)
800341e: 22c0 movs r2, #192 ; 0xc0
8003420: 615a str r2, [r3, #20]
periph_clk_init_struct.PLLSAI.PLLSAIR = RK043FN48H_FREQUENCY_DIVIDER;
8003422: 4b07 ldr r3, [pc, #28] ; (8003440 <BSP_LCD_ClockConfig+0x34>)
8003424: 2205 movs r2, #5
8003426: 61da str r2, [r3, #28]
periph_clk_init_struct.PLLSAIDivR = RCC_PLLSAIDIVR_4;
8003428: 4b05 ldr r3, [pc, #20] ; (8003440 <BSP_LCD_ClockConfig+0x34>)
800342a: f44f 3280 mov.w r2, #65536 ; 0x10000
800342e: 62da str r2, [r3, #44] ; 0x2c
HAL_RCCEx_PeriphCLKConfig(&periph_clk_init_struct);
8003430: 4803 ldr r0, [pc, #12] ; (8003440 <BSP_LCD_ClockConfig+0x34>)
8003432: f005 fdc7 bl 8008fc4 <HAL_RCCEx_PeriphCLKConfig>
}
8003436: bf00 nop
8003438: 3708 adds r7, #8
800343a: 46bd mov sp, r7
800343c: bd80 pop {r7, pc}
800343e: bf00 nop
8003440: 2000042c .word 0x2000042c
08003444 <LL_FillBuffer>:
* @param OffLine: Offset
* @param ColorIndex: Color index
* @retval None
*/
static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex)
{
8003444: b580 push {r7, lr}
8003446: b086 sub sp, #24
8003448: af02 add r7, sp, #8
800344a: 60f8 str r0, [r7, #12]
800344c: 60b9 str r1, [r7, #8]
800344e: 607a str r2, [r7, #4]
8003450: 603b str r3, [r7, #0]
/* Register to memory mode with ARGB8888 as color Mode */
hDma2dHandler.Init.Mode = DMA2D_R2M;
8003452: 4b1e ldr r3, [pc, #120] ; (80034cc <LL_FillBuffer+0x88>)
8003454: f44f 3240 mov.w r2, #196608 ; 0x30000
8003458: 605a str r2, [r3, #4]
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
800345a: 4b1d ldr r3, [pc, #116] ; (80034d0 <LL_FillBuffer+0x8c>)
800345c: 681b ldr r3, [r3, #0]
800345e: 4a1d ldr r2, [pc, #116] ; (80034d4 <LL_FillBuffer+0x90>)
8003460: 2134 movs r1, #52 ; 0x34
8003462: fb01 f303 mul.w r3, r1, r3
8003466: 4413 add r3, r2
8003468: 3348 adds r3, #72 ; 0x48
800346a: 681b ldr r3, [r3, #0]
800346c: 2b02 cmp r3, #2
800346e: d103 bne.n 8003478 <LL_FillBuffer+0x34>
{ /* RGB565 format */
hDma2dHandler.Init.ColorMode = DMA2D_RGB565;
8003470: 4b16 ldr r3, [pc, #88] ; (80034cc <LL_FillBuffer+0x88>)
8003472: 2202 movs r2, #2
8003474: 609a str r2, [r3, #8]
8003476: e002 b.n 800347e <LL_FillBuffer+0x3a>
}
else
{ /* ARGB8888 format */
hDma2dHandler.Init.ColorMode = DMA2D_ARGB8888;
8003478: 4b14 ldr r3, [pc, #80] ; (80034cc <LL_FillBuffer+0x88>)
800347a: 2200 movs r2, #0
800347c: 609a str r2, [r3, #8]
}
hDma2dHandler.Init.OutputOffset = OffLine;
800347e: 4a13 ldr r2, [pc, #76] ; (80034cc <LL_FillBuffer+0x88>)
8003480: 69bb ldr r3, [r7, #24]
8003482: 60d3 str r3, [r2, #12]
hDma2dHandler.Instance = DMA2D;
8003484: 4b11 ldr r3, [pc, #68] ; (80034cc <LL_FillBuffer+0x88>)
8003486: 4a14 ldr r2, [pc, #80] ; (80034d8 <LL_FillBuffer+0x94>)
8003488: 601a str r2, [r3, #0]
/* DMA2D Initialization */
if(HAL_DMA2D_Init(&hDma2dHandler) == HAL_OK)
800348a: 4810 ldr r0, [pc, #64] ; (80034cc <LL_FillBuffer+0x88>)
800348c: f002 fa28 bl 80058e0 <HAL_DMA2D_Init>
8003490: 4603 mov r3, r0
8003492: 2b00 cmp r3, #0
8003494: d115 bne.n 80034c2 <LL_FillBuffer+0x7e>
{
if(HAL_DMA2D_ConfigLayer(&hDma2dHandler, LayerIndex) == HAL_OK)
8003496: 68f9 ldr r1, [r7, #12]
8003498: 480c ldr r0, [pc, #48] ; (80034cc <LL_FillBuffer+0x88>)
800349a: f002 fb7f bl 8005b9c <HAL_DMA2D_ConfigLayer>
800349e: 4603 mov r3, r0
80034a0: 2b00 cmp r3, #0
80034a2: d10e bne.n 80034c2 <LL_FillBuffer+0x7e>
{
if (HAL_DMA2D_Start(&hDma2dHandler, ColorIndex, (uint32_t)pDst, xSize, ySize) == HAL_OK)
80034a4: 68ba ldr r2, [r7, #8]
80034a6: 683b ldr r3, [r7, #0]
80034a8: 9300 str r3, [sp, #0]
80034aa: 687b ldr r3, [r7, #4]
80034ac: 69f9 ldr r1, [r7, #28]
80034ae: 4807 ldr r0, [pc, #28] ; (80034cc <LL_FillBuffer+0x88>)
80034b0: f002 fa60 bl 8005974 <HAL_DMA2D_Start>
80034b4: 4603 mov r3, r0
80034b6: 2b00 cmp r3, #0
80034b8: d103 bne.n 80034c2 <LL_FillBuffer+0x7e>
{
/* Polling For DMA transfer */
HAL_DMA2D_PollForTransfer(&hDma2dHandler, 10);
80034ba: 210a movs r1, #10
80034bc: 4803 ldr r0, [pc, #12] ; (80034cc <LL_FillBuffer+0x88>)
80034be: f002 fa84 bl 80059ca <HAL_DMA2D_PollForTransfer>
}
}
}
}
80034c2: bf00 nop
80034c4: 3710 adds r7, #16
80034c6: 46bd mov sp, r7
80034c8: bd80 pop {r7, pc}
80034ca: bf00 nop
80034cc: 200003d0 .word 0x200003d0
80034d0: 20000410 .word 0x20000410
80034d4: 20008ea4 .word 0x20008ea4
80034d8: 4002b000 .word 0x4002b000
080034dc <BSP_SDRAM_Init>:
/**
* @brief Initializes the SDRAM device.
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_Init(void)
{
80034dc: b580 push {r7, lr}
80034de: af00 add r7, sp, #0
static uint8_t sdramstatus = SDRAM_ERROR;
/* SDRAM device configuration */
sdramHandle.Instance = FMC_SDRAM_DEVICE;
80034e0: 4b29 ldr r3, [pc, #164] ; (8003588 <BSP_SDRAM_Init+0xac>)
80034e2: 4a2a ldr r2, [pc, #168] ; (800358c <BSP_SDRAM_Init+0xb0>)
80034e4: 601a str r2, [r3, #0]
/* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
Timing.LoadToActiveDelay = 2;
80034e6: 4b2a ldr r3, [pc, #168] ; (8003590 <BSP_SDRAM_Init+0xb4>)
80034e8: 2202 movs r2, #2
80034ea: 601a str r2, [r3, #0]
Timing.ExitSelfRefreshDelay = 7;
80034ec: 4b28 ldr r3, [pc, #160] ; (8003590 <BSP_SDRAM_Init+0xb4>)
80034ee: 2207 movs r2, #7
80034f0: 605a str r2, [r3, #4]
Timing.SelfRefreshTime = 4;
80034f2: 4b27 ldr r3, [pc, #156] ; (8003590 <BSP_SDRAM_Init+0xb4>)
80034f4: 2204 movs r2, #4
80034f6: 609a str r2, [r3, #8]
Timing.RowCycleDelay = 7;
80034f8: 4b25 ldr r3, [pc, #148] ; (8003590 <BSP_SDRAM_Init+0xb4>)
80034fa: 2207 movs r2, #7
80034fc: 60da str r2, [r3, #12]
Timing.WriteRecoveryTime = 2;
80034fe: 4b24 ldr r3, [pc, #144] ; (8003590 <BSP_SDRAM_Init+0xb4>)
8003500: 2202 movs r2, #2
8003502: 611a str r2, [r3, #16]
Timing.RPDelay = 2;
8003504: 4b22 ldr r3, [pc, #136] ; (8003590 <BSP_SDRAM_Init+0xb4>)
8003506: 2202 movs r2, #2
8003508: 615a str r2, [r3, #20]
Timing.RCDDelay = 2;
800350a: 4b21 ldr r3, [pc, #132] ; (8003590 <BSP_SDRAM_Init+0xb4>)
800350c: 2202 movs r2, #2
800350e: 619a str r2, [r3, #24]
sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
8003510: 4b1d ldr r3, [pc, #116] ; (8003588 <BSP_SDRAM_Init+0xac>)
8003512: 2200 movs r2, #0
8003514: 605a str r2, [r3, #4]
sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
8003516: 4b1c ldr r3, [pc, #112] ; (8003588 <BSP_SDRAM_Init+0xac>)
8003518: 2200 movs r2, #0
800351a: 609a str r2, [r3, #8]
sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
800351c: 4b1a ldr r3, [pc, #104] ; (8003588 <BSP_SDRAM_Init+0xac>)
800351e: 2204 movs r2, #4
8003520: 60da str r2, [r3, #12]
sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
8003522: 4b19 ldr r3, [pc, #100] ; (8003588 <BSP_SDRAM_Init+0xac>)
8003524: 2210 movs r2, #16
8003526: 611a str r2, [r3, #16]
sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
8003528: 4b17 ldr r3, [pc, #92] ; (8003588 <BSP_SDRAM_Init+0xac>)
800352a: 2240 movs r2, #64 ; 0x40
800352c: 615a str r2, [r3, #20]
sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
800352e: 4b16 ldr r3, [pc, #88] ; (8003588 <BSP_SDRAM_Init+0xac>)
8003530: f44f 7280 mov.w r2, #256 ; 0x100
8003534: 619a str r2, [r3, #24]
sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
8003536: 4b14 ldr r3, [pc, #80] ; (8003588 <BSP_SDRAM_Init+0xac>)
8003538: 2200 movs r2, #0
800353a: 61da str r2, [r3, #28]
sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
800353c: 4b12 ldr r3, [pc, #72] ; (8003588 <BSP_SDRAM_Init+0xac>)
800353e: f44f 6200 mov.w r2, #2048 ; 0x800
8003542: 621a str r2, [r3, #32]
sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
8003544: 4b10 ldr r3, [pc, #64] ; (8003588 <BSP_SDRAM_Init+0xac>)
8003546: f44f 5280 mov.w r2, #4096 ; 0x1000
800354a: 625a str r2, [r3, #36] ; 0x24
sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
800354c: 4b0e ldr r3, [pc, #56] ; (8003588 <BSP_SDRAM_Init+0xac>)
800354e: 2200 movs r2, #0
8003550: 629a str r2, [r3, #40] ; 0x28
/* SDRAM controller initialization */
BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
8003552: 2100 movs r1, #0
8003554: 480c ldr r0, [pc, #48] ; (8003588 <BSP_SDRAM_Init+0xac>)
8003556: f000 f87f bl 8003658 <BSP_SDRAM_MspInit>
if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
800355a: 490d ldr r1, [pc, #52] ; (8003590 <BSP_SDRAM_Init+0xb4>)
800355c: 480a ldr r0, [pc, #40] ; (8003588 <BSP_SDRAM_Init+0xac>)
800355e: f006 f99a bl 8009896 <HAL_SDRAM_Init>
8003562: 4603 mov r3, r0
8003564: 2b00 cmp r3, #0
8003566: d003 beq.n 8003570 <BSP_SDRAM_Init+0x94>
{
sdramstatus = SDRAM_ERROR;
8003568: 4b0a ldr r3, [pc, #40] ; (8003594 <BSP_SDRAM_Init+0xb8>)
800356a: 2201 movs r2, #1
800356c: 701a strb r2, [r3, #0]
800356e: e002 b.n 8003576 <BSP_SDRAM_Init+0x9a>
}
else
{
sdramstatus = SDRAM_OK;
8003570: 4b08 ldr r3, [pc, #32] ; (8003594 <BSP_SDRAM_Init+0xb8>)
8003572: 2200 movs r2, #0
8003574: 701a strb r2, [r3, #0]
}
/* SDRAM initialization sequence */
BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
8003576: f240 6003 movw r0, #1539 ; 0x603
800357a: f000 f80d bl 8003598 <BSP_SDRAM_Initialization_sequence>
return sdramstatus;
800357e: 4b05 ldr r3, [pc, #20] ; (8003594 <BSP_SDRAM_Init+0xb8>)
8003580: 781b ldrb r3, [r3, #0]
}
8003582: 4618 mov r0, r3
8003584: bd80 pop {r7, pc}
8003586: bf00 nop
8003588: 20008f4c .word 0x20008f4c
800358c: a0000140 .word 0xa0000140
8003590: 200004b0 .word 0x200004b0
8003594: 20000054 .word 0x20000054
08003598 <BSP_SDRAM_Initialization_sequence>:
* @brief Programs the SDRAM device.
* @param RefreshCount: SDRAM refresh counter value
* @retval None
*/
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
{
8003598: b580 push {r7, lr}
800359a: b084 sub sp, #16
800359c: af00 add r7, sp, #0
800359e: 6078 str r0, [r7, #4]
__IO uint32_t tmpmrd = 0;
80035a0: 2300 movs r3, #0
80035a2: 60fb str r3, [r7, #12]
/* Step 1: Configure a clock configuration enable command */
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
80035a4: 4b2a ldr r3, [pc, #168] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
80035a6: 2201 movs r2, #1
80035a8: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
80035aa: 4b29 ldr r3, [pc, #164] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
80035ac: 2210 movs r2, #16
80035ae: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 1;
80035b0: 4b27 ldr r3, [pc, #156] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
80035b2: 2201 movs r2, #1
80035b4: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = 0;
80035b6: 4b26 ldr r3, [pc, #152] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
80035b8: 2200 movs r2, #0
80035ba: 60da str r2, [r3, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
80035bc: f64f 72ff movw r2, #65535 ; 0xffff
80035c0: 4923 ldr r1, [pc, #140] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
80035c2: 4824 ldr r0, [pc, #144] ; (8003654 <BSP_SDRAM_Initialization_sequence+0xbc>)
80035c4: f006 f99b bl 80098fe <HAL_SDRAM_SendCommand>
/* Step 2: Insert 100 us minimum delay */
/* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
HAL_Delay(1);
80035c8: 2001 movs r0, #1
80035ca: f001 f90d bl 80047e8 <HAL_Delay>
/* Step 3: Configure a PALL (precharge all) command */
Command.CommandMode = FMC_SDRAM_CMD_PALL;
80035ce: 4b20 ldr r3, [pc, #128] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
80035d0: 2202 movs r2, #2
80035d2: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
80035d4: 4b1e ldr r3, [pc, #120] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
80035d6: 2210 movs r2, #16
80035d8: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 1;
80035da: 4b1d ldr r3, [pc, #116] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
80035dc: 2201 movs r2, #1
80035de: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = 0;
80035e0: 4b1b ldr r3, [pc, #108] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
80035e2: 2200 movs r2, #0
80035e4: 60da str r2, [r3, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
80035e6: f64f 72ff movw r2, #65535 ; 0xffff
80035ea: 4919 ldr r1, [pc, #100] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
80035ec: 4819 ldr r0, [pc, #100] ; (8003654 <BSP_SDRAM_Initialization_sequence+0xbc>)
80035ee: f006 f986 bl 80098fe <HAL_SDRAM_SendCommand>
/* Step 4: Configure an Auto Refresh command */
Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
80035f2: 4b17 ldr r3, [pc, #92] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
80035f4: 2203 movs r2, #3
80035f6: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
80035f8: 4b15 ldr r3, [pc, #84] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
80035fa: 2210 movs r2, #16
80035fc: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 8;
80035fe: 4b14 ldr r3, [pc, #80] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003600: 2208 movs r2, #8
8003602: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = 0;
8003604: 4b12 ldr r3, [pc, #72] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003606: 2200 movs r2, #0
8003608: 60da str r2, [r3, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
800360a: f64f 72ff movw r2, #65535 ; 0xffff
800360e: 4910 ldr r1, [pc, #64] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003610: 4810 ldr r0, [pc, #64] ; (8003654 <BSP_SDRAM_Initialization_sequence+0xbc>)
8003612: f006 f974 bl 80098fe <HAL_SDRAM_SendCommand>
/* Step 5: Program the external memory mode register */
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
8003616: f44f 7308 mov.w r3, #544 ; 0x220
800361a: 60fb str r3, [r7, #12]
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
SDRAM_MODEREG_CAS_LATENCY_2 |\
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
800361c: 4b0c ldr r3, [pc, #48] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
800361e: 2204 movs r2, #4
8003620: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
8003622: 4b0b ldr r3, [pc, #44] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003624: 2210 movs r2, #16
8003626: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 1;
8003628: 4b09 ldr r3, [pc, #36] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
800362a: 2201 movs r2, #1
800362c: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = tmpmrd;
800362e: 68fb ldr r3, [r7, #12]
8003630: 4a07 ldr r2, [pc, #28] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003632: 60d3 str r3, [r2, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
8003634: f64f 72ff movw r2, #65535 ; 0xffff
8003638: 4905 ldr r1, [pc, #20] ; (8003650 <BSP_SDRAM_Initialization_sequence+0xb8>)
800363a: 4806 ldr r0, [pc, #24] ; (8003654 <BSP_SDRAM_Initialization_sequence+0xbc>)
800363c: f006 f95f bl 80098fe <HAL_SDRAM_SendCommand>
/* Step 6: Set the refresh rate counter */
/* Set the device refresh rate */
HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
8003640: 6879 ldr r1, [r7, #4]
8003642: 4804 ldr r0, [pc, #16] ; (8003654 <BSP_SDRAM_Initialization_sequence+0xbc>)
8003644: f006 f986 bl 8009954 <HAL_SDRAM_ProgramRefreshRate>
}
8003648: bf00 nop
800364a: 3710 adds r7, #16
800364c: 46bd mov sp, r7
800364e: bd80 pop {r7, pc}
8003650: 200004cc .word 0x200004cc
8003654: 20008f4c .word 0x20008f4c
08003658 <BSP_SDRAM_MspInit>:
* @param hsdram: SDRAM handle
* @param Params
* @retval None
*/
__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
{
8003658: b580 push {r7, lr}
800365a: b090 sub sp, #64 ; 0x40
800365c: af00 add r7, sp, #0
800365e: 6078 str r0, [r7, #4]
8003660: 6039 str r1, [r7, #0]
static DMA_HandleTypeDef dma_handle;
GPIO_InitTypeDef gpio_init_structure;
/* Enable FMC clock */
__HAL_RCC_FMC_CLK_ENABLE();
8003662: 4b70 ldr r3, [pc, #448] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
8003664: 6b9b ldr r3, [r3, #56] ; 0x38
8003666: 4a6f ldr r2, [pc, #444] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
8003668: f043 0301 orr.w r3, r3, #1
800366c: 6393 str r3, [r2, #56] ; 0x38
800366e: 4b6d ldr r3, [pc, #436] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
8003670: 6b9b ldr r3, [r3, #56] ; 0x38
8003672: f003 0301 and.w r3, r3, #1
8003676: 62bb str r3, [r7, #40] ; 0x28
8003678: 6abb ldr r3, [r7, #40] ; 0x28
/* Enable chosen DMAx clock */
__DMAx_CLK_ENABLE();
800367a: 4b6a ldr r3, [pc, #424] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
800367c: 6b1b ldr r3, [r3, #48] ; 0x30
800367e: 4a69 ldr r2, [pc, #420] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
8003680: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
8003684: 6313 str r3, [r2, #48] ; 0x30
8003686: 4b67 ldr r3, [pc, #412] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
8003688: 6b1b ldr r3, [r3, #48] ; 0x30
800368a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
800368e: 627b str r3, [r7, #36] ; 0x24
8003690: 6a7b ldr r3, [r7, #36] ; 0x24
/* Enable GPIOs clock */
__HAL_RCC_GPIOC_CLK_ENABLE();
8003692: 4b64 ldr r3, [pc, #400] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
8003694: 6b1b ldr r3, [r3, #48] ; 0x30
8003696: 4a63 ldr r2, [pc, #396] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
8003698: f043 0304 orr.w r3, r3, #4
800369c: 6313 str r3, [r2, #48] ; 0x30
800369e: 4b61 ldr r3, [pc, #388] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
80036a0: 6b1b ldr r3, [r3, #48] ; 0x30
80036a2: f003 0304 and.w r3, r3, #4
80036a6: 623b str r3, [r7, #32]
80036a8: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOD_CLK_ENABLE();
80036aa: 4b5e ldr r3, [pc, #376] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
80036ac: 6b1b ldr r3, [r3, #48] ; 0x30
80036ae: 4a5d ldr r2, [pc, #372] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
80036b0: f043 0308 orr.w r3, r3, #8
80036b4: 6313 str r3, [r2, #48] ; 0x30
80036b6: 4b5b ldr r3, [pc, #364] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
80036b8: 6b1b ldr r3, [r3, #48] ; 0x30
80036ba: f003 0308 and.w r3, r3, #8
80036be: 61fb str r3, [r7, #28]
80036c0: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOE_CLK_ENABLE();
80036c2: 4b58 ldr r3, [pc, #352] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
80036c4: 6b1b ldr r3, [r3, #48] ; 0x30
80036c6: 4a57 ldr r2, [pc, #348] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
80036c8: f043 0310 orr.w r3, r3, #16
80036cc: 6313 str r3, [r2, #48] ; 0x30
80036ce: 4b55 ldr r3, [pc, #340] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
80036d0: 6b1b ldr r3, [r3, #48] ; 0x30
80036d2: f003 0310 and.w r3, r3, #16
80036d6: 61bb str r3, [r7, #24]
80036d8: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOF_CLK_ENABLE();
80036da: 4b52 ldr r3, [pc, #328] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
80036dc: 6b1b ldr r3, [r3, #48] ; 0x30
80036de: 4a51 ldr r2, [pc, #324] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
80036e0: f043 0320 orr.w r3, r3, #32
80036e4: 6313 str r3, [r2, #48] ; 0x30
80036e6: 4b4f ldr r3, [pc, #316] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
80036e8: 6b1b ldr r3, [r3, #48] ; 0x30
80036ea: f003 0320 and.w r3, r3, #32
80036ee: 617b str r3, [r7, #20]
80036f0: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOG_CLK_ENABLE();
80036f2: 4b4c ldr r3, [pc, #304] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
80036f4: 6b1b ldr r3, [r3, #48] ; 0x30
80036f6: 4a4b ldr r2, [pc, #300] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
80036f8: f043 0340 orr.w r3, r3, #64 ; 0x40
80036fc: 6313 str r3, [r2, #48] ; 0x30
80036fe: 4b49 ldr r3, [pc, #292] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
8003700: 6b1b ldr r3, [r3, #48] ; 0x30
8003702: f003 0340 and.w r3, r3, #64 ; 0x40
8003706: 613b str r3, [r7, #16]
8003708: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOH_CLK_ENABLE();
800370a: 4b46 ldr r3, [pc, #280] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
800370c: 6b1b ldr r3, [r3, #48] ; 0x30
800370e: 4a45 ldr r2, [pc, #276] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
8003710: f043 0380 orr.w r3, r3, #128 ; 0x80
8003714: 6313 str r3, [r2, #48] ; 0x30
8003716: 4b43 ldr r3, [pc, #268] ; (8003824 <BSP_SDRAM_MspInit+0x1cc>)
8003718: 6b1b ldr r3, [r3, #48] ; 0x30
800371a: f003 0380 and.w r3, r3, #128 ; 0x80
800371e: 60fb str r3, [r7, #12]
8003720: 68fb ldr r3, [r7, #12]
/* Common GPIO configuration */
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
8003722: 2302 movs r3, #2
8003724: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Pull = GPIO_PULLUP;
8003726: 2301 movs r3, #1
8003728: 637b str r3, [r7, #52] ; 0x34
gpio_init_structure.Speed = GPIO_SPEED_FAST;
800372a: 2302 movs r3, #2
800372c: 63bb str r3, [r7, #56] ; 0x38
gpio_init_structure.Alternate = GPIO_AF12_FMC;
800372e: 230c movs r3, #12
8003730: 63fb str r3, [r7, #60] ; 0x3c
/* GPIOC configuration */
gpio_init_structure.Pin = GPIO_PIN_3;
8003732: 2308 movs r3, #8
8003734: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOC, &gpio_init_structure);
8003736: f107 032c add.w r3, r7, #44 ; 0x2c
800373a: 4619 mov r1, r3
800373c: 483a ldr r0, [pc, #232] ; (8003828 <BSP_SDRAM_MspInit+0x1d0>)
800373e: f003 fcdf bl 8007100 <HAL_GPIO_Init>
/* GPIOD configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
8003742: f24c 7303 movw r3, #50947 ; 0xc703
8003746: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOD, &gpio_init_structure);
8003748: f107 032c add.w r3, r7, #44 ; 0x2c
800374c: 4619 mov r1, r3
800374e: 4837 ldr r0, [pc, #220] ; (800382c <BSP_SDRAM_MspInit+0x1d4>)
8003750: f003 fcd6 bl 8007100 <HAL_GPIO_Init>
/* GPIOE configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
8003754: f64f 7383 movw r3, #65411 ; 0xff83
8003758: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
800375a: f107 032c add.w r3, r7, #44 ; 0x2c
800375e: 4619 mov r1, r3
8003760: 4833 ldr r0, [pc, #204] ; (8003830 <BSP_SDRAM_MspInit+0x1d8>)
8003762: f003 fccd bl 8007100 <HAL_GPIO_Init>
/* GPIOF configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
8003766: f64f 033f movw r3, #63551 ; 0xf83f
800376a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOF, &gpio_init_structure);
800376c: f107 032c add.w r3, r7, #44 ; 0x2c
8003770: 4619 mov r1, r3
8003772: 4830 ldr r0, [pc, #192] ; (8003834 <BSP_SDRAM_MspInit+0x1dc>)
8003774: f003 fcc4 bl 8007100 <HAL_GPIO_Init>
/* GPIOG configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
8003778: f248 1333 movw r3, #33075 ; 0x8133
800377c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_15;
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
800377e: f107 032c add.w r3, r7, #44 ; 0x2c
8003782: 4619 mov r1, r3
8003784: 482c ldr r0, [pc, #176] ; (8003838 <BSP_SDRAM_MspInit+0x1e0>)
8003786: f003 fcbb bl 8007100 <HAL_GPIO_Init>
/* GPIOH configuration */
gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
800378a: 2328 movs r3, #40 ; 0x28
800378c: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOH, &gpio_init_structure);
800378e: f107 032c add.w r3, r7, #44 ; 0x2c
8003792: 4619 mov r1, r3
8003794: 4829 ldr r0, [pc, #164] ; (800383c <BSP_SDRAM_MspInit+0x1e4>)
8003796: f003 fcb3 bl 8007100 <HAL_GPIO_Init>
/* Configure common DMA parameters */
dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
800379a: 4b29 ldr r3, [pc, #164] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
800379c: 2200 movs r2, #0
800379e: 605a str r2, [r3, #4]
dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
80037a0: 4b27 ldr r3, [pc, #156] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037a2: 2280 movs r2, #128 ; 0x80
80037a4: 609a str r2, [r3, #8]
dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
80037a6: 4b26 ldr r3, [pc, #152] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037a8: f44f 7200 mov.w r2, #512 ; 0x200
80037ac: 60da str r2, [r3, #12]
dma_handle.Init.MemInc = DMA_MINC_ENABLE;
80037ae: 4b24 ldr r3, [pc, #144] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037b0: f44f 6280 mov.w r2, #1024 ; 0x400
80037b4: 611a str r2, [r3, #16]
dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
80037b6: 4b22 ldr r3, [pc, #136] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037b8: f44f 5280 mov.w r2, #4096 ; 0x1000
80037bc: 615a str r2, [r3, #20]
dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
80037be: 4b20 ldr r3, [pc, #128] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037c0: f44f 4280 mov.w r2, #16384 ; 0x4000
80037c4: 619a str r2, [r3, #24]
dma_handle.Init.Mode = DMA_NORMAL;
80037c6: 4b1e ldr r3, [pc, #120] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037c8: 2200 movs r2, #0
80037ca: 61da str r2, [r3, #28]
dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
80037cc: 4b1c ldr r3, [pc, #112] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037ce: f44f 3200 mov.w r2, #131072 ; 0x20000
80037d2: 621a str r2, [r3, #32]
dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
80037d4: 4b1a ldr r3, [pc, #104] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037d6: 2200 movs r2, #0
80037d8: 625a str r2, [r3, #36] ; 0x24
dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
80037da: 4b19 ldr r3, [pc, #100] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037dc: 2203 movs r2, #3
80037de: 629a str r2, [r3, #40] ; 0x28
dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
80037e0: 4b17 ldr r3, [pc, #92] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037e2: 2200 movs r2, #0
80037e4: 62da str r2, [r3, #44] ; 0x2c
dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
80037e6: 4b16 ldr r3, [pc, #88] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037e8: 2200 movs r2, #0
80037ea: 631a str r2, [r3, #48] ; 0x30
dma_handle.Instance = SDRAM_DMAx_STREAM;
80037ec: 4b14 ldr r3, [pc, #80] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037ee: 4a15 ldr r2, [pc, #84] ; (8003844 <BSP_SDRAM_MspInit+0x1ec>)
80037f0: 601a str r2, [r3, #0]
/* Associate the DMA handle */
__HAL_LINKDMA(hsdram, hdma, dma_handle);
80037f2: 687b ldr r3, [r7, #4]
80037f4: 4a12 ldr r2, [pc, #72] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037f6: 631a str r2, [r3, #48] ; 0x30
80037f8: 4a11 ldr r2, [pc, #68] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
80037fa: 687b ldr r3, [r7, #4]
80037fc: 6393 str r3, [r2, #56] ; 0x38
/* Deinitialize the stream for new transfer */
HAL_DMA_DeInit(&dma_handle);
80037fe: 4810 ldr r0, [pc, #64] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
8003800: f001 ff5e bl 80056c0 <HAL_DMA_DeInit>
/* Configure the DMA stream */
HAL_DMA_Init(&dma_handle);
8003804: 480e ldr r0, [pc, #56] ; (8003840 <BSP_SDRAM_MspInit+0x1e8>)
8003806: f001 fead bl 8005564 <HAL_DMA_Init>
/* NVIC configuration for DMA transfer complete interrupt */
HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0);
800380a: 2200 movs r2, #0
800380c: 210f movs r1, #15
800380e: 2038 movs r0, #56 ; 0x38
8003810: f001 fcb4 bl 800517c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
8003814: 2038 movs r0, #56 ; 0x38
8003816: f001 fccd bl 80051b4 <HAL_NVIC_EnableIRQ>
}
800381a: bf00 nop
800381c: 3740 adds r7, #64 ; 0x40
800381e: 46bd mov sp, r7
8003820: bd80 pop {r7, pc}
8003822: bf00 nop
8003824: 40023800 .word 0x40023800
8003828: 40020800 .word 0x40020800
800382c: 40020c00 .word 0x40020c00
8003830: 40021000 .word 0x40021000
8003834: 40021400 .word 0x40021400
8003838: 40021800 .word 0x40021800
800383c: 40021c00 .word 0x40021c00
8003840: 200004dc .word 0x200004dc
8003844: 40026410 .word 0x40026410
08003848 <BSP_TS_Init>:
* @param ts_SizeX: Maximum X size of the TS area on LCD
* @param ts_SizeY: Maximum Y size of the TS area on LCD
* @retval TS_OK if all initializations are OK. Other value if error.
*/
uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY)
{
8003848: b580 push {r7, lr}
800384a: b084 sub sp, #16
800384c: af00 add r7, sp, #0
800384e: 4603 mov r3, r0
8003850: 460a mov r2, r1
8003852: 80fb strh r3, [r7, #6]
8003854: 4613 mov r3, r2
8003856: 80bb strh r3, [r7, #4]
uint8_t status = TS_OK;
8003858: 2300 movs r3, #0
800385a: 73fb strb r3, [r7, #15]
tsXBoundary = ts_SizeX;
800385c: 4a14 ldr r2, [pc, #80] ; (80038b0 <BSP_TS_Init+0x68>)
800385e: 88fb ldrh r3, [r7, #6]
8003860: 8013 strh r3, [r2, #0]
tsYBoundary = ts_SizeY;
8003862: 4a14 ldr r2, [pc, #80] ; (80038b4 <BSP_TS_Init+0x6c>)
8003864: 88bb ldrh r3, [r7, #4]
8003866: 8013 strh r3, [r2, #0]
/* Read ID and verify if the touch screen driver is ready */
ft5336_ts_drv.Init(TS_I2C_ADDRESS);
8003868: 4b13 ldr r3, [pc, #76] ; (80038b8 <BSP_TS_Init+0x70>)
800386a: 681b ldr r3, [r3, #0]
800386c: 2070 movs r0, #112 ; 0x70
800386e: 4798 blx r3
if(ft5336_ts_drv.ReadID(TS_I2C_ADDRESS) == FT5336_ID_VALUE)
8003870: 4b11 ldr r3, [pc, #68] ; (80038b8 <BSP_TS_Init+0x70>)
8003872: 685b ldr r3, [r3, #4]
8003874: 2070 movs r0, #112 ; 0x70
8003876: 4798 blx r3
8003878: 4603 mov r3, r0
800387a: 2b51 cmp r3, #81 ; 0x51
800387c: d111 bne.n 80038a2 <BSP_TS_Init+0x5a>
{
/* Initialize the TS driver structure */
tsDriver = &ft5336_ts_drv;
800387e: 4b0f ldr r3, [pc, #60] ; (80038bc <BSP_TS_Init+0x74>)
8003880: 4a0d ldr r2, [pc, #52] ; (80038b8 <BSP_TS_Init+0x70>)
8003882: 601a str r2, [r3, #0]
I2cAddress = TS_I2C_ADDRESS;
8003884: 4b0e ldr r3, [pc, #56] ; (80038c0 <BSP_TS_Init+0x78>)
8003886: 2270 movs r2, #112 ; 0x70
8003888: 701a strb r2, [r3, #0]
tsOrientation = TS_SWAP_XY;
800388a: 4b0e ldr r3, [pc, #56] ; (80038c4 <BSP_TS_Init+0x7c>)
800388c: 2208 movs r2, #8
800388e: 701a strb r2, [r3, #0]
/* Initialize the TS driver */
tsDriver->Start(I2cAddress);
8003890: 4b0a ldr r3, [pc, #40] ; (80038bc <BSP_TS_Init+0x74>)
8003892: 681b ldr r3, [r3, #0]
8003894: 68db ldr r3, [r3, #12]
8003896: 4a0a ldr r2, [pc, #40] ; (80038c0 <BSP_TS_Init+0x78>)
8003898: 7812 ldrb r2, [r2, #0]
800389a: b292 uxth r2, r2
800389c: 4610 mov r0, r2
800389e: 4798 blx r3
80038a0: e001 b.n 80038a6 <BSP_TS_Init+0x5e>
}
else
{
status = TS_DEVICE_NOT_FOUND;
80038a2: 2303 movs r3, #3
80038a4: 73fb strb r3, [r7, #15]
}
return status;
80038a6: 7bfb ldrb r3, [r7, #15]
}
80038a8: 4618 mov r0, r3
80038aa: 3710 adds r7, #16
80038ac: 46bd mov sp, r7
80038ae: bd80 pop {r7, pc}
80038b0: 20000540 .word 0x20000540
80038b4: 20000542 .word 0x20000542
80038b8: 20000000 .word 0x20000000
80038bc: 2000053c .word 0x2000053c
80038c0: 20000545 .word 0x20000545
80038c4: 20000544 .word 0x20000544
080038c8 <BSP_TS_GetState>:
* @brief Returns status and positions of the touch screen.
* @param TS_State: Pointer to touch screen current state structure
* @retval TS_OK if all initializations are OK. Other value if error.
*/
uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State)
{
80038c8: b590 push {r4, r7, lr}
80038ca: b097 sub sp, #92 ; 0x5c
80038cc: af02 add r7, sp, #8
80038ce: 6078 str r0, [r7, #4]
static uint32_t _x[TS_MAX_NB_TOUCH] = {0, 0};
static uint32_t _y[TS_MAX_NB_TOUCH] = {0, 0};
uint8_t ts_status = TS_OK;
80038d0: 2300 movs r3, #0
80038d2: f887 304f strb.w r3, [r7, #79] ; 0x4f
uint16_t brute_y[TS_MAX_NB_TOUCH];
uint16_t x_diff;
uint16_t y_diff;
uint32_t index;
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
uint32_t weight = 0;
80038d6: 2300 movs r3, #0
80038d8: 613b str r3, [r7, #16]
uint32_t area = 0;
80038da: 2300 movs r3, #0
80038dc: 60fb str r3, [r7, #12]
uint32_t event = 0;
80038de: 2300 movs r3, #0
80038e0: 60bb str r3, [r7, #8]
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
/* Check and update the number of touches active detected */
TS_State->touchDetected = tsDriver->DetectTouch(I2cAddress);
80038e2: 4b97 ldr r3, [pc, #604] ; (8003b40 <BSP_TS_GetState+0x278>)
80038e4: 681b ldr r3, [r3, #0]
80038e6: 691b ldr r3, [r3, #16]
80038e8: 4a96 ldr r2, [pc, #600] ; (8003b44 <BSP_TS_GetState+0x27c>)
80038ea: 7812 ldrb r2, [r2, #0]
80038ec: b292 uxth r2, r2
80038ee: 4610 mov r0, r2
80038f0: 4798 blx r3
80038f2: 4603 mov r3, r0
80038f4: 461a mov r2, r3
80038f6: 687b ldr r3, [r7, #4]
80038f8: 701a strb r2, [r3, #0]
if(TS_State->touchDetected)
80038fa: 687b ldr r3, [r7, #4]
80038fc: 781b ldrb r3, [r3, #0]
80038fe: 2b00 cmp r3, #0
8003900: f000 81a8 beq.w 8003c54 <BSP_TS_GetState+0x38c>
{
for(index=0; index < TS_State->touchDetected; index++)
8003904: 2300 movs r3, #0
8003906: 64bb str r3, [r7, #72] ; 0x48
8003908: e197 b.n 8003c3a <BSP_TS_GetState+0x372>
{
/* Get each touch coordinates */
tsDriver->GetXY(I2cAddress, &(brute_x[index]), &(brute_y[index]));
800390a: 4b8d ldr r3, [pc, #564] ; (8003b40 <BSP_TS_GetState+0x278>)
800390c: 681b ldr r3, [r3, #0]
800390e: 695b ldr r3, [r3, #20]
8003910: 4a8c ldr r2, [pc, #560] ; (8003b44 <BSP_TS_GetState+0x27c>)
8003912: 7812 ldrb r2, [r2, #0]
8003914: b290 uxth r0, r2
8003916: f107 0120 add.w r1, r7, #32
800391a: 6cba ldr r2, [r7, #72] ; 0x48
800391c: 0052 lsls r2, r2, #1
800391e: 188c adds r4, r1, r2
8003920: f107 0114 add.w r1, r7, #20
8003924: 6cba ldr r2, [r7, #72] ; 0x48
8003926: 0052 lsls r2, r2, #1
8003928: 440a add r2, r1
800392a: 4621 mov r1, r4
800392c: 4798 blx r3
if(tsOrientation == TS_SWAP_NONE)
800392e: 4b86 ldr r3, [pc, #536] ; (8003b48 <BSP_TS_GetState+0x280>)
8003930: 781b ldrb r3, [r3, #0]
8003932: 2b01 cmp r3, #1
8003934: d11b bne.n 800396e <BSP_TS_GetState+0xa6>
{
x[index] = brute_x[index];
8003936: 6cbb ldr r3, [r7, #72] ; 0x48
8003938: 005b lsls r3, r3, #1
800393a: f107 0250 add.w r2, r7, #80 ; 0x50
800393e: 4413 add r3, r2
8003940: f833 2c30 ldrh.w r2, [r3, #-48]
8003944: 6cbb ldr r3, [r7, #72] ; 0x48
8003946: 005b lsls r3, r3, #1
8003948: f107 0150 add.w r1, r7, #80 ; 0x50
800394c: 440b add r3, r1
800394e: f823 2c18 strh.w r2, [r3, #-24]
y[index] = brute_y[index];
8003952: 6cbb ldr r3, [r7, #72] ; 0x48
8003954: 005b lsls r3, r3, #1
8003956: f107 0250 add.w r2, r7, #80 ; 0x50
800395a: 4413 add r3, r2
800395c: f833 2c3c ldrh.w r2, [r3, #-60]
8003960: 6cbb ldr r3, [r7, #72] ; 0x48
8003962: 005b lsls r3, r3, #1
8003964: f107 0150 add.w r1, r7, #80 ; 0x50
8003968: 440b add r3, r1
800396a: f823 2c24 strh.w r2, [r3, #-36]
}
if(tsOrientation & TS_SWAP_X)
800396e: 4b76 ldr r3, [pc, #472] ; (8003b48 <BSP_TS_GetState+0x280>)
8003970: 781b ldrb r3, [r3, #0]
8003972: f003 0302 and.w r3, r3, #2
8003976: 2b00 cmp r3, #0
8003978: d010 beq.n 800399c <BSP_TS_GetState+0xd4>
{
x[index] = 4096 - brute_x[index];
800397a: 6cbb ldr r3, [r7, #72] ; 0x48
800397c: 005b lsls r3, r3, #1
800397e: f107 0250 add.w r2, r7, #80 ; 0x50
8003982: 4413 add r3, r2
8003984: f833 3c30 ldrh.w r3, [r3, #-48]
8003988: f5c3 5380 rsb r3, r3, #4096 ; 0x1000
800398c: b29a uxth r2, r3
800398e: 6cbb ldr r3, [r7, #72] ; 0x48
8003990: 005b lsls r3, r3, #1
8003992: f107 0150 add.w r1, r7, #80 ; 0x50
8003996: 440b add r3, r1
8003998: f823 2c18 strh.w r2, [r3, #-24]
}
if(tsOrientation & TS_SWAP_Y)
800399c: 4b6a ldr r3, [pc, #424] ; (8003b48 <BSP_TS_GetState+0x280>)
800399e: 781b ldrb r3, [r3, #0]
80039a0: f003 0304 and.w r3, r3, #4
80039a4: 2b00 cmp r3, #0
80039a6: d010 beq.n 80039ca <BSP_TS_GetState+0x102>
{
y[index] = 4096 - brute_y[index];
80039a8: 6cbb ldr r3, [r7, #72] ; 0x48
80039aa: 005b lsls r3, r3, #1
80039ac: f107 0250 add.w r2, r7, #80 ; 0x50
80039b0: 4413 add r3, r2
80039b2: f833 3c3c ldrh.w r3, [r3, #-60]
80039b6: f5c3 5380 rsb r3, r3, #4096 ; 0x1000
80039ba: b29a uxth r2, r3
80039bc: 6cbb ldr r3, [r7, #72] ; 0x48
80039be: 005b lsls r3, r3, #1
80039c0: f107 0150 add.w r1, r7, #80 ; 0x50
80039c4: 440b add r3, r1
80039c6: f823 2c24 strh.w r2, [r3, #-36]
}
if(tsOrientation & TS_SWAP_XY)
80039ca: 4b5f ldr r3, [pc, #380] ; (8003b48 <BSP_TS_GetState+0x280>)
80039cc: 781b ldrb r3, [r3, #0]
80039ce: f003 0308 and.w r3, r3, #8
80039d2: 2b00 cmp r3, #0
80039d4: d01b beq.n 8003a0e <BSP_TS_GetState+0x146>
{
y[index] = brute_x[index];
80039d6: 6cbb ldr r3, [r7, #72] ; 0x48
80039d8: 005b lsls r3, r3, #1
80039da: f107 0250 add.w r2, r7, #80 ; 0x50
80039de: 4413 add r3, r2
80039e0: f833 2c30 ldrh.w r2, [r3, #-48]
80039e4: 6cbb ldr r3, [r7, #72] ; 0x48
80039e6: 005b lsls r3, r3, #1
80039e8: f107 0150 add.w r1, r7, #80 ; 0x50
80039ec: 440b add r3, r1
80039ee: f823 2c24 strh.w r2, [r3, #-36]
x[index] = brute_y[index];
80039f2: 6cbb ldr r3, [r7, #72] ; 0x48
80039f4: 005b lsls r3, r3, #1
80039f6: f107 0250 add.w r2, r7, #80 ; 0x50
80039fa: 4413 add r3, r2
80039fc: f833 2c3c ldrh.w r2, [r3, #-60]
8003a00: 6cbb ldr r3, [r7, #72] ; 0x48
8003a02: 005b lsls r3, r3, #1
8003a04: f107 0150 add.w r1, r7, #80 ; 0x50
8003a08: 440b add r3, r1
8003a0a: f823 2c18 strh.w r2, [r3, #-24]
}
x_diff = x[index] > _x[index]? (x[index] - _x[index]): (_x[index] - x[index]);
8003a0e: 6cbb ldr r3, [r7, #72] ; 0x48
8003a10: 005b lsls r3, r3, #1
8003a12: f107 0250 add.w r2, r7, #80 ; 0x50
8003a16: 4413 add r3, r2
8003a18: f833 3c18 ldrh.w r3, [r3, #-24]
8003a1c: 4619 mov r1, r3
8003a1e: 4a4b ldr r2, [pc, #300] ; (8003b4c <BSP_TS_GetState+0x284>)
8003a20: 6cbb ldr r3, [r7, #72] ; 0x48
8003a22: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003a26: 4299 cmp r1, r3
8003a28: d90e bls.n 8003a48 <BSP_TS_GetState+0x180>
8003a2a: 6cbb ldr r3, [r7, #72] ; 0x48
8003a2c: 005b lsls r3, r3, #1
8003a2e: f107 0250 add.w r2, r7, #80 ; 0x50
8003a32: 4413 add r3, r2
8003a34: f833 2c18 ldrh.w r2, [r3, #-24]
8003a38: 4944 ldr r1, [pc, #272] ; (8003b4c <BSP_TS_GetState+0x284>)
8003a3a: 6cbb ldr r3, [r7, #72] ; 0x48
8003a3c: f851 3023 ldr.w r3, [r1, r3, lsl #2]
8003a40: b29b uxth r3, r3
8003a42: 1ad3 subs r3, r2, r3
8003a44: b29b uxth r3, r3
8003a46: e00d b.n 8003a64 <BSP_TS_GetState+0x19c>
8003a48: 4a40 ldr r2, [pc, #256] ; (8003b4c <BSP_TS_GetState+0x284>)
8003a4a: 6cbb ldr r3, [r7, #72] ; 0x48
8003a4c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003a50: b29a uxth r2, r3
8003a52: 6cbb ldr r3, [r7, #72] ; 0x48
8003a54: 005b lsls r3, r3, #1
8003a56: f107 0150 add.w r1, r7, #80 ; 0x50
8003a5a: 440b add r3, r1
8003a5c: f833 3c18 ldrh.w r3, [r3, #-24]
8003a60: 1ad3 subs r3, r2, r3
8003a62: b29b uxth r3, r3
8003a64: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
y_diff = y[index] > _y[index]? (y[index] - _y[index]): (_y[index] - y[index]);
8003a68: 6cbb ldr r3, [r7, #72] ; 0x48
8003a6a: 005b lsls r3, r3, #1
8003a6c: f107 0250 add.w r2, r7, #80 ; 0x50
8003a70: 4413 add r3, r2
8003a72: f833 3c24 ldrh.w r3, [r3, #-36]
8003a76: 4619 mov r1, r3
8003a78: 4a35 ldr r2, [pc, #212] ; (8003b50 <BSP_TS_GetState+0x288>)
8003a7a: 6cbb ldr r3, [r7, #72] ; 0x48
8003a7c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003a80: 4299 cmp r1, r3
8003a82: d90e bls.n 8003aa2 <BSP_TS_GetState+0x1da>
8003a84: 6cbb ldr r3, [r7, #72] ; 0x48
8003a86: 005b lsls r3, r3, #1
8003a88: f107 0250 add.w r2, r7, #80 ; 0x50
8003a8c: 4413 add r3, r2
8003a8e: f833 2c24 ldrh.w r2, [r3, #-36]
8003a92: 492f ldr r1, [pc, #188] ; (8003b50 <BSP_TS_GetState+0x288>)
8003a94: 6cbb ldr r3, [r7, #72] ; 0x48
8003a96: f851 3023 ldr.w r3, [r1, r3, lsl #2]
8003a9a: b29b uxth r3, r3
8003a9c: 1ad3 subs r3, r2, r3
8003a9e: b29b uxth r3, r3
8003aa0: e00d b.n 8003abe <BSP_TS_GetState+0x1f6>
8003aa2: 4a2b ldr r2, [pc, #172] ; (8003b50 <BSP_TS_GetState+0x288>)
8003aa4: 6cbb ldr r3, [r7, #72] ; 0x48
8003aa6: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003aaa: b29a uxth r2, r3
8003aac: 6cbb ldr r3, [r7, #72] ; 0x48
8003aae: 005b lsls r3, r3, #1
8003ab0: f107 0150 add.w r1, r7, #80 ; 0x50
8003ab4: 440b add r3, r1
8003ab6: f833 3c24 ldrh.w r3, [r3, #-36]
8003aba: 1ad3 subs r3, r2, r3
8003abc: b29b uxth r3, r3
8003abe: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
if ((x_diff + y_diff) > 5)
8003ac2: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46
8003ac6: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
8003aca: 4413 add r3, r2
8003acc: 2b05 cmp r3, #5
8003ace: dd17 ble.n 8003b00 <BSP_TS_GetState+0x238>
{
_x[index] = x[index];
8003ad0: 6cbb ldr r3, [r7, #72] ; 0x48
8003ad2: 005b lsls r3, r3, #1
8003ad4: f107 0250 add.w r2, r7, #80 ; 0x50
8003ad8: 4413 add r3, r2
8003ada: f833 3c18 ldrh.w r3, [r3, #-24]
8003ade: 4619 mov r1, r3
8003ae0: 4a1a ldr r2, [pc, #104] ; (8003b4c <BSP_TS_GetState+0x284>)
8003ae2: 6cbb ldr r3, [r7, #72] ; 0x48
8003ae4: f842 1023 str.w r1, [r2, r3, lsl #2]
_y[index] = y[index];
8003ae8: 6cbb ldr r3, [r7, #72] ; 0x48
8003aea: 005b lsls r3, r3, #1
8003aec: f107 0250 add.w r2, r7, #80 ; 0x50
8003af0: 4413 add r3, r2
8003af2: f833 3c24 ldrh.w r3, [r3, #-36]
8003af6: 4619 mov r1, r3
8003af8: 4a15 ldr r2, [pc, #84] ; (8003b50 <BSP_TS_GetState+0x288>)
8003afa: 6cbb ldr r3, [r7, #72] ; 0x48
8003afc: f842 1023 str.w r1, [r2, r3, lsl #2]
}
if(I2cAddress == FT5336_I2C_SLAVE_ADDRESS)
8003b00: 4b10 ldr r3, [pc, #64] ; (8003b44 <BSP_TS_GetState+0x27c>)
8003b02: 781b ldrb r3, [r3, #0]
8003b04: 2b70 cmp r3, #112 ; 0x70
8003b06: d125 bne.n 8003b54 <BSP_TS_GetState+0x28c>
{
TS_State->touchX[index] = x[index];
8003b08: 6cbb ldr r3, [r7, #72] ; 0x48
8003b0a: 005b lsls r3, r3, #1
8003b0c: f107 0250 add.w r2, r7, #80 ; 0x50
8003b10: 4413 add r3, r2
8003b12: f833 1c18 ldrh.w r1, [r3, #-24]
8003b16: 687a ldr r2, [r7, #4]
8003b18: 6cbb ldr r3, [r7, #72] ; 0x48
8003b1a: 005b lsls r3, r3, #1
8003b1c: 4413 add r3, r2
8003b1e: 460a mov r2, r1
8003b20: 805a strh r2, [r3, #2]
TS_State->touchY[index] = y[index];
8003b22: 6cbb ldr r3, [r7, #72] ; 0x48
8003b24: 005b lsls r3, r3, #1
8003b26: f107 0250 add.w r2, r7, #80 ; 0x50
8003b2a: 4413 add r3, r2
8003b2c: f833 1c24 ldrh.w r1, [r3, #-36]
8003b30: 687a ldr r2, [r7, #4]
8003b32: 6cbb ldr r3, [r7, #72] ; 0x48
8003b34: 3304 adds r3, #4
8003b36: 005b lsls r3, r3, #1
8003b38: 4413 add r3, r2
8003b3a: 460a mov r2, r1
8003b3c: 809a strh r2, [r3, #4]
8003b3e: e02c b.n 8003b9a <BSP_TS_GetState+0x2d2>
8003b40: 2000053c .word 0x2000053c
8003b44: 20000545 .word 0x20000545
8003b48: 20000544 .word 0x20000544
8003b4c: 20000548 .word 0x20000548
8003b50: 2000055c .word 0x2000055c
}
else
{
/* 2^12 = 4096 : indexes are expressed on a dynamic of 4096 */
TS_State->touchX[index] = (tsXBoundary * _x[index]) >> 12;
8003b54: 4b42 ldr r3, [pc, #264] ; (8003c60 <BSP_TS_GetState+0x398>)
8003b56: 881b ldrh r3, [r3, #0]
8003b58: 4619 mov r1, r3
8003b5a: 4a42 ldr r2, [pc, #264] ; (8003c64 <BSP_TS_GetState+0x39c>)
8003b5c: 6cbb ldr r3, [r7, #72] ; 0x48
8003b5e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003b62: fb03 f301 mul.w r3, r3, r1
8003b66: 0b1b lsrs r3, r3, #12
8003b68: b299 uxth r1, r3
8003b6a: 687a ldr r2, [r7, #4]
8003b6c: 6cbb ldr r3, [r7, #72] ; 0x48
8003b6e: 005b lsls r3, r3, #1
8003b70: 4413 add r3, r2
8003b72: 460a mov r2, r1
8003b74: 805a strh r2, [r3, #2]
TS_State->touchY[index] = (tsYBoundary * _y[index]) >> 12;
8003b76: 4b3c ldr r3, [pc, #240] ; (8003c68 <BSP_TS_GetState+0x3a0>)
8003b78: 881b ldrh r3, [r3, #0]
8003b7a: 4619 mov r1, r3
8003b7c: 4a3b ldr r2, [pc, #236] ; (8003c6c <BSP_TS_GetState+0x3a4>)
8003b7e: 6cbb ldr r3, [r7, #72] ; 0x48
8003b80: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003b84: fb03 f301 mul.w r3, r3, r1
8003b88: 0b1b lsrs r3, r3, #12
8003b8a: b299 uxth r1, r3
8003b8c: 687a ldr r2, [r7, #4]
8003b8e: 6cbb ldr r3, [r7, #72] ; 0x48
8003b90: 3304 adds r3, #4
8003b92: 005b lsls r3, r3, #1
8003b94: 4413 add r3, r2
8003b96: 460a mov r2, r1
8003b98: 809a strh r2, [r3, #4]
}
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
/* Get touch info related to the current touch */
ft5336_TS_GetTouchInfo(I2cAddress, index, &weight, &area, &event);
8003b9a: 4b35 ldr r3, [pc, #212] ; (8003c70 <BSP_TS_GetState+0x3a8>)
8003b9c: 781b ldrb r3, [r3, #0]
8003b9e: b298 uxth r0, r3
8003ba0: f107 010c add.w r1, r7, #12
8003ba4: f107 0210 add.w r2, r7, #16
8003ba8: f107 0308 add.w r3, r7, #8
8003bac: 9300 str r3, [sp, #0]
8003bae: 460b mov r3, r1
8003bb0: 6cb9 ldr r1, [r7, #72] ; 0x48
8003bb2: f7fc fef7 bl 80009a4 <ft5336_TS_GetTouchInfo>
/* Update TS_State structure */
TS_State->touchWeight[index] = weight;
8003bb6: 693b ldr r3, [r7, #16]
8003bb8: b2d9 uxtb r1, r3
8003bba: 687a ldr r2, [r7, #4]
8003bbc: 6cbb ldr r3, [r7, #72] ; 0x48
8003bbe: 4413 add r3, r2
8003bc0: 3316 adds r3, #22
8003bc2: 460a mov r2, r1
8003bc4: 701a strb r2, [r3, #0]
TS_State->touchArea[index] = area;
8003bc6: 68fb ldr r3, [r7, #12]
8003bc8: b2d9 uxtb r1, r3
8003bca: 687a ldr r2, [r7, #4]
8003bcc: 6cbb ldr r3, [r7, #72] ; 0x48
8003bce: 4413 add r3, r2
8003bd0: 3320 adds r3, #32
8003bd2: 460a mov r2, r1
8003bd4: 701a strb r2, [r3, #0]
/* Remap touch event */
switch(event)
8003bd6: 68bb ldr r3, [r7, #8]
8003bd8: 2b03 cmp r3, #3
8003bda: d827 bhi.n 8003c2c <BSP_TS_GetState+0x364>
8003bdc: a201 add r2, pc, #4 ; (adr r2, 8003be4 <BSP_TS_GetState+0x31c>)
8003bde: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003be2: bf00 nop
8003be4: 08003bf5 .word 0x08003bf5
8003be8: 08003c03 .word 0x08003c03
8003bec: 08003c11 .word 0x08003c11
8003bf0: 08003c1f .word 0x08003c1f
{
case FT5336_TOUCH_EVT_FLAG_PRESS_DOWN :
TS_State->touchEventId[index] = TOUCH_EVENT_PRESS_DOWN;
8003bf4: 687a ldr r2, [r7, #4]
8003bf6: 6cbb ldr r3, [r7, #72] ; 0x48
8003bf8: 4413 add r3, r2
8003bfa: 331b adds r3, #27
8003bfc: 2201 movs r2, #1
8003bfe: 701a strb r2, [r3, #0]
break;
8003c00: e018 b.n 8003c34 <BSP_TS_GetState+0x36c>
case FT5336_TOUCH_EVT_FLAG_LIFT_UP :
TS_State->touchEventId[index] = TOUCH_EVENT_LIFT_UP;
8003c02: 687a ldr r2, [r7, #4]
8003c04: 6cbb ldr r3, [r7, #72] ; 0x48
8003c06: 4413 add r3, r2
8003c08: 331b adds r3, #27
8003c0a: 2202 movs r2, #2
8003c0c: 701a strb r2, [r3, #0]
break;
8003c0e: e011 b.n 8003c34 <BSP_TS_GetState+0x36c>
case FT5336_TOUCH_EVT_FLAG_CONTACT :
TS_State->touchEventId[index] = TOUCH_EVENT_CONTACT;
8003c10: 687a ldr r2, [r7, #4]
8003c12: 6cbb ldr r3, [r7, #72] ; 0x48
8003c14: 4413 add r3, r2
8003c16: 331b adds r3, #27
8003c18: 2203 movs r2, #3
8003c1a: 701a strb r2, [r3, #0]
break;
8003c1c: e00a b.n 8003c34 <BSP_TS_GetState+0x36c>
case FT5336_TOUCH_EVT_FLAG_NO_EVENT :
TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT;
8003c1e: 687a ldr r2, [r7, #4]
8003c20: 6cbb ldr r3, [r7, #72] ; 0x48
8003c22: 4413 add r3, r2
8003c24: 331b adds r3, #27
8003c26: 2200 movs r2, #0
8003c28: 701a strb r2, [r3, #0]
break;
8003c2a: e003 b.n 8003c34 <BSP_TS_GetState+0x36c>
default :
ts_status = TS_ERROR;
8003c2c: 2301 movs r3, #1
8003c2e: f887 304f strb.w r3, [r7, #79] ; 0x4f
break;
8003c32: bf00 nop
for(index=0; index < TS_State->touchDetected; index++)
8003c34: 6cbb ldr r3, [r7, #72] ; 0x48
8003c36: 3301 adds r3, #1
8003c38: 64bb str r3, [r7, #72] ; 0x48
8003c3a: 687b ldr r3, [r7, #4]
8003c3c: 781b ldrb r3, [r3, #0]
8003c3e: 461a mov r2, r3
8003c40: 6cbb ldr r3, [r7, #72] ; 0x48
8003c42: 4293 cmp r3, r2
8003c44: f4ff ae61 bcc.w 800390a <BSP_TS_GetState+0x42>
} /* of for(index=0; index < TS_State->touchDetected; index++) */
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
/* Get gesture Id */
ts_status = BSP_TS_Get_GestureId(TS_State);
8003c48: 6878 ldr r0, [r7, #4]
8003c4a: f000 f813 bl 8003c74 <BSP_TS_Get_GestureId>
8003c4e: 4603 mov r3, r0
8003c50: f887 304f strb.w r3, [r7, #79] ; 0x4f
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
} /* end of if(TS_State->touchDetected != 0) */
return (ts_status);
8003c54: f897 304f ldrb.w r3, [r7, #79] ; 0x4f
}
8003c58: 4618 mov r0, r3
8003c5a: 3754 adds r7, #84 ; 0x54
8003c5c: 46bd mov sp, r7
8003c5e: bd90 pop {r4, r7, pc}
8003c60: 20000540 .word 0x20000540
8003c64: 20000548 .word 0x20000548
8003c68: 20000542 .word 0x20000542
8003c6c: 2000055c .word 0x2000055c
8003c70: 20000545 .word 0x20000545
08003c74 <BSP_TS_Get_GestureId>:
* @brief Update gesture Id following a touch detected.
* @param TS_State: Pointer to touch screen current state structure
* @retval TS_OK if all initializations are OK. Other value if error.
*/
uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State)
{
8003c74: b580 push {r7, lr}
8003c76: b084 sub sp, #16
8003c78: af00 add r7, sp, #0
8003c7a: 6078 str r0, [r7, #4]
uint32_t gestureId = 0;
8003c7c: 2300 movs r3, #0
8003c7e: 60bb str r3, [r7, #8]
uint8_t ts_status = TS_OK;
8003c80: 2300 movs r3, #0
8003c82: 73fb strb r3, [r7, #15]
/* Get gesture Id */
ft5336_TS_GetGestureID(I2cAddress, &gestureId);
8003c84: 4b3b ldr r3, [pc, #236] ; (8003d74 <BSP_TS_Get_GestureId+0x100>)
8003c86: 781b ldrb r3, [r3, #0]
8003c88: b29b uxth r3, r3
8003c8a: f107 0208 add.w r2, r7, #8
8003c8e: 4611 mov r1, r2
8003c90: 4618 mov r0, r3
8003c92: f7fc fe6e bl 8000972 <ft5336_TS_GetGestureID>
/* Remap gesture Id to a TS_GestureIdTypeDef value */
switch(gestureId)
8003c96: 68bb ldr r3, [r7, #8]
8003c98: 2b49 cmp r3, #73 ; 0x49
8003c9a: d05e beq.n 8003d5a <BSP_TS_Get_GestureId+0xe6>
8003c9c: 2b49 cmp r3, #73 ; 0x49
8003c9e: d860 bhi.n 8003d62 <BSP_TS_Get_GestureId+0xee>
8003ca0: 2b1c cmp r3, #28
8003ca2: d83f bhi.n 8003d24 <BSP_TS_Get_GestureId+0xb0>
8003ca4: 2b1c cmp r3, #28
8003ca6: d85c bhi.n 8003d62 <BSP_TS_Get_GestureId+0xee>
8003ca8: a201 add r2, pc, #4 ; (adr r2, 8003cb0 <BSP_TS_Get_GestureId+0x3c>)
8003caa: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003cae: bf00 nop
8003cb0: 08003d2b .word 0x08003d2b
8003cb4: 08003d63 .word 0x08003d63
8003cb8: 08003d63 .word 0x08003d63
8003cbc: 08003d63 .word 0x08003d63
8003cc0: 08003d63 .word 0x08003d63
8003cc4: 08003d63 .word 0x08003d63
8003cc8: 08003d63 .word 0x08003d63
8003ccc: 08003d63 .word 0x08003d63
8003cd0: 08003d63 .word 0x08003d63
8003cd4: 08003d63 .word 0x08003d63
8003cd8: 08003d63 .word 0x08003d63
8003cdc: 08003d63 .word 0x08003d63
8003ce0: 08003d63 .word 0x08003d63
8003ce4: 08003d63 .word 0x08003d63
8003ce8: 08003d63 .word 0x08003d63
8003cec: 08003d63 .word 0x08003d63
8003cf0: 08003d33 .word 0x08003d33
8003cf4: 08003d63 .word 0x08003d63
8003cf8: 08003d63 .word 0x08003d63
8003cfc: 08003d63 .word 0x08003d63
8003d00: 08003d3b .word 0x08003d3b
8003d04: 08003d63 .word 0x08003d63
8003d08: 08003d63 .word 0x08003d63
8003d0c: 08003d63 .word 0x08003d63
8003d10: 08003d43 .word 0x08003d43
8003d14: 08003d63 .word 0x08003d63
8003d18: 08003d63 .word 0x08003d63
8003d1c: 08003d63 .word 0x08003d63
8003d20: 08003d4b .word 0x08003d4b
8003d24: 2b40 cmp r3, #64 ; 0x40
8003d26: d014 beq.n 8003d52 <BSP_TS_Get_GestureId+0xde>
8003d28: e01b b.n 8003d62 <BSP_TS_Get_GestureId+0xee>
{
case FT5336_GEST_ID_NO_GESTURE :
TS_State->gestureId = GEST_ID_NO_GESTURE;
8003d2a: 687b ldr r3, [r7, #4]
8003d2c: 2200 movs r2, #0
8003d2e: 629a str r2, [r3, #40] ; 0x28
break;
8003d30: e01a b.n 8003d68 <BSP_TS_Get_GestureId+0xf4>
case FT5336_GEST_ID_MOVE_UP :
TS_State->gestureId = GEST_ID_MOVE_UP;
8003d32: 687b ldr r3, [r7, #4]
8003d34: 2201 movs r2, #1
8003d36: 629a str r2, [r3, #40] ; 0x28
break;
8003d38: e016 b.n 8003d68 <BSP_TS_Get_GestureId+0xf4>
case FT5336_GEST_ID_MOVE_RIGHT :
TS_State->gestureId = GEST_ID_MOVE_RIGHT;
8003d3a: 687b ldr r3, [r7, #4]
8003d3c: 2202 movs r2, #2
8003d3e: 629a str r2, [r3, #40] ; 0x28
break;
8003d40: e012 b.n 8003d68 <BSP_TS_Get_GestureId+0xf4>
case FT5336_GEST_ID_MOVE_DOWN :
TS_State->gestureId = GEST_ID_MOVE_DOWN;
8003d42: 687b ldr r3, [r7, #4]
8003d44: 2203 movs r2, #3
8003d46: 629a str r2, [r3, #40] ; 0x28
break;
8003d48: e00e b.n 8003d68 <BSP_TS_Get_GestureId+0xf4>
case FT5336_GEST_ID_MOVE_LEFT :
TS_State->gestureId = GEST_ID_MOVE_LEFT;
8003d4a: 687b ldr r3, [r7, #4]
8003d4c: 2204 movs r2, #4
8003d4e: 629a str r2, [r3, #40] ; 0x28
break;
8003d50: e00a b.n 8003d68 <BSP_TS_Get_GestureId+0xf4>
case FT5336_GEST_ID_ZOOM_IN :
TS_State->gestureId = GEST_ID_ZOOM_IN;
8003d52: 687b ldr r3, [r7, #4]
8003d54: 2205 movs r2, #5
8003d56: 629a str r2, [r3, #40] ; 0x28
break;
8003d58: e006 b.n 8003d68 <BSP_TS_Get_GestureId+0xf4>
case FT5336_GEST_ID_ZOOM_OUT :
TS_State->gestureId = GEST_ID_ZOOM_OUT;
8003d5a: 687b ldr r3, [r7, #4]
8003d5c: 2206 movs r2, #6
8003d5e: 629a str r2, [r3, #40] ; 0x28
break;
8003d60: e002 b.n 8003d68 <BSP_TS_Get_GestureId+0xf4>
default :
ts_status = TS_ERROR;
8003d62: 2301 movs r3, #1
8003d64: 73fb strb r3, [r7, #15]
break;
8003d66: bf00 nop
} /* of switch(gestureId) */
return(ts_status);
8003d68: 7bfb ldrb r3, [r7, #15]
}
8003d6a: 4618 mov r0, r3
8003d6c: 3710 adds r7, #16
8003d6e: 46bd mov sp, r7
8003d70: bd80 pop {r7, pc}
8003d72: bf00 nop
8003d74: 20000545 .word 0x20000545
08003d78 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8003d78: b580 push {r7, lr}
8003d7a: b082 sub sp, #8
8003d7c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
8003d7e: 4b11 ldr r3, [pc, #68] ; (8003dc4 <HAL_MspInit+0x4c>)
8003d80: 6c1b ldr r3, [r3, #64] ; 0x40
8003d82: 4a10 ldr r2, [pc, #64] ; (8003dc4 <HAL_MspInit+0x4c>)
8003d84: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8003d88: 6413 str r3, [r2, #64] ; 0x40
8003d8a: 4b0e ldr r3, [pc, #56] ; (8003dc4 <HAL_MspInit+0x4c>)
8003d8c: 6c1b ldr r3, [r3, #64] ; 0x40
8003d8e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8003d92: 607b str r3, [r7, #4]
8003d94: 687b ldr r3, [r7, #4]
__HAL_RCC_SYSCFG_CLK_ENABLE();
8003d96: 4b0b ldr r3, [pc, #44] ; (8003dc4 <HAL_MspInit+0x4c>)
8003d98: 6c5b ldr r3, [r3, #68] ; 0x44
8003d9a: 4a0a ldr r2, [pc, #40] ; (8003dc4 <HAL_MspInit+0x4c>)
8003d9c: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8003da0: 6453 str r3, [r2, #68] ; 0x44
8003da2: 4b08 ldr r3, [pc, #32] ; (8003dc4 <HAL_MspInit+0x4c>)
8003da4: 6c5b ldr r3, [r3, #68] ; 0x44
8003da6: f403 4380 and.w r3, r3, #16384 ; 0x4000
8003daa: 603b str r3, [r7, #0]
8003dac: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
8003dae: 2200 movs r2, #0
8003db0: 210f movs r1, #15
8003db2: f06f 0001 mvn.w r0, #1
8003db6: f001 f9e1 bl 800517c <HAL_NVIC_SetPriority>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8003dba: bf00 nop
8003dbc: 3708 adds r7, #8
8003dbe: 46bd mov sp, r7
8003dc0: bd80 pop {r7, pc}
8003dc2: bf00 nop
8003dc4: 40023800 .word 0x40023800
08003dc8 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8003dc8: b580 push {r7, lr}
8003dca: b08c sub sp, #48 ; 0x30
8003dcc: af00 add r7, sp, #0
8003dce: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8003dd0: f107 031c add.w r3, r7, #28
8003dd4: 2200 movs r2, #0
8003dd6: 601a str r2, [r3, #0]
8003dd8: 605a str r2, [r3, #4]
8003dda: 609a str r2, [r3, #8]
8003ddc: 60da str r2, [r3, #12]
8003dde: 611a str r2, [r3, #16]
if(hadc->Instance==ADC1)
8003de0: 687b ldr r3, [r7, #4]
8003de2: 681b ldr r3, [r3, #0]
8003de4: 4a2a ldr r2, [pc, #168] ; (8003e90 <HAL_ADC_MspInit+0xc8>)
8003de6: 4293 cmp r3, r2
8003de8: d124 bne.n 8003e34 <HAL_ADC_MspInit+0x6c>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
8003dea: 4b2a ldr r3, [pc, #168] ; (8003e94 <HAL_ADC_MspInit+0xcc>)
8003dec: 6c5b ldr r3, [r3, #68] ; 0x44
8003dee: 4a29 ldr r2, [pc, #164] ; (8003e94 <HAL_ADC_MspInit+0xcc>)
8003df0: f443 7380 orr.w r3, r3, #256 ; 0x100
8003df4: 6453 str r3, [r2, #68] ; 0x44
8003df6: 4b27 ldr r3, [pc, #156] ; (8003e94 <HAL_ADC_MspInit+0xcc>)
8003df8: 6c5b ldr r3, [r3, #68] ; 0x44
8003dfa: f403 7380 and.w r3, r3, #256 ; 0x100
8003dfe: 61bb str r3, [r7, #24]
8003e00: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOA_CLK_ENABLE();
8003e02: 4b24 ldr r3, [pc, #144] ; (8003e94 <HAL_ADC_MspInit+0xcc>)
8003e04: 6b1b ldr r3, [r3, #48] ; 0x30
8003e06: 4a23 ldr r2, [pc, #140] ; (8003e94 <HAL_ADC_MspInit+0xcc>)
8003e08: f043 0301 orr.w r3, r3, #1
8003e0c: 6313 str r3, [r2, #48] ; 0x30
8003e0e: 4b21 ldr r3, [pc, #132] ; (8003e94 <HAL_ADC_MspInit+0xcc>)
8003e10: 6b1b ldr r3, [r3, #48] ; 0x30
8003e12: f003 0301 and.w r3, r3, #1
8003e16: 617b str r3, [r7, #20]
8003e18: 697b ldr r3, [r7, #20]
/**ADC1 GPIO Configuration
PA0/WKUP ------> ADC1_IN0
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
8003e1a: 2301 movs r3, #1
8003e1c: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8003e1e: 2303 movs r3, #3
8003e20: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003e22: 2300 movs r3, #0
8003e24: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8003e26: f107 031c add.w r3, r7, #28
8003e2a: 4619 mov r1, r3
8003e2c: 481a ldr r0, [pc, #104] ; (8003e98 <HAL_ADC_MspInit+0xd0>)
8003e2e: f003 f967 bl 8007100 <HAL_GPIO_Init>
/* USER CODE BEGIN ADC3_MspInit 1 */
/* USER CODE END ADC3_MspInit 1 */
}
}
8003e32: e029 b.n 8003e88 <HAL_ADC_MspInit+0xc0>
else if(hadc->Instance==ADC3)
8003e34: 687b ldr r3, [r7, #4]
8003e36: 681b ldr r3, [r3, #0]
8003e38: 4a18 ldr r2, [pc, #96] ; (8003e9c <HAL_ADC_MspInit+0xd4>)
8003e3a: 4293 cmp r3, r2
8003e3c: d124 bne.n 8003e88 <HAL_ADC_MspInit+0xc0>
__HAL_RCC_ADC3_CLK_ENABLE();
8003e3e: 4b15 ldr r3, [pc, #84] ; (8003e94 <HAL_ADC_MspInit+0xcc>)
8003e40: 6c5b ldr r3, [r3, #68] ; 0x44
8003e42: 4a14 ldr r2, [pc, #80] ; (8003e94 <HAL_ADC_MspInit+0xcc>)
8003e44: f443 6380 orr.w r3, r3, #1024 ; 0x400
8003e48: 6453 str r3, [r2, #68] ; 0x44
8003e4a: 4b12 ldr r3, [pc, #72] ; (8003e94 <HAL_ADC_MspInit+0xcc>)
8003e4c: 6c5b ldr r3, [r3, #68] ; 0x44
8003e4e: f403 6380 and.w r3, r3, #1024 ; 0x400
8003e52: 613b str r3, [r7, #16]
8003e54: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOF_CLK_ENABLE();
8003e56: 4b0f ldr r3, [pc, #60] ; (8003e94 <HAL_ADC_MspInit+0xcc>)
8003e58: 6b1b ldr r3, [r3, #48] ; 0x30
8003e5a: 4a0e ldr r2, [pc, #56] ; (8003e94 <HAL_ADC_MspInit+0xcc>)
8003e5c: f043 0320 orr.w r3, r3, #32
8003e60: 6313 str r3, [r2, #48] ; 0x30
8003e62: 4b0c ldr r3, [pc, #48] ; (8003e94 <HAL_ADC_MspInit+0xcc>)
8003e64: 6b1b ldr r3, [r3, #48] ; 0x30
8003e66: f003 0320 and.w r3, r3, #32
8003e6a: 60fb str r3, [r7, #12]
8003e6c: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8;
8003e6e: f44f 63e0 mov.w r3, #1792 ; 0x700
8003e72: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8003e74: 2303 movs r3, #3
8003e76: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003e78: 2300 movs r3, #0
8003e7a: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8003e7c: f107 031c add.w r3, r7, #28
8003e80: 4619 mov r1, r3
8003e82: 4807 ldr r0, [pc, #28] ; (8003ea0 <HAL_ADC_MspInit+0xd8>)
8003e84: f003 f93c bl 8007100 <HAL_GPIO_Init>
}
8003e88: bf00 nop
8003e8a: 3730 adds r7, #48 ; 0x30
8003e8c: 46bd mov sp, r7
8003e8e: bd80 pop {r7, pc}
8003e90: 40012000 .word 0x40012000
8003e94: 40023800 .word 0x40023800
8003e98: 40020000 .word 0x40020000
8003e9c: 40012200 .word 0x40012200
8003ea0: 40021400 .word 0x40021400
08003ea4 <HAL_CRC_MspInit>:
* This function configures the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
{
8003ea4: b480 push {r7}
8003ea6: b085 sub sp, #20
8003ea8: af00 add r7, sp, #0
8003eaa: 6078 str r0, [r7, #4]
if(hcrc->Instance==CRC)
8003eac: 687b ldr r3, [r7, #4]
8003eae: 681b ldr r3, [r3, #0]
8003eb0: 4a0a ldr r2, [pc, #40] ; (8003edc <HAL_CRC_MspInit+0x38>)
8003eb2: 4293 cmp r3, r2
8003eb4: d10b bne.n 8003ece <HAL_CRC_MspInit+0x2a>
{
/* USER CODE BEGIN CRC_MspInit 0 */
/* USER CODE END CRC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CRC_CLK_ENABLE();
8003eb6: 4b0a ldr r3, [pc, #40] ; (8003ee0 <HAL_CRC_MspInit+0x3c>)
8003eb8: 6b1b ldr r3, [r3, #48] ; 0x30
8003eba: 4a09 ldr r2, [pc, #36] ; (8003ee0 <HAL_CRC_MspInit+0x3c>)
8003ebc: f443 5380 orr.w r3, r3, #4096 ; 0x1000
8003ec0: 6313 str r3, [r2, #48] ; 0x30
8003ec2: 4b07 ldr r3, [pc, #28] ; (8003ee0 <HAL_CRC_MspInit+0x3c>)
8003ec4: 6b1b ldr r3, [r3, #48] ; 0x30
8003ec6: f403 5380 and.w r3, r3, #4096 ; 0x1000
8003eca: 60fb str r3, [r7, #12]
8003ecc: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN CRC_MspInit 1 */
/* USER CODE END CRC_MspInit 1 */
}
}
8003ece: bf00 nop
8003ed0: 3714 adds r7, #20
8003ed2: 46bd mov sp, r7
8003ed4: f85d 7b04 ldr.w r7, [sp], #4
8003ed8: 4770 bx lr
8003eda: bf00 nop
8003edc: 40023000 .word 0x40023000
8003ee0: 40023800 .word 0x40023800
08003ee4 <HAL_DAC_MspInit>:
* This function configures the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
8003ee4: b580 push {r7, lr}
8003ee6: b08a sub sp, #40 ; 0x28
8003ee8: af00 add r7, sp, #0
8003eea: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8003eec: f107 0314 add.w r3, r7, #20
8003ef0: 2200 movs r2, #0
8003ef2: 601a str r2, [r3, #0]
8003ef4: 605a str r2, [r3, #4]
8003ef6: 609a str r2, [r3, #8]
8003ef8: 60da str r2, [r3, #12]
8003efa: 611a str r2, [r3, #16]
if(hdac->Instance==DAC)
8003efc: 687b ldr r3, [r7, #4]
8003efe: 681b ldr r3, [r3, #0]
8003f00: 4a19 ldr r2, [pc, #100] ; (8003f68 <HAL_DAC_MspInit+0x84>)
8003f02: 4293 cmp r3, r2
8003f04: d12b bne.n 8003f5e <HAL_DAC_MspInit+0x7a>
{
/* USER CODE BEGIN DAC_MspInit 0 */
/* USER CODE END DAC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DAC_CLK_ENABLE();
8003f06: 4b19 ldr r3, [pc, #100] ; (8003f6c <HAL_DAC_MspInit+0x88>)
8003f08: 6c1b ldr r3, [r3, #64] ; 0x40
8003f0a: 4a18 ldr r2, [pc, #96] ; (8003f6c <HAL_DAC_MspInit+0x88>)
8003f0c: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
8003f10: 6413 str r3, [r2, #64] ; 0x40
8003f12: 4b16 ldr r3, [pc, #88] ; (8003f6c <HAL_DAC_MspInit+0x88>)
8003f14: 6c1b ldr r3, [r3, #64] ; 0x40
8003f16: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
8003f1a: 613b str r3, [r7, #16]
8003f1c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8003f1e: 4b13 ldr r3, [pc, #76] ; (8003f6c <HAL_DAC_MspInit+0x88>)
8003f20: 6b1b ldr r3, [r3, #48] ; 0x30
8003f22: 4a12 ldr r2, [pc, #72] ; (8003f6c <HAL_DAC_MspInit+0x88>)
8003f24: f043 0301 orr.w r3, r3, #1
8003f28: 6313 str r3, [r2, #48] ; 0x30
8003f2a: 4b10 ldr r3, [pc, #64] ; (8003f6c <HAL_DAC_MspInit+0x88>)
8003f2c: 6b1b ldr r3, [r3, #48] ; 0x30
8003f2e: f003 0301 and.w r3, r3, #1
8003f32: 60fb str r3, [r7, #12]
8003f34: 68fb ldr r3, [r7, #12]
/**DAC GPIO Configuration
PA4 ------> DAC_OUT1
*/
GPIO_InitStruct.Pin = GPIO_PIN_4;
8003f36: 2310 movs r3, #16
8003f38: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8003f3a: 2303 movs r3, #3
8003f3c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003f3e: 2300 movs r3, #0
8003f40: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8003f42: f107 0314 add.w r3, r7, #20
8003f46: 4619 mov r1, r3
8003f48: 4809 ldr r0, [pc, #36] ; (8003f70 <HAL_DAC_MspInit+0x8c>)
8003f4a: f003 f8d9 bl 8007100 <HAL_GPIO_Init>
/* DAC interrupt Init */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
8003f4e: 2200 movs r2, #0
8003f50: 2100 movs r1, #0
8003f52: 2036 movs r0, #54 ; 0x36
8003f54: f001 f912 bl 800517c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
8003f58: 2036 movs r0, #54 ; 0x36
8003f5a: f001 f92b bl 80051b4 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN DAC_MspInit 1 */
/* USER CODE END DAC_MspInit 1 */
}
}
8003f5e: bf00 nop
8003f60: 3728 adds r7, #40 ; 0x28
8003f62: 46bd mov sp, r7
8003f64: bd80 pop {r7, pc}
8003f66: bf00 nop
8003f68: 40007400 .word 0x40007400
8003f6c: 40023800 .word 0x40023800
8003f70: 40020000 .word 0x40020000
08003f74 <HAL_DMA2D_MspInit>:
* This function configures the hardware resources used in this example
* @param hdma2d: DMA2D handle pointer
* @retval None
*/
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
{
8003f74: b480 push {r7}
8003f76: b085 sub sp, #20
8003f78: af00 add r7, sp, #0
8003f7a: 6078 str r0, [r7, #4]
if(hdma2d->Instance==DMA2D)
8003f7c: 687b ldr r3, [r7, #4]
8003f7e: 681b ldr r3, [r3, #0]
8003f80: 4a0a ldr r2, [pc, #40] ; (8003fac <HAL_DMA2D_MspInit+0x38>)
8003f82: 4293 cmp r3, r2
8003f84: d10b bne.n 8003f9e <HAL_DMA2D_MspInit+0x2a>
{
/* USER CODE BEGIN DMA2D_MspInit 0 */
/* USER CODE END DMA2D_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DMA2D_CLK_ENABLE();
8003f86: 4b0a ldr r3, [pc, #40] ; (8003fb0 <HAL_DMA2D_MspInit+0x3c>)
8003f88: 6b1b ldr r3, [r3, #48] ; 0x30
8003f8a: 4a09 ldr r2, [pc, #36] ; (8003fb0 <HAL_DMA2D_MspInit+0x3c>)
8003f8c: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8003f90: 6313 str r3, [r2, #48] ; 0x30
8003f92: 4b07 ldr r3, [pc, #28] ; (8003fb0 <HAL_DMA2D_MspInit+0x3c>)
8003f94: 6b1b ldr r3, [r3, #48] ; 0x30
8003f96: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8003f9a: 60fb str r3, [r7, #12]
8003f9c: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN DMA2D_MspInit 1 */
/* USER CODE END DMA2D_MspInit 1 */
}
}
8003f9e: bf00 nop
8003fa0: 3714 adds r7, #20
8003fa2: 46bd mov sp, r7
8003fa4: f85d 7b04 ldr.w r7, [sp], #4
8003fa8: 4770 bx lr
8003faa: bf00 nop
8003fac: 4002b000 .word 0x4002b000
8003fb0: 40023800 .word 0x40023800
08003fb4 <HAL_LTDC_MspInit>:
* This function configures the hardware resources used in this example
* @param hltdc: LTDC handle pointer
* @retval None
*/
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
{
8003fb4: b580 push {r7, lr}
8003fb6: b08e sub sp, #56 ; 0x38
8003fb8: af00 add r7, sp, #0
8003fba: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8003fbc: f107 0324 add.w r3, r7, #36 ; 0x24
8003fc0: 2200 movs r2, #0
8003fc2: 601a str r2, [r3, #0]
8003fc4: 605a str r2, [r3, #4]
8003fc6: 609a str r2, [r3, #8]
8003fc8: 60da str r2, [r3, #12]
8003fca: 611a str r2, [r3, #16]
if(hltdc->Instance==LTDC)
8003fcc: 687b ldr r3, [r7, #4]
8003fce: 681b ldr r3, [r3, #0]
8003fd0: 4a55 ldr r2, [pc, #340] ; (8004128 <HAL_LTDC_MspInit+0x174>)
8003fd2: 4293 cmp r3, r2
8003fd4: f040 80a3 bne.w 800411e <HAL_LTDC_MspInit+0x16a>
{
/* USER CODE BEGIN LTDC_MspInit 0 */
/* USER CODE END LTDC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_LTDC_CLK_ENABLE();
8003fd8: 4b54 ldr r3, [pc, #336] ; (800412c <HAL_LTDC_MspInit+0x178>)
8003fda: 6c5b ldr r3, [r3, #68] ; 0x44
8003fdc: 4a53 ldr r2, [pc, #332] ; (800412c <HAL_LTDC_MspInit+0x178>)
8003fde: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
8003fe2: 6453 str r3, [r2, #68] ; 0x44
8003fe4: 4b51 ldr r3, [pc, #324] ; (800412c <HAL_LTDC_MspInit+0x178>)
8003fe6: 6c5b ldr r3, [r3, #68] ; 0x44
8003fe8: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8003fec: 623b str r3, [r7, #32]
8003fee: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOE_CLK_ENABLE();
8003ff0: 4b4e ldr r3, [pc, #312] ; (800412c <HAL_LTDC_MspInit+0x178>)
8003ff2: 6b1b ldr r3, [r3, #48] ; 0x30
8003ff4: 4a4d ldr r2, [pc, #308] ; (800412c <HAL_LTDC_MspInit+0x178>)
8003ff6: f043 0310 orr.w r3, r3, #16
8003ffa: 6313 str r3, [r2, #48] ; 0x30
8003ffc: 4b4b ldr r3, [pc, #300] ; (800412c <HAL_LTDC_MspInit+0x178>)
8003ffe: 6b1b ldr r3, [r3, #48] ; 0x30
8004000: f003 0310 and.w r3, r3, #16
8004004: 61fb str r3, [r7, #28]
8004006: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOJ_CLK_ENABLE();
8004008: 4b48 ldr r3, [pc, #288] ; (800412c <HAL_LTDC_MspInit+0x178>)
800400a: 6b1b ldr r3, [r3, #48] ; 0x30
800400c: 4a47 ldr r2, [pc, #284] ; (800412c <HAL_LTDC_MspInit+0x178>)
800400e: f443 7300 orr.w r3, r3, #512 ; 0x200
8004012: 6313 str r3, [r2, #48] ; 0x30
8004014: 4b45 ldr r3, [pc, #276] ; (800412c <HAL_LTDC_MspInit+0x178>)
8004016: 6b1b ldr r3, [r3, #48] ; 0x30
8004018: f403 7300 and.w r3, r3, #512 ; 0x200
800401c: 61bb str r3, [r7, #24]
800401e: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOK_CLK_ENABLE();
8004020: 4b42 ldr r3, [pc, #264] ; (800412c <HAL_LTDC_MspInit+0x178>)
8004022: 6b1b ldr r3, [r3, #48] ; 0x30
8004024: 4a41 ldr r2, [pc, #260] ; (800412c <HAL_LTDC_MspInit+0x178>)
8004026: f443 6380 orr.w r3, r3, #1024 ; 0x400
800402a: 6313 str r3, [r2, #48] ; 0x30
800402c: 4b3f ldr r3, [pc, #252] ; (800412c <HAL_LTDC_MspInit+0x178>)
800402e: 6b1b ldr r3, [r3, #48] ; 0x30
8004030: f403 6380 and.w r3, r3, #1024 ; 0x400
8004034: 617b str r3, [r7, #20]
8004036: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOG_CLK_ENABLE();
8004038: 4b3c ldr r3, [pc, #240] ; (800412c <HAL_LTDC_MspInit+0x178>)
800403a: 6b1b ldr r3, [r3, #48] ; 0x30
800403c: 4a3b ldr r2, [pc, #236] ; (800412c <HAL_LTDC_MspInit+0x178>)
800403e: f043 0340 orr.w r3, r3, #64 ; 0x40
8004042: 6313 str r3, [r2, #48] ; 0x30
8004044: 4b39 ldr r3, [pc, #228] ; (800412c <HAL_LTDC_MspInit+0x178>)
8004046: 6b1b ldr r3, [r3, #48] ; 0x30
8004048: f003 0340 and.w r3, r3, #64 ; 0x40
800404c: 613b str r3, [r7, #16]
800404e: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOI_CLK_ENABLE();
8004050: 4b36 ldr r3, [pc, #216] ; (800412c <HAL_LTDC_MspInit+0x178>)
8004052: 6b1b ldr r3, [r3, #48] ; 0x30
8004054: 4a35 ldr r2, [pc, #212] ; (800412c <HAL_LTDC_MspInit+0x178>)
8004056: f443 7380 orr.w r3, r3, #256 ; 0x100
800405a: 6313 str r3, [r2, #48] ; 0x30
800405c: 4b33 ldr r3, [pc, #204] ; (800412c <HAL_LTDC_MspInit+0x178>)
800405e: 6b1b ldr r3, [r3, #48] ; 0x30
8004060: f403 7380 and.w r3, r3, #256 ; 0x100
8004064: 60fb str r3, [r7, #12]
8004066: 68fb ldr r3, [r7, #12]
PJ3 ------> LTDC_R4
PJ2 ------> LTDC_R3
PJ0 ------> LTDC_R1
PJ1 ------> LTDC_R2
*/
GPIO_InitStruct.Pin = LCD_B0_Pin;
8004068: 2310 movs r3, #16
800406a: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800406c: 2302 movs r3, #2
800406e: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004070: 2300 movs r3, #0
8004072: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8004074: 2300 movs r3, #0
8004076: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8004078: 230e movs r3, #14
800407a: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(LCD_B0_GPIO_Port, &GPIO_InitStruct);
800407c: f107 0324 add.w r3, r7, #36 ; 0x24
8004080: 4619 mov r1, r3
8004082: 482b ldr r0, [pc, #172] ; (8004130 <HAL_LTDC_MspInit+0x17c>)
8004084: f003 f83c bl 8007100 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_B1_Pin|LCD_B2_Pin|LCD_B3_Pin|LCD_G4_Pin
8004088: f64e 73ff movw r3, #61439 ; 0xefff
800408c: 627b str r3, [r7, #36] ; 0x24
|LCD_G1_Pin|LCD_G3_Pin|LCD_G0_Pin|LCD_G2_Pin
|LCD_R7_Pin|LCD_R5_Pin|LCD_R6_Pin|LCD_R4_Pin
|LCD_R3_Pin|LCD_R1_Pin|LCD_R2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800408e: 2302 movs r3, #2
8004090: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004092: 2300 movs r3, #0
8004094: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8004096: 2300 movs r3, #0
8004098: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
800409a: 230e movs r3, #14
800409c: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct);
800409e: f107 0324 add.w r3, r7, #36 ; 0x24
80040a2: 4619 mov r1, r3
80040a4: 4823 ldr r0, [pc, #140] ; (8004134 <HAL_LTDC_MspInit+0x180>)
80040a6: f003 f82b bl 8007100 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_DE_Pin|LCD_B7_Pin|LCD_B6_Pin|LCD_B5_Pin
80040aa: 23f7 movs r3, #247 ; 0xf7
80040ac: 627b str r3, [r7, #36] ; 0x24
|LCD_G6_Pin|LCD_G7_Pin|LCD_G5_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80040ae: 2302 movs r3, #2
80040b0: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80040b2: 2300 movs r3, #0
80040b4: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80040b6: 2300 movs r3, #0
80040b8: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80040ba: 230e movs r3, #14
80040bc: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);
80040be: f107 0324 add.w r3, r7, #36 ; 0x24
80040c2: 4619 mov r1, r3
80040c4: 481c ldr r0, [pc, #112] ; (8004138 <HAL_LTDC_MspInit+0x184>)
80040c6: f003 f81b bl 8007100 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_B4_Pin;
80040ca: f44f 5380 mov.w r3, #4096 ; 0x1000
80040ce: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80040d0: 2302 movs r3, #2
80040d2: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80040d4: 2300 movs r3, #0
80040d6: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80040d8: 2300 movs r3, #0
80040da: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
80040dc: 2309 movs r3, #9
80040de: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(LCD_B4_GPIO_Port, &GPIO_InitStruct);
80040e0: f107 0324 add.w r3, r7, #36 ; 0x24
80040e4: 4619 mov r1, r3
80040e6: 4815 ldr r0, [pc, #84] ; (800413c <HAL_LTDC_MspInit+0x188>)
80040e8: f003 f80a bl 8007100 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_HSYNC_Pin|LCD_VSYNC_Pin|LCD_R0_Pin|LCD_CLK_Pin;
80040ec: f44f 4346 mov.w r3, #50688 ; 0xc600
80040f0: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80040f2: 2302 movs r3, #2
80040f4: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80040f6: 2300 movs r3, #0
80040f8: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80040fa: 2300 movs r3, #0
80040fc: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80040fe: 230e movs r3, #14
8004100: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8004102: f107 0324 add.w r3, r7, #36 ; 0x24
8004106: 4619 mov r1, r3
8004108: 480d ldr r0, [pc, #52] ; (8004140 <HAL_LTDC_MspInit+0x18c>)
800410a: f002 fff9 bl 8007100 <HAL_GPIO_Init>
/* LTDC interrupt Init */
HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0);
800410e: 2200 movs r2, #0
8004110: 2105 movs r1, #5
8004112: 2058 movs r0, #88 ; 0x58
8004114: f001 f832 bl 800517c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(LTDC_IRQn);
8004118: 2058 movs r0, #88 ; 0x58
800411a: f001 f84b bl 80051b4 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN LTDC_MspInit 1 */
/* USER CODE END LTDC_MspInit 1 */
}
}
800411e: bf00 nop
8004120: 3738 adds r7, #56 ; 0x38
8004122: 46bd mov sp, r7
8004124: bd80 pop {r7, pc}
8004126: bf00 nop
8004128: 40016800 .word 0x40016800
800412c: 40023800 .word 0x40023800
8004130: 40021000 .word 0x40021000
8004134: 40022400 .word 0x40022400
8004138: 40022800 .word 0x40022800
800413c: 40021800 .word 0x40021800
8004140: 40022000 .word 0x40022000
08004144 <HAL_RNG_MspInit>:
* This function configures the hardware resources used in this example
* @param hrng: RNG handle pointer
* @retval None
*/
void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng)
{
8004144: b480 push {r7}
8004146: b085 sub sp, #20
8004148: af00 add r7, sp, #0
800414a: 6078 str r0, [r7, #4]
if(hrng->Instance==RNG)
800414c: 687b ldr r3, [r7, #4]
800414e: 681b ldr r3, [r3, #0]
8004150: 4a0a ldr r2, [pc, #40] ; (800417c <HAL_RNG_MspInit+0x38>)
8004152: 4293 cmp r3, r2
8004154: d10b bne.n 800416e <HAL_RNG_MspInit+0x2a>
{
/* USER CODE BEGIN RNG_MspInit 0 */
/* USER CODE END RNG_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_RNG_CLK_ENABLE();
8004156: 4b0a ldr r3, [pc, #40] ; (8004180 <HAL_RNG_MspInit+0x3c>)
8004158: 6b5b ldr r3, [r3, #52] ; 0x34
800415a: 4a09 ldr r2, [pc, #36] ; (8004180 <HAL_RNG_MspInit+0x3c>)
800415c: f043 0340 orr.w r3, r3, #64 ; 0x40
8004160: 6353 str r3, [r2, #52] ; 0x34
8004162: 4b07 ldr r3, [pc, #28] ; (8004180 <HAL_RNG_MspInit+0x3c>)
8004164: 6b5b ldr r3, [r3, #52] ; 0x34
8004166: f003 0340 and.w r3, r3, #64 ; 0x40
800416a: 60fb str r3, [r7, #12]
800416c: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN RNG_MspInit 1 */
/* USER CODE END RNG_MspInit 1 */
}
}
800416e: bf00 nop
8004170: 3714 adds r7, #20
8004172: 46bd mov sp, r7
8004174: f85d 7b04 ldr.w r7, [sp], #4
8004178: 4770 bx lr
800417a: bf00 nop
800417c: 50060800 .word 0x50060800
8004180: 40023800 .word 0x40023800
08004184 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8004184: b480 push {r7}
8004186: b089 sub sp, #36 ; 0x24
8004188: af00 add r7, sp, #0
800418a: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
800418c: 687b ldr r3, [r7, #4]
800418e: 681b ldr r3, [r3, #0]
8004190: 4a2e ldr r2, [pc, #184] ; (800424c <HAL_TIM_Base_MspInit+0xc8>)
8004192: 4293 cmp r3, r2
8004194: d10c bne.n 80041b0 <HAL_TIM_Base_MspInit+0x2c>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
8004196: 4b2e ldr r3, [pc, #184] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
8004198: 6c5b ldr r3, [r3, #68] ; 0x44
800419a: 4a2d ldr r2, [pc, #180] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
800419c: f043 0301 orr.w r3, r3, #1
80041a0: 6453 str r3, [r2, #68] ; 0x44
80041a2: 4b2b ldr r3, [pc, #172] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
80041a4: 6c5b ldr r3, [r3, #68] ; 0x44
80041a6: f003 0301 and.w r3, r3, #1
80041aa: 61fb str r3, [r7, #28]
80041ac: 69fb ldr r3, [r7, #28]
/* USER CODE BEGIN TIM8_MspInit 1 */
/* USER CODE END TIM8_MspInit 1 */
}
}
80041ae: e046 b.n 800423e <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM2)
80041b0: 687b ldr r3, [r7, #4]
80041b2: 681b ldr r3, [r3, #0]
80041b4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80041b8: d10c bne.n 80041d4 <HAL_TIM_Base_MspInit+0x50>
__HAL_RCC_TIM2_CLK_ENABLE();
80041ba: 4b25 ldr r3, [pc, #148] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
80041bc: 6c1b ldr r3, [r3, #64] ; 0x40
80041be: 4a24 ldr r2, [pc, #144] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
80041c0: f043 0301 orr.w r3, r3, #1
80041c4: 6413 str r3, [r2, #64] ; 0x40
80041c6: 4b22 ldr r3, [pc, #136] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
80041c8: 6c1b ldr r3, [r3, #64] ; 0x40
80041ca: f003 0301 and.w r3, r3, #1
80041ce: 61bb str r3, [r7, #24]
80041d0: 69bb ldr r3, [r7, #24]
}
80041d2: e034 b.n 800423e <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM3)
80041d4: 687b ldr r3, [r7, #4]
80041d6: 681b ldr r3, [r3, #0]
80041d8: 4a1e ldr r2, [pc, #120] ; (8004254 <HAL_TIM_Base_MspInit+0xd0>)
80041da: 4293 cmp r3, r2
80041dc: d10c bne.n 80041f8 <HAL_TIM_Base_MspInit+0x74>
__HAL_RCC_TIM3_CLK_ENABLE();
80041de: 4b1c ldr r3, [pc, #112] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
80041e0: 6c1b ldr r3, [r3, #64] ; 0x40
80041e2: 4a1b ldr r2, [pc, #108] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
80041e4: f043 0302 orr.w r3, r3, #2
80041e8: 6413 str r3, [r2, #64] ; 0x40
80041ea: 4b19 ldr r3, [pc, #100] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
80041ec: 6c1b ldr r3, [r3, #64] ; 0x40
80041ee: f003 0302 and.w r3, r3, #2
80041f2: 617b str r3, [r7, #20]
80041f4: 697b ldr r3, [r7, #20]
}
80041f6: e022 b.n 800423e <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM5)
80041f8: 687b ldr r3, [r7, #4]
80041fa: 681b ldr r3, [r3, #0]
80041fc: 4a16 ldr r2, [pc, #88] ; (8004258 <HAL_TIM_Base_MspInit+0xd4>)
80041fe: 4293 cmp r3, r2
8004200: d10c bne.n 800421c <HAL_TIM_Base_MspInit+0x98>
__HAL_RCC_TIM5_CLK_ENABLE();
8004202: 4b13 ldr r3, [pc, #76] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
8004204: 6c1b ldr r3, [r3, #64] ; 0x40
8004206: 4a12 ldr r2, [pc, #72] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
8004208: f043 0308 orr.w r3, r3, #8
800420c: 6413 str r3, [r2, #64] ; 0x40
800420e: 4b10 ldr r3, [pc, #64] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
8004210: 6c1b ldr r3, [r3, #64] ; 0x40
8004212: f003 0308 and.w r3, r3, #8
8004216: 613b str r3, [r7, #16]
8004218: 693b ldr r3, [r7, #16]
}
800421a: e010 b.n 800423e <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM8)
800421c: 687b ldr r3, [r7, #4]
800421e: 681b ldr r3, [r3, #0]
8004220: 4a0e ldr r2, [pc, #56] ; (800425c <HAL_TIM_Base_MspInit+0xd8>)
8004222: 4293 cmp r3, r2
8004224: d10b bne.n 800423e <HAL_TIM_Base_MspInit+0xba>
__HAL_RCC_TIM8_CLK_ENABLE();
8004226: 4b0a ldr r3, [pc, #40] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
8004228: 6c5b ldr r3, [r3, #68] ; 0x44
800422a: 4a09 ldr r2, [pc, #36] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
800422c: f043 0302 orr.w r3, r3, #2
8004230: 6453 str r3, [r2, #68] ; 0x44
8004232: 4b07 ldr r3, [pc, #28] ; (8004250 <HAL_TIM_Base_MspInit+0xcc>)
8004234: 6c5b ldr r3, [r3, #68] ; 0x44
8004236: f003 0302 and.w r3, r3, #2
800423a: 60fb str r3, [r7, #12]
800423c: 68fb ldr r3, [r7, #12]
}
800423e: bf00 nop
8004240: 3724 adds r7, #36 ; 0x24
8004242: 46bd mov sp, r7
8004244: f85d 7b04 ldr.w r7, [sp], #4
8004248: 4770 bx lr
800424a: bf00 nop
800424c: 40010000 .word 0x40010000
8004250: 40023800 .word 0x40023800
8004254: 40000400 .word 0x40000400
8004258: 40000c00 .word 0x40000c00
800425c: 40010400 .word 0x40010400
08004260 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8004260: b580 push {r7, lr}
8004262: b08a sub sp, #40 ; 0x28
8004264: af00 add r7, sp, #0
8004266: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8004268: f107 0314 add.w r3, r7, #20
800426c: 2200 movs r2, #0
800426e: 601a str r2, [r3, #0]
8004270: 605a str r2, [r3, #4]
8004272: 609a str r2, [r3, #8]
8004274: 60da str r2, [r3, #12]
8004276: 611a str r2, [r3, #16]
if(htim->Instance==TIM3)
8004278: 687b ldr r3, [r7, #4]
800427a: 681b ldr r3, [r3, #0]
800427c: 4a22 ldr r2, [pc, #136] ; (8004308 <HAL_TIM_MspPostInit+0xa8>)
800427e: 4293 cmp r3, r2
8004280: d11c bne.n 80042bc <HAL_TIM_MspPostInit+0x5c>
{
/* USER CODE BEGIN TIM3_MspPostInit 0 */
/* USER CODE END TIM3_MspPostInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
8004282: 4b22 ldr r3, [pc, #136] ; (800430c <HAL_TIM_MspPostInit+0xac>)
8004284: 6b1b ldr r3, [r3, #48] ; 0x30
8004286: 4a21 ldr r2, [pc, #132] ; (800430c <HAL_TIM_MspPostInit+0xac>)
8004288: f043 0302 orr.w r3, r3, #2
800428c: 6313 str r3, [r2, #48] ; 0x30
800428e: 4b1f ldr r3, [pc, #124] ; (800430c <HAL_TIM_MspPostInit+0xac>)
8004290: 6b1b ldr r3, [r3, #48] ; 0x30
8004292: f003 0302 and.w r3, r3, #2
8004296: 613b str r3, [r7, #16]
8004298: 693b ldr r3, [r7, #16]
/**TIM3 GPIO Configuration
PB4 ------> TIM3_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_4;
800429a: 2310 movs r3, #16
800429c: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800429e: 2302 movs r3, #2
80042a0: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80042a2: 2300 movs r3, #0
80042a4: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80042a6: 2300 movs r3, #0
80042a8: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
80042aa: 2302 movs r3, #2
80042ac: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80042ae: f107 0314 add.w r3, r7, #20
80042b2: 4619 mov r1, r3
80042b4: 4816 ldr r0, [pc, #88] ; (8004310 <HAL_TIM_MspPostInit+0xb0>)
80042b6: f002 ff23 bl 8007100 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM8_MspPostInit 1 */
/* USER CODE END TIM8_MspPostInit 1 */
}
}
80042ba: e020 b.n 80042fe <HAL_TIM_MspPostInit+0x9e>
else if(htim->Instance==TIM8)
80042bc: 687b ldr r3, [r7, #4]
80042be: 681b ldr r3, [r3, #0]
80042c0: 4a14 ldr r2, [pc, #80] ; (8004314 <HAL_TIM_MspPostInit+0xb4>)
80042c2: 4293 cmp r3, r2
80042c4: d11b bne.n 80042fe <HAL_TIM_MspPostInit+0x9e>
__HAL_RCC_GPIOI_CLK_ENABLE();
80042c6: 4b11 ldr r3, [pc, #68] ; (800430c <HAL_TIM_MspPostInit+0xac>)
80042c8: 6b1b ldr r3, [r3, #48] ; 0x30
80042ca: 4a10 ldr r2, [pc, #64] ; (800430c <HAL_TIM_MspPostInit+0xac>)
80042cc: f443 7380 orr.w r3, r3, #256 ; 0x100
80042d0: 6313 str r3, [r2, #48] ; 0x30
80042d2: 4b0e ldr r3, [pc, #56] ; (800430c <HAL_TIM_MspPostInit+0xac>)
80042d4: 6b1b ldr r3, [r3, #48] ; 0x30
80042d6: f403 7380 and.w r3, r3, #256 ; 0x100
80042da: 60fb str r3, [r7, #12]
80042dc: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_2;
80042de: 2304 movs r3, #4
80042e0: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80042e2: 2302 movs r3, #2
80042e4: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80042e6: 2300 movs r3, #0
80042e8: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80042ea: 2300 movs r3, #0
80042ec: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF3_TIM8;
80042ee: 2303 movs r3, #3
80042f0: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
80042f2: f107 0314 add.w r3, r7, #20
80042f6: 4619 mov r1, r3
80042f8: 4807 ldr r0, [pc, #28] ; (8004318 <HAL_TIM_MspPostInit+0xb8>)
80042fa: f002 ff01 bl 8007100 <HAL_GPIO_Init>
}
80042fe: bf00 nop
8004300: 3728 adds r7, #40 ; 0x28
8004302: 46bd mov sp, r7
8004304: bd80 pop {r7, pc}
8004306: bf00 nop
8004308: 40000400 .word 0x40000400
800430c: 40023800 .word 0x40023800
8004310: 40020400 .word 0x40020400
8004314: 40010400 .word 0x40010400
8004318: 40022000 .word 0x40022000
0800431c <HAL_FMC_MspInit>:
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
800431c: b580 push {r7, lr}
800431e: b086 sub sp, #24
8004320: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
8004322: 1d3b adds r3, r7, #4
8004324: 2200 movs r2, #0
8004326: 601a str r2, [r3, #0]
8004328: 605a str r2, [r3, #4]
800432a: 609a str r2, [r3, #8]
800432c: 60da str r2, [r3, #12]
800432e: 611a str r2, [r3, #16]
if (FMC_Initialized) {
8004330: 4b3a ldr r3, [pc, #232] ; (800441c <HAL_FMC_MspInit+0x100>)
8004332: 681b ldr r3, [r3, #0]
8004334: 2b00 cmp r3, #0
8004336: d16d bne.n 8004414 <HAL_FMC_MspInit+0xf8>
return;
}
FMC_Initialized = 1;
8004338: 4b38 ldr r3, [pc, #224] ; (800441c <HAL_FMC_MspInit+0x100>)
800433a: 2201 movs r2, #1
800433c: 601a str r2, [r3, #0]
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE();
800433e: 4b38 ldr r3, [pc, #224] ; (8004420 <HAL_FMC_MspInit+0x104>)
8004340: 6b9b ldr r3, [r3, #56] ; 0x38
8004342: 4a37 ldr r2, [pc, #220] ; (8004420 <HAL_FMC_MspInit+0x104>)
8004344: f043 0301 orr.w r3, r3, #1
8004348: 6393 str r3, [r2, #56] ; 0x38
800434a: 4b35 ldr r3, [pc, #212] ; (8004420 <HAL_FMC_MspInit+0x104>)
800434c: 6b9b ldr r3, [r3, #56] ; 0x38
800434e: f003 0301 and.w r3, r3, #1
8004352: 603b str r3, [r7, #0]
8004354: 683b ldr r3, [r7, #0]
PE10 ------> FMC_D7
PE12 ------> FMC_D9
PE15 ------> FMC_D12
PE13 ------> FMC_D10
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9
8004356: f64f 7383 movw r3, #65411 ; 0xff83
800435a: 607b str r3, [r7, #4]
|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10
|GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800435c: 2302 movs r3, #2
800435e: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004360: 2300 movs r3, #0
8004362: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004364: 2303 movs r3, #3
8004366: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8004368: 230c movs r3, #12
800436a: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
800436c: 1d3b adds r3, r7, #4
800436e: 4619 mov r1, r3
8004370: 482c ldr r0, [pc, #176] ; (8004424 <HAL_FMC_MspInit+0x108>)
8004372: f002 fec5 bl 8007100 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0
8004376: f248 1333 movw r3, #33075 ; 0x8133
800437a: 607b str r3, [r7, #4]
|GPIO_PIN_5|GPIO_PIN_4;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800437c: 2302 movs r3, #2
800437e: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004380: 2300 movs r3, #0
8004382: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004384: 2303 movs r3, #3
8004386: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8004388: 230c movs r3, #12
800438a: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
800438c: 1d3b adds r3, r7, #4
800438e: 4619 mov r1, r3
8004390: 4825 ldr r0, [pc, #148] ; (8004428 <HAL_FMC_MspInit+0x10c>)
8004392: f002 feb5 bl 8007100 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10
8004396: f24c 7303 movw r3, #50947 ; 0xc703
800439a: 607b str r3, [r7, #4]
|GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800439c: 2302 movs r3, #2
800439e: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80043a0: 2300 movs r3, #0
80043a2: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80043a4: 2303 movs r3, #3
80043a6: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80043a8: 230c movs r3, #12
80043aa: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80043ac: 1d3b adds r3, r7, #4
80043ae: 4619 mov r1, r3
80043b0: 481e ldr r0, [pc, #120] ; (800442c <HAL_FMC_MspInit+0x110>)
80043b2: f002 fea5 bl 8007100 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
80043b6: f64f 033f movw r3, #63551 ; 0xf83f
80043ba: 607b str r3, [r7, #4]
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15
|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80043bc: 2302 movs r3, #2
80043be: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80043c0: 2300 movs r3, #0
80043c2: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80043c4: 2303 movs r3, #3
80043c6: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80043c8: 230c movs r3, #12
80043ca: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
80043cc: 1d3b adds r3, r7, #4
80043ce: 4619 mov r1, r3
80043d0: 4817 ldr r0, [pc, #92] ; (8004430 <HAL_FMC_MspInit+0x114>)
80043d2: f002 fe95 bl 8007100 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_3;
80043d6: 2328 movs r3, #40 ; 0x28
80043d8: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80043da: 2302 movs r3, #2
80043dc: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80043de: 2300 movs r3, #0
80043e0: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80043e2: 2303 movs r3, #3
80043e4: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80043e6: 230c movs r3, #12
80043e8: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
80043ea: 1d3b adds r3, r7, #4
80043ec: 4619 mov r1, r3
80043ee: 4811 ldr r0, [pc, #68] ; (8004434 <HAL_FMC_MspInit+0x118>)
80043f0: f002 fe86 bl 8007100 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_3;
80043f4: 2308 movs r3, #8
80043f6: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80043f8: 2302 movs r3, #2
80043fa: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80043fc: 2300 movs r3, #0
80043fe: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004400: 2303 movs r3, #3
8004402: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8004404: 230c movs r3, #12
8004406: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8004408: 1d3b adds r3, r7, #4
800440a: 4619 mov r1, r3
800440c: 480a ldr r0, [pc, #40] ; (8004438 <HAL_FMC_MspInit+0x11c>)
800440e: f002 fe77 bl 8007100 <HAL_GPIO_Init>
8004412: e000 b.n 8004416 <HAL_FMC_MspInit+0xfa>
return;
8004414: bf00 nop
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
8004416: 3718 adds r7, #24
8004418: 46bd mov sp, r7
800441a: bd80 pop {r7, pc}
800441c: 20000570 .word 0x20000570
8004420: 40023800 .word 0x40023800
8004424: 40021000 .word 0x40021000
8004428: 40021800 .word 0x40021800
800442c: 40020c00 .word 0x40020c00
8004430: 40021400 .word 0x40021400
8004434: 40021c00 .word 0x40021c00
8004438: 40020800 .word 0x40020800
0800443c <HAL_SDRAM_MspInit>:
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
800443c: b580 push {r7, lr}
800443e: b082 sub sp, #8
8004440: af00 add r7, sp, #0
8004442: 6078 str r0, [r7, #4]
/* USER CODE BEGIN SDRAM_MspInit 0 */
/* USER CODE END SDRAM_MspInit 0 */
HAL_FMC_MspInit();
8004444: f7ff ff6a bl 800431c <HAL_FMC_MspInit>
/* USER CODE BEGIN SDRAM_MspInit 1 */
/* USER CODE END SDRAM_MspInit 1 */
}
8004448: bf00 nop
800444a: 3708 adds r7, #8
800444c: 46bd mov sp, r7
800444e: bd80 pop {r7, pc}
08004450 <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8004450: b580 push {r7, lr}
8004452: b08c sub sp, #48 ; 0x30
8004454: af00 add r7, sp, #0
8004456: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0;
8004458: 2300 movs r3, #0
800445a: 62fb str r3, [r7, #44] ; 0x2c
uint32_t uwPrescalerValue = 0;
800445c: 2300 movs r3, #0
800445e: 62bb str r3, [r7, #40] ; 0x28
uint32_t pFLatency;
/*Configure the TIM6 IRQ priority */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0);
8004460: 2200 movs r2, #0
8004462: 6879 ldr r1, [r7, #4]
8004464: 2036 movs r0, #54 ; 0x36
8004466: f000 fe89 bl 800517c <HAL_NVIC_SetPriority>
/* Enable the TIM6 global Interrupt */
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
800446a: 2036 movs r0, #54 ; 0x36
800446c: f000 fea2 bl 80051b4 <HAL_NVIC_EnableIRQ>
/* Enable TIM6 clock */
__HAL_RCC_TIM6_CLK_ENABLE();
8004470: 4b1f ldr r3, [pc, #124] ; (80044f0 <HAL_InitTick+0xa0>)
8004472: 6c1b ldr r3, [r3, #64] ; 0x40
8004474: 4a1e ldr r2, [pc, #120] ; (80044f0 <HAL_InitTick+0xa0>)
8004476: f043 0310 orr.w r3, r3, #16
800447a: 6413 str r3, [r2, #64] ; 0x40
800447c: 4b1c ldr r3, [pc, #112] ; (80044f0 <HAL_InitTick+0xa0>)
800447e: 6c1b ldr r3, [r3, #64] ; 0x40
8004480: f003 0310 and.w r3, r3, #16
8004484: 60fb str r3, [r7, #12]
8004486: 68fb ldr r3, [r7, #12]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
8004488: f107 0210 add.w r2, r7, #16
800448c: f107 0314 add.w r3, r7, #20
8004490: 4611 mov r1, r2
8004492: 4618 mov r0, r3
8004494: f004 fd64 bl 8008f60 <HAL_RCC_GetClockConfig>
/* Compute TIM6 clock */
uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
8004498: f004 fd4e bl 8008f38 <HAL_RCC_GetPCLK1Freq>
800449c: 4603 mov r3, r0
800449e: 005b lsls r3, r3, #1
80044a0: 62fb str r3, [r7, #44] ; 0x2c
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
80044a2: 6afb ldr r3, [r7, #44] ; 0x2c
80044a4: 4a13 ldr r2, [pc, #76] ; (80044f4 <HAL_InitTick+0xa4>)
80044a6: fba2 2303 umull r2, r3, r2, r3
80044aa: 0c9b lsrs r3, r3, #18
80044ac: 3b01 subs r3, #1
80044ae: 62bb str r3, [r7, #40] ; 0x28
/* Initialize TIM6 */
htim6.Instance = TIM6;
80044b0: 4b11 ldr r3, [pc, #68] ; (80044f8 <HAL_InitTick+0xa8>)
80044b2: 4a12 ldr r2, [pc, #72] ; (80044fc <HAL_InitTick+0xac>)
80044b4: 601a str r2, [r3, #0]
+ Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim6.Init.Period = (1000000U / 1000U) - 1U;
80044b6: 4b10 ldr r3, [pc, #64] ; (80044f8 <HAL_InitTick+0xa8>)
80044b8: f240 32e7 movw r2, #999 ; 0x3e7
80044bc: 60da str r2, [r3, #12]
htim6.Init.Prescaler = uwPrescalerValue;
80044be: 4a0e ldr r2, [pc, #56] ; (80044f8 <HAL_InitTick+0xa8>)
80044c0: 6abb ldr r3, [r7, #40] ; 0x28
80044c2: 6053 str r3, [r2, #4]
htim6.Init.ClockDivision = 0;
80044c4: 4b0c ldr r3, [pc, #48] ; (80044f8 <HAL_InitTick+0xa8>)
80044c6: 2200 movs r2, #0
80044c8: 611a str r2, [r3, #16]
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
80044ca: 4b0b ldr r3, [pc, #44] ; (80044f8 <HAL_InitTick+0xa8>)
80044cc: 2200 movs r2, #0
80044ce: 609a str r2, [r3, #8]
if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
80044d0: 4809 ldr r0, [pc, #36] ; (80044f8 <HAL_InitTick+0xa8>)
80044d2: f005 fa5f bl 8009994 <HAL_TIM_Base_Init>
80044d6: 4603 mov r3, r0
80044d8: 2b00 cmp r3, #0
80044da: d104 bne.n 80044e6 <HAL_InitTick+0x96>
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&htim6);
80044dc: 4806 ldr r0, [pc, #24] ; (80044f8 <HAL_InitTick+0xa8>)
80044de: f005 fab1 bl 8009a44 <HAL_TIM_Base_Start_IT>
80044e2: 4603 mov r3, r0
80044e4: e000 b.n 80044e8 <HAL_InitTick+0x98>
}
/* Return function status */
return HAL_ERROR;
80044e6: 2301 movs r3, #1
}
80044e8: 4618 mov r0, r3
80044ea: 3730 adds r7, #48 ; 0x30
80044ec: 46bd mov sp, r7
80044ee: bd80 pop {r7, pc}
80044f0: 40023800 .word 0x40023800
80044f4: 431bde83 .word 0x431bde83
80044f8: 20008f80 .word 0x20008f80
80044fc: 40001000 .word 0x40001000
08004500 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8004500: b480 push {r7}
8004502: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8004504: e7fe b.n 8004504 <NMI_Handler+0x4>
08004506 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8004506: b480 push {r7}
8004508: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800450a: e7fe b.n 800450a <HardFault_Handler+0x4>
0800450c <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
800450c: b480 push {r7}
800450e: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8004510: e7fe b.n 8004510 <MemManage_Handler+0x4>
08004512 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8004512: b480 push {r7}
8004514: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8004516: e7fe b.n 8004516 <BusFault_Handler+0x4>
08004518 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8004518: b480 push {r7}
800451a: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
800451c: e7fe b.n 800451c <UsageFault_Handler+0x4>
0800451e <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
800451e: b480 push {r7}
8004520: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8004522: bf00 nop
8004524: 46bd mov sp, r7
8004526: f85d 7b04 ldr.w r7, [sp], #4
800452a: 4770 bx lr
0800452c <TIM6_DAC_IRQHandler>:
/**
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
*/
void TIM6_DAC_IRQHandler(void)
{
800452c: b580 push {r7, lr}
800452e: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
if (hdac.State != HAL_DAC_STATE_RESET) {
8004530: 4b06 ldr r3, [pc, #24] ; (800454c <TIM6_DAC_IRQHandler+0x20>)
8004532: 791b ldrb r3, [r3, #4]
8004534: b2db uxtb r3, r3
8004536: 2b00 cmp r3, #0
8004538: d002 beq.n 8004540 <TIM6_DAC_IRQHandler+0x14>
HAL_DAC_IRQHandler(&hdac);
800453a: 4804 ldr r0, [pc, #16] ; (800454c <TIM6_DAC_IRQHandler+0x20>)
800453c: f000 ff54 bl 80053e8 <HAL_DAC_IRQHandler>
}
HAL_TIM_IRQHandler(&htim6);
8004540: 4803 ldr r0, [pc, #12] ; (8004550 <TIM6_DAC_IRQHandler+0x24>)
8004542: f005 fb58 bl 8009bf6 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
/* USER CODE END TIM6_DAC_IRQn 1 */
}
8004546: bf00 nop
8004548: bd80 pop {r7, pc}
800454a: bf00 nop
800454c: 20008ac4 .word 0x20008ac4
8004550: 20008f80 .word 0x20008f80
08004554 <ETH_IRQHandler>:
/**
* @brief This function handles Ethernet global interrupt.
*/
void ETH_IRQHandler(void)
{
8004554: b580 push {r7, lr}
8004556: af00 add r7, sp, #0
/* USER CODE BEGIN ETH_IRQn 0 */
/* USER CODE END ETH_IRQn 0 */
HAL_ETH_IRQHandler(&heth);
8004558: 4802 ldr r0, [pc, #8] ; (8004564 <ETH_IRQHandler+0x10>)
800455a: f002 f82f bl 80065bc <HAL_ETH_IRQHandler>
/* USER CODE BEGIN ETH_IRQn 1 */
/* USER CODE END ETH_IRQn 1 */
}
800455e: bf00 nop
8004560: bd80 pop {r7, pc}
8004562: bf00 nop
8004564: 2000a8ec .word 0x2000a8ec
08004568 <LTDC_IRQHandler>:
/**
* @brief This function handles LTDC global interrupt.
*/
void LTDC_IRQHandler(void)
{
8004568: b580 push {r7, lr}
800456a: af00 add r7, sp, #0
/* USER CODE BEGIN LTDC_IRQn 0 */
/* USER CODE END LTDC_IRQn 0 */
HAL_LTDC_IRQHandler(&hltdc);
800456c: 4802 ldr r0, [pc, #8] ; (8004578 <LTDC_IRQHandler+0x10>)
800456e: f003 fd89 bl 8008084 <HAL_LTDC_IRQHandler>
/* USER CODE BEGIN LTDC_IRQn 1 */
/* USER CODE END LTDC_IRQn 1 */
}
8004572: bf00 nop
8004574: bd80 pop {r7, pc}
8004576: bf00 nop
8004578: 20008984 .word 0x20008984
0800457c <_getpid>:
void initialise_monitor_handles()
{
}
int _getpid(void)
{
800457c: b480 push {r7}
800457e: af00 add r7, sp, #0
return 1;
8004580: 2301 movs r3, #1
}
8004582: 4618 mov r0, r3
8004584: 46bd mov sp, r7
8004586: f85d 7b04 ldr.w r7, [sp], #4
800458a: 4770 bx lr
0800458c <_kill>:
int _kill(int pid, int sig)
{
800458c: b480 push {r7}
800458e: b083 sub sp, #12
8004590: af00 add r7, sp, #0
8004592: 6078 str r0, [r7, #4]
8004594: 6039 str r1, [r7, #0]
errno = EINVAL;
8004596: 4b05 ldr r3, [pc, #20] ; (80045ac <_kill+0x20>)
8004598: 2216 movs r2, #22
800459a: 601a str r2, [r3, #0]
return -1;
800459c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
}
80045a0: 4618 mov r0, r3
80045a2: 370c adds r7, #12
80045a4: 46bd mov sp, r7
80045a6: f85d 7b04 ldr.w r7, [sp], #4
80045aa: 4770 bx lr
80045ac: 2000f880 .word 0x2000f880
080045b0 <_exit>:
void _exit (int status)
{
80045b0: b580 push {r7, lr}
80045b2: b082 sub sp, #8
80045b4: af00 add r7, sp, #0
80045b6: 6078 str r0, [r7, #4]
_kill(status, -1);
80045b8: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
80045bc: 6878 ldr r0, [r7, #4]
80045be: f7ff ffe5 bl 800458c <_kill>
while (1) {} /* Make sure we hang here */
80045c2: e7fe b.n 80045c2 <_exit+0x12>
080045c4 <_read>:
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
80045c4: b580 push {r7, lr}
80045c6: b086 sub sp, #24
80045c8: af00 add r7, sp, #0
80045ca: 60f8 str r0, [r7, #12]
80045cc: 60b9 str r1, [r7, #8]
80045ce: 607a str r2, [r7, #4]
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
80045d0: 2300 movs r3, #0
80045d2: 617b str r3, [r7, #20]
80045d4: e00a b.n 80045ec <_read+0x28>
{
*ptr++ = __io_getchar();
80045d6: f3af 8000 nop.w
80045da: 4601 mov r1, r0
80045dc: 68bb ldr r3, [r7, #8]
80045de: 1c5a adds r2, r3, #1
80045e0: 60ba str r2, [r7, #8]
80045e2: b2ca uxtb r2, r1
80045e4: 701a strb r2, [r3, #0]
for (DataIdx = 0; DataIdx < len; DataIdx++)
80045e6: 697b ldr r3, [r7, #20]
80045e8: 3301 adds r3, #1
80045ea: 617b str r3, [r7, #20]
80045ec: 697a ldr r2, [r7, #20]
80045ee: 687b ldr r3, [r7, #4]
80045f0: 429a cmp r2, r3
80045f2: dbf0 blt.n 80045d6 <_read+0x12>
}
return len;
80045f4: 687b ldr r3, [r7, #4]
}
80045f6: 4618 mov r0, r3
80045f8: 3718 adds r7, #24
80045fa: 46bd mov sp, r7
80045fc: bd80 pop {r7, pc}
080045fe <_write>:
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
80045fe: b580 push {r7, lr}
8004600: b086 sub sp, #24
8004602: af00 add r7, sp, #0
8004604: 60f8 str r0, [r7, #12]
8004606: 60b9 str r1, [r7, #8]
8004608: 607a str r2, [r7, #4]
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
800460a: 2300 movs r3, #0
800460c: 617b str r3, [r7, #20]
800460e: e009 b.n 8004624 <_write+0x26>
{
__io_putchar(*ptr++);
8004610: 68bb ldr r3, [r7, #8]
8004612: 1c5a adds r2, r3, #1
8004614: 60ba str r2, [r7, #8]
8004616: 781b ldrb r3, [r3, #0]
8004618: 4618 mov r0, r3
800461a: f3af 8000 nop.w
for (DataIdx = 0; DataIdx < len; DataIdx++)
800461e: 697b ldr r3, [r7, #20]
8004620: 3301 adds r3, #1
8004622: 617b str r3, [r7, #20]
8004624: 697a ldr r2, [r7, #20]
8004626: 687b ldr r3, [r7, #4]
8004628: 429a cmp r2, r3
800462a: dbf1 blt.n 8004610 <_write+0x12>
}
return len;
800462c: 687b ldr r3, [r7, #4]
}
800462e: 4618 mov r0, r3
8004630: 3718 adds r7, #24
8004632: 46bd mov sp, r7
8004634: bd80 pop {r7, pc}
08004636 <_close>:
int _close(int file)
{
8004636: b480 push {r7}
8004638: b083 sub sp, #12
800463a: af00 add r7, sp, #0
800463c: 6078 str r0, [r7, #4]
return -1;
800463e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
}
8004642: 4618 mov r0, r3
8004644: 370c adds r7, #12
8004646: 46bd mov sp, r7
8004648: f85d 7b04 ldr.w r7, [sp], #4
800464c: 4770 bx lr
0800464e <_fstat>:
int _fstat(int file, struct stat *st)
{
800464e: b480 push {r7}
8004650: b083 sub sp, #12
8004652: af00 add r7, sp, #0
8004654: 6078 str r0, [r7, #4]
8004656: 6039 str r1, [r7, #0]
st->st_mode = S_IFCHR;
8004658: 683b ldr r3, [r7, #0]
800465a: f44f 5200 mov.w r2, #8192 ; 0x2000
800465e: 605a str r2, [r3, #4]
return 0;
8004660: 2300 movs r3, #0
}
8004662: 4618 mov r0, r3
8004664: 370c adds r7, #12
8004666: 46bd mov sp, r7
8004668: f85d 7b04 ldr.w r7, [sp], #4
800466c: 4770 bx lr
0800466e <_isatty>:
int _isatty(int file)
{
800466e: b480 push {r7}
8004670: b083 sub sp, #12
8004672: af00 add r7, sp, #0
8004674: 6078 str r0, [r7, #4]
return 1;
8004676: 2301 movs r3, #1
}
8004678: 4618 mov r0, r3
800467a: 370c adds r7, #12
800467c: 46bd mov sp, r7
800467e: f85d 7b04 ldr.w r7, [sp], #4
8004682: 4770 bx lr
08004684 <_lseek>:
int _lseek(int file, int ptr, int dir)
{
8004684: b480 push {r7}
8004686: b085 sub sp, #20
8004688: af00 add r7, sp, #0
800468a: 60f8 str r0, [r7, #12]
800468c: 60b9 str r1, [r7, #8]
800468e: 607a str r2, [r7, #4]
return 0;
8004690: 2300 movs r3, #0
}
8004692: 4618 mov r0, r3
8004694: 3714 adds r7, #20
8004696: 46bd mov sp, r7
8004698: f85d 7b04 ldr.w r7, [sp], #4
800469c: 4770 bx lr
...
080046a0 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
80046a0: b480 push {r7}
80046a2: b087 sub sp, #28
80046a4: af00 add r7, sp, #0
80046a6: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
80046a8: 4a14 ldr r2, [pc, #80] ; (80046fc <_sbrk+0x5c>)
80046aa: 4b15 ldr r3, [pc, #84] ; (8004700 <_sbrk+0x60>)
80046ac: 1ad3 subs r3, r2, r3
80046ae: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
80046b0: 697b ldr r3, [r7, #20]
80046b2: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
80046b4: 4b13 ldr r3, [pc, #76] ; (8004704 <_sbrk+0x64>)
80046b6: 681b ldr r3, [r3, #0]
80046b8: 2b00 cmp r3, #0
80046ba: d102 bne.n 80046c2 <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
80046bc: 4b11 ldr r3, [pc, #68] ; (8004704 <_sbrk+0x64>)
80046be: 4a12 ldr r2, [pc, #72] ; (8004708 <_sbrk+0x68>)
80046c0: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
80046c2: 4b10 ldr r3, [pc, #64] ; (8004704 <_sbrk+0x64>)
80046c4: 681a ldr r2, [r3, #0]
80046c6: 687b ldr r3, [r7, #4]
80046c8: 4413 add r3, r2
80046ca: 693a ldr r2, [r7, #16]
80046cc: 429a cmp r2, r3
80046ce: d205 bcs.n 80046dc <_sbrk+0x3c>
{
errno = ENOMEM;
80046d0: 4b0e ldr r3, [pc, #56] ; (800470c <_sbrk+0x6c>)
80046d2: 220c movs r2, #12
80046d4: 601a str r2, [r3, #0]
return (void *)-1;
80046d6: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
80046da: e009 b.n 80046f0 <_sbrk+0x50>
}
prev_heap_end = __sbrk_heap_end;
80046dc: 4b09 ldr r3, [pc, #36] ; (8004704 <_sbrk+0x64>)
80046de: 681b ldr r3, [r3, #0]
80046e0: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
80046e2: 4b08 ldr r3, [pc, #32] ; (8004704 <_sbrk+0x64>)
80046e4: 681a ldr r2, [r3, #0]
80046e6: 687b ldr r3, [r7, #4]
80046e8: 4413 add r3, r2
80046ea: 4a06 ldr r2, [pc, #24] ; (8004704 <_sbrk+0x64>)
80046ec: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
80046ee: 68fb ldr r3, [r7, #12]
}
80046f0: 4618 mov r0, r3
80046f2: 371c adds r7, #28
80046f4: 46bd mov sp, r7
80046f6: f85d 7b04 ldr.w r7, [sp], #4
80046fa: 4770 bx lr
80046fc: 20050000 .word 0x20050000
8004700: 00000400 .word 0x00000400
8004704: 20000574 .word 0x20000574
8004708: 2000f898 .word 0x2000f898
800470c: 2000f880 .word 0x2000f880
08004710 <SystemInit>:
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
8004710: b480 push {r7}
8004712: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8004714: 4b08 ldr r3, [pc, #32] ; (8004738 <SystemInit+0x28>)
8004716: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800471a: 4a07 ldr r2, [pc, #28] ; (8004738 <SystemInit+0x28>)
800471c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8004720: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
8004724: 4b04 ldr r3, [pc, #16] ; (8004738 <SystemInit+0x28>)
8004726: f04f 6200 mov.w r2, #134217728 ; 0x8000000
800472a: 609a str r2, [r3, #8]
#endif
}
800472c: bf00 nop
800472e: 46bd mov sp, r7
8004730: f85d 7b04 ldr.w r7, [sp], #4
8004734: 4770 bx lr
8004736: bf00 nop
8004738: e000ed00 .word 0xe000ed00
0800473c <Reset_Handler>:
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler: ldr sp, =_estack /* set stack pointer */
800473c: f8df d034 ldr.w sp, [pc, #52] ; 8004774 <LoopFillZerobss+0x14>
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
8004740: 2100 movs r1, #0
b LoopCopyDataInit
8004742: e003 b.n 800474c <LoopCopyDataInit>
08004744 <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
8004744: 4b0c ldr r3, [pc, #48] ; (8004778 <LoopFillZerobss+0x18>)
ldr r3, [r3, r1]
8004746: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
8004748: 5043 str r3, [r0, r1]
adds r1, r1, #4
800474a: 3104 adds r1, #4
0800474c <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
800474c: 480b ldr r0, [pc, #44] ; (800477c <LoopFillZerobss+0x1c>)
ldr r3, =_edata
800474e: 4b0c ldr r3, [pc, #48] ; (8004780 <LoopFillZerobss+0x20>)
adds r2, r0, r1
8004750: 1842 adds r2, r0, r1
cmp r2, r3
8004752: 429a cmp r2, r3
bcc CopyDataInit
8004754: d3f6 bcc.n 8004744 <CopyDataInit>
ldr r2, =_sbss
8004756: 4a0b ldr r2, [pc, #44] ; (8004784 <LoopFillZerobss+0x24>)
b LoopFillZerobss
8004758: e002 b.n 8004760 <LoopFillZerobss>
0800475a <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
800475a: 2300 movs r3, #0
str r3, [r2], #4
800475c: f842 3b04 str.w r3, [r2], #4
08004760 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
8004760: 4b09 ldr r3, [pc, #36] ; (8004788 <LoopFillZerobss+0x28>)
cmp r2, r3
8004762: 429a cmp r2, r3
bcc FillZerobss
8004764: d3f9 bcc.n 800475a <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
8004766: f7ff ffd3 bl 8004710 <SystemInit>
/* Call static constructors */
bl __libc_init_array
800476a: f016 fbe3 bl 801af34 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800476e: f7fc f9f1 bl 8000b54 <main>
bx lr
8004772: 4770 bx lr
Reset_Handler: ldr sp, =_estack /* set stack pointer */
8004774: 20050000 .word 0x20050000
ldr r3, =_sidata
8004778: 080211b8 .word 0x080211b8
ldr r0, =_sdata
800477c: 20000000 .word 0x20000000
ldr r3, =_edata
8004780: 200000dc .word 0x200000dc
ldr r2, =_sbss
8004784: 200000dc .word 0x200000dc
ldr r3, = _ebss
8004788: 2000f894 .word 0x2000f894
0800478c <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
800478c: e7fe b.n 800478c <ADC_IRQHandler>
0800478e <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800478e: b580 push {r7, lr}
8004790: af00 add r7, sp, #0
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8004792: 2003 movs r0, #3
8004794: f000 fce7 bl 8005166 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8004798: 2000 movs r0, #0
800479a: f7ff fe59 bl 8004450 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
800479e: f7ff faeb bl 8003d78 <HAL_MspInit>
/* Return function status */
return HAL_OK;
80047a2: 2300 movs r3, #0
}
80047a4: 4618 mov r0, r3
80047a6: bd80 pop {r7, pc}
080047a8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80047a8: b480 push {r7}
80047aa: af00 add r7, sp, #0
uwTick += uwTickFreq;
80047ac: 4b06 ldr r3, [pc, #24] ; (80047c8 <HAL_IncTick+0x20>)
80047ae: 781b ldrb r3, [r3, #0]
80047b0: 461a mov r2, r3
80047b2: 4b06 ldr r3, [pc, #24] ; (80047cc <HAL_IncTick+0x24>)
80047b4: 681b ldr r3, [r3, #0]
80047b6: 4413 add r3, r2
80047b8: 4a04 ldr r2, [pc, #16] ; (80047cc <HAL_IncTick+0x24>)
80047ba: 6013 str r3, [r2, #0]
}
80047bc: bf00 nop
80047be: 46bd mov sp, r7
80047c0: f85d 7b04 ldr.w r7, [sp], #4
80047c4: 4770 bx lr
80047c6: bf00 nop
80047c8: 20000060 .word 0x20000060
80047cc: 20008fcc .word 0x20008fcc
080047d0 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80047d0: b480 push {r7}
80047d2: af00 add r7, sp, #0
return uwTick;
80047d4: 4b03 ldr r3, [pc, #12] ; (80047e4 <HAL_GetTick+0x14>)
80047d6: 681b ldr r3, [r3, #0]
}
80047d8: 4618 mov r0, r3
80047da: 46bd mov sp, r7
80047dc: f85d 7b04 ldr.w r7, [sp], #4
80047e0: 4770 bx lr
80047e2: bf00 nop
80047e4: 20008fcc .word 0x20008fcc
080047e8 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
80047e8: b580 push {r7, lr}
80047ea: b084 sub sp, #16
80047ec: af00 add r7, sp, #0
80047ee: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
80047f0: f7ff ffee bl 80047d0 <HAL_GetTick>
80047f4: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
80047f6: 687b ldr r3, [r7, #4]
80047f8: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
80047fa: 68fb ldr r3, [r7, #12]
80047fc: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8004800: d005 beq.n 800480e <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8004802: 4b0a ldr r3, [pc, #40] ; (800482c <HAL_Delay+0x44>)
8004804: 781b ldrb r3, [r3, #0]
8004806: 461a mov r2, r3
8004808: 68fb ldr r3, [r7, #12]
800480a: 4413 add r3, r2
800480c: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
800480e: bf00 nop
8004810: f7ff ffde bl 80047d0 <HAL_GetTick>
8004814: 4602 mov r2, r0
8004816: 68bb ldr r3, [r7, #8]
8004818: 1ad3 subs r3, r2, r3
800481a: 68fa ldr r2, [r7, #12]
800481c: 429a cmp r2, r3
800481e: d8f7 bhi.n 8004810 <HAL_Delay+0x28>
{
}
}
8004820: bf00 nop
8004822: bf00 nop
8004824: 3710 adds r7, #16
8004826: 46bd mov sp, r7
8004828: bd80 pop {r7, pc}
800482a: bf00 nop
800482c: 20000060 .word 0x20000060
08004830 <HAL_ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
8004830: b580 push {r7, lr}
8004832: b084 sub sp, #16
8004834: af00 add r7, sp, #0
8004836: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8004838: 2300 movs r3, #0
800483a: 73fb strb r3, [r7, #15]
/* Check ADC handle */
if(hadc == NULL)
800483c: 687b ldr r3, [r7, #4]
800483e: 2b00 cmp r3, #0
8004840: d101 bne.n 8004846 <HAL_ADC_Init+0x16>
{
return HAL_ERROR;
8004842: 2301 movs r3, #1
8004844: e031 b.n 80048aa <HAL_ADC_Init+0x7a>
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
}
if(hadc->State == HAL_ADC_STATE_RESET)
8004846: 687b ldr r3, [r7, #4]
8004848: 6c1b ldr r3, [r3, #64] ; 0x40
800484a: 2b00 cmp r3, #0
800484c: d109 bne.n 8004862 <HAL_ADC_Init+0x32>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
800484e: 6878 ldr r0, [r7, #4]
8004850: f7ff faba bl 8003dc8 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8004854: 687b ldr r3, [r7, #4]
8004856: 2200 movs r2, #0
8004858: 645a str r2, [r3, #68] ; 0x44
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
800485a: 687b ldr r3, [r7, #4]
800485c: 2200 movs r2, #0
800485e: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
8004862: 687b ldr r3, [r7, #4]
8004864: 6c1b ldr r3, [r3, #64] ; 0x40
8004866: f003 0310 and.w r3, r3, #16
800486a: 2b00 cmp r3, #0
800486c: d116 bne.n 800489c <HAL_ADC_Init+0x6c>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
800486e: 687b ldr r3, [r7, #4]
8004870: 6c1a ldr r2, [r3, #64] ; 0x40
8004872: 4b10 ldr r3, [pc, #64] ; (80048b4 <HAL_ADC_Init+0x84>)
8004874: 4013 ands r3, r2
8004876: f043 0202 orr.w r2, r3, #2
800487a: 687b ldr r3, [r7, #4]
800487c: 641a str r2, [r3, #64] ; 0x40
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Set ADC parameters */
ADC_Init(hadc);
800487e: 6878 ldr r0, [r7, #4]
8004880: f000 faca bl 8004e18 <ADC_Init>
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8004884: 687b ldr r3, [r7, #4]
8004886: 2200 movs r2, #0
8004888: 645a str r2, [r3, #68] ; 0x44
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
800488a: 687b ldr r3, [r7, #4]
800488c: 6c1b ldr r3, [r3, #64] ; 0x40
800488e: f023 0303 bic.w r3, r3, #3
8004892: f043 0201 orr.w r2, r3, #1
8004896: 687b ldr r3, [r7, #4]
8004898: 641a str r2, [r3, #64] ; 0x40
800489a: e001 b.n 80048a0 <HAL_ADC_Init+0x70>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
tmp_hal_status = HAL_ERROR;
800489c: 2301 movs r3, #1
800489e: 73fb strb r3, [r7, #15]
}
/* Release Lock */
__HAL_UNLOCK(hadc);
80048a0: 687b ldr r3, [r7, #4]
80048a2: 2200 movs r2, #0
80048a4: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Return function status */
return tmp_hal_status;
80048a8: 7bfb ldrb r3, [r7, #15]
}
80048aa: 4618 mov r0, r3
80048ac: 3710 adds r7, #16
80048ae: 46bd mov sp, r7
80048b0: bd80 pop {r7, pc}
80048b2: bf00 nop
80048b4: ffffeefd .word 0xffffeefd
080048b8 <HAL_ADC_Start>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
80048b8: b480 push {r7}
80048ba: b085 sub sp, #20
80048bc: af00 add r7, sp, #0
80048be: 6078 str r0, [r7, #4]
__IO uint32_t counter = 0;
80048c0: 2300 movs r3, #0
80048c2: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
80048c4: 687b ldr r3, [r7, #4]
80048c6: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80048ca: 2b01 cmp r3, #1
80048cc: d101 bne.n 80048d2 <HAL_ADC_Start+0x1a>
80048ce: 2302 movs r3, #2
80048d0: e0ad b.n 8004a2e <HAL_ADC_Start+0x176>
80048d2: 687b ldr r3, [r7, #4]
80048d4: 2201 movs r2, #1
80048d6: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
80048da: 687b ldr r3, [r7, #4]
80048dc: 681b ldr r3, [r3, #0]
80048de: 689b ldr r3, [r3, #8]
80048e0: f003 0301 and.w r3, r3, #1
80048e4: 2b01 cmp r3, #1
80048e6: d018 beq.n 800491a <HAL_ADC_Start+0x62>
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
80048e8: 687b ldr r3, [r7, #4]
80048ea: 681b ldr r3, [r3, #0]
80048ec: 689a ldr r2, [r3, #8]
80048ee: 687b ldr r3, [r7, #4]
80048f0: 681b ldr r3, [r3, #0]
80048f2: f042 0201 orr.w r2, r2, #1
80048f6: 609a str r2, [r3, #8]
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
80048f8: 4b50 ldr r3, [pc, #320] ; (8004a3c <HAL_ADC_Start+0x184>)
80048fa: 681b ldr r3, [r3, #0]
80048fc: 4a50 ldr r2, [pc, #320] ; (8004a40 <HAL_ADC_Start+0x188>)
80048fe: fba2 2303 umull r2, r3, r2, r3
8004902: 0c9a lsrs r2, r3, #18
8004904: 4613 mov r3, r2
8004906: 005b lsls r3, r3, #1
8004908: 4413 add r3, r2
800490a: 60fb str r3, [r7, #12]
while(counter != 0)
800490c: e002 b.n 8004914 <HAL_ADC_Start+0x5c>
{
counter--;
800490e: 68fb ldr r3, [r7, #12]
8004910: 3b01 subs r3, #1
8004912: 60fb str r3, [r7, #12]
while(counter != 0)
8004914: 68fb ldr r3, [r7, #12]
8004916: 2b00 cmp r3, #0
8004918: d1f9 bne.n 800490e <HAL_ADC_Start+0x56>
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
800491a: 687b ldr r3, [r7, #4]
800491c: 681b ldr r3, [r3, #0]
800491e: 689b ldr r3, [r3, #8]
8004920: f003 0301 and.w r3, r3, #1
8004924: 2b01 cmp r3, #1
8004926: d175 bne.n 8004a14 <HAL_ADC_Start+0x15c>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular group operation */
ADC_STATE_CLR_SET(hadc->State,
8004928: 687b ldr r3, [r7, #4]
800492a: 6c1a ldr r2, [r3, #64] ; 0x40
800492c: 4b45 ldr r3, [pc, #276] ; (8004a44 <HAL_ADC_Start+0x18c>)
800492e: 4013 ands r3, r2
8004930: f443 7280 orr.w r2, r3, #256 ; 0x100
8004934: 687b ldr r3, [r7, #4]
8004936: 641a str r2, [r3, #64] ; 0x40
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
8004938: 687b ldr r3, [r7, #4]
800493a: 681b ldr r3, [r3, #0]
800493c: 685b ldr r3, [r3, #4]
800493e: f403 6380 and.w r3, r3, #1024 ; 0x400
8004942: 2b00 cmp r3, #0
8004944: d007 beq.n 8004956 <HAL_ADC_Start+0x9e>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
8004946: 687b ldr r3, [r7, #4]
8004948: 6c1b ldr r3, [r3, #64] ; 0x40
800494a: f423 5340 bic.w r3, r3, #12288 ; 0x3000
800494e: f443 5280 orr.w r2, r3, #4096 ; 0x1000
8004952: 687b ldr r3, [r7, #4]
8004954: 641a str r2, [r3, #64] ; 0x40
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8004956: 687b ldr r3, [r7, #4]
8004958: 6c1b ldr r3, [r3, #64] ; 0x40
800495a: f403 5380 and.w r3, r3, #4096 ; 0x1000
800495e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8004962: d106 bne.n 8004972 <HAL_ADC_Start+0xba>
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
8004964: 687b ldr r3, [r7, #4]
8004966: 6c5b ldr r3, [r3, #68] ; 0x44
8004968: f023 0206 bic.w r2, r3, #6
800496c: 687b ldr r3, [r7, #4]
800496e: 645a str r2, [r3, #68] ; 0x44
8004970: e002 b.n 8004978 <HAL_ADC_Start+0xc0>
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
8004972: 687b ldr r3, [r7, #4]
8004974: 2200 movs r2, #0
8004976: 645a str r2, [r3, #68] ; 0x44
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
8004978: 687b ldr r3, [r7, #4]
800497a: 2200 movs r2, #0
800497c: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
8004980: 687b ldr r3, [r7, #4]
8004982: 681b ldr r3, [r3, #0]
8004984: f06f 0222 mvn.w r2, #34 ; 0x22
8004988: 601a str r2, [r3, #0]
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
800498a: 4b2f ldr r3, [pc, #188] ; (8004a48 <HAL_ADC_Start+0x190>)
800498c: 685b ldr r3, [r3, #4]
800498e: f003 031f and.w r3, r3, #31
8004992: 2b00 cmp r3, #0
8004994: d10f bne.n 80049b6 <HAL_ADC_Start+0xfe>
{
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
8004996: 687b ldr r3, [r7, #4]
8004998: 681b ldr r3, [r3, #0]
800499a: 689b ldr r3, [r3, #8]
800499c: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
80049a0: 2b00 cmp r3, #0
80049a2: d143 bne.n 8004a2c <HAL_ADC_Start+0x174>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
80049a4: 687b ldr r3, [r7, #4]
80049a6: 681b ldr r3, [r3, #0]
80049a8: 689a ldr r2, [r3, #8]
80049aa: 687b ldr r3, [r7, #4]
80049ac: 681b ldr r3, [r3, #0]
80049ae: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
80049b2: 609a str r2, [r3, #8]
80049b4: e03a b.n 8004a2c <HAL_ADC_Start+0x174>
}
}
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
80049b6: 687b ldr r3, [r7, #4]
80049b8: 681b ldr r3, [r3, #0]
80049ba: 4a24 ldr r2, [pc, #144] ; (8004a4c <HAL_ADC_Start+0x194>)
80049bc: 4293 cmp r3, r2
80049be: d10e bne.n 80049de <HAL_ADC_Start+0x126>
80049c0: 687b ldr r3, [r7, #4]
80049c2: 681b ldr r3, [r3, #0]
80049c4: 689b ldr r3, [r3, #8]
80049c6: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
80049ca: 2b00 cmp r3, #0
80049cc: d107 bne.n 80049de <HAL_ADC_Start+0x126>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
80049ce: 687b ldr r3, [r7, #4]
80049d0: 681b ldr r3, [r3, #0]
80049d2: 689a ldr r2, [r3, #8]
80049d4: 687b ldr r3, [r7, #4]
80049d6: 681b ldr r3, [r3, #0]
80049d8: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
80049dc: 609a str r2, [r3, #8]
}
/* if dual mode is selected, ADC3 works independently. */
/* check if the mode selected is not triple */
if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
80049de: 4b1a ldr r3, [pc, #104] ; (8004a48 <HAL_ADC_Start+0x190>)
80049e0: 685b ldr r3, [r3, #4]
80049e2: f003 0310 and.w r3, r3, #16
80049e6: 2b00 cmp r3, #0
80049e8: d120 bne.n 8004a2c <HAL_ADC_Start+0x174>
{
/* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
80049ea: 687b ldr r3, [r7, #4]
80049ec: 681b ldr r3, [r3, #0]
80049ee: 4a18 ldr r2, [pc, #96] ; (8004a50 <HAL_ADC_Start+0x198>)
80049f0: 4293 cmp r3, r2
80049f2: d11b bne.n 8004a2c <HAL_ADC_Start+0x174>
80049f4: 687b ldr r3, [r7, #4]
80049f6: 681b ldr r3, [r3, #0]
80049f8: 689b ldr r3, [r3, #8]
80049fa: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
80049fe: 2b00 cmp r3, #0
8004a00: d114 bne.n 8004a2c <HAL_ADC_Start+0x174>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
8004a02: 687b ldr r3, [r7, #4]
8004a04: 681b ldr r3, [r3, #0]
8004a06: 689a ldr r2, [r3, #8]
8004a08: 687b ldr r3, [r7, #4]
8004a0a: 681b ldr r3, [r3, #0]
8004a0c: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
8004a10: 609a str r2, [r3, #8]
8004a12: e00b b.n 8004a2c <HAL_ADC_Start+0x174>
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8004a14: 687b ldr r3, [r7, #4]
8004a16: 6c1b ldr r3, [r3, #64] ; 0x40
8004a18: f043 0210 orr.w r2, r3, #16
8004a1c: 687b ldr r3, [r7, #4]
8004a1e: 641a str r2, [r3, #64] ; 0x40
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8004a20: 687b ldr r3, [r7, #4]
8004a22: 6c5b ldr r3, [r3, #68] ; 0x44
8004a24: f043 0201 orr.w r2, r3, #1
8004a28: 687b ldr r3, [r7, #4]
8004a2a: 645a str r2, [r3, #68] ; 0x44
}
/* Return function status */
return HAL_OK;
8004a2c: 2300 movs r3, #0
}
8004a2e: 4618 mov r0, r3
8004a30: 3714 adds r7, #20
8004a32: 46bd mov sp, r7
8004a34: f85d 7b04 ldr.w r7, [sp], #4
8004a38: 4770 bx lr
8004a3a: bf00 nop
8004a3c: 20000058 .word 0x20000058
8004a40: 431bde83 .word 0x431bde83
8004a44: fffff8fe .word 0xfffff8fe
8004a48: 40012300 .word 0x40012300
8004a4c: 40012000 .word 0x40012000
8004a50: 40012200 .word 0x40012200
08004a54 <HAL_ADC_PollForConversion>:
* the configuration information for the specified ADC.
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
8004a54: b580 push {r7, lr}
8004a56: b084 sub sp, #16
8004a58: af00 add r7, sp, #0
8004a5a: 6078 str r0, [r7, #4]
8004a5c: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
8004a5e: 2300 movs r3, #0
8004a60: 60fb str r3, [r7, #12]
/* each conversion: */
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and polling for end of each conversion. */
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
8004a62: 687b ldr r3, [r7, #4]
8004a64: 681b ldr r3, [r3, #0]
8004a66: 689b ldr r3, [r3, #8]
8004a68: f403 6380 and.w r3, r3, #1024 ; 0x400
8004a6c: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8004a70: d113 bne.n 8004a9a <HAL_ADC_PollForConversion+0x46>
HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
8004a72: 687b ldr r3, [r7, #4]
8004a74: 681b ldr r3, [r3, #0]
8004a76: 689b ldr r3, [r3, #8]
8004a78: f403 7380 and.w r3, r3, #256 ; 0x100
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
8004a7c: f5b3 7f80 cmp.w r3, #256 ; 0x100
8004a80: d10b bne.n 8004a9a <HAL_ADC_PollForConversion+0x46>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8004a82: 687b ldr r3, [r7, #4]
8004a84: 6c1b ldr r3, [r3, #64] ; 0x40
8004a86: f043 0220 orr.w r2, r3, #32
8004a8a: 687b ldr r3, [r7, #4]
8004a8c: 641a str r2, [r3, #64] ; 0x40
/* Process unlocked */
__HAL_UNLOCK(hadc);
8004a8e: 687b ldr r3, [r7, #4]
8004a90: 2200 movs r2, #0
8004a92: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_ERROR;
8004a96: 2301 movs r3, #1
8004a98: e063 b.n 8004b62 <HAL_ADC_PollForConversion+0x10e>
}
/* Get tick */
tickstart = HAL_GetTick();
8004a9a: f7ff fe99 bl 80047d0 <HAL_GetTick>
8004a9e: 60f8 str r0, [r7, #12]
/* Check End of conversion flag */
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
8004aa0: e021 b.n 8004ae6 <HAL_ADC_PollForConversion+0x92>
{
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
8004aa2: 683b ldr r3, [r7, #0]
8004aa4: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8004aa8: d01d beq.n 8004ae6 <HAL_ADC_PollForConversion+0x92>
{
if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
8004aaa: 683b ldr r3, [r7, #0]
8004aac: 2b00 cmp r3, #0
8004aae: d007 beq.n 8004ac0 <HAL_ADC_PollForConversion+0x6c>
8004ab0: f7ff fe8e bl 80047d0 <HAL_GetTick>
8004ab4: 4602 mov r2, r0
8004ab6: 68fb ldr r3, [r7, #12]
8004ab8: 1ad3 subs r3, r2, r3
8004aba: 683a ldr r2, [r7, #0]
8004abc: 429a cmp r2, r3
8004abe: d212 bcs.n 8004ae6 <HAL_ADC_PollForConversion+0x92>
{
/* New check to avoid false timeout detection in case of preemption */
if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
8004ac0: 687b ldr r3, [r7, #4]
8004ac2: 681b ldr r3, [r3, #0]
8004ac4: 681b ldr r3, [r3, #0]
8004ac6: f003 0302 and.w r3, r3, #2
8004aca: 2b02 cmp r3, #2
8004acc: d00b beq.n 8004ae6 <HAL_ADC_PollForConversion+0x92>
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
8004ace: 687b ldr r3, [r7, #4]
8004ad0: 6c1b ldr r3, [r3, #64] ; 0x40
8004ad2: f043 0204 orr.w r2, r3, #4
8004ad6: 687b ldr r3, [r7, #4]
8004ad8: 641a str r2, [r3, #64] ; 0x40
/* Process unlocked */
__HAL_UNLOCK(hadc);
8004ada: 687b ldr r3, [r7, #4]
8004adc: 2200 movs r2, #0
8004ade: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
8004ae2: 2303 movs r3, #3
8004ae4: e03d b.n 8004b62 <HAL_ADC_PollForConversion+0x10e>
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
8004ae6: 687b ldr r3, [r7, #4]
8004ae8: 681b ldr r3, [r3, #0]
8004aea: 681b ldr r3, [r3, #0]
8004aec: f003 0302 and.w r3, r3, #2
8004af0: 2b02 cmp r3, #2
8004af2: d1d6 bne.n 8004aa2 <HAL_ADC_PollForConversion+0x4e>
}
}
}
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
8004af4: 687b ldr r3, [r7, #4]
8004af6: 681b ldr r3, [r3, #0]
8004af8: f06f 0212 mvn.w r2, #18
8004afc: 601a str r2, [r3, #0]
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8004afe: 687b ldr r3, [r7, #4]
8004b00: 6c1b ldr r3, [r3, #64] ; 0x40
8004b02: f443 7200 orr.w r2, r3, #512 ; 0x200
8004b06: 687b ldr r3, [r7, #4]
8004b08: 641a str r2, [r3, #64] ; 0x40
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F7, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8004b0a: 687b ldr r3, [r7, #4]
8004b0c: 681b ldr r3, [r3, #0]
8004b0e: 689b ldr r3, [r3, #8]
8004b10: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
8004b14: 2b00 cmp r3, #0
8004b16: d123 bne.n 8004b60 <HAL_ADC_PollForConversion+0x10c>
(hadc->Init.ContinuousConvMode == DISABLE) &&
8004b18: 687b ldr r3, [r7, #4]
8004b1a: 699b ldr r3, [r3, #24]
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8004b1c: 2b00 cmp r3, #0
8004b1e: d11f bne.n 8004b60 <HAL_ADC_PollForConversion+0x10c>
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
8004b20: 687b ldr r3, [r7, #4]
8004b22: 681b ldr r3, [r3, #0]
8004b24: 6adb ldr r3, [r3, #44] ; 0x2c
8004b26: f403 0370 and.w r3, r3, #15728640 ; 0xf00000
(hadc->Init.ContinuousConvMode == DISABLE) &&
8004b2a: 2b00 cmp r3, #0
8004b2c: d006 beq.n 8004b3c <HAL_ADC_PollForConversion+0xe8>
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
8004b2e: 687b ldr r3, [r7, #4]
8004b30: 681b ldr r3, [r3, #0]
8004b32: 689b ldr r3, [r3, #8]
8004b34: f403 6380 and.w r3, r3, #1024 ; 0x400
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
8004b38: 2b00 cmp r3, #0
8004b3a: d111 bne.n 8004b60 <HAL_ADC_PollForConversion+0x10c>
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
8004b3c: 687b ldr r3, [r7, #4]
8004b3e: 6c1b ldr r3, [r3, #64] ; 0x40
8004b40: f423 7280 bic.w r2, r3, #256 ; 0x100
8004b44: 687b ldr r3, [r7, #4]
8004b46: 641a str r2, [r3, #64] ; 0x40
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8004b48: 687b ldr r3, [r7, #4]
8004b4a: 6c1b ldr r3, [r3, #64] ; 0x40
8004b4c: f403 5380 and.w r3, r3, #4096 ; 0x1000
8004b50: 2b00 cmp r3, #0
8004b52: d105 bne.n 8004b60 <HAL_ADC_PollForConversion+0x10c>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8004b54: 687b ldr r3, [r7, #4]
8004b56: 6c1b ldr r3, [r3, #64] ; 0x40
8004b58: f043 0201 orr.w r2, r3, #1
8004b5c: 687b ldr r3, [r7, #4]
8004b5e: 641a str r2, [r3, #64] ; 0x40
}
}
/* Return ADC state */
return HAL_OK;
8004b60: 2300 movs r3, #0
}
8004b62: 4618 mov r0, r3
8004b64: 3710 adds r7, #16
8004b66: 46bd mov sp, r7
8004b68: bd80 pop {r7, pc}
08004b6a <HAL_ADC_GetValue>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval Converted value
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
{
8004b6a: b480 push {r7}
8004b6c: b083 sub sp, #12
8004b6e: af00 add r7, sp, #0
8004b70: 6078 str r0, [r7, #4]
/* Return the selected ADC converted value */
return hadc->Instance->DR;
8004b72: 687b ldr r3, [r7, #4]
8004b74: 681b ldr r3, [r3, #0]
8004b76: 6cdb ldr r3, [r3, #76] ; 0x4c
}
8004b78: 4618 mov r0, r3
8004b7a: 370c adds r7, #12
8004b7c: 46bd mov sp, r7
8004b7e: f85d 7b04 ldr.w r7, [sp], #4
8004b82: 4770 bx lr
08004b84 <HAL_ADC_ConfigChannel>:
* the configuration information for the specified ADC.
* @param sConfig ADC configuration structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8004b84: b480 push {r7}
8004b86: b085 sub sp, #20
8004b88: af00 add r7, sp, #0
8004b8a: 6078 str r0, [r7, #4]
8004b8c: 6039 str r1, [r7, #0]
__IO uint32_t counter = 0;
8004b8e: 2300 movs r3, #0
8004b90: 60fb str r3, [r7, #12]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8004b92: 687b ldr r3, [r7, #4]
8004b94: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8004b98: 2b01 cmp r3, #1
8004b9a: d101 bne.n 8004ba0 <HAL_ADC_ConfigChannel+0x1c>
8004b9c: 2302 movs r3, #2
8004b9e: e12a b.n 8004df6 <HAL_ADC_ConfigChannel+0x272>
8004ba0: 687b ldr r3, [r7, #4]
8004ba2: 2201 movs r2, #1
8004ba4: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE))
8004ba8: 683b ldr r3, [r7, #0]
8004baa: 681b ldr r3, [r3, #0]
8004bac: 2b09 cmp r3, #9
8004bae: d93a bls.n 8004c26 <HAL_ADC_ConfigChannel+0xa2>
8004bb0: 683b ldr r3, [r7, #0]
8004bb2: 681b ldr r3, [r3, #0]
8004bb4: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
8004bb8: d035 beq.n 8004c26 <HAL_ADC_ConfigChannel+0xa2>
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
8004bba: 687b ldr r3, [r7, #4]
8004bbc: 681b ldr r3, [r3, #0]
8004bbe: 68d9 ldr r1, [r3, #12]
8004bc0: 683b ldr r3, [r7, #0]
8004bc2: 681b ldr r3, [r3, #0]
8004bc4: b29b uxth r3, r3
8004bc6: 461a mov r2, r3
8004bc8: 4613 mov r3, r2
8004bca: 005b lsls r3, r3, #1
8004bcc: 4413 add r3, r2
8004bce: 3b1e subs r3, #30
8004bd0: 2207 movs r2, #7
8004bd2: fa02 f303 lsl.w r3, r2, r3
8004bd6: 43da mvns r2, r3
8004bd8: 687b ldr r3, [r7, #4]
8004bda: 681b ldr r3, [r3, #0]
8004bdc: 400a ands r2, r1
8004bde: 60da str r2, [r3, #12]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004be0: 683b ldr r3, [r7, #0]
8004be2: 681b ldr r3, [r3, #0]
8004be4: 4a87 ldr r2, [pc, #540] ; (8004e04 <HAL_ADC_ConfigChannel+0x280>)
8004be6: 4293 cmp r3, r2
8004be8: d10a bne.n 8004c00 <HAL_ADC_ConfigChannel+0x7c>
{
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
8004bea: 687b ldr r3, [r7, #4]
8004bec: 681b ldr r3, [r3, #0]
8004bee: 68d9 ldr r1, [r3, #12]
8004bf0: 683b ldr r3, [r7, #0]
8004bf2: 689b ldr r3, [r3, #8]
8004bf4: 061a lsls r2, r3, #24
8004bf6: 687b ldr r3, [r7, #4]
8004bf8: 681b ldr r3, [r3, #0]
8004bfa: 430a orrs r2, r1
8004bfc: 60da str r2, [r3, #12]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004bfe: e035 b.n 8004c6c <HAL_ADC_ConfigChannel+0xe8>
}
else
{
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
8004c00: 687b ldr r3, [r7, #4]
8004c02: 681b ldr r3, [r3, #0]
8004c04: 68d9 ldr r1, [r3, #12]
8004c06: 683b ldr r3, [r7, #0]
8004c08: 689a ldr r2, [r3, #8]
8004c0a: 683b ldr r3, [r7, #0]
8004c0c: 681b ldr r3, [r3, #0]
8004c0e: b29b uxth r3, r3
8004c10: 4618 mov r0, r3
8004c12: 4603 mov r3, r0
8004c14: 005b lsls r3, r3, #1
8004c16: 4403 add r3, r0
8004c18: 3b1e subs r3, #30
8004c1a: 409a lsls r2, r3
8004c1c: 687b ldr r3, [r7, #4]
8004c1e: 681b ldr r3, [r3, #0]
8004c20: 430a orrs r2, r1
8004c22: 60da str r2, [r3, #12]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004c24: e022 b.n 8004c6c <HAL_ADC_ConfigChannel+0xe8>
}
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
8004c26: 687b ldr r3, [r7, #4]
8004c28: 681b ldr r3, [r3, #0]
8004c2a: 6919 ldr r1, [r3, #16]
8004c2c: 683b ldr r3, [r7, #0]
8004c2e: 681b ldr r3, [r3, #0]
8004c30: b29b uxth r3, r3
8004c32: 461a mov r2, r3
8004c34: 4613 mov r3, r2
8004c36: 005b lsls r3, r3, #1
8004c38: 4413 add r3, r2
8004c3a: 2207 movs r2, #7
8004c3c: fa02 f303 lsl.w r3, r2, r3
8004c40: 43da mvns r2, r3
8004c42: 687b ldr r3, [r7, #4]
8004c44: 681b ldr r3, [r3, #0]
8004c46: 400a ands r2, r1
8004c48: 611a str r2, [r3, #16]
/* Set the new sample time */
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
8004c4a: 687b ldr r3, [r7, #4]
8004c4c: 681b ldr r3, [r3, #0]
8004c4e: 6919 ldr r1, [r3, #16]
8004c50: 683b ldr r3, [r7, #0]
8004c52: 689a ldr r2, [r3, #8]
8004c54: 683b ldr r3, [r7, #0]
8004c56: 681b ldr r3, [r3, #0]
8004c58: b29b uxth r3, r3
8004c5a: 4618 mov r0, r3
8004c5c: 4603 mov r3, r0
8004c5e: 005b lsls r3, r3, #1
8004c60: 4403 add r3, r0
8004c62: 409a lsls r2, r3
8004c64: 687b ldr r3, [r7, #4]
8004c66: 681b ldr r3, [r3, #0]
8004c68: 430a orrs r2, r1
8004c6a: 611a str r2, [r3, #16]
}
/* For Rank 1 to 6 */
if (sConfig->Rank < 7)
8004c6c: 683b ldr r3, [r7, #0]
8004c6e: 685b ldr r3, [r3, #4]
8004c70: 2b06 cmp r3, #6
8004c72: d824 bhi.n 8004cbe <HAL_ADC_ConfigChannel+0x13a>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
8004c74: 687b ldr r3, [r7, #4]
8004c76: 681b ldr r3, [r3, #0]
8004c78: 6b59 ldr r1, [r3, #52] ; 0x34
8004c7a: 683b ldr r3, [r7, #0]
8004c7c: 685a ldr r2, [r3, #4]
8004c7e: 4613 mov r3, r2
8004c80: 009b lsls r3, r3, #2
8004c82: 4413 add r3, r2
8004c84: 3b05 subs r3, #5
8004c86: 221f movs r2, #31
8004c88: fa02 f303 lsl.w r3, r2, r3
8004c8c: 43da mvns r2, r3
8004c8e: 687b ldr r3, [r7, #4]
8004c90: 681b ldr r3, [r3, #0]
8004c92: 400a ands r2, r1
8004c94: 635a str r2, [r3, #52] ; 0x34
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
8004c96: 687b ldr r3, [r7, #4]
8004c98: 681b ldr r3, [r3, #0]
8004c9a: 6b59 ldr r1, [r3, #52] ; 0x34
8004c9c: 683b ldr r3, [r7, #0]
8004c9e: 681b ldr r3, [r3, #0]
8004ca0: b29b uxth r3, r3
8004ca2: 4618 mov r0, r3
8004ca4: 683b ldr r3, [r7, #0]
8004ca6: 685a ldr r2, [r3, #4]
8004ca8: 4613 mov r3, r2
8004caa: 009b lsls r3, r3, #2
8004cac: 4413 add r3, r2
8004cae: 3b05 subs r3, #5
8004cb0: fa00 f203 lsl.w r2, r0, r3
8004cb4: 687b ldr r3, [r7, #4]
8004cb6: 681b ldr r3, [r3, #0]
8004cb8: 430a orrs r2, r1
8004cba: 635a str r2, [r3, #52] ; 0x34
8004cbc: e04c b.n 8004d58 <HAL_ADC_ConfigChannel+0x1d4>
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13)
8004cbe: 683b ldr r3, [r7, #0]
8004cc0: 685b ldr r3, [r3, #4]
8004cc2: 2b0c cmp r3, #12
8004cc4: d824 bhi.n 8004d10 <HAL_ADC_ConfigChannel+0x18c>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
8004cc6: 687b ldr r3, [r7, #4]
8004cc8: 681b ldr r3, [r3, #0]
8004cca: 6b19 ldr r1, [r3, #48] ; 0x30
8004ccc: 683b ldr r3, [r7, #0]
8004cce: 685a ldr r2, [r3, #4]
8004cd0: 4613 mov r3, r2
8004cd2: 009b lsls r3, r3, #2
8004cd4: 4413 add r3, r2
8004cd6: 3b23 subs r3, #35 ; 0x23
8004cd8: 221f movs r2, #31
8004cda: fa02 f303 lsl.w r3, r2, r3
8004cde: 43da mvns r2, r3
8004ce0: 687b ldr r3, [r7, #4]
8004ce2: 681b ldr r3, [r3, #0]
8004ce4: 400a ands r2, r1
8004ce6: 631a str r2, [r3, #48] ; 0x30
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
8004ce8: 687b ldr r3, [r7, #4]
8004cea: 681b ldr r3, [r3, #0]
8004cec: 6b19 ldr r1, [r3, #48] ; 0x30
8004cee: 683b ldr r3, [r7, #0]
8004cf0: 681b ldr r3, [r3, #0]
8004cf2: b29b uxth r3, r3
8004cf4: 4618 mov r0, r3
8004cf6: 683b ldr r3, [r7, #0]
8004cf8: 685a ldr r2, [r3, #4]
8004cfa: 4613 mov r3, r2
8004cfc: 009b lsls r3, r3, #2
8004cfe: 4413 add r3, r2
8004d00: 3b23 subs r3, #35 ; 0x23
8004d02: fa00 f203 lsl.w r2, r0, r3
8004d06: 687b ldr r3, [r7, #4]
8004d08: 681b ldr r3, [r3, #0]
8004d0a: 430a orrs r2, r1
8004d0c: 631a str r2, [r3, #48] ; 0x30
8004d0e: e023 b.n 8004d58 <HAL_ADC_ConfigChannel+0x1d4>
}
/* For Rank 13 to 16 */
else
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
8004d10: 687b ldr r3, [r7, #4]
8004d12: 681b ldr r3, [r3, #0]
8004d14: 6ad9 ldr r1, [r3, #44] ; 0x2c
8004d16: 683b ldr r3, [r7, #0]
8004d18: 685a ldr r2, [r3, #4]
8004d1a: 4613 mov r3, r2
8004d1c: 009b lsls r3, r3, #2
8004d1e: 4413 add r3, r2
8004d20: 3b41 subs r3, #65 ; 0x41
8004d22: 221f movs r2, #31
8004d24: fa02 f303 lsl.w r3, r2, r3
8004d28: 43da mvns r2, r3
8004d2a: 687b ldr r3, [r7, #4]
8004d2c: 681b ldr r3, [r3, #0]
8004d2e: 400a ands r2, r1
8004d30: 62da str r2, [r3, #44] ; 0x2c
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
8004d32: 687b ldr r3, [r7, #4]
8004d34: 681b ldr r3, [r3, #0]
8004d36: 6ad9 ldr r1, [r3, #44] ; 0x2c
8004d38: 683b ldr r3, [r7, #0]
8004d3a: 681b ldr r3, [r3, #0]
8004d3c: b29b uxth r3, r3
8004d3e: 4618 mov r0, r3
8004d40: 683b ldr r3, [r7, #0]
8004d42: 685a ldr r2, [r3, #4]
8004d44: 4613 mov r3, r2
8004d46: 009b lsls r3, r3, #2
8004d48: 4413 add r3, r2
8004d4a: 3b41 subs r3, #65 ; 0x41
8004d4c: fa00 f203 lsl.w r2, r0, r3
8004d50: 687b ldr r3, [r7, #4]
8004d52: 681b ldr r3, [r3, #0]
8004d54: 430a orrs r2, r1
8004d56: 62da str r2, [r3, #44] ; 0x2c
}
/* if no internal channel selected */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE))
8004d58: 687b ldr r3, [r7, #4]
8004d5a: 681b ldr r3, [r3, #0]
8004d5c: 4a2a ldr r2, [pc, #168] ; (8004e08 <HAL_ADC_ConfigChannel+0x284>)
8004d5e: 4293 cmp r3, r2
8004d60: d10a bne.n 8004d78 <HAL_ADC_ConfigChannel+0x1f4>
8004d62: 683b ldr r3, [r7, #0]
8004d64: 681b ldr r3, [r3, #0]
8004d66: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
8004d6a: d105 bne.n 8004d78 <HAL_ADC_ConfigChannel+0x1f4>
{
/* Disable the VBAT & TSVREFE channel*/
ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
8004d6c: 4b27 ldr r3, [pc, #156] ; (8004e0c <HAL_ADC_ConfigChannel+0x288>)
8004d6e: 685b ldr r3, [r3, #4]
8004d70: 4a26 ldr r2, [pc, #152] ; (8004e0c <HAL_ADC_ConfigChannel+0x288>)
8004d72: f423 0340 bic.w r3, r3, #12582912 ; 0xc00000
8004d76: 6053 str r3, [r2, #4]
}
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
8004d78: 687b ldr r3, [r7, #4]
8004d7a: 681b ldr r3, [r3, #0]
8004d7c: 4a22 ldr r2, [pc, #136] ; (8004e08 <HAL_ADC_ConfigChannel+0x284>)
8004d7e: 4293 cmp r3, r2
8004d80: d109 bne.n 8004d96 <HAL_ADC_ConfigChannel+0x212>
8004d82: 683b ldr r3, [r7, #0]
8004d84: 681b ldr r3, [r3, #0]
8004d86: 2b12 cmp r3, #18
8004d88: d105 bne.n 8004d96 <HAL_ADC_ConfigChannel+0x212>
{
/* Enable the VBAT channel*/
ADC->CCR |= ADC_CCR_VBATE;
8004d8a: 4b20 ldr r3, [pc, #128] ; (8004e0c <HAL_ADC_ConfigChannel+0x288>)
8004d8c: 685b ldr r3, [r3, #4]
8004d8e: 4a1f ldr r2, [pc, #124] ; (8004e0c <HAL_ADC_ConfigChannel+0x288>)
8004d90: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
8004d94: 6053 str r3, [r2, #4]
}
/* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
8004d96: 687b ldr r3, [r7, #4]
8004d98: 681b ldr r3, [r3, #0]
8004d9a: 4a1b ldr r2, [pc, #108] ; (8004e08 <HAL_ADC_ConfigChannel+0x284>)
8004d9c: 4293 cmp r3, r2
8004d9e: d125 bne.n 8004dec <HAL_ADC_ConfigChannel+0x268>
8004da0: 683b ldr r3, [r7, #0]
8004da2: 681b ldr r3, [r3, #0]
8004da4: 4a17 ldr r2, [pc, #92] ; (8004e04 <HAL_ADC_ConfigChannel+0x280>)
8004da6: 4293 cmp r3, r2
8004da8: d003 beq.n 8004db2 <HAL_ADC_ConfigChannel+0x22e>
8004daa: 683b ldr r3, [r7, #0]
8004dac: 681b ldr r3, [r3, #0]
8004dae: 2b11 cmp r3, #17
8004db0: d11c bne.n 8004dec <HAL_ADC_ConfigChannel+0x268>
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
8004db2: 4b16 ldr r3, [pc, #88] ; (8004e0c <HAL_ADC_ConfigChannel+0x288>)
8004db4: 685b ldr r3, [r3, #4]
8004db6: 4a15 ldr r2, [pc, #84] ; (8004e0c <HAL_ADC_ConfigChannel+0x288>)
8004db8: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8004dbc: 6053 str r3, [r2, #4]
if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004dbe: 683b ldr r3, [r7, #0]
8004dc0: 681b ldr r3, [r3, #0]
8004dc2: 4a10 ldr r2, [pc, #64] ; (8004e04 <HAL_ADC_ConfigChannel+0x280>)
8004dc4: 4293 cmp r3, r2
8004dc6: d111 bne.n 8004dec <HAL_ADC_ConfigChannel+0x268>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
8004dc8: 4b11 ldr r3, [pc, #68] ; (8004e10 <HAL_ADC_ConfigChannel+0x28c>)
8004dca: 681b ldr r3, [r3, #0]
8004dcc: 4a11 ldr r2, [pc, #68] ; (8004e14 <HAL_ADC_ConfigChannel+0x290>)
8004dce: fba2 2303 umull r2, r3, r2, r3
8004dd2: 0c9a lsrs r2, r3, #18
8004dd4: 4613 mov r3, r2
8004dd6: 009b lsls r3, r3, #2
8004dd8: 4413 add r3, r2
8004dda: 005b lsls r3, r3, #1
8004ddc: 60fb str r3, [r7, #12]
while(counter != 0)
8004dde: e002 b.n 8004de6 <HAL_ADC_ConfigChannel+0x262>
{
counter--;
8004de0: 68fb ldr r3, [r7, #12]
8004de2: 3b01 subs r3, #1
8004de4: 60fb str r3, [r7, #12]
while(counter != 0)
8004de6: 68fb ldr r3, [r7, #12]
8004de8: 2b00 cmp r3, #0
8004dea: d1f9 bne.n 8004de0 <HAL_ADC_ConfigChannel+0x25c>
}
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8004dec: 687b ldr r3, [r7, #4]
8004dee: 2200 movs r2, #0
8004df0: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Return function status */
return HAL_OK;
8004df4: 2300 movs r3, #0
}
8004df6: 4618 mov r0, r3
8004df8: 3714 adds r7, #20
8004dfa: 46bd mov sp, r7
8004dfc: f85d 7b04 ldr.w r7, [sp], #4
8004e00: 4770 bx lr
8004e02: bf00 nop
8004e04: 10000012 .word 0x10000012
8004e08: 40012000 .word 0x40012000
8004e0c: 40012300 .word 0x40012300
8004e10: 20000058 .word 0x20000058
8004e14: 431bde83 .word 0x431bde83
08004e18 <ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
8004e18: b480 push {r7}
8004e1a: b083 sub sp, #12
8004e1c: af00 add r7, sp, #0
8004e1e: 6078 str r0, [r7, #4]
/* Set ADC parameters */
/* Set the ADC clock prescaler */
ADC->CCR &= ~(ADC_CCR_ADCPRE);
8004e20: 4b78 ldr r3, [pc, #480] ; (8005004 <ADC_Init+0x1ec>)
8004e22: 685b ldr r3, [r3, #4]
8004e24: 4a77 ldr r2, [pc, #476] ; (8005004 <ADC_Init+0x1ec>)
8004e26: f423 3340 bic.w r3, r3, #196608 ; 0x30000
8004e2a: 6053 str r3, [r2, #4]
ADC->CCR |= hadc->Init.ClockPrescaler;
8004e2c: 4b75 ldr r3, [pc, #468] ; (8005004 <ADC_Init+0x1ec>)
8004e2e: 685a ldr r2, [r3, #4]
8004e30: 687b ldr r3, [r7, #4]
8004e32: 685b ldr r3, [r3, #4]
8004e34: 4973 ldr r1, [pc, #460] ; (8005004 <ADC_Init+0x1ec>)
8004e36: 4313 orrs r3, r2
8004e38: 604b str r3, [r1, #4]
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
8004e3a: 687b ldr r3, [r7, #4]
8004e3c: 681b ldr r3, [r3, #0]
8004e3e: 685a ldr r2, [r3, #4]
8004e40: 687b ldr r3, [r7, #4]
8004e42: 681b ldr r3, [r3, #0]
8004e44: f422 7280 bic.w r2, r2, #256 ; 0x100
8004e48: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
8004e4a: 687b ldr r3, [r7, #4]
8004e4c: 681b ldr r3, [r3, #0]
8004e4e: 6859 ldr r1, [r3, #4]
8004e50: 687b ldr r3, [r7, #4]
8004e52: 691b ldr r3, [r3, #16]
8004e54: 021a lsls r2, r3, #8
8004e56: 687b ldr r3, [r7, #4]
8004e58: 681b ldr r3, [r3, #0]
8004e5a: 430a orrs r2, r1
8004e5c: 605a str r2, [r3, #4]
/* Set ADC resolution */
hadc->Instance->CR1 &= ~(ADC_CR1_RES);
8004e5e: 687b ldr r3, [r7, #4]
8004e60: 681b ldr r3, [r3, #0]
8004e62: 685a ldr r2, [r3, #4]
8004e64: 687b ldr r3, [r7, #4]
8004e66: 681b ldr r3, [r3, #0]
8004e68: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000
8004e6c: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= hadc->Init.Resolution;
8004e6e: 687b ldr r3, [r7, #4]
8004e70: 681b ldr r3, [r3, #0]
8004e72: 6859 ldr r1, [r3, #4]
8004e74: 687b ldr r3, [r7, #4]
8004e76: 689a ldr r2, [r3, #8]
8004e78: 687b ldr r3, [r7, #4]
8004e7a: 681b ldr r3, [r3, #0]
8004e7c: 430a orrs r2, r1
8004e7e: 605a str r2, [r3, #4]
/* Set ADC data alignment */
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
8004e80: 687b ldr r3, [r7, #4]
8004e82: 681b ldr r3, [r3, #0]
8004e84: 689a ldr r2, [r3, #8]
8004e86: 687b ldr r3, [r7, #4]
8004e88: 681b ldr r3, [r3, #0]
8004e8a: f422 6200 bic.w r2, r2, #2048 ; 0x800
8004e8e: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.DataAlign;
8004e90: 687b ldr r3, [r7, #4]
8004e92: 681b ldr r3, [r3, #0]
8004e94: 6899 ldr r1, [r3, #8]
8004e96: 687b ldr r3, [r7, #4]
8004e98: 68da ldr r2, [r3, #12]
8004e9a: 687b ldr r3, [r7, #4]
8004e9c: 681b ldr r3, [r3, #0]
8004e9e: 430a orrs r2, r1
8004ea0: 609a str r2, [r3, #8]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8004ea2: 687b ldr r3, [r7, #4]
8004ea4: 6a9b ldr r3, [r3, #40] ; 0x28
8004ea6: 4a58 ldr r2, [pc, #352] ; (8005008 <ADC_Init+0x1f0>)
8004ea8: 4293 cmp r3, r2
8004eaa: d022 beq.n 8004ef2 <ADC_Init+0xda>
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
8004eac: 687b ldr r3, [r7, #4]
8004eae: 681b ldr r3, [r3, #0]
8004eb0: 689a ldr r2, [r3, #8]
8004eb2: 687b ldr r3, [r7, #4]
8004eb4: 681b ldr r3, [r3, #0]
8004eb6: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
8004eba: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
8004ebc: 687b ldr r3, [r7, #4]
8004ebe: 681b ldr r3, [r3, #0]
8004ec0: 6899 ldr r1, [r3, #8]
8004ec2: 687b ldr r3, [r7, #4]
8004ec4: 6a9a ldr r2, [r3, #40] ; 0x28
8004ec6: 687b ldr r3, [r7, #4]
8004ec8: 681b ldr r3, [r3, #0]
8004eca: 430a orrs r2, r1
8004ecc: 609a str r2, [r3, #8]
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
8004ece: 687b ldr r3, [r7, #4]
8004ed0: 681b ldr r3, [r3, #0]
8004ed2: 689a ldr r2, [r3, #8]
8004ed4: 687b ldr r3, [r7, #4]
8004ed6: 681b ldr r3, [r3, #0]
8004ed8: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
8004edc: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
8004ede: 687b ldr r3, [r7, #4]
8004ee0: 681b ldr r3, [r3, #0]
8004ee2: 6899 ldr r1, [r3, #8]
8004ee4: 687b ldr r3, [r7, #4]
8004ee6: 6ada ldr r2, [r3, #44] ; 0x2c
8004ee8: 687b ldr r3, [r7, #4]
8004eea: 681b ldr r3, [r3, #0]
8004eec: 430a orrs r2, r1
8004eee: 609a str r2, [r3, #8]
8004ef0: e00f b.n 8004f12 <ADC_Init+0xfa>
}
else
{
/* Reset the external trigger */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
8004ef2: 687b ldr r3, [r7, #4]
8004ef4: 681b ldr r3, [r3, #0]
8004ef6: 689a ldr r2, [r3, #8]
8004ef8: 687b ldr r3, [r7, #4]
8004efa: 681b ldr r3, [r3, #0]
8004efc: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
8004f00: 609a str r2, [r3, #8]
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
8004f02: 687b ldr r3, [r7, #4]
8004f04: 681b ldr r3, [r3, #0]
8004f06: 689a ldr r2, [r3, #8]
8004f08: 687b ldr r3, [r7, #4]
8004f0a: 681b ldr r3, [r3, #0]
8004f0c: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
8004f10: 609a str r2, [r3, #8]
}
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
8004f12: 687b ldr r3, [r7, #4]
8004f14: 681b ldr r3, [r3, #0]
8004f16: 689a ldr r2, [r3, #8]
8004f18: 687b ldr r3, [r7, #4]
8004f1a: 681b ldr r3, [r3, #0]
8004f1c: f022 0202 bic.w r2, r2, #2
8004f20: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
8004f22: 687b ldr r3, [r7, #4]
8004f24: 681b ldr r3, [r3, #0]
8004f26: 6899 ldr r1, [r3, #8]
8004f28: 687b ldr r3, [r7, #4]
8004f2a: 699b ldr r3, [r3, #24]
8004f2c: 005a lsls r2, r3, #1
8004f2e: 687b ldr r3, [r7, #4]
8004f30: 681b ldr r3, [r3, #0]
8004f32: 430a orrs r2, r1
8004f34: 609a str r2, [r3, #8]
if(hadc->Init.DiscontinuousConvMode != DISABLE)
8004f36: 687b ldr r3, [r7, #4]
8004f38: f893 3020 ldrb.w r3, [r3, #32]
8004f3c: 2b00 cmp r3, #0
8004f3e: d01b beq.n 8004f78 <ADC_Init+0x160>
{
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
/* Enable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
8004f40: 687b ldr r3, [r7, #4]
8004f42: 681b ldr r3, [r3, #0]
8004f44: 685a ldr r2, [r3, #4]
8004f46: 687b ldr r3, [r7, #4]
8004f48: 681b ldr r3, [r3, #0]
8004f4a: f442 6200 orr.w r2, r2, #2048 ; 0x800
8004f4e: 605a str r2, [r3, #4]
/* Set the number of channels to be converted in discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
8004f50: 687b ldr r3, [r7, #4]
8004f52: 681b ldr r3, [r3, #0]
8004f54: 685a ldr r2, [r3, #4]
8004f56: 687b ldr r3, [r7, #4]
8004f58: 681b ldr r3, [r3, #0]
8004f5a: f422 4260 bic.w r2, r2, #57344 ; 0xe000
8004f5e: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
8004f60: 687b ldr r3, [r7, #4]
8004f62: 681b ldr r3, [r3, #0]
8004f64: 6859 ldr r1, [r3, #4]
8004f66: 687b ldr r3, [r7, #4]
8004f68: 6a5b ldr r3, [r3, #36] ; 0x24
8004f6a: 3b01 subs r3, #1
8004f6c: 035a lsls r2, r3, #13
8004f6e: 687b ldr r3, [r7, #4]
8004f70: 681b ldr r3, [r3, #0]
8004f72: 430a orrs r2, r1
8004f74: 605a str r2, [r3, #4]
8004f76: e007 b.n 8004f88 <ADC_Init+0x170>
}
else
{
/* Disable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
8004f78: 687b ldr r3, [r7, #4]
8004f7a: 681b ldr r3, [r3, #0]
8004f7c: 685a ldr r2, [r3, #4]
8004f7e: 687b ldr r3, [r7, #4]
8004f80: 681b ldr r3, [r3, #0]
8004f82: f422 6200 bic.w r2, r2, #2048 ; 0x800
8004f86: 605a str r2, [r3, #4]
}
/* Set ADC number of conversion */
hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
8004f88: 687b ldr r3, [r7, #4]
8004f8a: 681b ldr r3, [r3, #0]
8004f8c: 6ada ldr r2, [r3, #44] ; 0x2c
8004f8e: 687b ldr r3, [r7, #4]
8004f90: 681b ldr r3, [r3, #0]
8004f92: f422 0270 bic.w r2, r2, #15728640 ; 0xf00000
8004f96: 62da str r2, [r3, #44] ; 0x2c
hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
8004f98: 687b ldr r3, [r7, #4]
8004f9a: 681b ldr r3, [r3, #0]
8004f9c: 6ad9 ldr r1, [r3, #44] ; 0x2c
8004f9e: 687b ldr r3, [r7, #4]
8004fa0: 69db ldr r3, [r3, #28]
8004fa2: 3b01 subs r3, #1
8004fa4: 051a lsls r2, r3, #20
8004fa6: 687b ldr r3, [r7, #4]
8004fa8: 681b ldr r3, [r3, #0]
8004faa: 430a orrs r2, r1
8004fac: 62da str r2, [r3, #44] ; 0x2c
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
8004fae: 687b ldr r3, [r7, #4]
8004fb0: 681b ldr r3, [r3, #0]
8004fb2: 689a ldr r2, [r3, #8]
8004fb4: 687b ldr r3, [r7, #4]
8004fb6: 681b ldr r3, [r3, #0]
8004fb8: f422 7200 bic.w r2, r2, #512 ; 0x200
8004fbc: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
8004fbe: 687b ldr r3, [r7, #4]
8004fc0: 681b ldr r3, [r3, #0]
8004fc2: 6899 ldr r1, [r3, #8]
8004fc4: 687b ldr r3, [r7, #4]
8004fc6: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
8004fca: 025a lsls r2, r3, #9
8004fcc: 687b ldr r3, [r7, #4]
8004fce: 681b ldr r3, [r3, #0]
8004fd0: 430a orrs r2, r1
8004fd2: 609a str r2, [r3, #8]
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
8004fd4: 687b ldr r3, [r7, #4]
8004fd6: 681b ldr r3, [r3, #0]
8004fd8: 689a ldr r2, [r3, #8]
8004fda: 687b ldr r3, [r7, #4]
8004fdc: 681b ldr r3, [r3, #0]
8004fde: f422 6280 bic.w r2, r2, #1024 ; 0x400
8004fe2: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
8004fe4: 687b ldr r3, [r7, #4]
8004fe6: 681b ldr r3, [r3, #0]
8004fe8: 6899 ldr r1, [r3, #8]
8004fea: 687b ldr r3, [r7, #4]
8004fec: 695b ldr r3, [r3, #20]
8004fee: 029a lsls r2, r3, #10
8004ff0: 687b ldr r3, [r7, #4]
8004ff2: 681b ldr r3, [r3, #0]
8004ff4: 430a orrs r2, r1
8004ff6: 609a str r2, [r3, #8]
}
8004ff8: bf00 nop
8004ffa: 370c adds r7, #12
8004ffc: 46bd mov sp, r7
8004ffe: f85d 7b04 ldr.w r7, [sp], #4
8005002: 4770 bx lr
8005004: 40012300 .word 0x40012300
8005008: 0f000001 .word 0x0f000001
0800500c <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800500c: b480 push {r7}
800500e: b085 sub sp, #20
8005010: af00 add r7, sp, #0
8005012: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8005014: 687b ldr r3, [r7, #4]
8005016: f003 0307 and.w r3, r3, #7
800501a: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
800501c: 4b0b ldr r3, [pc, #44] ; (800504c <__NVIC_SetPriorityGrouping+0x40>)
800501e: 68db ldr r3, [r3, #12]
8005020: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8005022: 68ba ldr r2, [r7, #8]
8005024: f64f 03ff movw r3, #63743 ; 0xf8ff
8005028: 4013 ands r3, r2
800502a: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
800502c: 68fb ldr r3, [r7, #12]
800502e: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8005030: 68bb ldr r3, [r7, #8]
8005032: 431a orrs r2, r3
reg_value = (reg_value |
8005034: 4b06 ldr r3, [pc, #24] ; (8005050 <__NVIC_SetPriorityGrouping+0x44>)
8005036: 4313 orrs r3, r2
8005038: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800503a: 4a04 ldr r2, [pc, #16] ; (800504c <__NVIC_SetPriorityGrouping+0x40>)
800503c: 68bb ldr r3, [r7, #8]
800503e: 60d3 str r3, [r2, #12]
}
8005040: bf00 nop
8005042: 3714 adds r7, #20
8005044: 46bd mov sp, r7
8005046: f85d 7b04 ldr.w r7, [sp], #4
800504a: 4770 bx lr
800504c: e000ed00 .word 0xe000ed00
8005050: 05fa0000 .word 0x05fa0000
08005054 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8005054: b480 push {r7}
8005056: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8005058: 4b04 ldr r3, [pc, #16] ; (800506c <__NVIC_GetPriorityGrouping+0x18>)
800505a: 68db ldr r3, [r3, #12]
800505c: 0a1b lsrs r3, r3, #8
800505e: f003 0307 and.w r3, r3, #7
}
8005062: 4618 mov r0, r3
8005064: 46bd mov sp, r7
8005066: f85d 7b04 ldr.w r7, [sp], #4
800506a: 4770 bx lr
800506c: e000ed00 .word 0xe000ed00
08005070 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8005070: b480 push {r7}
8005072: b083 sub sp, #12
8005074: af00 add r7, sp, #0
8005076: 4603 mov r3, r0
8005078: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800507a: f997 3007 ldrsb.w r3, [r7, #7]
800507e: 2b00 cmp r3, #0
8005080: db0b blt.n 800509a <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8005082: 79fb ldrb r3, [r7, #7]
8005084: f003 021f and.w r2, r3, #31
8005088: 4907 ldr r1, [pc, #28] ; (80050a8 <__NVIC_EnableIRQ+0x38>)
800508a: f997 3007 ldrsb.w r3, [r7, #7]
800508e: 095b lsrs r3, r3, #5
8005090: 2001 movs r0, #1
8005092: fa00 f202 lsl.w r2, r0, r2
8005096: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
800509a: bf00 nop
800509c: 370c adds r7, #12
800509e: 46bd mov sp, r7
80050a0: f85d 7b04 ldr.w r7, [sp], #4
80050a4: 4770 bx lr
80050a6: bf00 nop
80050a8: e000e100 .word 0xe000e100
080050ac <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80050ac: b480 push {r7}
80050ae: b083 sub sp, #12
80050b0: af00 add r7, sp, #0
80050b2: 4603 mov r3, r0
80050b4: 6039 str r1, [r7, #0]
80050b6: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80050b8: f997 3007 ldrsb.w r3, [r7, #7]
80050bc: 2b00 cmp r3, #0
80050be: db0a blt.n 80050d6 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80050c0: 683b ldr r3, [r7, #0]
80050c2: b2da uxtb r2, r3
80050c4: 490c ldr r1, [pc, #48] ; (80050f8 <__NVIC_SetPriority+0x4c>)
80050c6: f997 3007 ldrsb.w r3, [r7, #7]
80050ca: 0112 lsls r2, r2, #4
80050cc: b2d2 uxtb r2, r2
80050ce: 440b add r3, r1
80050d0: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80050d4: e00a b.n 80050ec <__NVIC_SetPriority+0x40>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80050d6: 683b ldr r3, [r7, #0]
80050d8: b2da uxtb r2, r3
80050da: 4908 ldr r1, [pc, #32] ; (80050fc <__NVIC_SetPriority+0x50>)
80050dc: 79fb ldrb r3, [r7, #7]
80050de: f003 030f and.w r3, r3, #15
80050e2: 3b04 subs r3, #4
80050e4: 0112 lsls r2, r2, #4
80050e6: b2d2 uxtb r2, r2
80050e8: 440b add r3, r1
80050ea: 761a strb r2, [r3, #24]
}
80050ec: bf00 nop
80050ee: 370c adds r7, #12
80050f0: 46bd mov sp, r7
80050f2: f85d 7b04 ldr.w r7, [sp], #4
80050f6: 4770 bx lr
80050f8: e000e100 .word 0xe000e100
80050fc: e000ed00 .word 0xe000ed00
08005100 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8005100: b480 push {r7}
8005102: b089 sub sp, #36 ; 0x24
8005104: af00 add r7, sp, #0
8005106: 60f8 str r0, [r7, #12]
8005108: 60b9 str r1, [r7, #8]
800510a: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
800510c: 68fb ldr r3, [r7, #12]
800510e: f003 0307 and.w r3, r3, #7
8005112: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8005114: 69fb ldr r3, [r7, #28]
8005116: f1c3 0307 rsb r3, r3, #7
800511a: 2b04 cmp r3, #4
800511c: bf28 it cs
800511e: 2304 movcs r3, #4
8005120: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8005122: 69fb ldr r3, [r7, #28]
8005124: 3304 adds r3, #4
8005126: 2b06 cmp r3, #6
8005128: d902 bls.n 8005130 <NVIC_EncodePriority+0x30>
800512a: 69fb ldr r3, [r7, #28]
800512c: 3b03 subs r3, #3
800512e: e000 b.n 8005132 <NVIC_EncodePriority+0x32>
8005130: 2300 movs r3, #0
8005132: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8005134: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
8005138: 69bb ldr r3, [r7, #24]
800513a: fa02 f303 lsl.w r3, r2, r3
800513e: 43da mvns r2, r3
8005140: 68bb ldr r3, [r7, #8]
8005142: 401a ands r2, r3
8005144: 697b ldr r3, [r7, #20]
8005146: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8005148: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
800514c: 697b ldr r3, [r7, #20]
800514e: fa01 f303 lsl.w r3, r1, r3
8005152: 43d9 mvns r1, r3
8005154: 687b ldr r3, [r7, #4]
8005156: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8005158: 4313 orrs r3, r2
);
}
800515a: 4618 mov r0, r3
800515c: 3724 adds r7, #36 ; 0x24
800515e: 46bd mov sp, r7
8005160: f85d 7b04 ldr.w r7, [sp], #4
8005164: 4770 bx lr
08005166 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8005166: b580 push {r7, lr}
8005168: b082 sub sp, #8
800516a: af00 add r7, sp, #0
800516c: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
800516e: 6878 ldr r0, [r7, #4]
8005170: f7ff ff4c bl 800500c <__NVIC_SetPriorityGrouping>
}
8005174: bf00 nop
8005176: 3708 adds r7, #8
8005178: 46bd mov sp, r7
800517a: bd80 pop {r7, pc}
0800517c <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800517c: b580 push {r7, lr}
800517e: b086 sub sp, #24
8005180: af00 add r7, sp, #0
8005182: 4603 mov r3, r0
8005184: 60b9 str r1, [r7, #8]
8005186: 607a str r2, [r7, #4]
8005188: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
800518a: 2300 movs r3, #0
800518c: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
800518e: f7ff ff61 bl 8005054 <__NVIC_GetPriorityGrouping>
8005192: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8005194: 687a ldr r2, [r7, #4]
8005196: 68b9 ldr r1, [r7, #8]
8005198: 6978 ldr r0, [r7, #20]
800519a: f7ff ffb1 bl 8005100 <NVIC_EncodePriority>
800519e: 4602 mov r2, r0
80051a0: f997 300f ldrsb.w r3, [r7, #15]
80051a4: 4611 mov r1, r2
80051a6: 4618 mov r0, r3
80051a8: f7ff ff80 bl 80050ac <__NVIC_SetPriority>
}
80051ac: bf00 nop
80051ae: 3718 adds r7, #24
80051b0: 46bd mov sp, r7
80051b2: bd80 pop {r7, pc}
080051b4 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80051b4: b580 push {r7, lr}
80051b6: b082 sub sp, #8
80051b8: af00 add r7, sp, #0
80051ba: 4603 mov r3, r0
80051bc: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80051be: f997 3007 ldrsb.w r3, [r7, #7]
80051c2: 4618 mov r0, r3
80051c4: f7ff ff54 bl 8005070 <__NVIC_EnableIRQ>
}
80051c8: bf00 nop
80051ca: 3708 adds r7, #8
80051cc: 46bd mov sp, r7
80051ce: bd80 pop {r7, pc}
080051d0 <HAL_CRC_Init>:
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
80051d0: b580 push {r7, lr}
80051d2: b082 sub sp, #8
80051d4: af00 add r7, sp, #0
80051d6: 6078 str r0, [r7, #4]
/* Check the CRC handle allocation */
if (hcrc == NULL)
80051d8: 687b ldr r3, [r7, #4]
80051da: 2b00 cmp r3, #0
80051dc: d101 bne.n 80051e2 <HAL_CRC_Init+0x12>
{
return HAL_ERROR;
80051de: 2301 movs r3, #1
80051e0: e054 b.n 800528c <HAL_CRC_Init+0xbc>
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if (hcrc->State == HAL_CRC_STATE_RESET)
80051e2: 687b ldr r3, [r7, #4]
80051e4: 7f5b ldrb r3, [r3, #29]
80051e6: b2db uxtb r3, r3
80051e8: 2b00 cmp r3, #0
80051ea: d105 bne.n 80051f8 <HAL_CRC_Init+0x28>
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
80051ec: 687b ldr r3, [r7, #4]
80051ee: 2200 movs r2, #0
80051f0: 771a strb r2, [r3, #28]
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
80051f2: 6878 ldr r0, [r7, #4]
80051f4: f7fe fe56 bl 8003ea4 <HAL_CRC_MspInit>
}
hcrc->State = HAL_CRC_STATE_BUSY;
80051f8: 687b ldr r3, [r7, #4]
80051fa: 2202 movs r2, #2
80051fc: 775a strb r2, [r3, #29]
/* check whether or not non-default generating polynomial has been
* picked up by user */
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
80051fe: 687b ldr r3, [r7, #4]
8005200: 791b ldrb r3, [r3, #4]
8005202: 2b00 cmp r3, #0
8005204: d10c bne.n 8005220 <HAL_CRC_Init+0x50>
{
/* initialize peripheral with default generating polynomial */
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
8005206: 687b ldr r3, [r7, #4]
8005208: 681b ldr r3, [r3, #0]
800520a: 4a22 ldr r2, [pc, #136] ; (8005294 <HAL_CRC_Init+0xc4>)
800520c: 615a str r2, [r3, #20]
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
800520e: 687b ldr r3, [r7, #4]
8005210: 681b ldr r3, [r3, #0]
8005212: 689a ldr r2, [r3, #8]
8005214: 687b ldr r3, [r7, #4]
8005216: 681b ldr r3, [r3, #0]
8005218: f022 0218 bic.w r2, r2, #24
800521c: 609a str r2, [r3, #8]
800521e: e00c b.n 800523a <HAL_CRC_Init+0x6a>
}
else
{
/* initialize CRC peripheral with generating polynomial defined by user */
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
8005220: 687b ldr r3, [r7, #4]
8005222: 6899 ldr r1, [r3, #8]
8005224: 687b ldr r3, [r7, #4]
8005226: 68db ldr r3, [r3, #12]
8005228: 461a mov r2, r3
800522a: 6878 ldr r0, [r7, #4]
800522c: f000 f834 bl 8005298 <HAL_CRCEx_Polynomial_Set>
8005230: 4603 mov r3, r0
8005232: 2b00 cmp r3, #0
8005234: d001 beq.n 800523a <HAL_CRC_Init+0x6a>
{
return HAL_ERROR;
8005236: 2301 movs r3, #1
8005238: e028 b.n 800528c <HAL_CRC_Init+0xbc>
}
/* check whether or not non-default CRC initial value has been
* picked up by user */
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
800523a: 687b ldr r3, [r7, #4]
800523c: 795b ldrb r3, [r3, #5]
800523e: 2b00 cmp r3, #0
8005240: d105 bne.n 800524e <HAL_CRC_Init+0x7e>
{
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
8005242: 687b ldr r3, [r7, #4]
8005244: 681b ldr r3, [r3, #0]
8005246: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800524a: 611a str r2, [r3, #16]
800524c: e004 b.n 8005258 <HAL_CRC_Init+0x88>
}
else
{
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
800524e: 687b ldr r3, [r7, #4]
8005250: 681b ldr r3, [r3, #0]
8005252: 687a ldr r2, [r7, #4]
8005254: 6912 ldr r2, [r2, #16]
8005256: 611a str r2, [r3, #16]
}
/* set input data inversion mode */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
8005258: 687b ldr r3, [r7, #4]
800525a: 681b ldr r3, [r3, #0]
800525c: 689b ldr r3, [r3, #8]
800525e: f023 0160 bic.w r1, r3, #96 ; 0x60
8005262: 687b ldr r3, [r7, #4]
8005264: 695a ldr r2, [r3, #20]
8005266: 687b ldr r3, [r7, #4]
8005268: 681b ldr r3, [r3, #0]
800526a: 430a orrs r2, r1
800526c: 609a str r2, [r3, #8]
/* set output data inversion mode */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
800526e: 687b ldr r3, [r7, #4]
8005270: 681b ldr r3, [r3, #0]
8005272: 689b ldr r3, [r3, #8]
8005274: f023 0180 bic.w r1, r3, #128 ; 0x80
8005278: 687b ldr r3, [r7, #4]
800527a: 699a ldr r2, [r3, #24]
800527c: 687b ldr r3, [r7, #4]
800527e: 681b ldr r3, [r3, #0]
8005280: 430a orrs r2, r1
8005282: 609a str r2, [r3, #8]
/* makes sure the input data format (bytes, halfwords or words stream)
* is properly specified by user */
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
8005284: 687b ldr r3, [r7, #4]
8005286: 2201 movs r2, #1
8005288: 775a strb r2, [r3, #29]
/* Return function status */
return HAL_OK;
800528a: 2300 movs r3, #0
}
800528c: 4618 mov r0, r3
800528e: 3708 adds r7, #8
8005290: 46bd mov sp, r7
8005292: bd80 pop {r7, pc}
8005294: 04c11db7 .word 0x04c11db7
08005298 <HAL_CRCEx_Polynomial_Set>:
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
8005298: b480 push {r7}
800529a: b087 sub sp, #28
800529c: af00 add r7, sp, #0
800529e: 60f8 str r0, [r7, #12]
80052a0: 60b9 str r1, [r7, #8]
80052a2: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80052a4: 2300 movs r3, #0
80052a6: 75fb strb r3, [r7, #23]
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
80052a8: 231f movs r3, #31
80052aa: 613b str r3, [r7, #16]
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
80052ac: bf00 nop
80052ae: 693b ldr r3, [r7, #16]
80052b0: 1e5a subs r2, r3, #1
80052b2: 613a str r2, [r7, #16]
80052b4: 2b00 cmp r3, #0
80052b6: d009 beq.n 80052cc <HAL_CRCEx_Polynomial_Set+0x34>
80052b8: 693b ldr r3, [r7, #16]
80052ba: f003 031f and.w r3, r3, #31
80052be: 68ba ldr r2, [r7, #8]
80052c0: fa22 f303 lsr.w r3, r2, r3
80052c4: f003 0301 and.w r3, r3, #1
80052c8: 2b00 cmp r3, #0
80052ca: d0f0 beq.n 80052ae <HAL_CRCEx_Polynomial_Set+0x16>
80052cc: 687b ldr r3, [r7, #4]
80052ce: 2b18 cmp r3, #24
80052d0: d846 bhi.n 8005360 <HAL_CRCEx_Polynomial_Set+0xc8>
80052d2: a201 add r2, pc, #4 ; (adr r2, 80052d8 <HAL_CRCEx_Polynomial_Set+0x40>)
80052d4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80052d8: 08005367 .word 0x08005367
80052dc: 08005361 .word 0x08005361
80052e0: 08005361 .word 0x08005361
80052e4: 08005361 .word 0x08005361
80052e8: 08005361 .word 0x08005361
80052ec: 08005361 .word 0x08005361
80052f0: 08005361 .word 0x08005361
80052f4: 08005361 .word 0x08005361
80052f8: 08005355 .word 0x08005355
80052fc: 08005361 .word 0x08005361
8005300: 08005361 .word 0x08005361
8005304: 08005361 .word 0x08005361
8005308: 08005361 .word 0x08005361
800530c: 08005361 .word 0x08005361
8005310: 08005361 .word 0x08005361
8005314: 08005361 .word 0x08005361
8005318: 08005349 .word 0x08005349
800531c: 08005361 .word 0x08005361
8005320: 08005361 .word 0x08005361
8005324: 08005361 .word 0x08005361
8005328: 08005361 .word 0x08005361
800532c: 08005361 .word 0x08005361
8005330: 08005361 .word 0x08005361
8005334: 08005361 .word 0x08005361
8005338: 0800533d .word 0x0800533d
}
switch (PolyLength)
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
800533c: 693b ldr r3, [r7, #16]
800533e: 2b06 cmp r3, #6
8005340: d913 bls.n 800536a <HAL_CRCEx_Polynomial_Set+0xd2>
{
status = HAL_ERROR;
8005342: 2301 movs r3, #1
8005344: 75fb strb r3, [r7, #23]
}
break;
8005346: e010 b.n 800536a <HAL_CRCEx_Polynomial_Set+0xd2>
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
8005348: 693b ldr r3, [r7, #16]
800534a: 2b07 cmp r3, #7
800534c: d90f bls.n 800536e <HAL_CRCEx_Polynomial_Set+0xd6>
{
status = HAL_ERROR;
800534e: 2301 movs r3, #1
8005350: 75fb strb r3, [r7, #23]
}
break;
8005352: e00c b.n 800536e <HAL_CRCEx_Polynomial_Set+0xd6>
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
8005354: 693b ldr r3, [r7, #16]
8005356: 2b0f cmp r3, #15
8005358: d90b bls.n 8005372 <HAL_CRCEx_Polynomial_Set+0xda>
{
status = HAL_ERROR;
800535a: 2301 movs r3, #1
800535c: 75fb strb r3, [r7, #23]
}
break;
800535e: e008 b.n 8005372 <HAL_CRCEx_Polynomial_Set+0xda>
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
status = HAL_ERROR;
8005360: 2301 movs r3, #1
8005362: 75fb strb r3, [r7, #23]
break;
8005364: e006 b.n 8005374 <HAL_CRCEx_Polynomial_Set+0xdc>
break;
8005366: bf00 nop
8005368: e004 b.n 8005374 <HAL_CRCEx_Polynomial_Set+0xdc>
break;
800536a: bf00 nop
800536c: e002 b.n 8005374 <HAL_CRCEx_Polynomial_Set+0xdc>
break;
800536e: bf00 nop
8005370: e000 b.n 8005374 <HAL_CRCEx_Polynomial_Set+0xdc>
break;
8005372: bf00 nop
}
if (status == HAL_OK)
8005374: 7dfb ldrb r3, [r7, #23]
8005376: 2b00 cmp r3, #0
8005378: d10d bne.n 8005396 <HAL_CRCEx_Polynomial_Set+0xfe>
{
/* set generating polynomial */
WRITE_REG(hcrc->Instance->POL, Pol);
800537a: 68fb ldr r3, [r7, #12]
800537c: 681b ldr r3, [r3, #0]
800537e: 68ba ldr r2, [r7, #8]
8005380: 615a str r2, [r3, #20]
/* set generating polynomial size */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
8005382: 68fb ldr r3, [r7, #12]
8005384: 681b ldr r3, [r3, #0]
8005386: 689b ldr r3, [r3, #8]
8005388: f023 0118 bic.w r1, r3, #24
800538c: 68fb ldr r3, [r7, #12]
800538e: 681b ldr r3, [r3, #0]
8005390: 687a ldr r2, [r7, #4]
8005392: 430a orrs r2, r1
8005394: 609a str r2, [r3, #8]
}
/* Return function status */
return status;
8005396: 7dfb ldrb r3, [r7, #23]
}
8005398: 4618 mov r0, r3
800539a: 371c adds r7, #28
800539c: 46bd mov sp, r7
800539e: f85d 7b04 ldr.w r7, [sp], #4
80053a2: 4770 bx lr
080053a4 <HAL_DAC_Init>:
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
{
80053a4: b580 push {r7, lr}
80053a6: b082 sub sp, #8
80053a8: af00 add r7, sp, #0
80053aa: 6078 str r0, [r7, #4]
/* Check DAC handle */
if (hdac == NULL)
80053ac: 687b ldr r3, [r7, #4]
80053ae: 2b00 cmp r3, #0
80053b0: d101 bne.n 80053b6 <HAL_DAC_Init+0x12>
{
return HAL_ERROR;
80053b2: 2301 movs r3, #1
80053b4: e014 b.n 80053e0 <HAL_DAC_Init+0x3c>
}
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
if (hdac->State == HAL_DAC_STATE_RESET)
80053b6: 687b ldr r3, [r7, #4]
80053b8: 791b ldrb r3, [r3, #4]
80053ba: b2db uxtb r3, r3
80053bc: 2b00 cmp r3, #0
80053be: d105 bne.n 80053cc <HAL_DAC_Init+0x28>
hdac->MspInitCallback = HAL_DAC_MspInit;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED;
80053c0: 687b ldr r3, [r7, #4]
80053c2: 2200 movs r2, #0
80053c4: 715a strb r2, [r3, #5]
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* Init the low level hardware */
hdac->MspInitCallback(hdac);
#else
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
80053c6: 6878 ldr r0, [r7, #4]
80053c8: f7fe fd8c bl 8003ee4 <HAL_DAC_MspInit>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_BUSY;
80053cc: 687b ldr r3, [r7, #4]
80053ce: 2202 movs r2, #2
80053d0: 711a strb r2, [r3, #4]
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
80053d2: 687b ldr r3, [r7, #4]
80053d4: 2200 movs r2, #0
80053d6: 611a str r2, [r3, #16]
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_READY;
80053d8: 687b ldr r3, [r7, #4]
80053da: 2201 movs r2, #1
80053dc: 711a strb r2, [r3, #4]
/* Return function status */
return HAL_OK;
80053de: 2300 movs r3, #0
}
80053e0: 4618 mov r0, r3
80053e2: 3708 adds r7, #8
80053e4: 46bd mov sp, r7
80053e6: bd80 pop {r7, pc}
080053e8 <HAL_DAC_IRQHandler>:
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
{
80053e8: b580 push {r7, lr}
80053ea: b082 sub sp, #8
80053ec: af00 add r7, sp, #0
80053ee: 6078 str r0, [r7, #4]
if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
80053f0: 687b ldr r3, [r7, #4]
80053f2: 681b ldr r3, [r3, #0]
80053f4: 681b ldr r3, [r3, #0]
80053f6: f403 5300 and.w r3, r3, #8192 ; 0x2000
80053fa: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
80053fe: d120 bne.n 8005442 <HAL_DAC_IRQHandler+0x5a>
{
/* Check underrun flag of DAC channel 1 */
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
8005400: 687b ldr r3, [r7, #4]
8005402: 681b ldr r3, [r3, #0]
8005404: 6b5b ldr r3, [r3, #52] ; 0x34
8005406: f403 5300 and.w r3, r3, #8192 ; 0x2000
800540a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800540e: d118 bne.n 8005442 <HAL_DAC_IRQHandler+0x5a>
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
8005410: 687b ldr r3, [r7, #4]
8005412: 2204 movs r2, #4
8005414: 711a strb r2, [r3, #4]
/* Set DAC error code to channel1 DMA underrun error */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
8005416: 687b ldr r3, [r7, #4]
8005418: 691b ldr r3, [r3, #16]
800541a: f043 0201 orr.w r2, r3, #1
800541e: 687b ldr r3, [r7, #4]
8005420: 611a str r2, [r3, #16]
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
8005422: 687b ldr r3, [r7, #4]
8005424: 681b ldr r3, [r3, #0]
8005426: f44f 5200 mov.w r2, #8192 ; 0x2000
800542a: 635a str r2, [r3, #52] ; 0x34
/* Disable the selected DAC channel1 DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
800542c: 687b ldr r3, [r7, #4]
800542e: 681b ldr r3, [r3, #0]
8005430: 681a ldr r2, [r3, #0]
8005432: 687b ldr r3, [r7, #4]
8005434: 681b ldr r3, [r3, #0]
8005436: f422 5280 bic.w r2, r2, #4096 ; 0x1000
800543a: 601a str r2, [r3, #0]
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh1(hdac);
#else
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
800543c: 6878 ldr r0, [r7, #4]
800543e: f000 f82d bl 800549c <HAL_DAC_DMAUnderrunCallbackCh1>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
8005442: 687b ldr r3, [r7, #4]
8005444: 681b ldr r3, [r3, #0]
8005446: 681b ldr r3, [r3, #0]
8005448: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
800544c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
8005450: d120 bne.n 8005494 <HAL_DAC_IRQHandler+0xac>
{
/* Check underrun flag of DAC channel 2 */
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
8005452: 687b ldr r3, [r7, #4]
8005454: 681b ldr r3, [r3, #0]
8005456: 6b5b ldr r3, [r3, #52] ; 0x34
8005458: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
800545c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
8005460: d118 bne.n 8005494 <HAL_DAC_IRQHandler+0xac>
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
8005462: 687b ldr r3, [r7, #4]
8005464: 2204 movs r2, #4
8005466: 711a strb r2, [r3, #4]
/* Set DAC error code to channel2 DMA underrun error */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
8005468: 687b ldr r3, [r7, #4]
800546a: 691b ldr r3, [r3, #16]
800546c: f043 0202 orr.w r2, r3, #2
8005470: 687b ldr r3, [r7, #4]
8005472: 611a str r2, [r3, #16]
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
8005474: 687b ldr r3, [r7, #4]
8005476: 681b ldr r3, [r3, #0]
8005478: f04f 5200 mov.w r2, #536870912 ; 0x20000000
800547c: 635a str r2, [r3, #52] ; 0x34
/* Disable the selected DAC channel2 DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
800547e: 687b ldr r3, [r7, #4]
8005480: 681b ldr r3, [r3, #0]
8005482: 681a ldr r2, [r3, #0]
8005484: 687b ldr r3, [r7, #4]
8005486: 681b ldr r3, [r3, #0]
8005488: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000
800548c: 601a str r2, [r3, #0]
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh2(hdac);
#else
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
800548e: 6878 ldr r0, [r7, #4]
8005490: f000 f85d bl 800554e <HAL_DACEx_DMAUnderrunCallbackCh2>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
}
8005494: bf00 nop
8005496: 3708 adds r7, #8
8005498: 46bd mov sp, r7
800549a: bd80 pop {r7, pc}
0800549c <HAL_DAC_DMAUnderrunCallbackCh1>:
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
{
800549c: b480 push {r7}
800549e: b083 sub sp, #12
80054a0: af00 add r7, sp, #0
80054a2: 6078 str r0, [r7, #4]
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
*/
}
80054a4: bf00 nop
80054a6: 370c adds r7, #12
80054a8: 46bd mov sp, r7
80054aa: f85d 7b04 ldr.w r7, [sp], #4
80054ae: 4770 bx lr
080054b0 <HAL_DAC_ConfigChannel>:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
80054b0: b480 push {r7}
80054b2: b087 sub sp, #28
80054b4: af00 add r7, sp, #0
80054b6: 60f8 str r0, [r7, #12]
80054b8: 60b9 str r1, [r7, #8]
80054ba: 607a str r2, [r7, #4]
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
80054bc: 68fb ldr r3, [r7, #12]
80054be: 795b ldrb r3, [r3, #5]
80054c0: 2b01 cmp r3, #1
80054c2: d101 bne.n 80054c8 <HAL_DAC_ConfigChannel+0x18>
80054c4: 2302 movs r3, #2
80054c6: e03c b.n 8005542 <HAL_DAC_ConfigChannel+0x92>
80054c8: 68fb ldr r3, [r7, #12]
80054ca: 2201 movs r2, #1
80054cc: 715a strb r2, [r3, #5]
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
80054ce: 68fb ldr r3, [r7, #12]
80054d0: 2202 movs r2, #2
80054d2: 711a strb r2, [r3, #4]
/* Get the DAC CR value */
tmpreg1 = hdac->Instance->CR;
80054d4: 68fb ldr r3, [r7, #12]
80054d6: 681b ldr r3, [r3, #0]
80054d8: 681b ldr r3, [r3, #0]
80054da: 617b str r3, [r7, #20]
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << (Channel & 0x10UL));
80054dc: 687b ldr r3, [r7, #4]
80054de: f003 0310 and.w r3, r3, #16
80054e2: f640 72fe movw r2, #4094 ; 0xffe
80054e6: fa02 f303 lsl.w r3, r2, r3
80054ea: 43db mvns r3, r3
80054ec: 697a ldr r2, [r7, #20]
80054ee: 4013 ands r3, r2
80054f0: 617b str r3, [r7, #20]
/* Configure for the selected DAC channel: buffer output, trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
80054f2: 68bb ldr r3, [r7, #8]
80054f4: 681a ldr r2, [r3, #0]
80054f6: 68bb ldr r3, [r7, #8]
80054f8: 685b ldr r3, [r3, #4]
80054fa: 4313 orrs r3, r2
80054fc: 613b str r3, [r7, #16]
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
80054fe: 687b ldr r3, [r7, #4]
8005500: f003 0310 and.w r3, r3, #16
8005504: 693a ldr r2, [r7, #16]
8005506: fa02 f303 lsl.w r3, r2, r3
800550a: 697a ldr r2, [r7, #20]
800550c: 4313 orrs r3, r2
800550e: 617b str r3, [r7, #20]
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
8005510: 68fb ldr r3, [r7, #12]
8005512: 681b ldr r3, [r3, #0]
8005514: 697a ldr r2, [r7, #20]
8005516: 601a str r2, [r3, #0]
/* Disable wave generation */
CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
8005518: 68fb ldr r3, [r7, #12]
800551a: 681b ldr r3, [r3, #0]
800551c: 6819 ldr r1, [r3, #0]
800551e: 687b ldr r3, [r7, #4]
8005520: f003 0310 and.w r3, r3, #16
8005524: 22c0 movs r2, #192 ; 0xc0
8005526: fa02 f303 lsl.w r3, r2, r3
800552a: 43da mvns r2, r3
800552c: 68fb ldr r3, [r7, #12]
800552e: 681b ldr r3, [r3, #0]
8005530: 400a ands r2, r1
8005532: 601a str r2, [r3, #0]
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
8005534: 68fb ldr r3, [r7, #12]
8005536: 2201 movs r2, #1
8005538: 711a strb r2, [r3, #4]
/* Process unlocked */
__HAL_UNLOCK(hdac);
800553a: 68fb ldr r3, [r7, #12]
800553c: 2200 movs r2, #0
800553e: 715a strb r2, [r3, #5]
/* Return function status */
return HAL_OK;
8005540: 2300 movs r3, #0
}
8005542: 4618 mov r0, r3
8005544: 371c adds r7, #28
8005546: 46bd mov sp, r7
8005548: f85d 7b04 ldr.w r7, [sp], #4
800554c: 4770 bx lr
0800554e <HAL_DACEx_DMAUnderrunCallbackCh2>:
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
{
800554e: b480 push {r7}
8005550: b083 sub sp, #12
8005552: af00 add r7, sp, #0
8005554: 6078 str r0, [r7, #4]
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
*/
}
8005556: bf00 nop
8005558: 370c adds r7, #12
800555a: 46bd mov sp, r7
800555c: f85d 7b04 ldr.w r7, [sp], #4
8005560: 4770 bx lr
...
08005564 <HAL_DMA_Init>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
8005564: b580 push {r7, lr}
8005566: b086 sub sp, #24
8005568: af00 add r7, sp, #0
800556a: 6078 str r0, [r7, #4]
uint32_t tmp = 0U;
800556c: 2300 movs r3, #0
800556e: 617b str r3, [r7, #20]
uint32_t tickstart = HAL_GetTick();
8005570: f7ff f92e bl 80047d0 <HAL_GetTick>
8005574: 6138 str r0, [r7, #16]
DMA_Base_Registers *regs;
/* Check the DMA peripheral state */
if(hdma == NULL)
8005576: 687b ldr r3, [r7, #4]
8005578: 2b00 cmp r3, #0
800557a: d101 bne.n 8005580 <HAL_DMA_Init+0x1c>
{
return HAL_ERROR;
800557c: 2301 movs r3, #1
800557e: e099 b.n 80056b4 <HAL_DMA_Init+0x150>
assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
}
/* Allocate lock resource */
__HAL_UNLOCK(hdma);
8005580: 687b ldr r3, [r7, #4]
8005582: 2200 movs r2, #0
8005584: f883 2034 strb.w r2, [r3, #52] ; 0x34
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8005588: 687b ldr r3, [r7, #4]
800558a: 2202 movs r2, #2
800558c: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
8005590: 687b ldr r3, [r7, #4]
8005592: 681b ldr r3, [r3, #0]
8005594: 681a ldr r2, [r3, #0]
8005596: 687b ldr r3, [r7, #4]
8005598: 681b ldr r3, [r3, #0]
800559a: f022 0201 bic.w r2, r2, #1
800559e: 601a str r2, [r3, #0]
/* Check if the DMA Stream is effectively disabled */
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
80055a0: e00f b.n 80055c2 <HAL_DMA_Init+0x5e>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
80055a2: f7ff f915 bl 80047d0 <HAL_GetTick>
80055a6: 4602 mov r2, r0
80055a8: 693b ldr r3, [r7, #16]
80055aa: 1ad3 subs r3, r2, r3
80055ac: 2b05 cmp r3, #5
80055ae: d908 bls.n 80055c2 <HAL_DMA_Init+0x5e>
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
80055b0: 687b ldr r3, [r7, #4]
80055b2: 2220 movs r2, #32
80055b4: 655a str r2, [r3, #84] ; 0x54
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_TIMEOUT;
80055b6: 687b ldr r3, [r7, #4]
80055b8: 2203 movs r2, #3
80055ba: f883 2035 strb.w r2, [r3, #53] ; 0x35
return HAL_TIMEOUT;
80055be: 2303 movs r3, #3
80055c0: e078 b.n 80056b4 <HAL_DMA_Init+0x150>
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
80055c2: 687b ldr r3, [r7, #4]
80055c4: 681b ldr r3, [r3, #0]
80055c6: 681b ldr r3, [r3, #0]
80055c8: f003 0301 and.w r3, r3, #1
80055cc: 2b00 cmp r3, #0
80055ce: d1e8 bne.n 80055a2 <HAL_DMA_Init+0x3e>
}
}
/* Get the CR register value */
tmp = hdma->Instance->CR;
80055d0: 687b ldr r3, [r7, #4]
80055d2: 681b ldr r3, [r3, #0]
80055d4: 681b ldr r3, [r3, #0]
80055d6: 617b str r3, [r7, #20]
/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
80055d8: 697a ldr r2, [r7, #20]
80055da: 4b38 ldr r3, [pc, #224] ; (80056bc <HAL_DMA_Init+0x158>)
80055dc: 4013 ands r3, r2
80055de: 617b str r3, [r7, #20]
DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
/* Prepare the DMA Stream configuration */
tmp |= hdma->Init.Channel | hdma->Init.Direction |
80055e0: 687b ldr r3, [r7, #4]
80055e2: 685a ldr r2, [r3, #4]
80055e4: 687b ldr r3, [r7, #4]
80055e6: 689b ldr r3, [r3, #8]
80055e8: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
80055ea: 687b ldr r3, [r7, #4]
80055ec: 68db ldr r3, [r3, #12]
tmp |= hdma->Init.Channel | hdma->Init.Direction |
80055ee: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
80055f0: 687b ldr r3, [r7, #4]
80055f2: 691b ldr r3, [r3, #16]
80055f4: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
80055f6: 687b ldr r3, [r7, #4]
80055f8: 695b ldr r3, [r3, #20]
hdma->Init.PeriphInc | hdma->Init.MemInc |
80055fa: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
80055fc: 687b ldr r3, [r7, #4]
80055fe: 699b ldr r3, [r3, #24]
8005600: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8005602: 687b ldr r3, [r7, #4]
8005604: 69db ldr r3, [r3, #28]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8005606: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8005608: 687b ldr r3, [r7, #4]
800560a: 6a1b ldr r3, [r3, #32]
800560c: 4313 orrs r3, r2
tmp |= hdma->Init.Channel | hdma->Init.Direction |
800560e: 697a ldr r2, [r7, #20]
8005610: 4313 orrs r3, r2
8005612: 617b str r3, [r7, #20]
/* the Memory burst and peripheral burst are not used when the FIFO is disabled */
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
8005614: 687b ldr r3, [r7, #4]
8005616: 6a5b ldr r3, [r3, #36] ; 0x24
8005618: 2b04 cmp r3, #4
800561a: d107 bne.n 800562c <HAL_DMA_Init+0xc8>
{
/* Get memory burst and peripheral burst */
tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
800561c: 687b ldr r3, [r7, #4]
800561e: 6ada ldr r2, [r3, #44] ; 0x2c
8005620: 687b ldr r3, [r7, #4]
8005622: 6b1b ldr r3, [r3, #48] ; 0x30
8005624: 4313 orrs r3, r2
8005626: 697a ldr r2, [r7, #20]
8005628: 4313 orrs r3, r2
800562a: 617b str r3, [r7, #20]
}
/* Write to DMA Stream CR register */
hdma->Instance->CR = tmp;
800562c: 687b ldr r3, [r7, #4]
800562e: 681b ldr r3, [r3, #0]
8005630: 697a ldr r2, [r7, #20]
8005632: 601a str r2, [r3, #0]
/* Get the FCR register value */
tmp = hdma->Instance->FCR;
8005634: 687b ldr r3, [r7, #4]
8005636: 681b ldr r3, [r3, #0]
8005638: 695b ldr r3, [r3, #20]
800563a: 617b str r3, [r7, #20]
/* Clear Direct mode and FIFO threshold bits */
tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
800563c: 697b ldr r3, [r7, #20]
800563e: f023 0307 bic.w r3, r3, #7
8005642: 617b str r3, [r7, #20]
/* Prepare the DMA Stream FIFO configuration */
tmp |= hdma->Init.FIFOMode;
8005644: 687b ldr r3, [r7, #4]
8005646: 6a5b ldr r3, [r3, #36] ; 0x24
8005648: 697a ldr r2, [r7, #20]
800564a: 4313 orrs r3, r2
800564c: 617b str r3, [r7, #20]
/* The FIFO threshold is not used when the FIFO mode is disabled */
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
800564e: 687b ldr r3, [r7, #4]
8005650: 6a5b ldr r3, [r3, #36] ; 0x24
8005652: 2b04 cmp r3, #4
8005654: d117 bne.n 8005686 <HAL_DMA_Init+0x122>
{
/* Get the FIFO threshold */
tmp |= hdma->Init.FIFOThreshold;
8005656: 687b ldr r3, [r7, #4]
8005658: 6a9b ldr r3, [r3, #40] ; 0x28
800565a: 697a ldr r2, [r7, #20]
800565c: 4313 orrs r3, r2
800565e: 617b str r3, [r7, #20]
/* Check compatibility between FIFO threshold level and size of the memory burst */
/* for INCR4, INCR8, INCR16 bursts */
if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
8005660: 687b ldr r3, [r7, #4]
8005662: 6adb ldr r3, [r3, #44] ; 0x2c
8005664: 2b00 cmp r3, #0
8005666: d00e beq.n 8005686 <HAL_DMA_Init+0x122>
{
if (DMA_CheckFifoParam(hdma) != HAL_OK)
8005668: 6878 ldr r0, [r7, #4]
800566a: f000 f8bd bl 80057e8 <DMA_CheckFifoParam>
800566e: 4603 mov r3, r0
8005670: 2b00 cmp r3, #0
8005672: d008 beq.n 8005686 <HAL_DMA_Init+0x122>
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
8005674: 687b ldr r3, [r7, #4]
8005676: 2240 movs r2, #64 ; 0x40
8005678: 655a str r2, [r3, #84] ; 0x54
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
800567a: 687b ldr r3, [r7, #4]
800567c: 2201 movs r2, #1
800567e: f883 2035 strb.w r2, [r3, #53] ; 0x35
return HAL_ERROR;
8005682: 2301 movs r3, #1
8005684: e016 b.n 80056b4 <HAL_DMA_Init+0x150>
}
}
}
/* Write to DMA Stream FCR */
hdma->Instance->FCR = tmp;
8005686: 687b ldr r3, [r7, #4]
8005688: 681b ldr r3, [r3, #0]
800568a: 697a ldr r2, [r7, #20]
800568c: 615a str r2, [r3, #20]
/* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
800568e: 6878 ldr r0, [r7, #4]
8005690: f000 f874 bl 800577c <DMA_CalcBaseAndBitshift>
8005694: 4603 mov r3, r0
8005696: 60fb str r3, [r7, #12]
/* Clear all interrupt flags */
regs->IFCR = 0x3FU << hdma->StreamIndex;
8005698: 687b ldr r3, [r7, #4]
800569a: 6ddb ldr r3, [r3, #92] ; 0x5c
800569c: 223f movs r2, #63 ; 0x3f
800569e: 409a lsls r2, r3
80056a0: 68fb ldr r3, [r7, #12]
80056a2: 609a str r2, [r3, #8]
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
80056a4: 687b ldr r3, [r7, #4]
80056a6: 2200 movs r2, #0
80056a8: 655a str r2, [r3, #84] ; 0x54
/* Initialize the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80056aa: 687b ldr r3, [r7, #4]
80056ac: 2201 movs r2, #1
80056ae: f883 2035 strb.w r2, [r3, #53] ; 0x35
return HAL_OK;
80056b2: 2300 movs r3, #0
}
80056b4: 4618 mov r0, r3
80056b6: 3718 adds r7, #24
80056b8: 46bd mov sp, r7
80056ba: bd80 pop {r7, pc}
80056bc: f010803f .word 0xf010803f
080056c0 <HAL_DMA_DeInit>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
80056c0: b580 push {r7, lr}
80056c2: b084 sub sp, #16
80056c4: af00 add r7, sp, #0
80056c6: 6078 str r0, [r7, #4]
DMA_Base_Registers *regs;
/* Check the DMA peripheral state */
if(hdma == NULL)
80056c8: 687b ldr r3, [r7, #4]
80056ca: 2b00 cmp r3, #0
80056cc: d101 bne.n 80056d2 <HAL_DMA_DeInit+0x12>
{
return HAL_ERROR;
80056ce: 2301 movs r3, #1
80056d0: e050 b.n 8005774 <HAL_DMA_DeInit+0xb4>
}
/* Check the DMA peripheral state */
if(hdma->State == HAL_DMA_STATE_BUSY)
80056d2: 687b ldr r3, [r7, #4]
80056d4: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
80056d8: b2db uxtb r3, r3
80056da: 2b02 cmp r3, #2
80056dc: d101 bne.n 80056e2 <HAL_DMA_DeInit+0x22>
{
/* Return error status */
return HAL_BUSY;
80056de: 2302 movs r3, #2
80056e0: e048 b.n 8005774 <HAL_DMA_DeInit+0xb4>
/* Check the parameters */
assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
/* Disable the selected DMA Streamx */
__HAL_DMA_DISABLE(hdma);
80056e2: 687b ldr r3, [r7, #4]
80056e4: 681b ldr r3, [r3, #0]
80056e6: 681a ldr r2, [r3, #0]
80056e8: 687b ldr r3, [r7, #4]
80056ea: 681b ldr r3, [r3, #0]
80056ec: f022 0201 bic.w r2, r2, #1
80056f0: 601a str r2, [r3, #0]
/* Reset DMA Streamx control register */
hdma->Instance->CR = 0U;
80056f2: 687b ldr r3, [r7, #4]
80056f4: 681b ldr r3, [r3, #0]
80056f6: 2200 movs r2, #0
80056f8: 601a str r2, [r3, #0]
/* Reset DMA Streamx number of data to transfer register */
hdma->Instance->NDTR = 0U;
80056fa: 687b ldr r3, [r7, #4]
80056fc: 681b ldr r3, [r3, #0]
80056fe: 2200 movs r2, #0
8005700: 605a str r2, [r3, #4]
/* Reset DMA Streamx peripheral address register */
hdma->Instance->PAR = 0U;
8005702: 687b ldr r3, [r7, #4]
8005704: 681b ldr r3, [r3, #0]
8005706: 2200 movs r2, #0
8005708: 609a str r2, [r3, #8]
/* Reset DMA Streamx memory 0 address register */
hdma->Instance->M0AR = 0U;
800570a: 687b ldr r3, [r7, #4]
800570c: 681b ldr r3, [r3, #0]
800570e: 2200 movs r2, #0
8005710: 60da str r2, [r3, #12]
/* Reset DMA Streamx memory 1 address register */
hdma->Instance->M1AR = 0U;
8005712: 687b ldr r3, [r7, #4]
8005714: 681b ldr r3, [r3, #0]
8005716: 2200 movs r2, #0
8005718: 611a str r2, [r3, #16]
/* Reset DMA Streamx FIFO control register */
hdma->Instance->FCR = (uint32_t)0x00000021U;
800571a: 687b ldr r3, [r7, #4]
800571c: 681b ldr r3, [r3, #0]
800571e: 2221 movs r2, #33 ; 0x21
8005720: 615a str r2, [r3, #20]
/* Get DMA steam Base Address */
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
8005722: 6878 ldr r0, [r7, #4]
8005724: f000 f82a bl 800577c <DMA_CalcBaseAndBitshift>
8005728: 4603 mov r3, r0
800572a: 60fb str r3, [r7, #12]
/* Clear all interrupt flags at correct offset within the register */
regs->IFCR = 0x3FU << hdma->StreamIndex;
800572c: 687b ldr r3, [r7, #4]
800572e: 6ddb ldr r3, [r3, #92] ; 0x5c
8005730: 223f movs r2, #63 ; 0x3f
8005732: 409a lsls r2, r3
8005734: 68fb ldr r3, [r7, #12]
8005736: 609a str r2, [r3, #8]
/* Clean all callbacks */
hdma->XferCpltCallback = NULL;
8005738: 687b ldr r3, [r7, #4]
800573a: 2200 movs r2, #0
800573c: 63da str r2, [r3, #60] ; 0x3c
hdma->XferHalfCpltCallback = NULL;
800573e: 687b ldr r3, [r7, #4]
8005740: 2200 movs r2, #0
8005742: 641a str r2, [r3, #64] ; 0x40
hdma->XferM1CpltCallback = NULL;
8005744: 687b ldr r3, [r7, #4]
8005746: 2200 movs r2, #0
8005748: 645a str r2, [r3, #68] ; 0x44
hdma->XferM1HalfCpltCallback = NULL;
800574a: 687b ldr r3, [r7, #4]
800574c: 2200 movs r2, #0
800574e: 649a str r2, [r3, #72] ; 0x48
hdma->XferErrorCallback = NULL;
8005750: 687b ldr r3, [r7, #4]
8005752: 2200 movs r2, #0
8005754: 64da str r2, [r3, #76] ; 0x4c
hdma->XferAbortCallback = NULL;
8005756: 687b ldr r3, [r7, #4]
8005758: 2200 movs r2, #0
800575a: 651a str r2, [r3, #80] ; 0x50
/* Reset the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
800575c: 687b ldr r3, [r7, #4]
800575e: 2200 movs r2, #0
8005760: 655a str r2, [r3, #84] ; 0x54
/* Reset the DMA state */
hdma->State = HAL_DMA_STATE_RESET;
8005762: 687b ldr r3, [r7, #4]
8005764: 2200 movs r2, #0
8005766: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Release Lock */
__HAL_UNLOCK(hdma);
800576a: 687b ldr r3, [r7, #4]
800576c: 2200 movs r2, #0
800576e: f883 2034 strb.w r2, [r3, #52] ; 0x34
return HAL_OK;
8005772: 2300 movs r3, #0
}
8005774: 4618 mov r0, r3
8005776: 3710 adds r7, #16
8005778: 46bd mov sp, r7
800577a: bd80 pop {r7, pc}
0800577c <DMA_CalcBaseAndBitshift>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval Stream base address
*/
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
{
800577c: b480 push {r7}
800577e: b085 sub sp, #20
8005780: af00 add r7, sp, #0
8005782: 6078 str r0, [r7, #4]
uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
8005784: 687b ldr r3, [r7, #4]
8005786: 681b ldr r3, [r3, #0]
8005788: b2db uxtb r3, r3
800578a: 3b10 subs r3, #16
800578c: 4a13 ldr r2, [pc, #76] ; (80057dc <DMA_CalcBaseAndBitshift+0x60>)
800578e: fba2 2303 umull r2, r3, r2, r3
8005792: 091b lsrs r3, r3, #4
8005794: 60fb str r3, [r7, #12]
/* lookup table for necessary bitshift of flags within status registers */
static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
hdma->StreamIndex = flagBitshiftOffset[stream_number];
8005796: 4a12 ldr r2, [pc, #72] ; (80057e0 <DMA_CalcBaseAndBitshift+0x64>)
8005798: 68fb ldr r3, [r7, #12]
800579a: 4413 add r3, r2
800579c: 781b ldrb r3, [r3, #0]
800579e: 461a mov r2, r3
80057a0: 687b ldr r3, [r7, #4]
80057a2: 65da str r2, [r3, #92] ; 0x5c
if (stream_number > 3U)
80057a4: 68fb ldr r3, [r7, #12]
80057a6: 2b03 cmp r3, #3
80057a8: d908 bls.n 80057bc <DMA_CalcBaseAndBitshift+0x40>
{
/* return pointer to HISR and HIFCR */
hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
80057aa: 687b ldr r3, [r7, #4]
80057ac: 681b ldr r3, [r3, #0]
80057ae: 461a mov r2, r3
80057b0: 4b0c ldr r3, [pc, #48] ; (80057e4 <DMA_CalcBaseAndBitshift+0x68>)
80057b2: 4013 ands r3, r2
80057b4: 1d1a adds r2, r3, #4
80057b6: 687b ldr r3, [r7, #4]
80057b8: 659a str r2, [r3, #88] ; 0x58
80057ba: e006 b.n 80057ca <DMA_CalcBaseAndBitshift+0x4e>
}
else
{
/* return pointer to LISR and LIFCR */
hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
80057bc: 687b ldr r3, [r7, #4]
80057be: 681b ldr r3, [r3, #0]
80057c0: 461a mov r2, r3
80057c2: 4b08 ldr r3, [pc, #32] ; (80057e4 <DMA_CalcBaseAndBitshift+0x68>)
80057c4: 4013 ands r3, r2
80057c6: 687a ldr r2, [r7, #4]
80057c8: 6593 str r3, [r2, #88] ; 0x58
}
return hdma->StreamBaseAddress;
80057ca: 687b ldr r3, [r7, #4]
80057cc: 6d9b ldr r3, [r3, #88] ; 0x58
}
80057ce: 4618 mov r0, r3
80057d0: 3714 adds r7, #20
80057d2: 46bd mov sp, r7
80057d4: f85d 7b04 ldr.w r7, [sp], #4
80057d8: 4770 bx lr
80057da: bf00 nop
80057dc: aaaaaaab .word 0xaaaaaaab
80057e0: 08020f14 .word 0x08020f14
80057e4: fffffc00 .word 0xfffffc00
080057e8 <DMA_CheckFifoParam>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{
80057e8: b480 push {r7}
80057ea: b085 sub sp, #20
80057ec: af00 add r7, sp, #0
80057ee: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80057f0: 2300 movs r3, #0
80057f2: 73fb strb r3, [r7, #15]
uint32_t tmp = hdma->Init.FIFOThreshold;
80057f4: 687b ldr r3, [r7, #4]
80057f6: 6a9b ldr r3, [r3, #40] ; 0x28
80057f8: 60bb str r3, [r7, #8]
/* Memory Data size equal to Byte */
if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
80057fa: 687b ldr r3, [r7, #4]
80057fc: 699b ldr r3, [r3, #24]
80057fe: 2b00 cmp r3, #0
8005800: d11f bne.n 8005842 <DMA_CheckFifoParam+0x5a>
8005802: 68bb ldr r3, [r7, #8]
8005804: 2b03 cmp r3, #3
8005806: d856 bhi.n 80058b6 <DMA_CheckFifoParam+0xce>
8005808: a201 add r2, pc, #4 ; (adr r2, 8005810 <DMA_CheckFifoParam+0x28>)
800580a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800580e: bf00 nop
8005810: 08005821 .word 0x08005821
8005814: 08005833 .word 0x08005833
8005818: 08005821 .word 0x08005821
800581c: 080058b7 .word 0x080058b7
{
switch (tmp)
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
8005820: 687b ldr r3, [r7, #4]
8005822: 6adb ldr r3, [r3, #44] ; 0x2c
8005824: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8005828: 2b00 cmp r3, #0
800582a: d046 beq.n 80058ba <DMA_CheckFifoParam+0xd2>
{
status = HAL_ERROR;
800582c: 2301 movs r3, #1
800582e: 73fb strb r3, [r7, #15]
}
break;
8005830: e043 b.n 80058ba <DMA_CheckFifoParam+0xd2>
case DMA_FIFO_THRESHOLD_HALFFULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
8005832: 687b ldr r3, [r7, #4]
8005834: 6adb ldr r3, [r3, #44] ; 0x2c
8005836: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000
800583a: d140 bne.n 80058be <DMA_CheckFifoParam+0xd6>
{
status = HAL_ERROR;
800583c: 2301 movs r3, #1
800583e: 73fb strb r3, [r7, #15]
}
break;
8005840: e03d b.n 80058be <DMA_CheckFifoParam+0xd6>
break;
}
}
/* Memory Data size equal to Half-Word */
else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
8005842: 687b ldr r3, [r7, #4]
8005844: 699b ldr r3, [r3, #24]
8005846: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800584a: d121 bne.n 8005890 <DMA_CheckFifoParam+0xa8>
800584c: 68bb ldr r3, [r7, #8]
800584e: 2b03 cmp r3, #3
8005850: d837 bhi.n 80058c2 <DMA_CheckFifoParam+0xda>
8005852: a201 add r2, pc, #4 ; (adr r2, 8005858 <DMA_CheckFifoParam+0x70>)
8005854: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005858: 08005869 .word 0x08005869
800585c: 0800586f .word 0x0800586f
8005860: 08005869 .word 0x08005869
8005864: 08005881 .word 0x08005881
{
switch (tmp)
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
status = HAL_ERROR;
8005868: 2301 movs r3, #1
800586a: 73fb strb r3, [r7, #15]
break;
800586c: e030 b.n 80058d0 <DMA_CheckFifoParam+0xe8>
case DMA_FIFO_THRESHOLD_HALFFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
800586e: 687b ldr r3, [r7, #4]
8005870: 6adb ldr r3, [r3, #44] ; 0x2c
8005872: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8005876: 2b00 cmp r3, #0
8005878: d025 beq.n 80058c6 <DMA_CheckFifoParam+0xde>
{
status = HAL_ERROR;
800587a: 2301 movs r3, #1
800587c: 73fb strb r3, [r7, #15]
}
break;
800587e: e022 b.n 80058c6 <DMA_CheckFifoParam+0xde>
case DMA_FIFO_THRESHOLD_FULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
8005880: 687b ldr r3, [r7, #4]
8005882: 6adb ldr r3, [r3, #44] ; 0x2c
8005884: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000
8005888: d11f bne.n 80058ca <DMA_CheckFifoParam+0xe2>
{
status = HAL_ERROR;
800588a: 2301 movs r3, #1
800588c: 73fb strb r3, [r7, #15]
}
break;
800588e: e01c b.n 80058ca <DMA_CheckFifoParam+0xe2>
}
/* Memory Data size equal to Word */
else
{
switch (tmp)
8005890: 68bb ldr r3, [r7, #8]
8005892: 2b02 cmp r3, #2
8005894: d903 bls.n 800589e <DMA_CheckFifoParam+0xb6>
8005896: 68bb ldr r3, [r7, #8]
8005898: 2b03 cmp r3, #3
800589a: d003 beq.n 80058a4 <DMA_CheckFifoParam+0xbc>
{
status = HAL_ERROR;
}
break;
default:
break;
800589c: e018 b.n 80058d0 <DMA_CheckFifoParam+0xe8>
status = HAL_ERROR;
800589e: 2301 movs r3, #1
80058a0: 73fb strb r3, [r7, #15]
break;
80058a2: e015 b.n 80058d0 <DMA_CheckFifoParam+0xe8>
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
80058a4: 687b ldr r3, [r7, #4]
80058a6: 6adb ldr r3, [r3, #44] ; 0x2c
80058a8: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
80058ac: 2b00 cmp r3, #0
80058ae: d00e beq.n 80058ce <DMA_CheckFifoParam+0xe6>
status = HAL_ERROR;
80058b0: 2301 movs r3, #1
80058b2: 73fb strb r3, [r7, #15]
break;
80058b4: e00b b.n 80058ce <DMA_CheckFifoParam+0xe6>
break;
80058b6: bf00 nop
80058b8: e00a b.n 80058d0 <DMA_CheckFifoParam+0xe8>
break;
80058ba: bf00 nop
80058bc: e008 b.n 80058d0 <DMA_CheckFifoParam+0xe8>
break;
80058be: bf00 nop
80058c0: e006 b.n 80058d0 <DMA_CheckFifoParam+0xe8>
break;
80058c2: bf00 nop
80058c4: e004 b.n 80058d0 <DMA_CheckFifoParam+0xe8>
break;
80058c6: bf00 nop
80058c8: e002 b.n 80058d0 <DMA_CheckFifoParam+0xe8>
break;
80058ca: bf00 nop
80058cc: e000 b.n 80058d0 <DMA_CheckFifoParam+0xe8>
break;
80058ce: bf00 nop
}
}
return status;
80058d0: 7bfb ldrb r3, [r7, #15]
}
80058d2: 4618 mov r0, r3
80058d4: 3714 adds r7, #20
80058d6: 46bd mov sp, r7
80058d8: f85d 7b04 ldr.w r7, [sp], #4
80058dc: 4770 bx lr
80058de: bf00 nop
080058e0 <HAL_DMA2D_Init>:
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
{
80058e0: b580 push {r7, lr}
80058e2: b082 sub sp, #8
80058e4: af00 add r7, sp, #0
80058e6: 6078 str r0, [r7, #4]
/* Check the DMA2D peripheral state */
if (hdma2d == NULL)
80058e8: 687b ldr r3, [r7, #4]
80058ea: 2b00 cmp r3, #0
80058ec: d101 bne.n 80058f2 <HAL_DMA2D_Init+0x12>
{
return HAL_ERROR;
80058ee: 2301 movs r3, #1
80058f0: e039 b.n 8005966 <HAL_DMA2D_Init+0x86>
/* Init the low level hardware */
hdma2d->MspInitCallback(hdma2d);
}
#else
if (hdma2d->State == HAL_DMA2D_STATE_RESET)
80058f2: 687b ldr r3, [r7, #4]
80058f4: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
80058f8: b2db uxtb r3, r3
80058fa: 2b00 cmp r3, #0
80058fc: d106 bne.n 800590c <HAL_DMA2D_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hdma2d->Lock = HAL_UNLOCKED;
80058fe: 687b ldr r3, [r7, #4]
8005900: 2200 movs r2, #0
8005902: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Init the low level hardware */
HAL_DMA2D_MspInit(hdma2d);
8005906: 6878 ldr r0, [r7, #4]
8005908: f7fe fb34 bl 8003f74 <HAL_DMA2D_MspInit>
}
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
800590c: 687b ldr r3, [r7, #4]
800590e: 2202 movs r2, #2
8005910: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* DMA2D CR register configuration -------------------------------------------*/
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
8005914: 687b ldr r3, [r7, #4]
8005916: 681b ldr r3, [r3, #0]
8005918: 681b ldr r3, [r3, #0]
800591a: f423 3140 bic.w r1, r3, #196608 ; 0x30000
800591e: 687b ldr r3, [r7, #4]
8005920: 685a ldr r2, [r3, #4]
8005922: 687b ldr r3, [r7, #4]
8005924: 681b ldr r3, [r3, #0]
8005926: 430a orrs r2, r1
8005928: 601a str r2, [r3, #0]
/* DMA2D OPFCCR register configuration ---------------------------------------*/
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
800592a: 687b ldr r3, [r7, #4]
800592c: 681b ldr r3, [r3, #0]
800592e: 6b5b ldr r3, [r3, #52] ; 0x34
8005930: f023 0107 bic.w r1, r3, #7
8005934: 687b ldr r3, [r7, #4]
8005936: 689a ldr r2, [r3, #8]
8005938: 687b ldr r3, [r7, #4]
800593a: 681b ldr r3, [r3, #0]
800593c: 430a orrs r2, r1
800593e: 635a str r2, [r3, #52] ; 0x34
/* DMA2D OOR register configuration ------------------------------------------*/
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
8005940: 687b ldr r3, [r7, #4]
8005942: 681b ldr r3, [r3, #0]
8005944: 6c1a ldr r2, [r3, #64] ; 0x40
8005946: 4b0a ldr r3, [pc, #40] ; (8005970 <HAL_DMA2D_Init+0x90>)
8005948: 4013 ands r3, r2
800594a: 687a ldr r2, [r7, #4]
800594c: 68d1 ldr r1, [r2, #12]
800594e: 687a ldr r2, [r7, #4]
8005950: 6812 ldr r2, [r2, #0]
8005952: 430b orrs r3, r1
8005954: 6413 str r3, [r2, #64] ; 0x40
(hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* Update error code */
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
8005956: 687b ldr r3, [r7, #4]
8005958: 2200 movs r2, #0
800595a: 63da str r2, [r3, #60] ; 0x3c
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
800595c: 687b ldr r3, [r7, #4]
800595e: 2201 movs r2, #1
8005960: f883 2039 strb.w r2, [r3, #57] ; 0x39
return HAL_OK;
8005964: 2300 movs r3, #0
}
8005966: 4618 mov r0, r3
8005968: 3708 adds r7, #8
800596a: 46bd mov sp, r7
800596c: bd80 pop {r7, pc}
800596e: bf00 nop
8005970: ffffc000 .word 0xffffc000
08005974 <HAL_DMA2D_Start>:
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
uint32_t Height)
{
8005974: b580 push {r7, lr}
8005976: b086 sub sp, #24
8005978: af02 add r7, sp, #8
800597a: 60f8 str r0, [r7, #12]
800597c: 60b9 str r1, [r7, #8]
800597e: 607a str r2, [r7, #4]
8005980: 603b str r3, [r7, #0]
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
assert_param(IS_DMA2D_PIXEL(Width));
/* Process locked */
__HAL_LOCK(hdma2d);
8005982: 68fb ldr r3, [r7, #12]
8005984: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
8005988: 2b01 cmp r3, #1
800598a: d101 bne.n 8005990 <HAL_DMA2D_Start+0x1c>
800598c: 2302 movs r3, #2
800598e: e018 b.n 80059c2 <HAL_DMA2D_Start+0x4e>
8005990: 68fb ldr r3, [r7, #12]
8005992: 2201 movs r2, #1
8005994: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8005998: 68fb ldr r3, [r7, #12]
800599a: 2202 movs r2, #2
800599c: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
80059a0: 69bb ldr r3, [r7, #24]
80059a2: 9300 str r3, [sp, #0]
80059a4: 683b ldr r3, [r7, #0]
80059a6: 687a ldr r2, [r7, #4]
80059a8: 68b9 ldr r1, [r7, #8]
80059aa: 68f8 ldr r0, [r7, #12]
80059ac: f000 f988 bl 8005cc0 <DMA2D_SetConfig>
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
80059b0: 68fb ldr r3, [r7, #12]
80059b2: 681b ldr r3, [r3, #0]
80059b4: 681a ldr r2, [r3, #0]
80059b6: 68fb ldr r3, [r7, #12]
80059b8: 681b ldr r3, [r3, #0]
80059ba: f042 0201 orr.w r2, r2, #1
80059be: 601a str r2, [r3, #0]
return HAL_OK;
80059c0: 2300 movs r3, #0
}
80059c2: 4618 mov r0, r3
80059c4: 3710 adds r7, #16
80059c6: 46bd mov sp, r7
80059c8: bd80 pop {r7, pc}
080059ca <HAL_DMA2D_PollForTransfer>:
* the configuration information for the DMA2D.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
{
80059ca: b580 push {r7, lr}
80059cc: b086 sub sp, #24
80059ce: af00 add r7, sp, #0
80059d0: 6078 str r0, [r7, #4]
80059d2: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t layer_start;
__IO uint32_t isrflags = 0x0U;
80059d4: 2300 movs r3, #0
80059d6: 60fb str r3, [r7, #12]
/* Polling for DMA2D transfer */
if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
80059d8: 687b ldr r3, [r7, #4]
80059da: 681b ldr r3, [r3, #0]
80059dc: 681b ldr r3, [r3, #0]
80059de: f003 0301 and.w r3, r3, #1
80059e2: 2b00 cmp r3, #0
80059e4: d056 beq.n 8005a94 <HAL_DMA2D_PollForTransfer+0xca>
{
/* Get tick */
tickstart = HAL_GetTick();
80059e6: f7fe fef3 bl 80047d0 <HAL_GetTick>
80059ea: 6178 str r0, [r7, #20]
while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
80059ec: e04b b.n 8005a86 <HAL_DMA2D_PollForTransfer+0xbc>
{
isrflags = READ_REG(hdma2d->Instance->ISR);
80059ee: 687b ldr r3, [r7, #4]
80059f0: 681b ldr r3, [r3, #0]
80059f2: 685b ldr r3, [r3, #4]
80059f4: 60fb str r3, [r7, #12]
if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
80059f6: 68fb ldr r3, [r7, #12]
80059f8: f003 0321 and.w r3, r3, #33 ; 0x21
80059fc: 2b00 cmp r3, #0
80059fe: d023 beq.n 8005a48 <HAL_DMA2D_PollForTransfer+0x7e>
{
if ((isrflags & DMA2D_FLAG_CE) != 0U)
8005a00: 68fb ldr r3, [r7, #12]
8005a02: f003 0320 and.w r3, r3, #32
8005a06: 2b00 cmp r3, #0
8005a08: d005 beq.n 8005a16 <HAL_DMA2D_PollForTransfer+0x4c>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
8005a0a: 687b ldr r3, [r7, #4]
8005a0c: 6bdb ldr r3, [r3, #60] ; 0x3c
8005a0e: f043 0202 orr.w r2, r3, #2
8005a12: 687b ldr r3, [r7, #4]
8005a14: 63da str r2, [r3, #60] ; 0x3c
}
if ((isrflags & DMA2D_FLAG_TE) != 0U)
8005a16: 68fb ldr r3, [r7, #12]
8005a18: f003 0301 and.w r3, r3, #1
8005a1c: 2b00 cmp r3, #0
8005a1e: d005 beq.n 8005a2c <HAL_DMA2D_PollForTransfer+0x62>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
8005a20: 687b ldr r3, [r7, #4]
8005a22: 6bdb ldr r3, [r3, #60] ; 0x3c
8005a24: f043 0201 orr.w r2, r3, #1
8005a28: 687b ldr r3, [r7, #4]
8005a2a: 63da str r2, [r3, #60] ; 0x3c
}
/* Clear the transfer and configuration error flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
8005a2c: 687b ldr r3, [r7, #4]
8005a2e: 681b ldr r3, [r3, #0]
8005a30: 2221 movs r2, #33 ; 0x21
8005a32: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
8005a34: 687b ldr r3, [r7, #4]
8005a36: 2204 movs r2, #4
8005a38: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005a3c: 687b ldr r3, [r7, #4]
8005a3e: 2200 movs r2, #0
8005a40: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_ERROR;
8005a44: 2301 movs r3, #1
8005a46: e0a5 b.n 8005b94 <HAL_DMA2D_PollForTransfer+0x1ca>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8005a48: 683b ldr r3, [r7, #0]
8005a4a: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8005a4e: d01a beq.n 8005a86 <HAL_DMA2D_PollForTransfer+0xbc>
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
8005a50: f7fe febe bl 80047d0 <HAL_GetTick>
8005a54: 4602 mov r2, r0
8005a56: 697b ldr r3, [r7, #20]
8005a58: 1ad3 subs r3, r2, r3
8005a5a: 683a ldr r2, [r7, #0]
8005a5c: 429a cmp r2, r3
8005a5e: d302 bcc.n 8005a66 <HAL_DMA2D_PollForTransfer+0x9c>
8005a60: 683b ldr r3, [r7, #0]
8005a62: 2b00 cmp r3, #0
8005a64: d10f bne.n 8005a86 <HAL_DMA2D_PollForTransfer+0xbc>
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
8005a66: 687b ldr r3, [r7, #4]
8005a68: 6bdb ldr r3, [r3, #60] ; 0x3c
8005a6a: f043 0220 orr.w r2, r3, #32
8005a6e: 687b ldr r3, [r7, #4]
8005a70: 63da str r2, [r3, #60] ; 0x3c
/* Change the DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
8005a72: 687b ldr r3, [r7, #4]
8005a74: 2203 movs r2, #3
8005a76: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005a7a: 687b ldr r3, [r7, #4]
8005a7c: 2200 movs r2, #0
8005a7e: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_TIMEOUT;
8005a82: 2303 movs r3, #3
8005a84: e086 b.n 8005b94 <HAL_DMA2D_PollForTransfer+0x1ca>
while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
8005a86: 687b ldr r3, [r7, #4]
8005a88: 681b ldr r3, [r3, #0]
8005a8a: 685b ldr r3, [r3, #4]
8005a8c: f003 0302 and.w r3, r3, #2
8005a90: 2b00 cmp r3, #0
8005a92: d0ac beq.n 80059ee <HAL_DMA2D_PollForTransfer+0x24>
}
}
}
}
/* Polling for CLUT loading (foreground or background) */
layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
8005a94: 687b ldr r3, [r7, #4]
8005a96: 681b ldr r3, [r3, #0]
8005a98: 69db ldr r3, [r3, #28]
8005a9a: f003 0320 and.w r3, r3, #32
8005a9e: 613b str r3, [r7, #16]
layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
8005aa0: 687b ldr r3, [r7, #4]
8005aa2: 681b ldr r3, [r3, #0]
8005aa4: 6a5b ldr r3, [r3, #36] ; 0x24
8005aa6: f003 0320 and.w r3, r3, #32
8005aaa: 693a ldr r2, [r7, #16]
8005aac: 4313 orrs r3, r2
8005aae: 613b str r3, [r7, #16]
if (layer_start != 0U)
8005ab0: 693b ldr r3, [r7, #16]
8005ab2: 2b00 cmp r3, #0
8005ab4: d061 beq.n 8005b7a <HAL_DMA2D_PollForTransfer+0x1b0>
{
/* Get tick */
tickstart = HAL_GetTick();
8005ab6: f7fe fe8b bl 80047d0 <HAL_GetTick>
8005aba: 6178 str r0, [r7, #20]
while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
8005abc: e056 b.n 8005b6c <HAL_DMA2D_PollForTransfer+0x1a2>
{
isrflags = READ_REG(hdma2d->Instance->ISR);
8005abe: 687b ldr r3, [r7, #4]
8005ac0: 681b ldr r3, [r3, #0]
8005ac2: 685b ldr r3, [r3, #4]
8005ac4: 60fb str r3, [r7, #12]
if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
8005ac6: 68fb ldr r3, [r7, #12]
8005ac8: f003 0329 and.w r3, r3, #41 ; 0x29
8005acc: 2b00 cmp r3, #0
8005ace: d02e beq.n 8005b2e <HAL_DMA2D_PollForTransfer+0x164>
{
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
8005ad0: 68fb ldr r3, [r7, #12]
8005ad2: f003 0308 and.w r3, r3, #8
8005ad6: 2b00 cmp r3, #0
8005ad8: d005 beq.n 8005ae6 <HAL_DMA2D_PollForTransfer+0x11c>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
8005ada: 687b ldr r3, [r7, #4]
8005adc: 6bdb ldr r3, [r3, #60] ; 0x3c
8005ade: f043 0204 orr.w r2, r3, #4
8005ae2: 687b ldr r3, [r7, #4]
8005ae4: 63da str r2, [r3, #60] ; 0x3c
}
if ((isrflags & DMA2D_FLAG_CE) != 0U)
8005ae6: 68fb ldr r3, [r7, #12]
8005ae8: f003 0320 and.w r3, r3, #32
8005aec: 2b00 cmp r3, #0
8005aee: d005 beq.n 8005afc <HAL_DMA2D_PollForTransfer+0x132>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
8005af0: 687b ldr r3, [r7, #4]
8005af2: 6bdb ldr r3, [r3, #60] ; 0x3c
8005af4: f043 0202 orr.w r2, r3, #2
8005af8: 687b ldr r3, [r7, #4]
8005afa: 63da str r2, [r3, #60] ; 0x3c
}
if ((isrflags & DMA2D_FLAG_TE) != 0U)
8005afc: 68fb ldr r3, [r7, #12]
8005afe: f003 0301 and.w r3, r3, #1
8005b02: 2b00 cmp r3, #0
8005b04: d005 beq.n 8005b12 <HAL_DMA2D_PollForTransfer+0x148>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
8005b06: 687b ldr r3, [r7, #4]
8005b08: 6bdb ldr r3, [r3, #60] ; 0x3c
8005b0a: f043 0201 orr.w r2, r3, #1
8005b0e: 687b ldr r3, [r7, #4]
8005b10: 63da str r2, [r3, #60] ; 0x3c
}
/* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
8005b12: 687b ldr r3, [r7, #4]
8005b14: 681b ldr r3, [r3, #0]
8005b16: 2229 movs r2, #41 ; 0x29
8005b18: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
8005b1a: 687b ldr r3, [r7, #4]
8005b1c: 2204 movs r2, #4
8005b1e: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005b22: 687b ldr r3, [r7, #4]
8005b24: 2200 movs r2, #0
8005b26: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_ERROR;
8005b2a: 2301 movs r3, #1
8005b2c: e032 b.n 8005b94 <HAL_DMA2D_PollForTransfer+0x1ca>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8005b2e: 683b ldr r3, [r7, #0]
8005b30: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8005b34: d01a beq.n 8005b6c <HAL_DMA2D_PollForTransfer+0x1a2>
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
8005b36: f7fe fe4b bl 80047d0 <HAL_GetTick>
8005b3a: 4602 mov r2, r0
8005b3c: 697b ldr r3, [r7, #20]
8005b3e: 1ad3 subs r3, r2, r3
8005b40: 683a ldr r2, [r7, #0]
8005b42: 429a cmp r2, r3
8005b44: d302 bcc.n 8005b4c <HAL_DMA2D_PollForTransfer+0x182>
8005b46: 683b ldr r3, [r7, #0]
8005b48: 2b00 cmp r3, #0
8005b4a: d10f bne.n 8005b6c <HAL_DMA2D_PollForTransfer+0x1a2>
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
8005b4c: 687b ldr r3, [r7, #4]
8005b4e: 6bdb ldr r3, [r3, #60] ; 0x3c
8005b50: f043 0220 orr.w r2, r3, #32
8005b54: 687b ldr r3, [r7, #4]
8005b56: 63da str r2, [r3, #60] ; 0x3c
/* Change the DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
8005b58: 687b ldr r3, [r7, #4]
8005b5a: 2203 movs r2, #3
8005b5c: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005b60: 687b ldr r3, [r7, #4]
8005b62: 2200 movs r2, #0
8005b64: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_TIMEOUT;
8005b68: 2303 movs r3, #3
8005b6a: e013 b.n 8005b94 <HAL_DMA2D_PollForTransfer+0x1ca>
while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
8005b6c: 687b ldr r3, [r7, #4]
8005b6e: 681b ldr r3, [r3, #0]
8005b70: 685b ldr r3, [r3, #4]
8005b72: f003 0310 and.w r3, r3, #16
8005b76: 2b00 cmp r3, #0
8005b78: d0a1 beq.n 8005abe <HAL_DMA2D_PollForTransfer+0xf4>
}
}
}
/* Clear the transfer complete and CLUT loading flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC);
8005b7a: 687b ldr r3, [r7, #4]
8005b7c: 681b ldr r3, [r3, #0]
8005b7e: 2212 movs r2, #18
8005b80: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
8005b82: 687b ldr r3, [r7, #4]
8005b84: 2201 movs r2, #1
8005b86: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005b8a: 687b ldr r3, [r7, #4]
8005b8c: 2200 movs r2, #0
8005b8e: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_OK;
8005b92: 2300 movs r3, #0
}
8005b94: 4618 mov r0, r3
8005b96: 3718 adds r7, #24
8005b98: 46bd mov sp, r7
8005b9a: bd80 pop {r7, pc}
08005b9c <HAL_DMA2D_ConfigLayer>:
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
8005b9c: b480 push {r7}
8005b9e: b087 sub sp, #28
8005ba0: af00 add r7, sp, #0
8005ba2: 6078 str r0, [r7, #4]
8005ba4: 6039 str r1, [r7, #0]
uint32_t regValue;
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
if (hdma2d->Init.Mode != DMA2D_R2M)
8005ba6: 687b ldr r3, [r7, #4]
8005ba8: 685b ldr r3, [r3, #4]
8005baa: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* Process locked */
__HAL_LOCK(hdma2d);
8005bae: 687b ldr r3, [r7, #4]
8005bb0: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
8005bb4: 2b01 cmp r3, #1
8005bb6: d101 bne.n 8005bbc <HAL_DMA2D_ConfigLayer+0x20>
8005bb8: 2302 movs r3, #2
8005bba: e079 b.n 8005cb0 <HAL_DMA2D_ConfigLayer+0x114>
8005bbc: 687b ldr r3, [r7, #4]
8005bbe: 2201 movs r2, #1
8005bc0: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8005bc4: 687b ldr r3, [r7, #4]
8005bc6: 2202 movs r2, #2
8005bc8: f883 2039 strb.w r2, [r3, #57] ; 0x39
pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
8005bcc: 683b ldr r3, [r7, #0]
8005bce: 011b lsls r3, r3, #4
8005bd0: 3318 adds r3, #24
8005bd2: 687a ldr r2, [r7, #4]
8005bd4: 4413 add r3, r2
8005bd6: 613b str r3, [r7, #16]
#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \
(pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
#else
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
8005bd8: 693b ldr r3, [r7, #16]
8005bda: 685a ldr r2, [r3, #4]
8005bdc: 693b ldr r3, [r7, #16]
8005bde: 689b ldr r3, [r3, #8]
8005be0: 041b lsls r3, r3, #16
8005be2: 4313 orrs r3, r2
8005be4: 617b str r3, [r7, #20]
regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
8005be6: 4b35 ldr r3, [pc, #212] ; (8005cbc <HAL_DMA2D_ConfigLayer+0x120>)
8005be8: 60fb str r3, [r7, #12]
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8005bea: 693b ldr r3, [r7, #16]
8005bec: 685b ldr r3, [r3, #4]
8005bee: 2b0a cmp r3, #10
8005bf0: d003 beq.n 8005bfa <HAL_DMA2D_ConfigLayer+0x5e>
8005bf2: 693b ldr r3, [r7, #16]
8005bf4: 685b ldr r3, [r3, #4]
8005bf6: 2b09 cmp r3, #9
8005bf8: d107 bne.n 8005c0a <HAL_DMA2D_ConfigLayer+0x6e>
{
regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
8005bfa: 693b ldr r3, [r7, #16]
8005bfc: 68db ldr r3, [r3, #12]
8005bfe: f003 437f and.w r3, r3, #4278190080 ; 0xff000000
8005c02: 697a ldr r2, [r7, #20]
8005c04: 4313 orrs r3, r2
8005c06: 617b str r3, [r7, #20]
8005c08: e005 b.n 8005c16 <HAL_DMA2D_ConfigLayer+0x7a>
}
else
{
regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
8005c0a: 693b ldr r3, [r7, #16]
8005c0c: 68db ldr r3, [r3, #12]
8005c0e: 061b lsls r3, r3, #24
8005c10: 697a ldr r2, [r7, #20]
8005c12: 4313 orrs r3, r2
8005c14: 617b str r3, [r7, #20]
}
/* Configure the background DMA2D layer */
if (LayerIdx == DMA2D_BACKGROUND_LAYER)
8005c16: 683b ldr r3, [r7, #0]
8005c18: 2b00 cmp r3, #0
8005c1a: d120 bne.n 8005c5e <HAL_DMA2D_ConfigLayer+0xc2>
{
/* Write DMA2D BGPFCCR register */
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
8005c1c: 687b ldr r3, [r7, #4]
8005c1e: 681b ldr r3, [r3, #0]
8005c20: 6a5a ldr r2, [r3, #36] ; 0x24
8005c22: 68fb ldr r3, [r7, #12]
8005c24: 43db mvns r3, r3
8005c26: ea02 0103 and.w r1, r2, r3
8005c2a: 687b ldr r3, [r7, #4]
8005c2c: 681b ldr r3, [r3, #0]
8005c2e: 697a ldr r2, [r7, #20]
8005c30: 430a orrs r2, r1
8005c32: 625a str r2, [r3, #36] ; 0x24
/* DMA2D BGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
8005c34: 687b ldr r3, [r7, #4]
8005c36: 681b ldr r3, [r3, #0]
8005c38: 693a ldr r2, [r7, #16]
8005c3a: 6812 ldr r2, [r2, #0]
8005c3c: 619a str r2, [r3, #24]
/* DMA2D BGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8005c3e: 693b ldr r3, [r7, #16]
8005c40: 685b ldr r3, [r3, #4]
8005c42: 2b0a cmp r3, #10
8005c44: d003 beq.n 8005c4e <HAL_DMA2D_ConfigLayer+0xb2>
8005c46: 693b ldr r3, [r7, #16]
8005c48: 685b ldr r3, [r3, #4]
8005c4a: 2b09 cmp r3, #9
8005c4c: d127 bne.n 8005c9e <HAL_DMA2D_ConfigLayer+0x102>
{
WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
8005c4e: 693b ldr r3, [r7, #16]
8005c50: 68da ldr r2, [r3, #12]
8005c52: 687b ldr r3, [r7, #4]
8005c54: 681b ldr r3, [r3, #0]
8005c56: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000
8005c5a: 629a str r2, [r3, #40] ; 0x28
8005c5c: e01f b.n 8005c9e <HAL_DMA2D_ConfigLayer+0x102>
else
{
/* Write DMA2D FGPFCCR register */
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
8005c5e: 687b ldr r3, [r7, #4]
8005c60: 681b ldr r3, [r3, #0]
8005c62: 69da ldr r2, [r3, #28]
8005c64: 68fb ldr r3, [r7, #12]
8005c66: 43db mvns r3, r3
8005c68: ea02 0103 and.w r1, r2, r3
8005c6c: 687b ldr r3, [r7, #4]
8005c6e: 681b ldr r3, [r3, #0]
8005c70: 697a ldr r2, [r7, #20]
8005c72: 430a orrs r2, r1
8005c74: 61da str r2, [r3, #28]
/* DMA2D FGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
8005c76: 687b ldr r3, [r7, #4]
8005c78: 681b ldr r3, [r3, #0]
8005c7a: 693a ldr r2, [r7, #16]
8005c7c: 6812 ldr r2, [r2, #0]
8005c7e: 611a str r2, [r3, #16]
/* DMA2D FGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8005c80: 693b ldr r3, [r7, #16]
8005c82: 685b ldr r3, [r3, #4]
8005c84: 2b0a cmp r3, #10
8005c86: d003 beq.n 8005c90 <HAL_DMA2D_ConfigLayer+0xf4>
8005c88: 693b ldr r3, [r7, #16]
8005c8a: 685b ldr r3, [r3, #4]
8005c8c: 2b09 cmp r3, #9
8005c8e: d106 bne.n 8005c9e <HAL_DMA2D_ConfigLayer+0x102>
{
WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
8005c90: 693b ldr r3, [r7, #16]
8005c92: 68da ldr r2, [r3, #12]
8005c94: 687b ldr r3, [r7, #4]
8005c96: 681b ldr r3, [r3, #0]
8005c98: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000
8005c9c: 621a str r2, [r3, #32]
DMA2D_FGCOLR_RED));
}
}
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
8005c9e: 687b ldr r3, [r7, #4]
8005ca0: 2201 movs r2, #1
8005ca2: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005ca6: 687b ldr r3, [r7, #4]
8005ca8: 2200 movs r2, #0
8005caa: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_OK;
8005cae: 2300 movs r3, #0
}
8005cb0: 4618 mov r0, r3
8005cb2: 371c adds r7, #28
8005cb4: 46bd mov sp, r7
8005cb6: f85d 7b04 ldr.w r7, [sp], #4
8005cba: 4770 bx lr
8005cbc: ff03000f .word 0xff03000f
08005cc0 <DMA2D_SetConfig>:
* @param Height The height of data to be transferred from source to destination.
* @retval HAL status
*/
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
uint32_t Height)
{
8005cc0: b480 push {r7}
8005cc2: b08b sub sp, #44 ; 0x2c
8005cc4: af00 add r7, sp, #0
8005cc6: 60f8 str r0, [r7, #12]
8005cc8: 60b9 str r1, [r7, #8]
8005cca: 607a str r2, [r7, #4]
8005ccc: 603b str r3, [r7, #0]
uint32_t tmp2;
uint32_t tmp3;
uint32_t tmp4;
/* Configure DMA2D data size */
MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos)));
8005cce: 68fb ldr r3, [r7, #12]
8005cd0: 681b ldr r3, [r3, #0]
8005cd2: 6c5b ldr r3, [r3, #68] ; 0x44
8005cd4: f003 4140 and.w r1, r3, #3221225472 ; 0xc0000000
8005cd8: 683b ldr r3, [r7, #0]
8005cda: 041a lsls r2, r3, #16
8005cdc: 6b3b ldr r3, [r7, #48] ; 0x30
8005cde: 431a orrs r2, r3
8005ce0: 68fb ldr r3, [r7, #12]
8005ce2: 681b ldr r3, [r3, #0]
8005ce4: 430a orrs r2, r1
8005ce6: 645a str r2, [r3, #68] ; 0x44
/* Configure DMA2D destination address */
WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
8005ce8: 68fb ldr r3, [r7, #12]
8005cea: 681b ldr r3, [r3, #0]
8005cec: 687a ldr r2, [r7, #4]
8005cee: 63da str r2, [r3, #60] ; 0x3c
/* Register to memory DMA2D mode selected */
if (hdma2d->Init.Mode == DMA2D_R2M)
8005cf0: 68fb ldr r3, [r7, #12]
8005cf2: 685b ldr r3, [r3, #4]
8005cf4: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
8005cf8: d174 bne.n 8005de4 <DMA2D_SetConfig+0x124>
{
tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
8005cfa: 68bb ldr r3, [r7, #8]
8005cfc: f003 437f and.w r3, r3, #4278190080 ; 0xff000000
8005d00: 623b str r3, [r7, #32]
tmp2 = pdata & DMA2D_OCOLR_RED_1;
8005d02: 68bb ldr r3, [r7, #8]
8005d04: f403 037f and.w r3, r3, #16711680 ; 0xff0000
8005d08: 61fb str r3, [r7, #28]
tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
8005d0a: 68bb ldr r3, [r7, #8]
8005d0c: f403 437f and.w r3, r3, #65280 ; 0xff00
8005d10: 61bb str r3, [r7, #24]
tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
8005d12: 68bb ldr r3, [r7, #8]
8005d14: b2db uxtb r3, r3
8005d16: 617b str r3, [r7, #20]
/* Prepare the value to be written to the OCOLR register according to the color mode */
if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
8005d18: 68fb ldr r3, [r7, #12]
8005d1a: 689b ldr r3, [r3, #8]
8005d1c: 2b00 cmp r3, #0
8005d1e: d108 bne.n 8005d32 <DMA2D_SetConfig+0x72>
{
tmp = (tmp3 | tmp2 | tmp1 | tmp4);
8005d20: 69ba ldr r2, [r7, #24]
8005d22: 69fb ldr r3, [r7, #28]
8005d24: 431a orrs r2, r3
8005d26: 6a3b ldr r3, [r7, #32]
8005d28: 4313 orrs r3, r2
8005d2a: 697a ldr r2, [r7, #20]
8005d2c: 4313 orrs r3, r2
8005d2e: 627b str r3, [r7, #36] ; 0x24
8005d30: e053 b.n 8005dda <DMA2D_SetConfig+0x11a>
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
8005d32: 68fb ldr r3, [r7, #12]
8005d34: 689b ldr r3, [r3, #8]
8005d36: 2b01 cmp r3, #1
8005d38: d106 bne.n 8005d48 <DMA2D_SetConfig+0x88>
{
tmp = (tmp3 | tmp2 | tmp4);
8005d3a: 69ba ldr r2, [r7, #24]
8005d3c: 69fb ldr r3, [r7, #28]
8005d3e: 4313 orrs r3, r2
8005d40: 697a ldr r2, [r7, #20]
8005d42: 4313 orrs r3, r2
8005d44: 627b str r3, [r7, #36] ; 0x24
8005d46: e048 b.n 8005dda <DMA2D_SetConfig+0x11a>
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
8005d48: 68fb ldr r3, [r7, #12]
8005d4a: 689b ldr r3, [r3, #8]
8005d4c: 2b02 cmp r3, #2
8005d4e: d111 bne.n 8005d74 <DMA2D_SetConfig+0xb4>
{
tmp2 = (tmp2 >> 19U);
8005d50: 69fb ldr r3, [r7, #28]
8005d52: 0cdb lsrs r3, r3, #19
8005d54: 61fb str r3, [r7, #28]
tmp3 = (tmp3 >> 10U);
8005d56: 69bb ldr r3, [r7, #24]
8005d58: 0a9b lsrs r3, r3, #10
8005d5a: 61bb str r3, [r7, #24]
tmp4 = (tmp4 >> 3U);
8005d5c: 697b ldr r3, [r7, #20]
8005d5e: 08db lsrs r3, r3, #3
8005d60: 617b str r3, [r7, #20]
tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
8005d62: 69bb ldr r3, [r7, #24]
8005d64: 015a lsls r2, r3, #5
8005d66: 69fb ldr r3, [r7, #28]
8005d68: 02db lsls r3, r3, #11
8005d6a: 4313 orrs r3, r2
8005d6c: 697a ldr r2, [r7, #20]
8005d6e: 4313 orrs r3, r2
8005d70: 627b str r3, [r7, #36] ; 0x24
8005d72: e032 b.n 8005dda <DMA2D_SetConfig+0x11a>
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
8005d74: 68fb ldr r3, [r7, #12]
8005d76: 689b ldr r3, [r3, #8]
8005d78: 2b03 cmp r3, #3
8005d7a: d117 bne.n 8005dac <DMA2D_SetConfig+0xec>
{
tmp1 = (tmp1 >> 31U);
8005d7c: 6a3b ldr r3, [r7, #32]
8005d7e: 0fdb lsrs r3, r3, #31
8005d80: 623b str r3, [r7, #32]
tmp2 = (tmp2 >> 19U);
8005d82: 69fb ldr r3, [r7, #28]
8005d84: 0cdb lsrs r3, r3, #19
8005d86: 61fb str r3, [r7, #28]
tmp3 = (tmp3 >> 11U);
8005d88: 69bb ldr r3, [r7, #24]
8005d8a: 0adb lsrs r3, r3, #11
8005d8c: 61bb str r3, [r7, #24]
tmp4 = (tmp4 >> 3U);
8005d8e: 697b ldr r3, [r7, #20]
8005d90: 08db lsrs r3, r3, #3
8005d92: 617b str r3, [r7, #20]
tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
8005d94: 69bb ldr r3, [r7, #24]
8005d96: 015a lsls r2, r3, #5
8005d98: 69fb ldr r3, [r7, #28]
8005d9a: 029b lsls r3, r3, #10
8005d9c: 431a orrs r2, r3
8005d9e: 6a3b ldr r3, [r7, #32]
8005da0: 03db lsls r3, r3, #15
8005da2: 4313 orrs r3, r2
8005da4: 697a ldr r2, [r7, #20]
8005da6: 4313 orrs r3, r2
8005da8: 627b str r3, [r7, #36] ; 0x24
8005daa: e016 b.n 8005dda <DMA2D_SetConfig+0x11a>
}
else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
{
tmp1 = (tmp1 >> 28U);
8005dac: 6a3b ldr r3, [r7, #32]
8005dae: 0f1b lsrs r3, r3, #28
8005db0: 623b str r3, [r7, #32]
tmp2 = (tmp2 >> 20U);
8005db2: 69fb ldr r3, [r7, #28]
8005db4: 0d1b lsrs r3, r3, #20
8005db6: 61fb str r3, [r7, #28]
tmp3 = (tmp3 >> 12U);
8005db8: 69bb ldr r3, [r7, #24]
8005dba: 0b1b lsrs r3, r3, #12
8005dbc: 61bb str r3, [r7, #24]
tmp4 = (tmp4 >> 4U);
8005dbe: 697b ldr r3, [r7, #20]
8005dc0: 091b lsrs r3, r3, #4
8005dc2: 617b str r3, [r7, #20]
tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
8005dc4: 69bb ldr r3, [r7, #24]
8005dc6: 011a lsls r2, r3, #4
8005dc8: 69fb ldr r3, [r7, #28]
8005dca: 021b lsls r3, r3, #8
8005dcc: 431a orrs r2, r3
8005dce: 6a3b ldr r3, [r7, #32]
8005dd0: 031b lsls r3, r3, #12
8005dd2: 4313 orrs r3, r2
8005dd4: 697a ldr r2, [r7, #20]
8005dd6: 4313 orrs r3, r2
8005dd8: 627b str r3, [r7, #36] ; 0x24
}
/* Write to DMA2D OCOLR register */
WRITE_REG(hdma2d->Instance->OCOLR, tmp);
8005dda: 68fb ldr r3, [r7, #12]
8005ddc: 681b ldr r3, [r3, #0]
8005dde: 6a7a ldr r2, [r7, #36] ; 0x24
8005de0: 639a str r2, [r3, #56] ; 0x38
else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
{
/* Configure DMA2D source address */
WRITE_REG(hdma2d->Instance->FGMAR, pdata);
}
}
8005de2: e003 b.n 8005dec <DMA2D_SetConfig+0x12c>
WRITE_REG(hdma2d->Instance->FGMAR, pdata);
8005de4: 68fb ldr r3, [r7, #12]
8005de6: 681b ldr r3, [r3, #0]
8005de8: 68ba ldr r2, [r7, #8]
8005dea: 60da str r2, [r3, #12]
}
8005dec: bf00 nop
8005dee: 372c adds r7, #44 ; 0x2c
8005df0: 46bd mov sp, r7
8005df2: f85d 7b04 ldr.w r7, [sp], #4
8005df6: 4770 bx lr
08005df8 <HAL_ETH_Init>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
8005df8: b580 push {r7, lr}
8005dfa: b088 sub sp, #32
8005dfc: af00 add r7, sp, #0
8005dfe: 6078 str r0, [r7, #4]
uint32_t tempreg = 0, phyreg = 0;
8005e00: 2300 movs r3, #0
8005e02: 61fb str r3, [r7, #28]
8005e04: 2300 movs r3, #0
8005e06: 60fb str r3, [r7, #12]
uint32_t hclk = 60000000;
8005e08: 4ba9 ldr r3, [pc, #676] ; (80060b0 <HAL_ETH_Init+0x2b8>)
8005e0a: 61bb str r3, [r7, #24]
uint32_t tickstart = 0;
8005e0c: 2300 movs r3, #0
8005e0e: 617b str r3, [r7, #20]
uint32_t err = ETH_SUCCESS;
8005e10: 2300 movs r3, #0
8005e12: 613b str r3, [r7, #16]
/* Check the ETH peripheral state */
if(heth == NULL)
8005e14: 687b ldr r3, [r7, #4]
8005e16: 2b00 cmp r3, #0
8005e18: d101 bne.n 8005e1e <HAL_ETH_Init+0x26>
{
return HAL_ERROR;
8005e1a: 2301 movs r3, #1
8005e1c: e181 b.n 8006122 <HAL_ETH_Init+0x32a>
assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
if(heth->State == HAL_ETH_STATE_RESET)
8005e1e: 687b ldr r3, [r7, #4]
8005e20: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
8005e24: b2db uxtb r3, r3
8005e26: 2b00 cmp r3, #0
8005e28: d106 bne.n 8005e38 <HAL_ETH_Init+0x40>
{
/* Allocate lock resource and initialize it */
heth->Lock = HAL_UNLOCKED;
8005e2a: 687b ldr r3, [r7, #4]
8005e2c: 2200 movs r2, #0
8005e2e: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
heth->MspInitCallback(heth);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
8005e32: 6878 ldr r0, [r7, #4]
8005e34: f005 f92a bl 800b08c <HAL_ETH_MspInit>
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8005e38: 4b9e ldr r3, [pc, #632] ; (80060b4 <HAL_ETH_Init+0x2bc>)
8005e3a: 6c5b ldr r3, [r3, #68] ; 0x44
8005e3c: 4a9d ldr r2, [pc, #628] ; (80060b4 <HAL_ETH_Init+0x2bc>)
8005e3e: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8005e42: 6453 str r3, [r2, #68] ; 0x44
8005e44: 4b9b ldr r3, [pc, #620] ; (80060b4 <HAL_ETH_Init+0x2bc>)
8005e46: 6c5b ldr r3, [r3, #68] ; 0x44
8005e48: f403 4380 and.w r3, r3, #16384 ; 0x4000
8005e4c: 60bb str r3, [r7, #8]
8005e4e: 68bb ldr r3, [r7, #8]
/* Select MII or RMII Mode*/
SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
8005e50: 4b99 ldr r3, [pc, #612] ; (80060b8 <HAL_ETH_Init+0x2c0>)
8005e52: 685b ldr r3, [r3, #4]
8005e54: 4a98 ldr r2, [pc, #608] ; (80060b8 <HAL_ETH_Init+0x2c0>)
8005e56: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
8005e5a: 6053 str r3, [r2, #4]
SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
8005e5c: 4b96 ldr r3, [pc, #600] ; (80060b8 <HAL_ETH_Init+0x2c0>)
8005e5e: 685a ldr r2, [r3, #4]
8005e60: 687b ldr r3, [r7, #4]
8005e62: 6a1b ldr r3, [r3, #32]
8005e64: 4994 ldr r1, [pc, #592] ; (80060b8 <HAL_ETH_Init+0x2c0>)
8005e66: 4313 orrs r3, r2
8005e68: 604b str r3, [r1, #4]
/* Ethernet Software reset */
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
/* After reset all the registers holds their respective reset values */
(heth->Instance)->DMABMR |= ETH_DMABMR_SR;
8005e6a: 687b ldr r3, [r7, #4]
8005e6c: 681b ldr r3, [r3, #0]
8005e6e: f503 5380 add.w r3, r3, #4096 ; 0x1000
8005e72: 681a ldr r2, [r3, #0]
8005e74: 687b ldr r3, [r7, #4]
8005e76: 681b ldr r3, [r3, #0]
8005e78: f042 0201 orr.w r2, r2, #1
8005e7c: f503 5380 add.w r3, r3, #4096 ; 0x1000
8005e80: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8005e82: f7fe fca5 bl 80047d0 <HAL_GetTick>
8005e86: 6178 str r0, [r7, #20]
/* Wait for software reset */
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
8005e88: e011 b.n 8005eae <HAL_ETH_Init+0xb6>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
8005e8a: f7fe fca1 bl 80047d0 <HAL_GetTick>
8005e8e: 4602 mov r2, r0
8005e90: 697b ldr r3, [r7, #20]
8005e92: 1ad3 subs r3, r2, r3
8005e94: f5b3 7ffa cmp.w r3, #500 ; 0x1f4
8005e98: d909 bls.n 8005eae <HAL_ETH_Init+0xb6>
{
heth->State= HAL_ETH_STATE_TIMEOUT;
8005e9a: 687b ldr r3, [r7, #4]
8005e9c: 2203 movs r2, #3
8005e9e: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8005ea2: 687b ldr r3, [r7, #4]
8005ea4: 2200 movs r2, #0
8005ea6: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
not available, please check your external PHY or the IO configuration */
return HAL_TIMEOUT;
8005eaa: 2303 movs r3, #3
8005eac: e139 b.n 8006122 <HAL_ETH_Init+0x32a>
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
8005eae: 687b ldr r3, [r7, #4]
8005eb0: 681b ldr r3, [r3, #0]
8005eb2: f503 5380 add.w r3, r3, #4096 ; 0x1000
8005eb6: 681b ldr r3, [r3, #0]
8005eb8: f003 0301 and.w r3, r3, #1
8005ebc: 2b00 cmp r3, #0
8005ebe: d1e4 bne.n 8005e8a <HAL_ETH_Init+0x92>
}
}
/*-------------------------------- MAC Initialization ----------------------*/
/* Get the ETHERNET MACMIIAR value */
tempreg = (heth->Instance)->MACMIIAR;
8005ec0: 687b ldr r3, [r7, #4]
8005ec2: 681b ldr r3, [r3, #0]
8005ec4: 691b ldr r3, [r3, #16]
8005ec6: 61fb str r3, [r7, #28]
/* Clear CSR Clock Range CR[2:0] bits */
tempreg &= ETH_MACMIIAR_CR_MASK;
8005ec8: 69fb ldr r3, [r7, #28]
8005eca: f023 031c bic.w r3, r3, #28
8005ece: 61fb str r3, [r7, #28]
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
8005ed0: f003 f826 bl 8008f20 <HAL_RCC_GetHCLKFreq>
8005ed4: 61b8 str r0, [r7, #24]
/* Set CR bits depending on hclk value */
if((hclk >= 20000000)&&(hclk < 35000000))
8005ed6: 69bb ldr r3, [r7, #24]
8005ed8: 4a78 ldr r2, [pc, #480] ; (80060bc <HAL_ETH_Init+0x2c4>)
8005eda: 4293 cmp r3, r2
8005edc: d908 bls.n 8005ef0 <HAL_ETH_Init+0xf8>
8005ede: 69bb ldr r3, [r7, #24]
8005ee0: 4a77 ldr r2, [pc, #476] ; (80060c0 <HAL_ETH_Init+0x2c8>)
8005ee2: 4293 cmp r3, r2
8005ee4: d804 bhi.n 8005ef0 <HAL_ETH_Init+0xf8>
{
/* CSR Clock Range between 20-35 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
8005ee6: 69fb ldr r3, [r7, #28]
8005ee8: f043 0308 orr.w r3, r3, #8
8005eec: 61fb str r3, [r7, #28]
8005eee: e027 b.n 8005f40 <HAL_ETH_Init+0x148>
}
else if((hclk >= 35000000)&&(hclk < 60000000))
8005ef0: 69bb ldr r3, [r7, #24]
8005ef2: 4a73 ldr r2, [pc, #460] ; (80060c0 <HAL_ETH_Init+0x2c8>)
8005ef4: 4293 cmp r3, r2
8005ef6: d908 bls.n 8005f0a <HAL_ETH_Init+0x112>
8005ef8: 69bb ldr r3, [r7, #24]
8005efa: 4a6d ldr r2, [pc, #436] ; (80060b0 <HAL_ETH_Init+0x2b8>)
8005efc: 4293 cmp r3, r2
8005efe: d204 bcs.n 8005f0a <HAL_ETH_Init+0x112>
{
/* CSR Clock Range between 35-60 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
8005f00: 69fb ldr r3, [r7, #28]
8005f02: f043 030c orr.w r3, r3, #12
8005f06: 61fb str r3, [r7, #28]
8005f08: e01a b.n 8005f40 <HAL_ETH_Init+0x148>
}
else if((hclk >= 60000000)&&(hclk < 100000000))
8005f0a: 69bb ldr r3, [r7, #24]
8005f0c: 4a68 ldr r2, [pc, #416] ; (80060b0 <HAL_ETH_Init+0x2b8>)
8005f0e: 4293 cmp r3, r2
8005f10: d303 bcc.n 8005f1a <HAL_ETH_Init+0x122>
8005f12: 69bb ldr r3, [r7, #24]
8005f14: 4a6b ldr r2, [pc, #428] ; (80060c4 <HAL_ETH_Init+0x2cc>)
8005f16: 4293 cmp r3, r2
8005f18: d911 bls.n 8005f3e <HAL_ETH_Init+0x146>
{
/* CSR Clock Range between 60-100 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
}
else if((hclk >= 100000000)&&(hclk < 150000000))
8005f1a: 69bb ldr r3, [r7, #24]
8005f1c: 4a69 ldr r2, [pc, #420] ; (80060c4 <HAL_ETH_Init+0x2cc>)
8005f1e: 4293 cmp r3, r2
8005f20: d908 bls.n 8005f34 <HAL_ETH_Init+0x13c>
8005f22: 69bb ldr r3, [r7, #24]
8005f24: 4a68 ldr r2, [pc, #416] ; (80060c8 <HAL_ETH_Init+0x2d0>)
8005f26: 4293 cmp r3, r2
8005f28: d804 bhi.n 8005f34 <HAL_ETH_Init+0x13c>
{
/* CSR Clock Range between 100-150 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
8005f2a: 69fb ldr r3, [r7, #28]
8005f2c: f043 0304 orr.w r3, r3, #4
8005f30: 61fb str r3, [r7, #28]
8005f32: e005 b.n 8005f40 <HAL_ETH_Init+0x148>
}
else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */
{
/* CSR Clock Range between 150-216 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
8005f34: 69fb ldr r3, [r7, #28]
8005f36: f043 0310 orr.w r3, r3, #16
8005f3a: 61fb str r3, [r7, #28]
8005f3c: e000 b.n 8005f40 <HAL_ETH_Init+0x148>
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
8005f3e: bf00 nop
}
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
(heth->Instance)->MACMIIAR = (uint32_t)tempreg;
8005f40: 687b ldr r3, [r7, #4]
8005f42: 681b ldr r3, [r3, #0]
8005f44: 69fa ldr r2, [r7, #28]
8005f46: 611a str r2, [r3, #16]
/*-------------------- PHY initialization and configuration ----------------*/
/* Put the PHY in reset mode */
if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
8005f48: f44f 4200 mov.w r2, #32768 ; 0x8000
8005f4c: 2100 movs r1, #0
8005f4e: 6878 ldr r0, [r7, #4]
8005f50: f000 fc17 bl 8006782 <HAL_ETH_WritePHYRegister>
8005f54: 4603 mov r3, r0
8005f56: 2b00 cmp r3, #0
8005f58: d00b beq.n 8005f72 <HAL_ETH_Init+0x17a>
{
/* In case of write timeout */
err = ETH_ERROR;
8005f5a: 2301 movs r3, #1
8005f5c: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
8005f5e: 6939 ldr r1, [r7, #16]
8005f60: 6878 ldr r0, [r7, #4]
8005f62: f000 fdcd bl 8006b00 <ETH_MACDMAConfig>
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
8005f66: 687b ldr r3, [r7, #4]
8005f68: 2201 movs r2, #1
8005f6a: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return HAL_ERROR */
return HAL_ERROR;
8005f6e: 2301 movs r3, #1
8005f70: e0d7 b.n 8006122 <HAL_ETH_Init+0x32a>
}
/* Delay to assure PHY reset */
HAL_Delay(PHY_RESET_DELAY);
8005f72: 20ff movs r0, #255 ; 0xff
8005f74: f7fe fc38 bl 80047e8 <HAL_Delay>
if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
8005f78: 687b ldr r3, [r7, #4]
8005f7a: 685b ldr r3, [r3, #4]
8005f7c: 2b00 cmp r3, #0
8005f7e: f000 80a5 beq.w 80060cc <HAL_ETH_Init+0x2d4>
{
/* Get tick */
tickstart = HAL_GetTick();
8005f82: f7fe fc25 bl 80047d0 <HAL_GetTick>
8005f86: 6178 str r0, [r7, #20]
/* We wait for linked status */
do
{
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
8005f88: f107 030c add.w r3, r7, #12
8005f8c: 461a mov r2, r3
8005f8e: 2101 movs r1, #1
8005f90: 6878 ldr r0, [r7, #4]
8005f92: f000 fb8e bl 80066b2 <HAL_ETH_ReadPHYRegister>
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
8005f96: f7fe fc1b bl 80047d0 <HAL_GetTick>
8005f9a: 4602 mov r2, r0
8005f9c: 697b ldr r3, [r7, #20]
8005f9e: 1ad3 subs r3, r2, r3
8005fa0: f241 3288 movw r2, #5000 ; 0x1388
8005fa4: 4293 cmp r3, r2
8005fa6: d90f bls.n 8005fc8 <HAL_ETH_Init+0x1d0>
{
/* In case of write timeout */
err = ETH_ERROR;
8005fa8: 2301 movs r3, #1
8005faa: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
8005fac: 6939 ldr r1, [r7, #16]
8005fae: 6878 ldr r0, [r7, #4]
8005fb0: f000 fda6 bl 8006b00 <ETH_MACDMAConfig>
heth->State= HAL_ETH_STATE_READY;
8005fb4: 687b ldr r3, [r7, #4]
8005fb6: 2201 movs r2, #1
8005fb8: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8005fbc: 687b ldr r3, [r7, #4]
8005fbe: 2200 movs r2, #0
8005fc0: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_TIMEOUT;
8005fc4: 2303 movs r3, #3
8005fc6: e0ac b.n 8006122 <HAL_ETH_Init+0x32a>
}
} while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
8005fc8: 68fb ldr r3, [r7, #12]
8005fca: f003 0304 and.w r3, r3, #4
8005fce: 2b00 cmp r3, #0
8005fd0: d0da beq.n 8005f88 <HAL_ETH_Init+0x190>
/* Enable Auto-Negotiation */
if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
8005fd2: f44f 5280 mov.w r2, #4096 ; 0x1000
8005fd6: 2100 movs r1, #0
8005fd8: 6878 ldr r0, [r7, #4]
8005fda: f000 fbd2 bl 8006782 <HAL_ETH_WritePHYRegister>
8005fde: 4603 mov r3, r0
8005fe0: 2b00 cmp r3, #0
8005fe2: d00b beq.n 8005ffc <HAL_ETH_Init+0x204>
{
/* In case of write timeout */
err = ETH_ERROR;
8005fe4: 2301 movs r3, #1
8005fe6: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
8005fe8: 6939 ldr r1, [r7, #16]
8005fea: 6878 ldr r0, [r7, #4]
8005fec: f000 fd88 bl 8006b00 <ETH_MACDMAConfig>
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
8005ff0: 687b ldr r3, [r7, #4]
8005ff2: 2201 movs r2, #1
8005ff4: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return HAL_ERROR */
return HAL_ERROR;
8005ff8: 2301 movs r3, #1
8005ffa: e092 b.n 8006122 <HAL_ETH_Init+0x32a>
}
/* Get tick */
tickstart = HAL_GetTick();
8005ffc: f7fe fbe8 bl 80047d0 <HAL_GetTick>
8006000: 6178 str r0, [r7, #20]
/* Wait until the auto-negotiation will be completed */
do
{
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
8006002: f107 030c add.w r3, r7, #12
8006006: 461a mov r2, r3
8006008: 2101 movs r1, #1
800600a: 6878 ldr r0, [r7, #4]
800600c: f000 fb51 bl 80066b2 <HAL_ETH_ReadPHYRegister>
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
8006010: f7fe fbde bl 80047d0 <HAL_GetTick>
8006014: 4602 mov r2, r0
8006016: 697b ldr r3, [r7, #20]
8006018: 1ad3 subs r3, r2, r3
800601a: f241 3288 movw r2, #5000 ; 0x1388
800601e: 4293 cmp r3, r2
8006020: d90f bls.n 8006042 <HAL_ETH_Init+0x24a>
{
/* In case of write timeout */
err = ETH_ERROR;
8006022: 2301 movs r3, #1
8006024: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
8006026: 6939 ldr r1, [r7, #16]
8006028: 6878 ldr r0, [r7, #4]
800602a: f000 fd69 bl 8006b00 <ETH_MACDMAConfig>
heth->State= HAL_ETH_STATE_READY;
800602e: 687b ldr r3, [r7, #4]
8006030: 2201 movs r2, #1
8006032: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006036: 687b ldr r3, [r7, #4]
8006038: 2200 movs r2, #0
800603a: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_TIMEOUT;
800603e: 2303 movs r3, #3
8006040: e06f b.n 8006122 <HAL_ETH_Init+0x32a>
}
} while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
8006042: 68fb ldr r3, [r7, #12]
8006044: f003 0320 and.w r3, r3, #32
8006048: 2b00 cmp r3, #0
800604a: d0da beq.n 8006002 <HAL_ETH_Init+0x20a>
/* Read the result of the auto-negotiation */
if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
800604c: f107 030c add.w r3, r7, #12
8006050: 461a mov r2, r3
8006052: 2110 movs r1, #16
8006054: 6878 ldr r0, [r7, #4]
8006056: f000 fb2c bl 80066b2 <HAL_ETH_ReadPHYRegister>
800605a: 4603 mov r3, r0
800605c: 2b00 cmp r3, #0
800605e: d00b beq.n 8006078 <HAL_ETH_Init+0x280>
{
/* In case of write timeout */
err = ETH_ERROR;
8006060: 2301 movs r3, #1
8006062: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
8006064: 6939 ldr r1, [r7, #16]
8006066: 6878 ldr r0, [r7, #4]
8006068: f000 fd4a bl 8006b00 <ETH_MACDMAConfig>
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
800606c: 687b ldr r3, [r7, #4]
800606e: 2201 movs r2, #1
8006070: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return HAL_ERROR */
return HAL_ERROR;
8006074: 2301 movs r3, #1
8006076: e054 b.n 8006122 <HAL_ETH_Init+0x32a>
}
/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
8006078: 68fb ldr r3, [r7, #12]
800607a: f003 0304 and.w r3, r3, #4
800607e: 2b00 cmp r3, #0
8006080: d004 beq.n 800608c <HAL_ETH_Init+0x294>
{
/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
8006082: 687b ldr r3, [r7, #4]
8006084: f44f 6200 mov.w r2, #2048 ; 0x800
8006088: 60da str r2, [r3, #12]
800608a: e002 b.n 8006092 <HAL_ETH_Init+0x29a>
}
else
{
/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
(heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
800608c: 687b ldr r3, [r7, #4]
800608e: 2200 movs r2, #0
8006090: 60da str r2, [r3, #12]
}
/* Configure the MAC with the speed fixed by the auto-negotiation process */
if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
8006092: 68fb ldr r3, [r7, #12]
8006094: f003 0302 and.w r3, r3, #2
8006098: 2b00 cmp r3, #0
800609a: d003 beq.n 80060a4 <HAL_ETH_Init+0x2ac>
{
/* Set Ethernet speed to 10M following the auto-negotiation */
(heth->Init).Speed = ETH_SPEED_10M;
800609c: 687b ldr r3, [r7, #4]
800609e: 2200 movs r2, #0
80060a0: 609a str r2, [r3, #8]
80060a2: e035 b.n 8006110 <HAL_ETH_Init+0x318>
}
else
{
/* Set Ethernet speed to 100M following the auto-negotiation */
(heth->Init).Speed = ETH_SPEED_100M;
80060a4: 687b ldr r3, [r7, #4]
80060a6: f44f 4280 mov.w r2, #16384 ; 0x4000
80060aa: 609a str r2, [r3, #8]
80060ac: e030 b.n 8006110 <HAL_ETH_Init+0x318>
80060ae: bf00 nop
80060b0: 03938700 .word 0x03938700
80060b4: 40023800 .word 0x40023800
80060b8: 40013800 .word 0x40013800
80060bc: 01312cff .word 0x01312cff
80060c0: 02160ebf .word 0x02160ebf
80060c4: 05f5e0ff .word 0x05f5e0ff
80060c8: 08f0d17f .word 0x08f0d17f
/* Check parameters */
assert_param(IS_ETH_SPEED(heth->Init.Speed));
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
/* Set MAC Speed and Duplex Mode */
if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
80060cc: 687b ldr r3, [r7, #4]
80060ce: 68db ldr r3, [r3, #12]
80060d0: 08db lsrs r3, r3, #3
80060d2: b29a uxth r2, r3
(uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
80060d4: 687b ldr r3, [r7, #4]
80060d6: 689b ldr r3, [r3, #8]
80060d8: 085b lsrs r3, r3, #1
80060da: b29b uxth r3, r3
if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
80060dc: 4313 orrs r3, r2
80060de: b29b uxth r3, r3
80060e0: 461a mov r2, r3
80060e2: 2100 movs r1, #0
80060e4: 6878 ldr r0, [r7, #4]
80060e6: f000 fb4c bl 8006782 <HAL_ETH_WritePHYRegister>
80060ea: 4603 mov r3, r0
80060ec: 2b00 cmp r3, #0
80060ee: d00b beq.n 8006108 <HAL_ETH_Init+0x310>
{
/* In case of write timeout */
err = ETH_ERROR;
80060f0: 2301 movs r3, #1
80060f2: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
80060f4: 6939 ldr r1, [r7, #16]
80060f6: 6878 ldr r0, [r7, #4]
80060f8: f000 fd02 bl 8006b00 <ETH_MACDMAConfig>
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
80060fc: 687b ldr r3, [r7, #4]
80060fe: 2201 movs r2, #1
8006100: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return HAL_ERROR */
return HAL_ERROR;
8006104: 2301 movs r3, #1
8006106: e00c b.n 8006122 <HAL_ETH_Init+0x32a>
}
/* Delay to assure PHY configuration */
HAL_Delay(PHY_CONFIG_DELAY);
8006108: f640 70ff movw r0, #4095 ; 0xfff
800610c: f7fe fb6c bl 80047e8 <HAL_Delay>
}
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
8006110: 6939 ldr r1, [r7, #16]
8006112: 6878 ldr r0, [r7, #4]
8006114: f000 fcf4 bl 8006b00 <ETH_MACDMAConfig>
/* Set ETH HAL State to Ready */
heth->State= HAL_ETH_STATE_READY;
8006118: 687b ldr r3, [r7, #4]
800611a: 2201 movs r2, #1
800611c: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return function status */
return HAL_OK;
8006120: 2300 movs r3, #0
}
8006122: 4618 mov r0, r3
8006124: 3720 adds r7, #32
8006126: 46bd mov sp, r7
8006128: bd80 pop {r7, pc}
800612a: bf00 nop
0800612c <HAL_ETH_DMATxDescListInit>:
* @param TxBuff Pointer to the first TxBuffer list
* @param TxBuffCount Number of the used Tx desc in the list
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
{
800612c: b480 push {r7}
800612e: b087 sub sp, #28
8006130: af00 add r7, sp, #0
8006132: 60f8 str r0, [r7, #12]
8006134: 60b9 str r1, [r7, #8]
8006136: 607a str r2, [r7, #4]
8006138: 603b str r3, [r7, #0]
uint32_t i = 0;
800613a: 2300 movs r3, #0
800613c: 617b str r3, [r7, #20]
ETH_DMADescTypeDef *dmatxdesc;
/* Process Locked */
__HAL_LOCK(heth);
800613e: 68fb ldr r3, [r7, #12]
8006140: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8006144: 2b01 cmp r3, #1
8006146: d101 bne.n 800614c <HAL_ETH_DMATxDescListInit+0x20>
8006148: 2302 movs r3, #2
800614a: e052 b.n 80061f2 <HAL_ETH_DMATxDescListInit+0xc6>
800614c: 68fb ldr r3, [r7, #12]
800614e: 2201 movs r2, #1
8006150: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
8006154: 68fb ldr r3, [r7, #12]
8006156: 2202 movs r2, #2
8006158: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
heth->TxDesc = DMATxDescTab;
800615c: 68fb ldr r3, [r7, #12]
800615e: 68ba ldr r2, [r7, #8]
8006160: 62da str r2, [r3, #44] ; 0x2c
/* Fill each DMATxDesc descriptor with the right values */
for(i=0; i < TxBuffCount; i++)
8006162: 2300 movs r3, #0
8006164: 617b str r3, [r7, #20]
8006166: e030 b.n 80061ca <HAL_ETH_DMATxDescListInit+0x9e>
{
/* Get the pointer on the member (i) of the Tx Desc list */
dmatxdesc = DMATxDescTab + i;
8006168: 697b ldr r3, [r7, #20]
800616a: 015b lsls r3, r3, #5
800616c: 68ba ldr r2, [r7, #8]
800616e: 4413 add r3, r2
8006170: 613b str r3, [r7, #16]
/* Set Second Address Chained bit */
dmatxdesc->Status = ETH_DMATXDESC_TCH;
8006172: 693b ldr r3, [r7, #16]
8006174: f44f 1280 mov.w r2, #1048576 ; 0x100000
8006178: 601a str r2, [r3, #0]
/* Set Buffer1 address pointer */
dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
800617a: 697b ldr r3, [r7, #20]
800617c: f240 52f4 movw r2, #1524 ; 0x5f4
8006180: fb02 f303 mul.w r3, r2, r3
8006184: 687a ldr r2, [r7, #4]
8006186: 4413 add r3, r2
8006188: 461a mov r2, r3
800618a: 693b ldr r3, [r7, #16]
800618c: 609a str r2, [r3, #8]
if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
800618e: 68fb ldr r3, [r7, #12]
8006190: 69db ldr r3, [r3, #28]
8006192: 2b00 cmp r3, #0
8006194: d105 bne.n 80061a2 <HAL_ETH_DMATxDescListInit+0x76>
{
/* Set the DMA Tx descriptors checksum insertion */
dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
8006196: 693b ldr r3, [r7, #16]
8006198: 681b ldr r3, [r3, #0]
800619a: f443 0240 orr.w r2, r3, #12582912 ; 0xc00000
800619e: 693b ldr r3, [r7, #16]
80061a0: 601a str r2, [r3, #0]
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
if(i < (TxBuffCount-1))
80061a2: 683b ldr r3, [r7, #0]
80061a4: 3b01 subs r3, #1
80061a6: 697a ldr r2, [r7, #20]
80061a8: 429a cmp r2, r3
80061aa: d208 bcs.n 80061be <HAL_ETH_DMATxDescListInit+0x92>
{
/* Set next descriptor address register with next descriptor base address */
dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
80061ac: 697b ldr r3, [r7, #20]
80061ae: 3301 adds r3, #1
80061b0: 015b lsls r3, r3, #5
80061b2: 68ba ldr r2, [r7, #8]
80061b4: 4413 add r3, r2
80061b6: 461a mov r2, r3
80061b8: 693b ldr r3, [r7, #16]
80061ba: 60da str r2, [r3, #12]
80061bc: e002 b.n 80061c4 <HAL_ETH_DMATxDescListInit+0x98>
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
80061be: 68ba ldr r2, [r7, #8]
80061c0: 693b ldr r3, [r7, #16]
80061c2: 60da str r2, [r3, #12]
for(i=0; i < TxBuffCount; i++)
80061c4: 697b ldr r3, [r7, #20]
80061c6: 3301 adds r3, #1
80061c8: 617b str r3, [r7, #20]
80061ca: 697a ldr r2, [r7, #20]
80061cc: 683b ldr r3, [r7, #0]
80061ce: 429a cmp r2, r3
80061d0: d3ca bcc.n 8006168 <HAL_ETH_DMATxDescListInit+0x3c>
}
}
/* Set Transmit Descriptor List Address Register */
(heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
80061d2: 68fb ldr r3, [r7, #12]
80061d4: 6819 ldr r1, [r3, #0]
80061d6: 68ba ldr r2, [r7, #8]
80061d8: f241 0310 movw r3, #4112 ; 0x1010
80061dc: 440b add r3, r1
80061de: 601a str r2, [r3, #0]
/* Set ETH HAL State to Ready */
heth->State= HAL_ETH_STATE_READY;
80061e0: 68fb ldr r3, [r7, #12]
80061e2: 2201 movs r2, #1
80061e4: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80061e8: 68fb ldr r3, [r7, #12]
80061ea: 2200 movs r2, #0
80061ec: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
80061f0: 2300 movs r3, #0
}
80061f2: 4618 mov r0, r3
80061f4: 371c adds r7, #28
80061f6: 46bd mov sp, r7
80061f8: f85d 7b04 ldr.w r7, [sp], #4
80061fc: 4770 bx lr
080061fe <HAL_ETH_DMARxDescListInit>:
* @param RxBuff Pointer to the first RxBuffer list
* @param RxBuffCount Number of the used Rx desc in the list
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
{
80061fe: b480 push {r7}
8006200: b087 sub sp, #28
8006202: af00 add r7, sp, #0
8006204: 60f8 str r0, [r7, #12]
8006206: 60b9 str r1, [r7, #8]
8006208: 607a str r2, [r7, #4]
800620a: 603b str r3, [r7, #0]
uint32_t i = 0;
800620c: 2300 movs r3, #0
800620e: 617b str r3, [r7, #20]
ETH_DMADescTypeDef *DMARxDesc;
/* Process Locked */
__HAL_LOCK(heth);
8006210: 68fb ldr r3, [r7, #12]
8006212: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8006216: 2b01 cmp r3, #1
8006218: d101 bne.n 800621e <HAL_ETH_DMARxDescListInit+0x20>
800621a: 2302 movs r3, #2
800621c: e056 b.n 80062cc <HAL_ETH_DMARxDescListInit+0xce>
800621e: 68fb ldr r3, [r7, #12]
8006220: 2201 movs r2, #1
8006222: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
8006226: 68fb ldr r3, [r7, #12]
8006228: 2202 movs r2, #2
800622a: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
heth->RxDesc = DMARxDescTab;
800622e: 68fb ldr r3, [r7, #12]
8006230: 68ba ldr r2, [r7, #8]
8006232: 629a str r2, [r3, #40] ; 0x28
/* Fill each DMARxDesc descriptor with the right values */
for(i=0; i < RxBuffCount; i++)
8006234: 2300 movs r3, #0
8006236: 617b str r3, [r7, #20]
8006238: e034 b.n 80062a4 <HAL_ETH_DMARxDescListInit+0xa6>
{
/* Get the pointer on the member (i) of the Rx Desc list */
DMARxDesc = DMARxDescTab+i;
800623a: 697b ldr r3, [r7, #20]
800623c: 015b lsls r3, r3, #5
800623e: 68ba ldr r2, [r7, #8]
8006240: 4413 add r3, r2
8006242: 613b str r3, [r7, #16]
/* Set Own bit of the Rx descriptor Status */
DMARxDesc->Status = ETH_DMARXDESC_OWN;
8006244: 693b ldr r3, [r7, #16]
8006246: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
800624a: 601a str r2, [r3, #0]
/* Set Buffer1 size and Second Address Chained bit */
DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
800624c: 693b ldr r3, [r7, #16]
800624e: f244 52f4 movw r2, #17908 ; 0x45f4
8006252: 605a str r2, [r3, #4]
/* Set Buffer1 address pointer */
DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
8006254: 697b ldr r3, [r7, #20]
8006256: f240 52f4 movw r2, #1524 ; 0x5f4
800625a: fb02 f303 mul.w r3, r2, r3
800625e: 687a ldr r2, [r7, #4]
8006260: 4413 add r3, r2
8006262: 461a mov r2, r3
8006264: 693b ldr r3, [r7, #16]
8006266: 609a str r2, [r3, #8]
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
8006268: 68fb ldr r3, [r7, #12]
800626a: 699b ldr r3, [r3, #24]
800626c: 2b01 cmp r3, #1
800626e: d105 bne.n 800627c <HAL_ETH_DMARxDescListInit+0x7e>
{
/* Enable Ethernet DMA Rx Descriptor interrupt */
DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
8006270: 693b ldr r3, [r7, #16]
8006272: 685b ldr r3, [r3, #4]
8006274: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000
8006278: 693b ldr r3, [r7, #16]
800627a: 605a str r2, [r3, #4]
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
if(i < (RxBuffCount-1))
800627c: 683b ldr r3, [r7, #0]
800627e: 3b01 subs r3, #1
8006280: 697a ldr r2, [r7, #20]
8006282: 429a cmp r2, r3
8006284: d208 bcs.n 8006298 <HAL_ETH_DMARxDescListInit+0x9a>
{
/* Set next descriptor address register with next descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
8006286: 697b ldr r3, [r7, #20]
8006288: 3301 adds r3, #1
800628a: 015b lsls r3, r3, #5
800628c: 68ba ldr r2, [r7, #8]
800628e: 4413 add r3, r2
8006290: 461a mov r2, r3
8006292: 693b ldr r3, [r7, #16]
8006294: 60da str r2, [r3, #12]
8006296: e002 b.n 800629e <HAL_ETH_DMARxDescListInit+0xa0>
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
8006298: 68ba ldr r2, [r7, #8]
800629a: 693b ldr r3, [r7, #16]
800629c: 60da str r2, [r3, #12]
for(i=0; i < RxBuffCount; i++)
800629e: 697b ldr r3, [r7, #20]
80062a0: 3301 adds r3, #1
80062a2: 617b str r3, [r7, #20]
80062a4: 697a ldr r2, [r7, #20]
80062a6: 683b ldr r3, [r7, #0]
80062a8: 429a cmp r2, r3
80062aa: d3c6 bcc.n 800623a <HAL_ETH_DMARxDescListInit+0x3c>
}
}
/* Set Receive Descriptor List Address Register */
(heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
80062ac: 68fb ldr r3, [r7, #12]
80062ae: 6819 ldr r1, [r3, #0]
80062b0: 68ba ldr r2, [r7, #8]
80062b2: f241 030c movw r3, #4108 ; 0x100c
80062b6: 440b add r3, r1
80062b8: 601a str r2, [r3, #0]
/* Set ETH HAL State to Ready */
heth->State= HAL_ETH_STATE_READY;
80062ba: 68fb ldr r3, [r7, #12]
80062bc: 2201 movs r2, #1
80062be: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80062c2: 68fb ldr r3, [r7, #12]
80062c4: 2200 movs r2, #0
80062c6: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
80062ca: 2300 movs r3, #0
}
80062cc: 4618 mov r0, r3
80062ce: 371c adds r7, #28
80062d0: 46bd mov sp, r7
80062d2: f85d 7b04 ldr.w r7, [sp], #4
80062d6: 4770 bx lr
080062d8 <HAL_ETH_TransmitFrame>:
* the configuration information for ETHERNET module
* @param FrameLength Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
{
80062d8: b480 push {r7}
80062da: b087 sub sp, #28
80062dc: af00 add r7, sp, #0
80062de: 6078 str r0, [r7, #4]
80062e0: 6039 str r1, [r7, #0]
uint32_t bufcount = 0, size = 0, i = 0;
80062e2: 2300 movs r3, #0
80062e4: 617b str r3, [r7, #20]
80062e6: 2300 movs r3, #0
80062e8: 60fb str r3, [r7, #12]
80062ea: 2300 movs r3, #0
80062ec: 613b str r3, [r7, #16]
/* Process Locked */
__HAL_LOCK(heth);
80062ee: 687b ldr r3, [r7, #4]
80062f0: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
80062f4: 2b01 cmp r3, #1
80062f6: d101 bne.n 80062fc <HAL_ETH_TransmitFrame+0x24>
80062f8: 2302 movs r3, #2
80062fa: e0cd b.n 8006498 <HAL_ETH_TransmitFrame+0x1c0>
80062fc: 687b ldr r3, [r7, #4]
80062fe: 2201 movs r2, #1
8006300: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
8006304: 687b ldr r3, [r7, #4]
8006306: 2202 movs r2, #2
8006308: f883 2044 strb.w r2, [r3, #68] ; 0x44
if (FrameLength == 0)
800630c: 683b ldr r3, [r7, #0]
800630e: 2b00 cmp r3, #0
8006310: d109 bne.n 8006326 <HAL_ETH_TransmitFrame+0x4e>
{
/* Set ETH HAL state to READY */
heth->State = HAL_ETH_STATE_READY;
8006312: 687b ldr r3, [r7, #4]
8006314: 2201 movs r2, #1
8006316: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800631a: 687b ldr r3, [r7, #4]
800631c: 2200 movs r2, #0
800631e: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_ERROR;
8006322: 2301 movs r3, #1
8006324: e0b8 b.n 8006498 <HAL_ETH_TransmitFrame+0x1c0>
}
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
8006326: 687b ldr r3, [r7, #4]
8006328: 6adb ldr r3, [r3, #44] ; 0x2c
800632a: 681b ldr r3, [r3, #0]
800632c: 2b00 cmp r3, #0
800632e: da09 bge.n 8006344 <HAL_ETH_TransmitFrame+0x6c>
{
/* OWN bit set */
heth->State = HAL_ETH_STATE_BUSY_TX;
8006330: 687b ldr r3, [r7, #4]
8006332: 2212 movs r2, #18
8006334: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006338: 687b ldr r3, [r7, #4]
800633a: 2200 movs r2, #0
800633c: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_ERROR;
8006340: 2301 movs r3, #1
8006342: e0a9 b.n 8006498 <HAL_ETH_TransmitFrame+0x1c0>
}
/* Get the number of needed Tx buffers for the current frame */
if (FrameLength > ETH_TX_BUF_SIZE)
8006344: 683b ldr r3, [r7, #0]
8006346: f240 52f4 movw r2, #1524 ; 0x5f4
800634a: 4293 cmp r3, r2
800634c: d915 bls.n 800637a <HAL_ETH_TransmitFrame+0xa2>
{
bufcount = FrameLength/ETH_TX_BUF_SIZE;
800634e: 683b ldr r3, [r7, #0]
8006350: 4a54 ldr r2, [pc, #336] ; (80064a4 <HAL_ETH_TransmitFrame+0x1cc>)
8006352: fba2 2303 umull r2, r3, r2, r3
8006356: 0a9b lsrs r3, r3, #10
8006358: 617b str r3, [r7, #20]
if (FrameLength % ETH_TX_BUF_SIZE)
800635a: 683a ldr r2, [r7, #0]
800635c: 4b51 ldr r3, [pc, #324] ; (80064a4 <HAL_ETH_TransmitFrame+0x1cc>)
800635e: fba3 1302 umull r1, r3, r3, r2
8006362: 0a9b lsrs r3, r3, #10
8006364: f240 51f4 movw r1, #1524 ; 0x5f4
8006368: fb01 f303 mul.w r3, r1, r3
800636c: 1ad3 subs r3, r2, r3
800636e: 2b00 cmp r3, #0
8006370: d005 beq.n 800637e <HAL_ETH_TransmitFrame+0xa6>
{
bufcount++;
8006372: 697b ldr r3, [r7, #20]
8006374: 3301 adds r3, #1
8006376: 617b str r3, [r7, #20]
8006378: e001 b.n 800637e <HAL_ETH_TransmitFrame+0xa6>
}
}
else
{
bufcount = 1;
800637a: 2301 movs r3, #1
800637c: 617b str r3, [r7, #20]
}
if (bufcount == 1)
800637e: 697b ldr r3, [r7, #20]
8006380: 2b01 cmp r3, #1
8006382: d11c bne.n 80063be <HAL_ETH_TransmitFrame+0xe6>
{
/* Set LAST and FIRST segment */
heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
8006384: 687b ldr r3, [r7, #4]
8006386: 6adb ldr r3, [r3, #44] ; 0x2c
8006388: 681a ldr r2, [r3, #0]
800638a: 687b ldr r3, [r7, #4]
800638c: 6adb ldr r3, [r3, #44] ; 0x2c
800638e: f042 5240 orr.w r2, r2, #805306368 ; 0x30000000
8006392: 601a str r2, [r3, #0]
/* Set frame size */
heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
8006394: 687b ldr r3, [r7, #4]
8006396: 6adb ldr r3, [r3, #44] ; 0x2c
8006398: 683a ldr r2, [r7, #0]
800639a: f3c2 020c ubfx r2, r2, #0, #13
800639e: 605a str r2, [r3, #4]
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
80063a0: 687b ldr r3, [r7, #4]
80063a2: 6adb ldr r3, [r3, #44] ; 0x2c
80063a4: 681a ldr r2, [r3, #0]
80063a6: 687b ldr r3, [r7, #4]
80063a8: 6adb ldr r3, [r3, #44] ; 0x2c
80063aa: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000
80063ae: 601a str r2, [r3, #0]
/* Point to next descriptor */
heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
80063b0: 687b ldr r3, [r7, #4]
80063b2: 6adb ldr r3, [r3, #44] ; 0x2c
80063b4: 68db ldr r3, [r3, #12]
80063b6: 461a mov r2, r3
80063b8: 687b ldr r3, [r7, #4]
80063ba: 62da str r2, [r3, #44] ; 0x2c
80063bc: e04b b.n 8006456 <HAL_ETH_TransmitFrame+0x17e>
}
else
{
for (i=0; i< bufcount; i++)
80063be: 2300 movs r3, #0
80063c0: 613b str r3, [r7, #16]
80063c2: e044 b.n 800644e <HAL_ETH_TransmitFrame+0x176>
{
/* Clear FIRST and LAST segment bits */
heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
80063c4: 687b ldr r3, [r7, #4]
80063c6: 6adb ldr r3, [r3, #44] ; 0x2c
80063c8: 681a ldr r2, [r3, #0]
80063ca: 687b ldr r3, [r7, #4]
80063cc: 6adb ldr r3, [r3, #44] ; 0x2c
80063ce: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
80063d2: 601a str r2, [r3, #0]
if (i == 0)
80063d4: 693b ldr r3, [r7, #16]
80063d6: 2b00 cmp r3, #0
80063d8: d107 bne.n 80063ea <HAL_ETH_TransmitFrame+0x112>
{
/* Setting the first segment bit */
heth->TxDesc->Status |= ETH_DMATXDESC_FS;
80063da: 687b ldr r3, [r7, #4]
80063dc: 6adb ldr r3, [r3, #44] ; 0x2c
80063de: 681a ldr r2, [r3, #0]
80063e0: 687b ldr r3, [r7, #4]
80063e2: 6adb ldr r3, [r3, #44] ; 0x2c
80063e4: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
80063e8: 601a str r2, [r3, #0]
}
/* Program size */
heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
80063ea: 687b ldr r3, [r7, #4]
80063ec: 6adb ldr r3, [r3, #44] ; 0x2c
80063ee: f240 52f4 movw r2, #1524 ; 0x5f4
80063f2: 605a str r2, [r3, #4]
if (i == (bufcount-1))
80063f4: 697b ldr r3, [r7, #20]
80063f6: 3b01 subs r3, #1
80063f8: 693a ldr r2, [r7, #16]
80063fa: 429a cmp r2, r3
80063fc: d116 bne.n 800642c <HAL_ETH_TransmitFrame+0x154>
{
/* Setting the last segment bit */
heth->TxDesc->Status |= ETH_DMATXDESC_LS;
80063fe: 687b ldr r3, [r7, #4]
8006400: 6adb ldr r3, [r3, #44] ; 0x2c
8006402: 681a ldr r2, [r3, #0]
8006404: 687b ldr r3, [r7, #4]
8006406: 6adb ldr r3, [r3, #44] ; 0x2c
8006408: f042 5200 orr.w r2, r2, #536870912 ; 0x20000000
800640c: 601a str r2, [r3, #0]
size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
800640e: 697b ldr r3, [r7, #20]
8006410: 4a25 ldr r2, [pc, #148] ; (80064a8 <HAL_ETH_TransmitFrame+0x1d0>)
8006412: fb02 f203 mul.w r2, r2, r3
8006416: 683b ldr r3, [r7, #0]
8006418: 4413 add r3, r2
800641a: f203 53f4 addw r3, r3, #1524 ; 0x5f4
800641e: 60fb str r3, [r7, #12]
heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
8006420: 687b ldr r3, [r7, #4]
8006422: 6adb ldr r3, [r3, #44] ; 0x2c
8006424: 68fa ldr r2, [r7, #12]
8006426: f3c2 020c ubfx r2, r2, #0, #13
800642a: 605a str r2, [r3, #4]
}
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
800642c: 687b ldr r3, [r7, #4]
800642e: 6adb ldr r3, [r3, #44] ; 0x2c
8006430: 681a ldr r2, [r3, #0]
8006432: 687b ldr r3, [r7, #4]
8006434: 6adb ldr r3, [r3, #44] ; 0x2c
8006436: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000
800643a: 601a str r2, [r3, #0]
/* point to next descriptor */
heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
800643c: 687b ldr r3, [r7, #4]
800643e: 6adb ldr r3, [r3, #44] ; 0x2c
8006440: 68db ldr r3, [r3, #12]
8006442: 461a mov r2, r3
8006444: 687b ldr r3, [r7, #4]
8006446: 62da str r2, [r3, #44] ; 0x2c
for (i=0; i< bufcount; i++)
8006448: 693b ldr r3, [r7, #16]
800644a: 3301 adds r3, #1
800644c: 613b str r3, [r7, #16]
800644e: 693a ldr r2, [r7, #16]
8006450: 697b ldr r3, [r7, #20]
8006452: 429a cmp r2, r3
8006454: d3b6 bcc.n 80063c4 <HAL_ETH_TransmitFrame+0xec>
}
}
/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
8006456: 687b ldr r3, [r7, #4]
8006458: 681a ldr r2, [r3, #0]
800645a: f241 0314 movw r3, #4116 ; 0x1014
800645e: 4413 add r3, r2
8006460: 681b ldr r3, [r3, #0]
8006462: f003 0304 and.w r3, r3, #4
8006466: 2b00 cmp r3, #0
8006468: d00d beq.n 8006486 <HAL_ETH_TransmitFrame+0x1ae>
{
/* Clear TBUS ETHERNET DMA flag */
(heth->Instance)->DMASR = ETH_DMASR_TBUS;
800646a: 687b ldr r3, [r7, #4]
800646c: 681a ldr r2, [r3, #0]
800646e: f241 0314 movw r3, #4116 ; 0x1014
8006472: 4413 add r3, r2
8006474: 2204 movs r2, #4
8006476: 601a str r2, [r3, #0]
/* Resume DMA transmission*/
(heth->Instance)->DMATPDR = 0;
8006478: 687b ldr r3, [r7, #4]
800647a: 681a ldr r2, [r3, #0]
800647c: f241 0304 movw r3, #4100 ; 0x1004
8006480: 4413 add r3, r2
8006482: 2200 movs r2, #0
8006484: 601a str r2, [r3, #0]
}
/* Set ETH HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
8006486: 687b ldr r3, [r7, #4]
8006488: 2201 movs r2, #1
800648a: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800648e: 687b ldr r3, [r7, #4]
8006490: 2200 movs r2, #0
8006492: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006496: 2300 movs r3, #0
}
8006498: 4618 mov r0, r3
800649a: 371c adds r7, #28
800649c: 46bd mov sp, r7
800649e: f85d 7b04 ldr.w r7, [sp], #4
80064a2: 4770 bx lr
80064a4: ac02b00b .word 0xac02b00b
80064a8: fffffa0c .word 0xfffffa0c
080064ac <HAL_ETH_GetReceivedFrame_IT>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
{
80064ac: b480 push {r7}
80064ae: b085 sub sp, #20
80064b0: af00 add r7, sp, #0
80064b2: 6078 str r0, [r7, #4]
uint32_t descriptorscancounter = 0;
80064b4: 2300 movs r3, #0
80064b6: 60fb str r3, [r7, #12]
/* Process Locked */
__HAL_LOCK(heth);
80064b8: 687b ldr r3, [r7, #4]
80064ba: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
80064be: 2b01 cmp r3, #1
80064c0: d101 bne.n 80064c6 <HAL_ETH_GetReceivedFrame_IT+0x1a>
80064c2: 2302 movs r3, #2
80064c4: e074 b.n 80065b0 <HAL_ETH_GetReceivedFrame_IT+0x104>
80064c6: 687b ldr r3, [r7, #4]
80064c8: 2201 movs r2, #1
80064ca: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set ETH HAL State to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
80064ce: 687b ldr r3, [r7, #4]
80064d0: 2202 movs r2, #2
80064d2: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Scan descriptors owned by CPU */
while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
80064d6: e05a b.n 800658e <HAL_ETH_GetReceivedFrame_IT+0xe2>
{
/* Just for security */
descriptorscancounter++;
80064d8: 68fb ldr r3, [r7, #12]
80064da: 3301 adds r3, #1
80064dc: 60fb str r3, [r7, #12]
/* Check if first segment in frame */
/* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
80064de: 687b ldr r3, [r7, #4]
80064e0: 6a9b ldr r3, [r3, #40] ; 0x28
80064e2: 681b ldr r3, [r3, #0]
80064e4: f403 7340 and.w r3, r3, #768 ; 0x300
80064e8: f5b3 7f00 cmp.w r3, #512 ; 0x200
80064ec: d10d bne.n 800650a <HAL_ETH_GetReceivedFrame_IT+0x5e>
{
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
80064ee: 687b ldr r3, [r7, #4]
80064f0: 6a9a ldr r2, [r3, #40] ; 0x28
80064f2: 687b ldr r3, [r7, #4]
80064f4: 631a str r2, [r3, #48] ; 0x30
heth->RxFrameInfos.SegCount = 1;
80064f6: 687b ldr r3, [r7, #4]
80064f8: 2201 movs r2, #1
80064fa: 639a str r2, [r3, #56] ; 0x38
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
80064fc: 687b ldr r3, [r7, #4]
80064fe: 6a9b ldr r3, [r3, #40] ; 0x28
8006500: 68db ldr r3, [r3, #12]
8006502: 461a mov r2, r3
8006504: 687b ldr r3, [r7, #4]
8006506: 629a str r2, [r3, #40] ; 0x28
8006508: e041 b.n 800658e <HAL_ETH_GetReceivedFrame_IT+0xe2>
}
/* Check if intermediate segment */
/* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
800650a: 687b ldr r3, [r7, #4]
800650c: 6a9b ldr r3, [r3, #40] ; 0x28
800650e: 681b ldr r3, [r3, #0]
8006510: f403 7340 and.w r3, r3, #768 ; 0x300
8006514: 2b00 cmp r3, #0
8006516: d10b bne.n 8006530 <HAL_ETH_GetReceivedFrame_IT+0x84>
{
/* Increment segment count */
(heth->RxFrameInfos.SegCount)++;
8006518: 687b ldr r3, [r7, #4]
800651a: 6b9b ldr r3, [r3, #56] ; 0x38
800651c: 1c5a adds r2, r3, #1
800651e: 687b ldr r3, [r7, #4]
8006520: 639a str r2, [r3, #56] ; 0x38
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
8006522: 687b ldr r3, [r7, #4]
8006524: 6a9b ldr r3, [r3, #40] ; 0x28
8006526: 68db ldr r3, [r3, #12]
8006528: 461a mov r2, r3
800652a: 687b ldr r3, [r7, #4]
800652c: 629a str r2, [r3, #40] ; 0x28
800652e: e02e b.n 800658e <HAL_ETH_GetReceivedFrame_IT+0xe2>
}
/* Should be last segment */
else
{
/* Last segment */
heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
8006530: 687b ldr r3, [r7, #4]
8006532: 6a9a ldr r2, [r3, #40] ; 0x28
8006534: 687b ldr r3, [r7, #4]
8006536: 635a str r2, [r3, #52] ; 0x34
/* Increment segment count */
(heth->RxFrameInfos.SegCount)++;
8006538: 687b ldr r3, [r7, #4]
800653a: 6b9b ldr r3, [r3, #56] ; 0x38
800653c: 1c5a adds r2, r3, #1
800653e: 687b ldr r3, [r7, #4]
8006540: 639a str r2, [r3, #56] ; 0x38
/* Check if last segment is first segment: one segment contains the frame */
if ((heth->RxFrameInfos.SegCount) == 1)
8006542: 687b ldr r3, [r7, #4]
8006544: 6b9b ldr r3, [r3, #56] ; 0x38
8006546: 2b01 cmp r3, #1
8006548: d103 bne.n 8006552 <HAL_ETH_GetReceivedFrame_IT+0xa6>
{
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
800654a: 687b ldr r3, [r7, #4]
800654c: 6a9a ldr r2, [r3, #40] ; 0x28
800654e: 687b ldr r3, [r7, #4]
8006550: 631a str r2, [r3, #48] ; 0x30
}
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
8006552: 687b ldr r3, [r7, #4]
8006554: 6a9b ldr r3, [r3, #40] ; 0x28
8006556: 681b ldr r3, [r3, #0]
8006558: 0c1b lsrs r3, r3, #16
800655a: f3c3 030d ubfx r3, r3, #0, #14
800655e: 1f1a subs r2, r3, #4
8006560: 687b ldr r3, [r7, #4]
8006562: 63da str r2, [r3, #60] ; 0x3c
/* Get the address of the buffer start address */
heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
8006564: 687b ldr r3, [r7, #4]
8006566: 6b1b ldr r3, [r3, #48] ; 0x30
8006568: 689a ldr r2, [r3, #8]
800656a: 687b ldr r3, [r7, #4]
800656c: 641a str r2, [r3, #64] ; 0x40
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
800656e: 687b ldr r3, [r7, #4]
8006570: 6a9b ldr r3, [r3, #40] ; 0x28
8006572: 68db ldr r3, [r3, #12]
8006574: 461a mov r2, r3
8006576: 687b ldr r3, [r7, #4]
8006578: 629a str r2, [r3, #40] ; 0x28
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
800657a: 687b ldr r3, [r7, #4]
800657c: 2201 movs r2, #1
800657e: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006582: 687b ldr r3, [r7, #4]
8006584: 2200 movs r2, #0
8006586: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
800658a: 2300 movs r3, #0
800658c: e010 b.n 80065b0 <HAL_ETH_GetReceivedFrame_IT+0x104>
while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
800658e: 687b ldr r3, [r7, #4]
8006590: 6a9b ldr r3, [r3, #40] ; 0x28
8006592: 681b ldr r3, [r3, #0]
8006594: 2b00 cmp r3, #0
8006596: db02 blt.n 800659e <HAL_ETH_GetReceivedFrame_IT+0xf2>
8006598: 68fb ldr r3, [r7, #12]
800659a: 2b03 cmp r3, #3
800659c: d99c bls.n 80064d8 <HAL_ETH_GetReceivedFrame_IT+0x2c>
}
}
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
800659e: 687b ldr r3, [r7, #4]
80065a0: 2201 movs r2, #1
80065a2: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80065a6: 687b ldr r3, [r7, #4]
80065a8: 2200 movs r2, #0
80065aa: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_ERROR;
80065ae: 2301 movs r3, #1
}
80065b0: 4618 mov r0, r3
80065b2: 3714 adds r7, #20
80065b4: 46bd mov sp, r7
80065b6: f85d 7b04 ldr.w r7, [sp], #4
80065ba: 4770 bx lr
080065bc <HAL_ETH_IRQHandler>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
{
80065bc: b580 push {r7, lr}
80065be: b082 sub sp, #8
80065c0: af00 add r7, sp, #0
80065c2: 6078 str r0, [r7, #4]
/* Frame received */
if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
80065c4: 687b ldr r3, [r7, #4]
80065c6: 681a ldr r2, [r3, #0]
80065c8: f241 0314 movw r3, #4116 ; 0x1014
80065cc: 4413 add r3, r2
80065ce: 681b ldr r3, [r3, #0]
80065d0: f003 0340 and.w r3, r3, #64 ; 0x40
80065d4: 2b40 cmp r3, #64 ; 0x40
80065d6: d112 bne.n 80065fe <HAL_ETH_IRQHandler+0x42>
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/*Call registered Receive complete callback*/
heth->RxCpltCallback(heth);
#else
/* Receive complete callback */
HAL_ETH_RxCpltCallback(heth);
80065d8: 6878 ldr r0, [r7, #4]
80065da: f004 fdf9 bl 800b1d0 <HAL_ETH_RxCpltCallback>
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the Eth DMA Rx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
80065de: 687b ldr r3, [r7, #4]
80065e0: 681a ldr r2, [r3, #0]
80065e2: f241 0314 movw r3, #4116 ; 0x1014
80065e6: 4413 add r3, r2
80065e8: 2240 movs r2, #64 ; 0x40
80065ea: 601a str r2, [r3, #0]
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
80065ec: 687b ldr r3, [r7, #4]
80065ee: 2201 movs r2, #1
80065f0: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80065f4: 687b ldr r3, [r7, #4]
80065f6: 2200 movs r2, #0
80065f8: f883 2045 strb.w r2, [r3, #69] ; 0x45
80065fc: e01b b.n 8006636 <HAL_ETH_IRQHandler+0x7a>
}
/* Frame transmitted */
else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
80065fe: 687b ldr r3, [r7, #4]
8006600: 681a ldr r2, [r3, #0]
8006602: f241 0314 movw r3, #4116 ; 0x1014
8006606: 4413 add r3, r2
8006608: 681b ldr r3, [r3, #0]
800660a: f003 0301 and.w r3, r3, #1
800660e: 2b01 cmp r3, #1
8006610: d111 bne.n 8006636 <HAL_ETH_IRQHandler+0x7a>
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/* Call resgistered Transfer complete callback*/
heth->TxCpltCallback(heth);
#else
/* Transfer complete callback */
HAL_ETH_TxCpltCallback(heth);
8006612: 6878 ldr r0, [r7, #4]
8006614: f000 f839 bl 800668a <HAL_ETH_TxCpltCallback>
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the Eth DMA Tx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
8006618: 687b ldr r3, [r7, #4]
800661a: 681a ldr r2, [r3, #0]
800661c: f241 0314 movw r3, #4116 ; 0x1014
8006620: 4413 add r3, r2
8006622: 2201 movs r2, #1
8006624: 601a str r2, [r3, #0]
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
8006626: 687b ldr r3, [r7, #4]
8006628: 2201 movs r2, #1
800662a: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800662e: 687b ldr r3, [r7, #4]
8006630: 2200 movs r2, #0
8006632: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
/* Clear the interrupt flags */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
8006636: 687b ldr r3, [r7, #4]
8006638: 681a ldr r2, [r3, #0]
800663a: f241 0314 movw r3, #4116 ; 0x1014
800663e: 4413 add r3, r2
8006640: f44f 3280 mov.w r2, #65536 ; 0x10000
8006644: 601a str r2, [r3, #0]
/* ETH DMA Error */
if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
8006646: 687b ldr r3, [r7, #4]
8006648: 681a ldr r2, [r3, #0]
800664a: f241 0314 movw r3, #4116 ; 0x1014
800664e: 4413 add r3, r2
8006650: 681b ldr r3, [r3, #0]
8006652: f403 4300 and.w r3, r3, #32768 ; 0x8000
8006656: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
800665a: d112 bne.n 8006682 <HAL_ETH_IRQHandler+0xc6>
{
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
heth->DMAErrorCallback(heth);
#else
/* Ethernet Error callback */
HAL_ETH_ErrorCallback(heth);
800665c: 6878 ldr r0, [r7, #4]
800665e: f000 f81e bl 800669e <HAL_ETH_ErrorCallback>
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the interrupt flags */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
8006662: 687b ldr r3, [r7, #4]
8006664: 681a ldr r2, [r3, #0]
8006666: f241 0314 movw r3, #4116 ; 0x1014
800666a: 4413 add r3, r2
800666c: f44f 4200 mov.w r2, #32768 ; 0x8000
8006670: 601a str r2, [r3, #0]
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
8006672: 687b ldr r3, [r7, #4]
8006674: 2201 movs r2, #1
8006676: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800667a: 687b ldr r3, [r7, #4]
800667c: 2200 movs r2, #0
800667e: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
}
8006682: bf00 nop
8006684: 3708 adds r7, #8
8006686: 46bd mov sp, r7
8006688: bd80 pop {r7, pc}
0800668a <HAL_ETH_TxCpltCallback>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
{
800668a: b480 push {r7}
800668c: b083 sub sp, #12
800668e: af00 add r7, sp, #0
8006690: 6078 str r0, [r7, #4]
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_TxCpltCallback could be implemented in the user file
*/
}
8006692: bf00 nop
8006694: 370c adds r7, #12
8006696: 46bd mov sp, r7
8006698: f85d 7b04 ldr.w r7, [sp], #4
800669c: 4770 bx lr
0800669e <HAL_ETH_ErrorCallback>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
{
800669e: b480 push {r7}
80066a0: b083 sub sp, #12
80066a2: af00 add r7, sp, #0
80066a4: 6078 str r0, [r7, #4]
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_ErrorCallback could be implemented in the user file
*/
}
80066a6: bf00 nop
80066a8: 370c adds r7, #12
80066aa: 46bd mov sp, r7
80066ac: f85d 7b04 ldr.w r7, [sp], #4
80066b0: 4770 bx lr
080066b2 <HAL_ETH_ReadPHYRegister>:
* More PHY register could be read depending on the used PHY
* @param RegValue PHY register value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
{
80066b2: b580 push {r7, lr}
80066b4: b086 sub sp, #24
80066b6: af00 add r7, sp, #0
80066b8: 60f8 str r0, [r7, #12]
80066ba: 460b mov r3, r1
80066bc: 607a str r2, [r7, #4]
80066be: 817b strh r3, [r7, #10]
uint32_t tmpreg = 0;
80066c0: 2300 movs r3, #0
80066c2: 617b str r3, [r7, #20]
uint32_t tickstart = 0;
80066c4: 2300 movs r3, #0
80066c6: 613b str r3, [r7, #16]
/* Check parameters */
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
/* Check the ETH peripheral state */
if(heth->State == HAL_ETH_STATE_BUSY_RD)
80066c8: 68fb ldr r3, [r7, #12]
80066ca: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
80066ce: b2db uxtb r3, r3
80066d0: 2b82 cmp r3, #130 ; 0x82
80066d2: d101 bne.n 80066d8 <HAL_ETH_ReadPHYRegister+0x26>
{
return HAL_BUSY;
80066d4: 2302 movs r3, #2
80066d6: e050 b.n 800677a <HAL_ETH_ReadPHYRegister+0xc8>
}
/* Set ETH HAL State to BUSY_RD */
heth->State = HAL_ETH_STATE_BUSY_RD;
80066d8: 68fb ldr r3, [r7, #12]
80066da: 2282 movs r2, #130 ; 0x82
80066dc: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Get the ETHERNET MACMIIAR value */
tmpreg = heth->Instance->MACMIIAR;
80066e0: 68fb ldr r3, [r7, #12]
80066e2: 681b ldr r3, [r3, #0]
80066e4: 691b ldr r3, [r3, #16]
80066e6: 617b str r3, [r7, #20]
/* Keep only the CSR Clock Range CR[2:0] bits value */
tmpreg &= ~ETH_MACMIIAR_CR_MASK;
80066e8: 697b ldr r3, [r7, #20]
80066ea: f003 031c and.w r3, r3, #28
80066ee: 617b str r3, [r7, #20]
/* Prepare the MII address register value */
tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
80066f0: 68fb ldr r3, [r7, #12]
80066f2: 8a1b ldrh r3, [r3, #16]
80066f4: 02db lsls r3, r3, #11
80066f6: b29b uxth r3, r3
80066f8: 697a ldr r2, [r7, #20]
80066fa: 4313 orrs r3, r2
80066fc: 617b str r3, [r7, #20]
tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
80066fe: 897b ldrh r3, [r7, #10]
8006700: 019b lsls r3, r3, #6
8006702: f403 63f8 and.w r3, r3, #1984 ; 0x7c0
8006706: 697a ldr r2, [r7, #20]
8006708: 4313 orrs r3, r2
800670a: 617b str r3, [r7, #20]
tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
800670c: 697b ldr r3, [r7, #20]
800670e: f023 0302 bic.w r3, r3, #2
8006712: 617b str r3, [r7, #20]
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
8006714: 697b ldr r3, [r7, #20]
8006716: f043 0301 orr.w r3, r3, #1
800671a: 617b str r3, [r7, #20]
/* Write the result value into the MII Address register */
heth->Instance->MACMIIAR = tmpreg;
800671c: 68fb ldr r3, [r7, #12]
800671e: 681b ldr r3, [r3, #0]
8006720: 697a ldr r2, [r7, #20]
8006722: 611a str r2, [r3, #16]
/* Get tick */
tickstart = HAL_GetTick();
8006724: f7fe f854 bl 80047d0 <HAL_GetTick>
8006728: 6138 str r0, [r7, #16]
/* Check for the Busy flag */
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
800672a: e015 b.n 8006758 <HAL_ETH_ReadPHYRegister+0xa6>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
800672c: f7fe f850 bl 80047d0 <HAL_GetTick>
8006730: 4602 mov r2, r0
8006732: 693b ldr r3, [r7, #16]
8006734: 1ad3 subs r3, r2, r3
8006736: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
800673a: d309 bcc.n 8006750 <HAL_ETH_ReadPHYRegister+0x9e>
{
heth->State= HAL_ETH_STATE_READY;
800673c: 68fb ldr r3, [r7, #12]
800673e: 2201 movs r2, #1
8006740: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006744: 68fb ldr r3, [r7, #12]
8006746: 2200 movs r2, #0
8006748: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_TIMEOUT;
800674c: 2303 movs r3, #3
800674e: e014 b.n 800677a <HAL_ETH_ReadPHYRegister+0xc8>
}
tmpreg = heth->Instance->MACMIIAR;
8006750: 68fb ldr r3, [r7, #12]
8006752: 681b ldr r3, [r3, #0]
8006754: 691b ldr r3, [r3, #16]
8006756: 617b str r3, [r7, #20]
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
8006758: 697b ldr r3, [r7, #20]
800675a: f003 0301 and.w r3, r3, #1
800675e: 2b00 cmp r3, #0
8006760: d1e4 bne.n 800672c <HAL_ETH_ReadPHYRegister+0x7a>
}
/* Get MACMIIDR value */
*RegValue = (uint16_t)(heth->Instance->MACMIIDR);
8006762: 68fb ldr r3, [r7, #12]
8006764: 681b ldr r3, [r3, #0]
8006766: 695b ldr r3, [r3, #20]
8006768: b29b uxth r3, r3
800676a: 461a mov r2, r3
800676c: 687b ldr r3, [r7, #4]
800676e: 601a str r2, [r3, #0]
/* Set ETH HAL State to READY */
heth->State = HAL_ETH_STATE_READY;
8006770: 68fb ldr r3, [r7, #12]
8006772: 2201 movs r2, #1
8006774: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return function status */
return HAL_OK;
8006778: 2300 movs r3, #0
}
800677a: 4618 mov r0, r3
800677c: 3718 adds r7, #24
800677e: 46bd mov sp, r7
8006780: bd80 pop {r7, pc}
08006782 <HAL_ETH_WritePHYRegister>:
* More PHY register could be written depending on the used PHY
* @param RegValue the value to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
{
8006782: b580 push {r7, lr}
8006784: b086 sub sp, #24
8006786: af00 add r7, sp, #0
8006788: 60f8 str r0, [r7, #12]
800678a: 460b mov r3, r1
800678c: 607a str r2, [r7, #4]
800678e: 817b strh r3, [r7, #10]
uint32_t tmpreg = 0;
8006790: 2300 movs r3, #0
8006792: 617b str r3, [r7, #20]
uint32_t tickstart = 0;
8006794: 2300 movs r3, #0
8006796: 613b str r3, [r7, #16]
/* Check parameters */
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
/* Check the ETH peripheral state */
if(heth->State == HAL_ETH_STATE_BUSY_WR)
8006798: 68fb ldr r3, [r7, #12]
800679a: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800679e: b2db uxtb r3, r3
80067a0: 2b42 cmp r3, #66 ; 0x42
80067a2: d101 bne.n 80067a8 <HAL_ETH_WritePHYRegister+0x26>
{
return HAL_BUSY;
80067a4: 2302 movs r3, #2
80067a6: e04e b.n 8006846 <HAL_ETH_WritePHYRegister+0xc4>
}
/* Set ETH HAL State to BUSY_WR */
heth->State = HAL_ETH_STATE_BUSY_WR;
80067a8: 68fb ldr r3, [r7, #12]
80067aa: 2242 movs r2, #66 ; 0x42
80067ac: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Get the ETHERNET MACMIIAR value */
tmpreg = heth->Instance->MACMIIAR;
80067b0: 68fb ldr r3, [r7, #12]
80067b2: 681b ldr r3, [r3, #0]
80067b4: 691b ldr r3, [r3, #16]
80067b6: 617b str r3, [r7, #20]
/* Keep only the CSR Clock Range CR[2:0] bits value */
tmpreg &= ~ETH_MACMIIAR_CR_MASK;
80067b8: 697b ldr r3, [r7, #20]
80067ba: f003 031c and.w r3, r3, #28
80067be: 617b str r3, [r7, #20]
/* Prepare the MII register address value */
tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
80067c0: 68fb ldr r3, [r7, #12]
80067c2: 8a1b ldrh r3, [r3, #16]
80067c4: 02db lsls r3, r3, #11
80067c6: b29b uxth r3, r3
80067c8: 697a ldr r2, [r7, #20]
80067ca: 4313 orrs r3, r2
80067cc: 617b str r3, [r7, #20]
tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
80067ce: 897b ldrh r3, [r7, #10]
80067d0: 019b lsls r3, r3, #6
80067d2: f403 63f8 and.w r3, r3, #1984 ; 0x7c0
80067d6: 697a ldr r2, [r7, #20]
80067d8: 4313 orrs r3, r2
80067da: 617b str r3, [r7, #20]
tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
80067dc: 697b ldr r3, [r7, #20]
80067de: f043 0302 orr.w r3, r3, #2
80067e2: 617b str r3, [r7, #20]
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
80067e4: 697b ldr r3, [r7, #20]
80067e6: f043 0301 orr.w r3, r3, #1
80067ea: 617b str r3, [r7, #20]
/* Give the value to the MII data register */
heth->Instance->MACMIIDR = (uint16_t)RegValue;
80067ec: 687b ldr r3, [r7, #4]
80067ee: b29a uxth r2, r3
80067f0: 68fb ldr r3, [r7, #12]
80067f2: 681b ldr r3, [r3, #0]
80067f4: 615a str r2, [r3, #20]
/* Write the result value into the MII Address register */
heth->Instance->MACMIIAR = tmpreg;
80067f6: 68fb ldr r3, [r7, #12]
80067f8: 681b ldr r3, [r3, #0]
80067fa: 697a ldr r2, [r7, #20]
80067fc: 611a str r2, [r3, #16]
/* Get tick */
tickstart = HAL_GetTick();
80067fe: f7fd ffe7 bl 80047d0 <HAL_GetTick>
8006802: 6138 str r0, [r7, #16]
/* Check for the Busy flag */
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
8006804: e015 b.n 8006832 <HAL_ETH_WritePHYRegister+0xb0>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
8006806: f7fd ffe3 bl 80047d0 <HAL_GetTick>
800680a: 4602 mov r2, r0
800680c: 693b ldr r3, [r7, #16]
800680e: 1ad3 subs r3, r2, r3
8006810: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8006814: d309 bcc.n 800682a <HAL_ETH_WritePHYRegister+0xa8>
{
heth->State= HAL_ETH_STATE_READY;
8006816: 68fb ldr r3, [r7, #12]
8006818: 2201 movs r2, #1
800681a: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800681e: 68fb ldr r3, [r7, #12]
8006820: 2200 movs r2, #0
8006822: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_TIMEOUT;
8006826: 2303 movs r3, #3
8006828: e00d b.n 8006846 <HAL_ETH_WritePHYRegister+0xc4>
}
tmpreg = heth->Instance->MACMIIAR;
800682a: 68fb ldr r3, [r7, #12]
800682c: 681b ldr r3, [r3, #0]
800682e: 691b ldr r3, [r3, #16]
8006830: 617b str r3, [r7, #20]
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
8006832: 697b ldr r3, [r7, #20]
8006834: f003 0301 and.w r3, r3, #1
8006838: 2b00 cmp r3, #0
800683a: d1e4 bne.n 8006806 <HAL_ETH_WritePHYRegister+0x84>
}
/* Set ETH HAL State to READY */
heth->State = HAL_ETH_STATE_READY;
800683c: 68fb ldr r3, [r7, #12]
800683e: 2201 movs r2, #1
8006840: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return function status */
return HAL_OK;
8006844: 2300 movs r3, #0
}
8006846: 4618 mov r0, r3
8006848: 3718 adds r7, #24
800684a: 46bd mov sp, r7
800684c: bd80 pop {r7, pc}
0800684e <HAL_ETH_Start>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
{
800684e: b580 push {r7, lr}
8006850: b082 sub sp, #8
8006852: af00 add r7, sp, #0
8006854: 6078 str r0, [r7, #4]
/* Process Locked */
__HAL_LOCK(heth);
8006856: 687b ldr r3, [r7, #4]
8006858: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800685c: 2b01 cmp r3, #1
800685e: d101 bne.n 8006864 <HAL_ETH_Start+0x16>
8006860: 2302 movs r3, #2
8006862: e01f b.n 80068a4 <HAL_ETH_Start+0x56>
8006864: 687b ldr r3, [r7, #4]
8006866: 2201 movs r2, #1
8006868: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
800686c: 687b ldr r3, [r7, #4]
800686e: 2202 movs r2, #2
8006870: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Enable transmit state machine of the MAC for transmission on the MII */
ETH_MACTransmissionEnable(heth);
8006874: 6878 ldr r0, [r7, #4]
8006876: f000 fb45 bl 8006f04 <ETH_MACTransmissionEnable>
/* Enable receive state machine of the MAC for reception from the MII */
ETH_MACReceptionEnable(heth);
800687a: 6878 ldr r0, [r7, #4]
800687c: f000 fb7c bl 8006f78 <ETH_MACReceptionEnable>
/* Flush Transmit FIFO */
ETH_FlushTransmitFIFO(heth);
8006880: 6878 ldr r0, [r7, #4]
8006882: f000 fc13 bl 80070ac <ETH_FlushTransmitFIFO>
/* Start DMA transmission */
ETH_DMATransmissionEnable(heth);
8006886: 6878 ldr r0, [r7, #4]
8006888: f000 fbb0 bl 8006fec <ETH_DMATransmissionEnable>
/* Start DMA reception */
ETH_DMAReceptionEnable(heth);
800688c: 6878 ldr r0, [r7, #4]
800688e: f000 fbdd bl 800704c <ETH_DMAReceptionEnable>
/* Set the ETH state to READY*/
heth->State= HAL_ETH_STATE_READY;
8006892: 687b ldr r3, [r7, #4]
8006894: 2201 movs r2, #1
8006896: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800689a: 687b ldr r3, [r7, #4]
800689c: 2200 movs r2, #0
800689e: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
80068a2: 2300 movs r3, #0
}
80068a4: 4618 mov r0, r3
80068a6: 3708 adds r7, #8
80068a8: 46bd mov sp, r7
80068aa: bd80 pop {r7, pc}
080068ac <HAL_ETH_Stop>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
{
80068ac: b580 push {r7, lr}
80068ae: b082 sub sp, #8
80068b0: af00 add r7, sp, #0
80068b2: 6078 str r0, [r7, #4]
/* Process Locked */
__HAL_LOCK(heth);
80068b4: 687b ldr r3, [r7, #4]
80068b6: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
80068ba: 2b01 cmp r3, #1
80068bc: d101 bne.n 80068c2 <HAL_ETH_Stop+0x16>
80068be: 2302 movs r3, #2
80068c0: e01f b.n 8006902 <HAL_ETH_Stop+0x56>
80068c2: 687b ldr r3, [r7, #4]
80068c4: 2201 movs r2, #1
80068c6: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
80068ca: 687b ldr r3, [r7, #4]
80068cc: 2202 movs r2, #2
80068ce: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Stop DMA transmission */
ETH_DMATransmissionDisable(heth);
80068d2: 6878 ldr r0, [r7, #4]
80068d4: f000 fba2 bl 800701c <ETH_DMATransmissionDisable>
/* Stop DMA reception */
ETH_DMAReceptionDisable(heth);
80068d8: 6878 ldr r0, [r7, #4]
80068da: f000 fbcf bl 800707c <ETH_DMAReceptionDisable>
/* Disable receive state machine of the MAC for reception from the MII */
ETH_MACReceptionDisable(heth);
80068de: 6878 ldr r0, [r7, #4]
80068e0: f000 fb67 bl 8006fb2 <ETH_MACReceptionDisable>
/* Flush Transmit FIFO */
ETH_FlushTransmitFIFO(heth);
80068e4: 6878 ldr r0, [r7, #4]
80068e6: f000 fbe1 bl 80070ac <ETH_FlushTransmitFIFO>
/* Disable transmit state machine of the MAC for transmission on the MII */
ETH_MACTransmissionDisable(heth);
80068ea: 6878 ldr r0, [r7, #4]
80068ec: f000 fb27 bl 8006f3e <ETH_MACTransmissionDisable>
/* Set the ETH state*/
heth->State = HAL_ETH_STATE_READY;
80068f0: 687b ldr r3, [r7, #4]
80068f2: 2201 movs r2, #1
80068f4: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80068f8: 687b ldr r3, [r7, #4]
80068fa: 2200 movs r2, #0
80068fc: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006900: 2300 movs r3, #0
}
8006902: 4618 mov r0, r3
8006904: 3708 adds r7, #8
8006906: 46bd mov sp, r7
8006908: bd80 pop {r7, pc}
...
0800690c <HAL_ETH_ConfigMAC>:
* the configuration information for ETHERNET module
* @param macconf MAC Configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
{
800690c: b580 push {r7, lr}
800690e: b084 sub sp, #16
8006910: af00 add r7, sp, #0
8006912: 6078 str r0, [r7, #4]
8006914: 6039 str r1, [r7, #0]
uint32_t tmpreg = 0;
8006916: 2300 movs r3, #0
8006918: 60fb str r3, [r7, #12]
/* Process Locked */
__HAL_LOCK(heth);
800691a: 687b ldr r3, [r7, #4]
800691c: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8006920: 2b01 cmp r3, #1
8006922: d101 bne.n 8006928 <HAL_ETH_ConfigMAC+0x1c>
8006924: 2302 movs r3, #2
8006926: e0e4 b.n 8006af2 <HAL_ETH_ConfigMAC+0x1e6>
8006928: 687b ldr r3, [r7, #4]
800692a: 2201 movs r2, #1
800692c: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State= HAL_ETH_STATE_BUSY;
8006930: 687b ldr r3, [r7, #4]
8006932: 2202 movs r2, #2
8006934: f883 2044 strb.w r2, [r3, #68] ; 0x44
assert_param(IS_ETH_SPEED(heth->Init.Speed));
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
if (macconf != NULL)
8006938: 683b ldr r3, [r7, #0]
800693a: 2b00 cmp r3, #0
800693c: f000 80b1 beq.w 8006aa2 <HAL_ETH_ConfigMAC+0x196>
assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg = (heth->Instance)->MACCR;
8006940: 687b ldr r3, [r7, #4]
8006942: 681b ldr r3, [r3, #0]
8006944: 681b ldr r3, [r3, #0]
8006946: 60fb str r3, [r7, #12]
/* Clear WD, PCE, PS, TE and RE bits */
tmpreg &= ETH_MACCR_CLEAR_MASK;
8006948: 68fa ldr r2, [r7, #12]
800694a: 4b6c ldr r3, [pc, #432] ; (8006afc <HAL_ETH_ConfigMAC+0x1f0>)
800694c: 4013 ands r3, r2
800694e: 60fb str r3, [r7, #12]
tmpreg |= (uint32_t)(macconf->Watchdog |
8006950: 683b ldr r3, [r7, #0]
8006952: 681a ldr r2, [r3, #0]
macconf->Jabber |
8006954: 683b ldr r3, [r7, #0]
8006956: 685b ldr r3, [r3, #4]
tmpreg |= (uint32_t)(macconf->Watchdog |
8006958: 431a orrs r2, r3
macconf->InterFrameGap |
800695a: 683b ldr r3, [r7, #0]
800695c: 689b ldr r3, [r3, #8]
macconf->Jabber |
800695e: 431a orrs r2, r3
macconf->CarrierSense |
8006960: 683b ldr r3, [r7, #0]
8006962: 68db ldr r3, [r3, #12]
macconf->InterFrameGap |
8006964: 431a orrs r2, r3
(heth->Init).Speed |
8006966: 687b ldr r3, [r7, #4]
8006968: 689b ldr r3, [r3, #8]
macconf->CarrierSense |
800696a: 431a orrs r2, r3
macconf->ReceiveOwn |
800696c: 683b ldr r3, [r7, #0]
800696e: 691b ldr r3, [r3, #16]
(heth->Init).Speed |
8006970: 431a orrs r2, r3
macconf->LoopbackMode |
8006972: 683b ldr r3, [r7, #0]
8006974: 695b ldr r3, [r3, #20]
macconf->ReceiveOwn |
8006976: 431a orrs r2, r3
(heth->Init).DuplexMode |
8006978: 687b ldr r3, [r7, #4]
800697a: 68db ldr r3, [r3, #12]
macconf->LoopbackMode |
800697c: 431a orrs r2, r3
macconf->ChecksumOffload |
800697e: 683b ldr r3, [r7, #0]
8006980: 699b ldr r3, [r3, #24]
(heth->Init).DuplexMode |
8006982: 431a orrs r2, r3
macconf->RetryTransmission |
8006984: 683b ldr r3, [r7, #0]
8006986: 69db ldr r3, [r3, #28]
macconf->ChecksumOffload |
8006988: 431a orrs r2, r3
macconf->AutomaticPadCRCStrip |
800698a: 683b ldr r3, [r7, #0]
800698c: 6a1b ldr r3, [r3, #32]
macconf->RetryTransmission |
800698e: 431a orrs r2, r3
macconf->BackOffLimit |
8006990: 683b ldr r3, [r7, #0]
8006992: 6a5b ldr r3, [r3, #36] ; 0x24
macconf->AutomaticPadCRCStrip |
8006994: 431a orrs r2, r3
macconf->DeferralCheck);
8006996: 683b ldr r3, [r7, #0]
8006998: 6a9b ldr r3, [r3, #40] ; 0x28
macconf->BackOffLimit |
800699a: 4313 orrs r3, r2
tmpreg |= (uint32_t)(macconf->Watchdog |
800699c: 68fa ldr r2, [r7, #12]
800699e: 4313 orrs r3, r2
80069a0: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg;
80069a2: 687b ldr r3, [r7, #4]
80069a4: 681b ldr r3, [r3, #0]
80069a6: 68fa ldr r2, [r7, #12]
80069a8: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
80069aa: 687b ldr r3, [r7, #4]
80069ac: 681b ldr r3, [r3, #0]
80069ae: 681b ldr r3, [r3, #0]
80069b0: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
80069b2: 2001 movs r0, #1
80069b4: f7fd ff18 bl 80047e8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
80069b8: 687b ldr r3, [r7, #4]
80069ba: 681b ldr r3, [r3, #0]
80069bc: 68fa ldr r2, [r7, #12]
80069be: 601a str r2, [r3, #0]
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Write to ETHERNET MACFFR */
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
80069c0: 683b ldr r3, [r7, #0]
80069c2: 6ada ldr r2, [r3, #44] ; 0x2c
macconf->SourceAddrFilter |
80069c4: 683b ldr r3, [r7, #0]
80069c6: 6b1b ldr r3, [r3, #48] ; 0x30
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
80069c8: 431a orrs r2, r3
macconf->PassControlFrames |
80069ca: 683b ldr r3, [r7, #0]
80069cc: 6b5b ldr r3, [r3, #52] ; 0x34
macconf->SourceAddrFilter |
80069ce: 431a orrs r2, r3
macconf->BroadcastFramesReception |
80069d0: 683b ldr r3, [r7, #0]
80069d2: 6b9b ldr r3, [r3, #56] ; 0x38
macconf->PassControlFrames |
80069d4: 431a orrs r2, r3
macconf->DestinationAddrFilter |
80069d6: 683b ldr r3, [r7, #0]
80069d8: 6bdb ldr r3, [r3, #60] ; 0x3c
macconf->BroadcastFramesReception |
80069da: 431a orrs r2, r3
macconf->PromiscuousMode |
80069dc: 683b ldr r3, [r7, #0]
80069de: 6c1b ldr r3, [r3, #64] ; 0x40
macconf->DestinationAddrFilter |
80069e0: 431a orrs r2, r3
macconf->MulticastFramesFilter |
80069e2: 683b ldr r3, [r7, #0]
80069e4: 6c5b ldr r3, [r3, #68] ; 0x44
macconf->PromiscuousMode |
80069e6: ea42 0103 orr.w r1, r2, r3
macconf->UnicastFramesFilter);
80069ea: 683b ldr r3, [r7, #0]
80069ec: 6c9a ldr r2, [r3, #72] ; 0x48
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
80069ee: 687b ldr r3, [r7, #4]
80069f0: 681b ldr r3, [r3, #0]
macconf->MulticastFramesFilter |
80069f2: 430a orrs r2, r1
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
80069f4: 605a str r2, [r3, #4]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACFFR;
80069f6: 687b ldr r3, [r7, #4]
80069f8: 681b ldr r3, [r3, #0]
80069fa: 685b ldr r3, [r3, #4]
80069fc: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
80069fe: 2001 movs r0, #1
8006a00: f7fd fef2 bl 80047e8 <HAL_Delay>
(heth->Instance)->MACFFR = tmpreg;
8006a04: 687b ldr r3, [r7, #4]
8006a06: 681b ldr r3, [r3, #0]
8006a08: 68fa ldr r2, [r7, #12]
8006a0a: 605a str r2, [r3, #4]
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
/* Write to ETHERNET MACHTHR */
(heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
8006a0c: 687b ldr r3, [r7, #4]
8006a0e: 681b ldr r3, [r3, #0]
8006a10: 683a ldr r2, [r7, #0]
8006a12: 6cd2 ldr r2, [r2, #76] ; 0x4c
8006a14: 609a str r2, [r3, #8]
/* Write to ETHERNET MACHTLR */
(heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
8006a16: 687b ldr r3, [r7, #4]
8006a18: 681b ldr r3, [r3, #0]
8006a1a: 683a ldr r2, [r7, #0]
8006a1c: 6d12 ldr r2, [r2, #80] ; 0x50
8006a1e: 60da str r2, [r3, #12]
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
/* Get the ETHERNET MACFCR value */
tmpreg = (heth->Instance)->MACFCR;
8006a20: 687b ldr r3, [r7, #4]
8006a22: 681b ldr r3, [r3, #0]
8006a24: 699b ldr r3, [r3, #24]
8006a26: 60fb str r3, [r7, #12]
/* Clear xx bits */
tmpreg &= ETH_MACFCR_CLEAR_MASK;
8006a28: 68fa ldr r2, [r7, #12]
8006a2a: f64f 7341 movw r3, #65345 ; 0xff41
8006a2e: 4013 ands r3, r2
8006a30: 60fb str r3, [r7, #12]
tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
8006a32: 683b ldr r3, [r7, #0]
8006a34: 6d5b ldr r3, [r3, #84] ; 0x54
8006a36: 041a lsls r2, r3, #16
macconf->ZeroQuantaPause |
8006a38: 683b ldr r3, [r7, #0]
8006a3a: 6d9b ldr r3, [r3, #88] ; 0x58
tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
8006a3c: 431a orrs r2, r3
macconf->PauseLowThreshold |
8006a3e: 683b ldr r3, [r7, #0]
8006a40: 6ddb ldr r3, [r3, #92] ; 0x5c
macconf->ZeroQuantaPause |
8006a42: 431a orrs r2, r3
macconf->UnicastPauseFrameDetect |
8006a44: 683b ldr r3, [r7, #0]
8006a46: 6e1b ldr r3, [r3, #96] ; 0x60
macconf->PauseLowThreshold |
8006a48: 431a orrs r2, r3
macconf->ReceiveFlowControl |
8006a4a: 683b ldr r3, [r7, #0]
8006a4c: 6e5b ldr r3, [r3, #100] ; 0x64
macconf->UnicastPauseFrameDetect |
8006a4e: 431a orrs r2, r3
macconf->TransmitFlowControl);
8006a50: 683b ldr r3, [r7, #0]
8006a52: 6e9b ldr r3, [r3, #104] ; 0x68
macconf->ReceiveFlowControl |
8006a54: 4313 orrs r3, r2
tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
8006a56: 68fa ldr r2, [r7, #12]
8006a58: 4313 orrs r3, r2
8006a5a: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACFCR */
(heth->Instance)->MACFCR = (uint32_t)tmpreg;
8006a5c: 687b ldr r3, [r7, #4]
8006a5e: 681b ldr r3, [r3, #0]
8006a60: 68fa ldr r2, [r7, #12]
8006a62: 619a str r2, [r3, #24]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACFCR;
8006a64: 687b ldr r3, [r7, #4]
8006a66: 681b ldr r3, [r3, #0]
8006a68: 699b ldr r3, [r3, #24]
8006a6a: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006a6c: 2001 movs r0, #1
8006a6e: f7fd febb bl 80047e8 <HAL_Delay>
(heth->Instance)->MACFCR = tmpreg;
8006a72: 687b ldr r3, [r7, #4]
8006a74: 681b ldr r3, [r3, #0]
8006a76: 68fa ldr r2, [r7, #12]
8006a78: 619a str r2, [r3, #24]
/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
8006a7a: 683b ldr r3, [r7, #0]
8006a7c: 6ed9 ldr r1, [r3, #108] ; 0x6c
macconf->VLANTagIdentifier);
8006a7e: 683b ldr r3, [r7, #0]
8006a80: 6f1a ldr r2, [r3, #112] ; 0x70
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
8006a82: 687b ldr r3, [r7, #4]
8006a84: 681b ldr r3, [r3, #0]
8006a86: 430a orrs r2, r1
8006a88: 61da str r2, [r3, #28]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACVLANTR;
8006a8a: 687b ldr r3, [r7, #4]
8006a8c: 681b ldr r3, [r3, #0]
8006a8e: 69db ldr r3, [r3, #28]
8006a90: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006a92: 2001 movs r0, #1
8006a94: f7fd fea8 bl 80047e8 <HAL_Delay>
(heth->Instance)->MACVLANTR = tmpreg;
8006a98: 687b ldr r3, [r7, #4]
8006a9a: 681b ldr r3, [r3, #0]
8006a9c: 68fa ldr r2, [r7, #12]
8006a9e: 61da str r2, [r3, #28]
8006aa0: e01e b.n 8006ae0 <HAL_ETH_ConfigMAC+0x1d4>
}
else /* macconf == NULL : here we just configure Speed and Duplex mode */
{
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg = (heth->Instance)->MACCR;
8006aa2: 687b ldr r3, [r7, #4]
8006aa4: 681b ldr r3, [r3, #0]
8006aa6: 681b ldr r3, [r3, #0]
8006aa8: 60fb str r3, [r7, #12]
/* Clear FES and DM bits */
tmpreg &= ~((uint32_t)0x00004800);
8006aaa: 68fb ldr r3, [r7, #12]
8006aac: f423 4390 bic.w r3, r3, #18432 ; 0x4800
8006ab0: 60fb str r3, [r7, #12]
tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
8006ab2: 687b ldr r3, [r7, #4]
8006ab4: 689a ldr r2, [r3, #8]
8006ab6: 687b ldr r3, [r7, #4]
8006ab8: 68db ldr r3, [r3, #12]
8006aba: 4313 orrs r3, r2
8006abc: 68fa ldr r2, [r7, #12]
8006abe: 4313 orrs r3, r2
8006ac0: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg;
8006ac2: 687b ldr r3, [r7, #4]
8006ac4: 681b ldr r3, [r3, #0]
8006ac6: 68fa ldr r2, [r7, #12]
8006ac8: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8006aca: 687b ldr r3, [r7, #4]
8006acc: 681b ldr r3, [r3, #0]
8006ace: 681b ldr r3, [r3, #0]
8006ad0: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006ad2: 2001 movs r0, #1
8006ad4: f7fd fe88 bl 80047e8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8006ad8: 687b ldr r3, [r7, #4]
8006ada: 681b ldr r3, [r3, #0]
8006adc: 68fa ldr r2, [r7, #12]
8006ade: 601a str r2, [r3, #0]
}
/* Set the ETH state to Ready */
heth->State= HAL_ETH_STATE_READY;
8006ae0: 687b ldr r3, [r7, #4]
8006ae2: 2201 movs r2, #1
8006ae4: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006ae8: 687b ldr r3, [r7, #4]
8006aea: 2200 movs r2, #0
8006aec: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006af0: 2300 movs r3, #0
}
8006af2: 4618 mov r0, r3
8006af4: 3710 adds r7, #16
8006af6: 46bd mov sp, r7
8006af8: bd80 pop {r7, pc}
8006afa: bf00 nop
8006afc: ff20810f .word 0xff20810f
08006b00 <ETH_MACDMAConfig>:
* the configuration information for ETHERNET module
* @param err Ethernet Init error
* @retval HAL status
*/
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
{
8006b00: b580 push {r7, lr}
8006b02: b0b0 sub sp, #192 ; 0xc0
8006b04: af00 add r7, sp, #0
8006b06: 6078 str r0, [r7, #4]
8006b08: 6039 str r1, [r7, #0]
ETH_MACInitTypeDef macinit;
ETH_DMAInitTypeDef dmainit;
uint32_t tmpreg = 0;
8006b0a: 2300 movs r3, #0
8006b0c: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
if (err != ETH_SUCCESS) /* Auto-negotiation failed */
8006b10: 683b ldr r3, [r7, #0]
8006b12: 2b00 cmp r3, #0
8006b14: d007 beq.n 8006b26 <ETH_MACDMAConfig+0x26>
{
/* Set Ethernet duplex mode to Full-duplex */
(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
8006b16: 687b ldr r3, [r7, #4]
8006b18: f44f 6200 mov.w r2, #2048 ; 0x800
8006b1c: 60da str r2, [r3, #12]
/* Set Ethernet speed to 100M */
(heth->Init).Speed = ETH_SPEED_100M;
8006b1e: 687b ldr r3, [r7, #4]
8006b20: f44f 4280 mov.w r2, #16384 ; 0x4000
8006b24: 609a str r2, [r3, #8]
}
/* Ethernet MAC default initialization **************************************/
macinit.Watchdog = ETH_WATCHDOG_ENABLE;
8006b26: 2300 movs r3, #0
8006b28: 64bb str r3, [r7, #72] ; 0x48
macinit.Jabber = ETH_JABBER_ENABLE;
8006b2a: 2300 movs r3, #0
8006b2c: 64fb str r3, [r7, #76] ; 0x4c
macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
8006b2e: 2300 movs r3, #0
8006b30: 653b str r3, [r7, #80] ; 0x50
macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
8006b32: 2300 movs r3, #0
8006b34: 657b str r3, [r7, #84] ; 0x54
macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
8006b36: 2300 movs r3, #0
8006b38: 65bb str r3, [r7, #88] ; 0x58
macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
8006b3a: 2300 movs r3, #0
8006b3c: 65fb str r3, [r7, #92] ; 0x5c
if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
8006b3e: 687b ldr r3, [r7, #4]
8006b40: 69db ldr r3, [r3, #28]
8006b42: 2b00 cmp r3, #0
8006b44: d103 bne.n 8006b4e <ETH_MACDMAConfig+0x4e>
{
macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
8006b46: f44f 6380 mov.w r3, #1024 ; 0x400
8006b4a: 663b str r3, [r7, #96] ; 0x60
8006b4c: e001 b.n 8006b52 <ETH_MACDMAConfig+0x52>
}
else
{
macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
8006b4e: 2300 movs r3, #0
8006b50: 663b str r3, [r7, #96] ; 0x60
}
macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
8006b52: f44f 7300 mov.w r3, #512 ; 0x200
8006b56: 667b str r3, [r7, #100] ; 0x64
macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
8006b58: 2300 movs r3, #0
8006b5a: 66bb str r3, [r7, #104] ; 0x68
macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
8006b5c: 2300 movs r3, #0
8006b5e: 66fb str r3, [r7, #108] ; 0x6c
macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
8006b60: 2300 movs r3, #0
8006b62: 673b str r3, [r7, #112] ; 0x70
macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
8006b64: 2300 movs r3, #0
8006b66: 677b str r3, [r7, #116] ; 0x74
macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
8006b68: 2300 movs r3, #0
8006b6a: 67bb str r3, [r7, #120] ; 0x78
macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
8006b6c: 2340 movs r3, #64 ; 0x40
8006b6e: 67fb str r3, [r7, #124] ; 0x7c
macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
8006b70: 2300 movs r3, #0
8006b72: f8c7 3080 str.w r3, [r7, #128] ; 0x80
macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
8006b76: 2300 movs r3, #0
8006b78: f8c7 3084 str.w r3, [r7, #132] ; 0x84
macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
8006b7c: 2300 movs r3, #0
8006b7e: f8c7 3088 str.w r3, [r7, #136] ; 0x88
macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
8006b82: 2300 movs r3, #0
8006b84: f8c7 308c str.w r3, [r7, #140] ; 0x8c
macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
8006b88: 2300 movs r3, #0
8006b8a: f8c7 3090 str.w r3, [r7, #144] ; 0x90
macinit.HashTableHigh = 0x0;
8006b8e: 2300 movs r3, #0
8006b90: f8c7 3094 str.w r3, [r7, #148] ; 0x94
macinit.HashTableLow = 0x0;
8006b94: 2300 movs r3, #0
8006b96: f8c7 3098 str.w r3, [r7, #152] ; 0x98
macinit.PauseTime = 0x0;
8006b9a: 2300 movs r3, #0
8006b9c: f8c7 309c str.w r3, [r7, #156] ; 0x9c
macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
8006ba0: 2380 movs r3, #128 ; 0x80
8006ba2: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
8006ba6: 2300 movs r3, #0
8006ba8: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
8006bac: 2300 movs r3, #0
8006bae: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
8006bb2: 2300 movs r3, #0
8006bb4: f8c7 30ac str.w r3, [r7, #172] ; 0xac
macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
8006bb8: 2300 movs r3, #0
8006bba: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
8006bbe: 2300 movs r3, #0
8006bc0: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
macinit.VLANTagIdentifier = 0x0;
8006bc4: 2300 movs r3, #0
8006bc6: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg = (heth->Instance)->MACCR;
8006bca: 687b ldr r3, [r7, #4]
8006bcc: 681b ldr r3, [r3, #0]
8006bce: 681b ldr r3, [r3, #0]
8006bd0: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Clear WD, PCE, PS, TE and RE bits */
tmpreg &= ETH_MACCR_CLEAR_MASK;
8006bd4: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006bd8: 4bab ldr r3, [pc, #684] ; (8006e88 <ETH_MACDMAConfig+0x388>)
8006bda: 4013 ands r3, r2
8006bdc: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Set the IPCO bit according to ETH ChecksumOffload value */
/* Set the DR bit according to ETH RetryTransmission value */
/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
/* Set the BL bit according to ETH BackOffLimit value */
/* Set the DC bit according to ETH DeferralCheck value */
tmpreg |= (uint32_t)(macinit.Watchdog |
8006be0: 6cba ldr r2, [r7, #72] ; 0x48
macinit.Jabber |
8006be2: 6cfb ldr r3, [r7, #76] ; 0x4c
tmpreg |= (uint32_t)(macinit.Watchdog |
8006be4: 431a orrs r2, r3
macinit.InterFrameGap |
8006be6: 6d3b ldr r3, [r7, #80] ; 0x50
macinit.Jabber |
8006be8: 431a orrs r2, r3
macinit.CarrierSense |
8006bea: 6d7b ldr r3, [r7, #84] ; 0x54
macinit.InterFrameGap |
8006bec: 431a orrs r2, r3
(heth->Init).Speed |
8006bee: 687b ldr r3, [r7, #4]
8006bf0: 689b ldr r3, [r3, #8]
macinit.CarrierSense |
8006bf2: 431a orrs r2, r3
macinit.ReceiveOwn |
8006bf4: 6dbb ldr r3, [r7, #88] ; 0x58
(heth->Init).Speed |
8006bf6: 431a orrs r2, r3
macinit.LoopbackMode |
8006bf8: 6dfb ldr r3, [r7, #92] ; 0x5c
macinit.ReceiveOwn |
8006bfa: 431a orrs r2, r3
(heth->Init).DuplexMode |
8006bfc: 687b ldr r3, [r7, #4]
8006bfe: 68db ldr r3, [r3, #12]
macinit.LoopbackMode |
8006c00: 431a orrs r2, r3
macinit.ChecksumOffload |
8006c02: 6e3b ldr r3, [r7, #96] ; 0x60
(heth->Init).DuplexMode |
8006c04: 431a orrs r2, r3
macinit.RetryTransmission |
8006c06: 6e7b ldr r3, [r7, #100] ; 0x64
macinit.ChecksumOffload |
8006c08: 431a orrs r2, r3
macinit.AutomaticPadCRCStrip |
8006c0a: 6ebb ldr r3, [r7, #104] ; 0x68
macinit.RetryTransmission |
8006c0c: 431a orrs r2, r3
macinit.BackOffLimit |
8006c0e: 6efb ldr r3, [r7, #108] ; 0x6c
macinit.AutomaticPadCRCStrip |
8006c10: 431a orrs r2, r3
macinit.DeferralCheck);
8006c12: 6f3b ldr r3, [r7, #112] ; 0x70
macinit.BackOffLimit |
8006c14: 4313 orrs r3, r2
tmpreg |= (uint32_t)(macinit.Watchdog |
8006c16: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006c1a: 4313 orrs r3, r2
8006c1c: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg;
8006c20: 687b ldr r3, [r7, #4]
8006c22: 681b ldr r3, [r3, #0]
8006c24: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006c28: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8006c2a: 687b ldr r3, [r7, #4]
8006c2c: 681b ldr r3, [r3, #0]
8006c2e: 681b ldr r3, [r3, #0]
8006c30: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006c34: 2001 movs r0, #1
8006c36: f7fd fdd7 bl 80047e8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8006c3a: 687b ldr r3, [r7, #4]
8006c3c: 681b ldr r3, [r3, #0]
8006c3e: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006c42: 601a str r2, [r3, #0]
/* Set the DAIF bit according to ETH DestinationAddrFilter value */
/* Set the PR bit according to ETH PromiscuousMode value */
/* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
/* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
/* Write to ETHERNET MACFFR */
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
8006c44: 6f7a ldr r2, [r7, #116] ; 0x74
macinit.SourceAddrFilter |
8006c46: 6fbb ldr r3, [r7, #120] ; 0x78
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
8006c48: 431a orrs r2, r3
macinit.PassControlFrames |
8006c4a: 6ffb ldr r3, [r7, #124] ; 0x7c
macinit.SourceAddrFilter |
8006c4c: 431a orrs r2, r3
macinit.BroadcastFramesReception |
8006c4e: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80
macinit.PassControlFrames |
8006c52: 431a orrs r2, r3
macinit.DestinationAddrFilter |
8006c54: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
macinit.BroadcastFramesReception |
8006c58: 431a orrs r2, r3
macinit.PromiscuousMode |
8006c5a: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88
macinit.DestinationAddrFilter |
8006c5e: 431a orrs r2, r3
macinit.MulticastFramesFilter |
8006c60: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
macinit.PromiscuousMode |
8006c64: ea42 0103 orr.w r1, r2, r3
macinit.UnicastFramesFilter);
8006c68: f8d7 2090 ldr.w r2, [r7, #144] ; 0x90
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
8006c6c: 687b ldr r3, [r7, #4]
8006c6e: 681b ldr r3, [r3, #0]
macinit.MulticastFramesFilter |
8006c70: 430a orrs r2, r1
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
8006c72: 605a str r2, [r3, #4]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACFFR;
8006c74: 687b ldr r3, [r7, #4]
8006c76: 681b ldr r3, [r3, #0]
8006c78: 685b ldr r3, [r3, #4]
8006c7a: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006c7e: 2001 movs r0, #1
8006c80: f7fd fdb2 bl 80047e8 <HAL_Delay>
(heth->Instance)->MACFFR = tmpreg;
8006c84: 687b ldr r3, [r7, #4]
8006c86: 681b ldr r3, [r3, #0]
8006c88: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006c8c: 605a str r2, [r3, #4]
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
/* Write to ETHERNET MACHTHR */
(heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
8006c8e: 687b ldr r3, [r7, #4]
8006c90: 681b ldr r3, [r3, #0]
8006c92: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94
8006c96: 609a str r2, [r3, #8]
/* Write to ETHERNET MACHTLR */
(heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
8006c98: 687b ldr r3, [r7, #4]
8006c9a: 681b ldr r3, [r3, #0]
8006c9c: f8d7 2098 ldr.w r2, [r7, #152] ; 0x98
8006ca0: 60da str r2, [r3, #12]
/*----------------------- ETHERNET MACFCR Configuration -------------------*/
/* Get the ETHERNET MACFCR value */
tmpreg = (heth->Instance)->MACFCR;
8006ca2: 687b ldr r3, [r7, #4]
8006ca4: 681b ldr r3, [r3, #0]
8006ca6: 699b ldr r3, [r3, #24]
8006ca8: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Clear xx bits */
tmpreg &= ETH_MACFCR_CLEAR_MASK;
8006cac: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006cb0: f64f 7341 movw r3, #65345 ; 0xff41
8006cb4: 4013 ands r3, r2
8006cb6: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
/* Set the PLT bit according to ETH PauseLowThreshold value */
/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
/* Set the RFE bit according to ETH ReceiveFlowControl value */
/* Set the TFE bit according to ETH TransmitFlowControl value */
tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
8006cba: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c
8006cbe: 041a lsls r2, r3, #16
macinit.ZeroQuantaPause |
8006cc0: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0
tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
8006cc4: 431a orrs r2, r3
macinit.PauseLowThreshold |
8006cc6: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
macinit.ZeroQuantaPause |
8006cca: 431a orrs r2, r3
macinit.UnicastPauseFrameDetect |
8006ccc: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8
macinit.PauseLowThreshold |
8006cd0: 431a orrs r2, r3
macinit.ReceiveFlowControl |
8006cd2: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac
macinit.UnicastPauseFrameDetect |
8006cd6: 431a orrs r2, r3
macinit.TransmitFlowControl);
8006cd8: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0
macinit.ReceiveFlowControl |
8006cdc: 4313 orrs r3, r2
tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
8006cde: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006ce2: 4313 orrs r3, r2
8006ce4: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Write to ETHERNET MACFCR */
(heth->Instance)->MACFCR = (uint32_t)tmpreg;
8006ce8: 687b ldr r3, [r7, #4]
8006cea: 681b ldr r3, [r3, #0]
8006cec: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006cf0: 619a str r2, [r3, #24]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACFCR;
8006cf2: 687b ldr r3, [r7, #4]
8006cf4: 681b ldr r3, [r3, #0]
8006cf6: 699b ldr r3, [r3, #24]
8006cf8: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006cfc: 2001 movs r0, #1
8006cfe: f7fd fd73 bl 80047e8 <HAL_Delay>
(heth->Instance)->MACFCR = tmpreg;
8006d02: 687b ldr r3, [r7, #4]
8006d04: 681b ldr r3, [r3, #0]
8006d06: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006d0a: 619a str r2, [r3, #24]
/*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
/* Set the ETV bit according to ETH VLANTagComparison value */
/* Set the VL bit according to ETH VLANTagIdentifier value */
(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
8006d0c: f8d7 10b4 ldr.w r1, [r7, #180] ; 0xb4
macinit.VLANTagIdentifier);
8006d10: f8d7 20b8 ldr.w r2, [r7, #184] ; 0xb8
(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
8006d14: 687b ldr r3, [r7, #4]
8006d16: 681b ldr r3, [r3, #0]
8006d18: 430a orrs r2, r1
8006d1a: 61da str r2, [r3, #28]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACVLANTR;
8006d1c: 687b ldr r3, [r7, #4]
8006d1e: 681b ldr r3, [r3, #0]
8006d20: 69db ldr r3, [r3, #28]
8006d22: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006d26: 2001 movs r0, #1
8006d28: f7fd fd5e bl 80047e8 <HAL_Delay>
(heth->Instance)->MACVLANTR = tmpreg;
8006d2c: 687b ldr r3, [r7, #4]
8006d2e: 681b ldr r3, [r3, #0]
8006d30: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006d34: 61da str r2, [r3, #28]
/* Ethernet DMA default initialization ************************************/
dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
8006d36: 2300 movs r3, #0
8006d38: 60bb str r3, [r7, #8]
dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
8006d3a: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8006d3e: 60fb str r3, [r7, #12]
dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
8006d40: 2300 movs r3, #0
8006d42: 613b str r3, [r7, #16]
dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
8006d44: f44f 1300 mov.w r3, #2097152 ; 0x200000
8006d48: 617b str r3, [r7, #20]
dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
8006d4a: 2300 movs r3, #0
8006d4c: 61bb str r3, [r7, #24]
dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
8006d4e: 2300 movs r3, #0
8006d50: 61fb str r3, [r7, #28]
dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
8006d52: 2300 movs r3, #0
8006d54: 623b str r3, [r7, #32]
dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
8006d56: 2300 movs r3, #0
8006d58: 627b str r3, [r7, #36] ; 0x24
dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
8006d5a: 2304 movs r3, #4
8006d5c: 62bb str r3, [r7, #40] ; 0x28
dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
8006d5e: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8006d62: 62fb str r3, [r7, #44] ; 0x2c
dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
8006d64: f44f 3380 mov.w r3, #65536 ; 0x10000
8006d68: 633b str r3, [r7, #48] ; 0x30
dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
8006d6a: f44f 0380 mov.w r3, #4194304 ; 0x400000
8006d6e: 637b str r3, [r7, #52] ; 0x34
dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
8006d70: f44f 5300 mov.w r3, #8192 ; 0x2000
8006d74: 63bb str r3, [r7, #56] ; 0x38
dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
8006d76: 2380 movs r3, #128 ; 0x80
8006d78: 63fb str r3, [r7, #60] ; 0x3c
dmainit.DescriptorSkipLength = 0x0;
8006d7a: 2300 movs r3, #0
8006d7c: 643b str r3, [r7, #64] ; 0x40
dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
8006d7e: 2300 movs r3, #0
8006d80: 647b str r3, [r7, #68] ; 0x44
/* Get the ETHERNET DMAOMR value */
tmpreg = (heth->Instance)->DMAOMR;
8006d82: 687b ldr r3, [r7, #4]
8006d84: 681a ldr r2, [r3, #0]
8006d86: f241 0318 movw r3, #4120 ; 0x1018
8006d8a: 4413 add r3, r2
8006d8c: 681b ldr r3, [r3, #0]
8006d8e: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Clear xx bits */
tmpreg &= ETH_DMAOMR_CLEAR_MASK;
8006d92: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006d96: 4b3d ldr r3, [pc, #244] ; (8006e8c <ETH_MACDMAConfig+0x38c>)
8006d98: 4013 ands r3, r2
8006d9a: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Set the TTC bit according to ETH TransmitThresholdControl value */
/* Set the FEF bit according to ETH ForwardErrorFrames value */
/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
/* Set the RTC bit according to ETH ReceiveThresholdControl value */
/* Set the OSF bit according to ETH SecondFrameOperate value */
tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
8006d9e: 68ba ldr r2, [r7, #8]
dmainit.ReceiveStoreForward |
8006da0: 68fb ldr r3, [r7, #12]
tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
8006da2: 431a orrs r2, r3
dmainit.FlushReceivedFrame |
8006da4: 693b ldr r3, [r7, #16]
dmainit.ReceiveStoreForward |
8006da6: 431a orrs r2, r3
dmainit.TransmitStoreForward |
8006da8: 697b ldr r3, [r7, #20]
dmainit.FlushReceivedFrame |
8006daa: 431a orrs r2, r3
dmainit.TransmitThresholdControl |
8006dac: 69bb ldr r3, [r7, #24]
dmainit.TransmitStoreForward |
8006dae: 431a orrs r2, r3
dmainit.ForwardErrorFrames |
8006db0: 69fb ldr r3, [r7, #28]
dmainit.TransmitThresholdControl |
8006db2: 431a orrs r2, r3
dmainit.ForwardUndersizedGoodFrames |
8006db4: 6a3b ldr r3, [r7, #32]
dmainit.ForwardErrorFrames |
8006db6: 431a orrs r2, r3
dmainit.ReceiveThresholdControl |
8006db8: 6a7b ldr r3, [r7, #36] ; 0x24
dmainit.ForwardUndersizedGoodFrames |
8006dba: 431a orrs r2, r3
dmainit.SecondFrameOperate);
8006dbc: 6abb ldr r3, [r7, #40] ; 0x28
dmainit.ReceiveThresholdControl |
8006dbe: 4313 orrs r3, r2
tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
8006dc0: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006dc4: 4313 orrs r3, r2
8006dc6: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Write to ETHERNET DMAOMR */
(heth->Instance)->DMAOMR = (uint32_t)tmpreg;
8006dca: 687b ldr r3, [r7, #4]
8006dcc: 681a ldr r2, [r3, #0]
8006dce: f241 0318 movw r3, #4120 ; 0x1018
8006dd2: 4413 add r3, r2
8006dd4: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006dd8: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->DMAOMR;
8006dda: 687b ldr r3, [r7, #4]
8006ddc: 681a ldr r2, [r3, #0]
8006dde: f241 0318 movw r3, #4120 ; 0x1018
8006de2: 4413 add r3, r2
8006de4: 681b ldr r3, [r3, #0]
8006de6: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006dea: 2001 movs r0, #1
8006dec: f7fd fcfc bl 80047e8 <HAL_Delay>
(heth->Instance)->DMAOMR = tmpreg;
8006df0: 687b ldr r3, [r7, #4]
8006df2: 681a ldr r2, [r3, #0]
8006df4: f241 0318 movw r3, #4120 ; 0x1018
8006df8: 4413 add r3, r2
8006dfa: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006dfe: 601a str r2, [r3, #0]
/* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
/* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
/* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
/* Set the DSL bit according to ETH DesciptorSkipLength value */
/* Set the PR and DA bits according to ETH DMAArbitration value */
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
8006e00: 6afa ldr r2, [r7, #44] ; 0x2c
dmainit.FixedBurst |
8006e02: 6b3b ldr r3, [r7, #48] ; 0x30
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
8006e04: 431a orrs r2, r3
dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
8006e06: 6b7b ldr r3, [r7, #52] ; 0x34
dmainit.FixedBurst |
8006e08: 431a orrs r2, r3
dmainit.TxDMABurstLength |
8006e0a: 6bbb ldr r3, [r7, #56] ; 0x38
dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
8006e0c: 431a orrs r2, r3
dmainit.EnhancedDescriptorFormat |
8006e0e: 6bfb ldr r3, [r7, #60] ; 0x3c
dmainit.TxDMABurstLength |
8006e10: 431a orrs r2, r3
(dmainit.DescriptorSkipLength << 2) |
8006e12: 6c3b ldr r3, [r7, #64] ; 0x40
8006e14: 009b lsls r3, r3, #2
dmainit.EnhancedDescriptorFormat |
8006e16: 431a orrs r2, r3
dmainit.DMAArbitration |
8006e18: 6c7b ldr r3, [r7, #68] ; 0x44
(dmainit.DescriptorSkipLength << 2) |
8006e1a: 431a orrs r2, r3
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
8006e1c: 687b ldr r3, [r7, #4]
8006e1e: 681b ldr r3, [r3, #0]
8006e20: f442 0200 orr.w r2, r2, #8388608 ; 0x800000
8006e24: f503 5380 add.w r3, r3, #4096 ; 0x1000
8006e28: 601a str r2, [r3, #0]
ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->DMABMR;
8006e2a: 687b ldr r3, [r7, #4]
8006e2c: 681b ldr r3, [r3, #0]
8006e2e: f503 5380 add.w r3, r3, #4096 ; 0x1000
8006e32: 681b ldr r3, [r3, #0]
8006e34: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006e38: 2001 movs r0, #1
8006e3a: f7fd fcd5 bl 80047e8 <HAL_Delay>
(heth->Instance)->DMABMR = tmpreg;
8006e3e: 687b ldr r3, [r7, #4]
8006e40: 681b ldr r3, [r3, #0]
8006e42: f503 5380 add.w r3, r3, #4096 ; 0x1000
8006e46: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006e4a: 601a str r2, [r3, #0]
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
8006e4c: 687b ldr r3, [r7, #4]
8006e4e: 699b ldr r3, [r3, #24]
8006e50: 2b01 cmp r3, #1
8006e52: d10d bne.n 8006e70 <ETH_MACDMAConfig+0x370>
{
/* Enable the Ethernet Rx Interrupt */
__HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
8006e54: 687b ldr r3, [r7, #4]
8006e56: 681a ldr r2, [r3, #0]
8006e58: f241 031c movw r3, #4124 ; 0x101c
8006e5c: 4413 add r3, r2
8006e5e: 681b ldr r3, [r3, #0]
8006e60: 687a ldr r2, [r7, #4]
8006e62: 6811 ldr r1, [r2, #0]
8006e64: 4a0a ldr r2, [pc, #40] ; (8006e90 <ETH_MACDMAConfig+0x390>)
8006e66: 431a orrs r2, r3
8006e68: f241 031c movw r3, #4124 ; 0x101c
8006e6c: 440b add r3, r1
8006e6e: 601a str r2, [r3, #0]
}
/* Initialize MAC address in ethernet MAC */
ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
8006e70: 687b ldr r3, [r7, #4]
8006e72: 695b ldr r3, [r3, #20]
8006e74: 461a mov r2, r3
8006e76: 2100 movs r1, #0
8006e78: 6878 ldr r0, [r7, #4]
8006e7a: f000 f80b bl 8006e94 <ETH_MACAddressConfig>
}
8006e7e: bf00 nop
8006e80: 37c0 adds r7, #192 ; 0xc0
8006e82: 46bd mov sp, r7
8006e84: bd80 pop {r7, pc}
8006e86: bf00 nop
8006e88: ff20810f .word 0xff20810f
8006e8c: f8de3f23 .word 0xf8de3f23
8006e90: 00010040 .word 0x00010040
08006e94 <ETH_MACAddressConfig>:
* @arg ETH_MAC_Address3: MAC Address3
* @param Addr Pointer to MAC address buffer data (6 bytes)
* @retval HAL status
*/
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
{
8006e94: b480 push {r7}
8006e96: b087 sub sp, #28
8006e98: af00 add r7, sp, #0
8006e9a: 60f8 str r0, [r7, #12]
8006e9c: 60b9 str r1, [r7, #8]
8006e9e: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
/* Calculate the selected MAC address high register */
tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
8006ea0: 687b ldr r3, [r7, #4]
8006ea2: 3305 adds r3, #5
8006ea4: 781b ldrb r3, [r3, #0]
8006ea6: 021b lsls r3, r3, #8
8006ea8: 687a ldr r2, [r7, #4]
8006eaa: 3204 adds r2, #4
8006eac: 7812 ldrb r2, [r2, #0]
8006eae: 4313 orrs r3, r2
8006eb0: 617b str r3, [r7, #20]
/* Load the selected MAC address high register */
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
8006eb2: 68ba ldr r2, [r7, #8]
8006eb4: 4b11 ldr r3, [pc, #68] ; (8006efc <ETH_MACAddressConfig+0x68>)
8006eb6: 4413 add r3, r2
8006eb8: 461a mov r2, r3
8006eba: 697b ldr r3, [r7, #20]
8006ebc: 6013 str r3, [r2, #0]
/* Calculate the selected MAC address low register */
tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
8006ebe: 687b ldr r3, [r7, #4]
8006ec0: 3303 adds r3, #3
8006ec2: 781b ldrb r3, [r3, #0]
8006ec4: 061a lsls r2, r3, #24
8006ec6: 687b ldr r3, [r7, #4]
8006ec8: 3302 adds r3, #2
8006eca: 781b ldrb r3, [r3, #0]
8006ecc: 041b lsls r3, r3, #16
8006ece: 431a orrs r2, r3
8006ed0: 687b ldr r3, [r7, #4]
8006ed2: 3301 adds r3, #1
8006ed4: 781b ldrb r3, [r3, #0]
8006ed6: 021b lsls r3, r3, #8
8006ed8: 4313 orrs r3, r2
8006eda: 687a ldr r2, [r7, #4]
8006edc: 7812 ldrb r2, [r2, #0]
8006ede: 4313 orrs r3, r2
8006ee0: 617b str r3, [r7, #20]
/* Load the selected MAC address low register */
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
8006ee2: 68ba ldr r2, [r7, #8]
8006ee4: 4b06 ldr r3, [pc, #24] ; (8006f00 <ETH_MACAddressConfig+0x6c>)
8006ee6: 4413 add r3, r2
8006ee8: 461a mov r2, r3
8006eea: 697b ldr r3, [r7, #20]
8006eec: 6013 str r3, [r2, #0]
}
8006eee: bf00 nop
8006ef0: 371c adds r7, #28
8006ef2: 46bd mov sp, r7
8006ef4: f85d 7b04 ldr.w r7, [sp], #4
8006ef8: 4770 bx lr
8006efa: bf00 nop
8006efc: 40028040 .word 0x40028040
8006f00: 40028044 .word 0x40028044
08006f04 <ETH_MACTransmissionEnable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
{
8006f04: b580 push {r7, lr}
8006f06: b084 sub sp, #16
8006f08: af00 add r7, sp, #0
8006f0a: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
8006f0c: 2300 movs r3, #0
8006f0e: 60fb str r3, [r7, #12]
/* Enable the MAC transmission */
(heth->Instance)->MACCR |= ETH_MACCR_TE;
8006f10: 687b ldr r3, [r7, #4]
8006f12: 681b ldr r3, [r3, #0]
8006f14: 681a ldr r2, [r3, #0]
8006f16: 687b ldr r3, [r7, #4]
8006f18: 681b ldr r3, [r3, #0]
8006f1a: f042 0208 orr.w r2, r2, #8
8006f1e: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8006f20: 687b ldr r3, [r7, #4]
8006f22: 681b ldr r3, [r3, #0]
8006f24: 681b ldr r3, [r3, #0]
8006f26: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006f28: 2001 movs r0, #1
8006f2a: f7fd fc5d bl 80047e8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8006f2e: 687b ldr r3, [r7, #4]
8006f30: 681b ldr r3, [r3, #0]
8006f32: 68fa ldr r2, [r7, #12]
8006f34: 601a str r2, [r3, #0]
}
8006f36: bf00 nop
8006f38: 3710 adds r7, #16
8006f3a: 46bd mov sp, r7
8006f3c: bd80 pop {r7, pc}
08006f3e <ETH_MACTransmissionDisable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
{
8006f3e: b580 push {r7, lr}
8006f40: b084 sub sp, #16
8006f42: af00 add r7, sp, #0
8006f44: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
8006f46: 2300 movs r3, #0
8006f48: 60fb str r3, [r7, #12]
/* Disable the MAC transmission */
(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
8006f4a: 687b ldr r3, [r7, #4]
8006f4c: 681b ldr r3, [r3, #0]
8006f4e: 681a ldr r2, [r3, #0]
8006f50: 687b ldr r3, [r7, #4]
8006f52: 681b ldr r3, [r3, #0]
8006f54: f022 0208 bic.w r2, r2, #8
8006f58: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8006f5a: 687b ldr r3, [r7, #4]
8006f5c: 681b ldr r3, [r3, #0]
8006f5e: 681b ldr r3, [r3, #0]
8006f60: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006f62: 2001 movs r0, #1
8006f64: f7fd fc40 bl 80047e8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8006f68: 687b ldr r3, [r7, #4]
8006f6a: 681b ldr r3, [r3, #0]
8006f6c: 68fa ldr r2, [r7, #12]
8006f6e: 601a str r2, [r3, #0]
}
8006f70: bf00 nop
8006f72: 3710 adds r7, #16
8006f74: 46bd mov sp, r7
8006f76: bd80 pop {r7, pc}
08006f78 <ETH_MACReceptionEnable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
{
8006f78: b580 push {r7, lr}
8006f7a: b084 sub sp, #16
8006f7c: af00 add r7, sp, #0
8006f7e: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
8006f80: 2300 movs r3, #0
8006f82: 60fb str r3, [r7, #12]
/* Enable the MAC reception */
(heth->Instance)->MACCR |= ETH_MACCR_RE;
8006f84: 687b ldr r3, [r7, #4]
8006f86: 681b ldr r3, [r3, #0]
8006f88: 681a ldr r2, [r3, #0]
8006f8a: 687b ldr r3, [r7, #4]
8006f8c: 681b ldr r3, [r3, #0]
8006f8e: f042 0204 orr.w r2, r2, #4
8006f92: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8006f94: 687b ldr r3, [r7, #4]
8006f96: 681b ldr r3, [r3, #0]
8006f98: 681b ldr r3, [r3, #0]
8006f9a: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006f9c: 2001 movs r0, #1
8006f9e: f7fd fc23 bl 80047e8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8006fa2: 687b ldr r3, [r7, #4]
8006fa4: 681b ldr r3, [r3, #0]
8006fa6: 68fa ldr r2, [r7, #12]
8006fa8: 601a str r2, [r3, #0]
}
8006faa: bf00 nop
8006fac: 3710 adds r7, #16
8006fae: 46bd mov sp, r7
8006fb0: bd80 pop {r7, pc}
08006fb2 <ETH_MACReceptionDisable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
{
8006fb2: b580 push {r7, lr}
8006fb4: b084 sub sp, #16
8006fb6: af00 add r7, sp, #0
8006fb8: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
8006fba: 2300 movs r3, #0
8006fbc: 60fb str r3, [r7, #12]
/* Disable the MAC reception */
(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
8006fbe: 687b ldr r3, [r7, #4]
8006fc0: 681b ldr r3, [r3, #0]
8006fc2: 681a ldr r2, [r3, #0]
8006fc4: 687b ldr r3, [r7, #4]
8006fc6: 681b ldr r3, [r3, #0]
8006fc8: f022 0204 bic.w r2, r2, #4
8006fcc: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8006fce: 687b ldr r3, [r7, #4]
8006fd0: 681b ldr r3, [r3, #0]
8006fd2: 681b ldr r3, [r3, #0]
8006fd4: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006fd6: 2001 movs r0, #1
8006fd8: f7fd fc06 bl 80047e8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8006fdc: 687b ldr r3, [r7, #4]
8006fde: 681b ldr r3, [r3, #0]
8006fe0: 68fa ldr r2, [r7, #12]
8006fe2: 601a str r2, [r3, #0]
}
8006fe4: bf00 nop
8006fe6: 3710 adds r7, #16
8006fe8: 46bd mov sp, r7
8006fea: bd80 pop {r7, pc}
08006fec <ETH_DMATransmissionEnable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
{
8006fec: b480 push {r7}
8006fee: b083 sub sp, #12
8006ff0: af00 add r7, sp, #0
8006ff2: 6078 str r0, [r7, #4]
/* Enable the DMA transmission */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
8006ff4: 687b ldr r3, [r7, #4]
8006ff6: 681a ldr r2, [r3, #0]
8006ff8: f241 0318 movw r3, #4120 ; 0x1018
8006ffc: 4413 add r3, r2
8006ffe: 681b ldr r3, [r3, #0]
8007000: 687a ldr r2, [r7, #4]
8007002: 6811 ldr r1, [r2, #0]
8007004: f443 5200 orr.w r2, r3, #8192 ; 0x2000
8007008: f241 0318 movw r3, #4120 ; 0x1018
800700c: 440b add r3, r1
800700e: 601a str r2, [r3, #0]
}
8007010: bf00 nop
8007012: 370c adds r7, #12
8007014: 46bd mov sp, r7
8007016: f85d 7b04 ldr.w r7, [sp], #4
800701a: 4770 bx lr
0800701c <ETH_DMATransmissionDisable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
{
800701c: b480 push {r7}
800701e: b083 sub sp, #12
8007020: af00 add r7, sp, #0
8007022: 6078 str r0, [r7, #4]
/* Disable the DMA transmission */
(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
8007024: 687b ldr r3, [r7, #4]
8007026: 681a ldr r2, [r3, #0]
8007028: f241 0318 movw r3, #4120 ; 0x1018
800702c: 4413 add r3, r2
800702e: 681b ldr r3, [r3, #0]
8007030: 687a ldr r2, [r7, #4]
8007032: 6811 ldr r1, [r2, #0]
8007034: f423 5200 bic.w r2, r3, #8192 ; 0x2000
8007038: f241 0318 movw r3, #4120 ; 0x1018
800703c: 440b add r3, r1
800703e: 601a str r2, [r3, #0]
}
8007040: bf00 nop
8007042: 370c adds r7, #12
8007044: 46bd mov sp, r7
8007046: f85d 7b04 ldr.w r7, [sp], #4
800704a: 4770 bx lr
0800704c <ETH_DMAReceptionEnable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
{
800704c: b480 push {r7}
800704e: b083 sub sp, #12
8007050: af00 add r7, sp, #0
8007052: 6078 str r0, [r7, #4]
/* Enable the DMA reception */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
8007054: 687b ldr r3, [r7, #4]
8007056: 681a ldr r2, [r3, #0]
8007058: f241 0318 movw r3, #4120 ; 0x1018
800705c: 4413 add r3, r2
800705e: 681b ldr r3, [r3, #0]
8007060: 687a ldr r2, [r7, #4]
8007062: 6811 ldr r1, [r2, #0]
8007064: f043 0202 orr.w r2, r3, #2
8007068: f241 0318 movw r3, #4120 ; 0x1018
800706c: 440b add r3, r1
800706e: 601a str r2, [r3, #0]
}
8007070: bf00 nop
8007072: 370c adds r7, #12
8007074: 46bd mov sp, r7
8007076: f85d 7b04 ldr.w r7, [sp], #4
800707a: 4770 bx lr
0800707c <ETH_DMAReceptionDisable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
{
800707c: b480 push {r7}
800707e: b083 sub sp, #12
8007080: af00 add r7, sp, #0
8007082: 6078 str r0, [r7, #4]
/* Disable the DMA reception */
(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
8007084: 687b ldr r3, [r7, #4]
8007086: 681a ldr r2, [r3, #0]
8007088: f241 0318 movw r3, #4120 ; 0x1018
800708c: 4413 add r3, r2
800708e: 681b ldr r3, [r3, #0]
8007090: 687a ldr r2, [r7, #4]
8007092: 6811 ldr r1, [r2, #0]
8007094: f023 0202 bic.w r2, r3, #2
8007098: f241 0318 movw r3, #4120 ; 0x1018
800709c: 440b add r3, r1
800709e: 601a str r2, [r3, #0]
}
80070a0: bf00 nop
80070a2: 370c adds r7, #12
80070a4: 46bd mov sp, r7
80070a6: f85d 7b04 ldr.w r7, [sp], #4
80070aa: 4770 bx lr
080070ac <ETH_FlushTransmitFIFO>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
{
80070ac: b580 push {r7, lr}
80070ae: b084 sub sp, #16
80070b0: af00 add r7, sp, #0
80070b2: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
80070b4: 2300 movs r3, #0
80070b6: 60fb str r3, [r7, #12]
/* Set the Flush Transmit FIFO bit */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
80070b8: 687b ldr r3, [r7, #4]
80070ba: 681a ldr r2, [r3, #0]
80070bc: f241 0318 movw r3, #4120 ; 0x1018
80070c0: 4413 add r3, r2
80070c2: 681b ldr r3, [r3, #0]
80070c4: 687a ldr r2, [r7, #4]
80070c6: 6811 ldr r1, [r2, #0]
80070c8: f443 1280 orr.w r2, r3, #1048576 ; 0x100000
80070cc: f241 0318 movw r3, #4120 ; 0x1018
80070d0: 440b add r3, r1
80070d2: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->DMAOMR;
80070d4: 687b ldr r3, [r7, #4]
80070d6: 681a ldr r2, [r3, #0]
80070d8: f241 0318 movw r3, #4120 ; 0x1018
80070dc: 4413 add r3, r2
80070de: 681b ldr r3, [r3, #0]
80070e0: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
80070e2: 2001 movs r0, #1
80070e4: f7fd fb80 bl 80047e8 <HAL_Delay>
(heth->Instance)->DMAOMR = tmpreg;
80070e8: 687b ldr r3, [r7, #4]
80070ea: 6819 ldr r1, [r3, #0]
80070ec: 68fa ldr r2, [r7, #12]
80070ee: f241 0318 movw r3, #4120 ; 0x1018
80070f2: 440b add r3, r1
80070f4: 601a str r2, [r3, #0]
}
80070f6: bf00 nop
80070f8: 3710 adds r7, #16
80070fa: 46bd mov sp, r7
80070fc: bd80 pop {r7, pc}
...
08007100 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8007100: b480 push {r7}
8007102: b089 sub sp, #36 ; 0x24
8007104: af00 add r7, sp, #0
8007106: 6078 str r0, [r7, #4]
8007108: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
800710a: 2300 movs r3, #0
800710c: 61fb str r3, [r7, #28]
uint32_t ioposition = 0x00;
800710e: 2300 movs r3, #0
8007110: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
8007112: 2300 movs r3, #0
8007114: 613b str r3, [r7, #16]
uint32_t temp = 0x00;
8007116: 2300 movs r3, #0
8007118: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
800711a: 2300 movs r3, #0
800711c: 61fb str r3, [r7, #28]
800711e: e175 b.n 800740c <HAL_GPIO_Init+0x30c>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
8007120: 2201 movs r2, #1
8007122: 69fb ldr r3, [r7, #28]
8007124: fa02 f303 lsl.w r3, r2, r3
8007128: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
800712a: 683b ldr r3, [r7, #0]
800712c: 681b ldr r3, [r3, #0]
800712e: 697a ldr r2, [r7, #20]
8007130: 4013 ands r3, r2
8007132: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
8007134: 693a ldr r2, [r7, #16]
8007136: 697b ldr r3, [r7, #20]
8007138: 429a cmp r2, r3
800713a: f040 8164 bne.w 8007406 <HAL_GPIO_Init+0x306>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
800713e: 683b ldr r3, [r7, #0]
8007140: 685b ldr r3, [r3, #4]
8007142: 2b01 cmp r3, #1
8007144: d00b beq.n 800715e <HAL_GPIO_Init+0x5e>
8007146: 683b ldr r3, [r7, #0]
8007148: 685b ldr r3, [r3, #4]
800714a: 2b02 cmp r3, #2
800714c: d007 beq.n 800715e <HAL_GPIO_Init+0x5e>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
800714e: 683b ldr r3, [r7, #0]
8007150: 685b ldr r3, [r3, #4]
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
8007152: 2b11 cmp r3, #17
8007154: d003 beq.n 800715e <HAL_GPIO_Init+0x5e>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8007156: 683b ldr r3, [r7, #0]
8007158: 685b ldr r3, [r3, #4]
800715a: 2b12 cmp r3, #18
800715c: d130 bne.n 80071c0 <HAL_GPIO_Init+0xc0>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
800715e: 687b ldr r3, [r7, #4]
8007160: 689b ldr r3, [r3, #8]
8007162: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
8007164: 69fb ldr r3, [r7, #28]
8007166: 005b lsls r3, r3, #1
8007168: 2203 movs r2, #3
800716a: fa02 f303 lsl.w r3, r2, r3
800716e: 43db mvns r3, r3
8007170: 69ba ldr r2, [r7, #24]
8007172: 4013 ands r3, r2
8007174: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2));
8007176: 683b ldr r3, [r7, #0]
8007178: 68da ldr r2, [r3, #12]
800717a: 69fb ldr r3, [r7, #28]
800717c: 005b lsls r3, r3, #1
800717e: fa02 f303 lsl.w r3, r2, r3
8007182: 69ba ldr r2, [r7, #24]
8007184: 4313 orrs r3, r2
8007186: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8007188: 687b ldr r3, [r7, #4]
800718a: 69ba ldr r2, [r7, #24]
800718c: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
800718e: 687b ldr r3, [r7, #4]
8007190: 685b ldr r3, [r3, #4]
8007192: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8007194: 2201 movs r2, #1
8007196: 69fb ldr r3, [r7, #28]
8007198: fa02 f303 lsl.w r3, r2, r3
800719c: 43db mvns r3, r3
800719e: 69ba ldr r2, [r7, #24]
80071a0: 4013 ands r3, r2
80071a2: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
80071a4: 683b ldr r3, [r7, #0]
80071a6: 685b ldr r3, [r3, #4]
80071a8: 091b lsrs r3, r3, #4
80071aa: f003 0201 and.w r2, r3, #1
80071ae: 69fb ldr r3, [r7, #28]
80071b0: fa02 f303 lsl.w r3, r2, r3
80071b4: 69ba ldr r2, [r7, #24]
80071b6: 4313 orrs r3, r2
80071b8: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
80071ba: 687b ldr r3, [r7, #4]
80071bc: 69ba ldr r2, [r7, #24]
80071be: 605a str r2, [r3, #4]
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80071c0: 687b ldr r3, [r7, #4]
80071c2: 68db ldr r3, [r3, #12]
80071c4: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
80071c6: 69fb ldr r3, [r7, #28]
80071c8: 005b lsls r3, r3, #1
80071ca: 2203 movs r2, #3
80071cc: fa02 f303 lsl.w r3, r2, r3
80071d0: 43db mvns r3, r3
80071d2: 69ba ldr r2, [r7, #24]
80071d4: 4013 ands r3, r2
80071d6: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2));
80071d8: 683b ldr r3, [r7, #0]
80071da: 689a ldr r2, [r3, #8]
80071dc: 69fb ldr r3, [r7, #28]
80071de: 005b lsls r3, r3, #1
80071e0: fa02 f303 lsl.w r3, r2, r3
80071e4: 69ba ldr r2, [r7, #24]
80071e6: 4313 orrs r3, r2
80071e8: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
80071ea: 687b ldr r3, [r7, #4]
80071ec: 69ba ldr r2, [r7, #24]
80071ee: 60da str r2, [r3, #12]
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
80071f0: 683b ldr r3, [r7, #0]
80071f2: 685b ldr r3, [r3, #4]
80071f4: 2b02 cmp r3, #2
80071f6: d003 beq.n 8007200 <HAL_GPIO_Init+0x100>
80071f8: 683b ldr r3, [r7, #0]
80071fa: 685b ldr r3, [r3, #4]
80071fc: 2b12 cmp r3, #18
80071fe: d123 bne.n 8007248 <HAL_GPIO_Init+0x148>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
8007200: 69fb ldr r3, [r7, #28]
8007202: 08da lsrs r2, r3, #3
8007204: 687b ldr r3, [r7, #4]
8007206: 3208 adds r2, #8
8007208: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800720c: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
800720e: 69fb ldr r3, [r7, #28]
8007210: f003 0307 and.w r3, r3, #7
8007214: 009b lsls r3, r3, #2
8007216: 220f movs r2, #15
8007218: fa02 f303 lsl.w r3, r2, r3
800721c: 43db mvns r3, r3
800721e: 69ba ldr r2, [r7, #24]
8007220: 4013 ands r3, r2
8007222: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
8007224: 683b ldr r3, [r7, #0]
8007226: 691a ldr r2, [r3, #16]
8007228: 69fb ldr r3, [r7, #28]
800722a: f003 0307 and.w r3, r3, #7
800722e: 009b lsls r3, r3, #2
8007230: fa02 f303 lsl.w r3, r2, r3
8007234: 69ba ldr r2, [r7, #24]
8007236: 4313 orrs r3, r2
8007238: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3] = temp;
800723a: 69fb ldr r3, [r7, #28]
800723c: 08da lsrs r2, r3, #3
800723e: 687b ldr r3, [r7, #4]
8007240: 3208 adds r2, #8
8007242: 69b9 ldr r1, [r7, #24]
8007244: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8007248: 687b ldr r3, [r7, #4]
800724a: 681b ldr r3, [r3, #0]
800724c: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
800724e: 69fb ldr r3, [r7, #28]
8007250: 005b lsls r3, r3, #1
8007252: 2203 movs r2, #3
8007254: fa02 f303 lsl.w r3, r2, r3
8007258: 43db mvns r3, r3
800725a: 69ba ldr r2, [r7, #24]
800725c: 4013 ands r3, r2
800725e: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
8007260: 683b ldr r3, [r7, #0]
8007262: 685b ldr r3, [r3, #4]
8007264: f003 0203 and.w r2, r3, #3
8007268: 69fb ldr r3, [r7, #28]
800726a: 005b lsls r3, r3, #1
800726c: fa02 f303 lsl.w r3, r2, r3
8007270: 69ba ldr r2, [r7, #24]
8007272: 4313 orrs r3, r2
8007274: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8007276: 687b ldr r3, [r7, #4]
8007278: 69ba ldr r2, [r7, #24]
800727a: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
800727c: 683b ldr r3, [r7, #0]
800727e: 685b ldr r3, [r3, #4]
8007280: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8007284: 2b00 cmp r3, #0
8007286: f000 80be beq.w 8007406 <HAL_GPIO_Init+0x306>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800728a: 4b66 ldr r3, [pc, #408] ; (8007424 <HAL_GPIO_Init+0x324>)
800728c: 6c5b ldr r3, [r3, #68] ; 0x44
800728e: 4a65 ldr r2, [pc, #404] ; (8007424 <HAL_GPIO_Init+0x324>)
8007290: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8007294: 6453 str r3, [r2, #68] ; 0x44
8007296: 4b63 ldr r3, [pc, #396] ; (8007424 <HAL_GPIO_Init+0x324>)
8007298: 6c5b ldr r3, [r3, #68] ; 0x44
800729a: f403 4380 and.w r3, r3, #16384 ; 0x4000
800729e: 60fb str r3, [r7, #12]
80072a0: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2];
80072a2: 4a61 ldr r2, [pc, #388] ; (8007428 <HAL_GPIO_Init+0x328>)
80072a4: 69fb ldr r3, [r7, #28]
80072a6: 089b lsrs r3, r3, #2
80072a8: 3302 adds r3, #2
80072aa: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80072ae: 61bb str r3, [r7, #24]
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
80072b0: 69fb ldr r3, [r7, #28]
80072b2: f003 0303 and.w r3, r3, #3
80072b6: 009b lsls r3, r3, #2
80072b8: 220f movs r2, #15
80072ba: fa02 f303 lsl.w r3, r2, r3
80072be: 43db mvns r3, r3
80072c0: 69ba ldr r2, [r7, #24]
80072c2: 4013 ands r3, r2
80072c4: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
80072c6: 687b ldr r3, [r7, #4]
80072c8: 4a58 ldr r2, [pc, #352] ; (800742c <HAL_GPIO_Init+0x32c>)
80072ca: 4293 cmp r3, r2
80072cc: d037 beq.n 800733e <HAL_GPIO_Init+0x23e>
80072ce: 687b ldr r3, [r7, #4]
80072d0: 4a57 ldr r2, [pc, #348] ; (8007430 <HAL_GPIO_Init+0x330>)
80072d2: 4293 cmp r3, r2
80072d4: d031 beq.n 800733a <HAL_GPIO_Init+0x23a>
80072d6: 687b ldr r3, [r7, #4]
80072d8: 4a56 ldr r2, [pc, #344] ; (8007434 <HAL_GPIO_Init+0x334>)
80072da: 4293 cmp r3, r2
80072dc: d02b beq.n 8007336 <HAL_GPIO_Init+0x236>
80072de: 687b ldr r3, [r7, #4]
80072e0: 4a55 ldr r2, [pc, #340] ; (8007438 <HAL_GPIO_Init+0x338>)
80072e2: 4293 cmp r3, r2
80072e4: d025 beq.n 8007332 <HAL_GPIO_Init+0x232>
80072e6: 687b ldr r3, [r7, #4]
80072e8: 4a54 ldr r2, [pc, #336] ; (800743c <HAL_GPIO_Init+0x33c>)
80072ea: 4293 cmp r3, r2
80072ec: d01f beq.n 800732e <HAL_GPIO_Init+0x22e>
80072ee: 687b ldr r3, [r7, #4]
80072f0: 4a53 ldr r2, [pc, #332] ; (8007440 <HAL_GPIO_Init+0x340>)
80072f2: 4293 cmp r3, r2
80072f4: d019 beq.n 800732a <HAL_GPIO_Init+0x22a>
80072f6: 687b ldr r3, [r7, #4]
80072f8: 4a52 ldr r2, [pc, #328] ; (8007444 <HAL_GPIO_Init+0x344>)
80072fa: 4293 cmp r3, r2
80072fc: d013 beq.n 8007326 <HAL_GPIO_Init+0x226>
80072fe: 687b ldr r3, [r7, #4]
8007300: 4a51 ldr r2, [pc, #324] ; (8007448 <HAL_GPIO_Init+0x348>)
8007302: 4293 cmp r3, r2
8007304: d00d beq.n 8007322 <HAL_GPIO_Init+0x222>
8007306: 687b ldr r3, [r7, #4]
8007308: 4a50 ldr r2, [pc, #320] ; (800744c <HAL_GPIO_Init+0x34c>)
800730a: 4293 cmp r3, r2
800730c: d007 beq.n 800731e <HAL_GPIO_Init+0x21e>
800730e: 687b ldr r3, [r7, #4]
8007310: 4a4f ldr r2, [pc, #316] ; (8007450 <HAL_GPIO_Init+0x350>)
8007312: 4293 cmp r3, r2
8007314: d101 bne.n 800731a <HAL_GPIO_Init+0x21a>
8007316: 2309 movs r3, #9
8007318: e012 b.n 8007340 <HAL_GPIO_Init+0x240>
800731a: 230a movs r3, #10
800731c: e010 b.n 8007340 <HAL_GPIO_Init+0x240>
800731e: 2308 movs r3, #8
8007320: e00e b.n 8007340 <HAL_GPIO_Init+0x240>
8007322: 2307 movs r3, #7
8007324: e00c b.n 8007340 <HAL_GPIO_Init+0x240>
8007326: 2306 movs r3, #6
8007328: e00a b.n 8007340 <HAL_GPIO_Init+0x240>
800732a: 2305 movs r3, #5
800732c: e008 b.n 8007340 <HAL_GPIO_Init+0x240>
800732e: 2304 movs r3, #4
8007330: e006 b.n 8007340 <HAL_GPIO_Init+0x240>
8007332: 2303 movs r3, #3
8007334: e004 b.n 8007340 <HAL_GPIO_Init+0x240>
8007336: 2302 movs r3, #2
8007338: e002 b.n 8007340 <HAL_GPIO_Init+0x240>
800733a: 2301 movs r3, #1
800733c: e000 b.n 8007340 <HAL_GPIO_Init+0x240>
800733e: 2300 movs r3, #0
8007340: 69fa ldr r2, [r7, #28]
8007342: f002 0203 and.w r2, r2, #3
8007346: 0092 lsls r2, r2, #2
8007348: 4093 lsls r3, r2
800734a: 69ba ldr r2, [r7, #24]
800734c: 4313 orrs r3, r2
800734e: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2] = temp;
8007350: 4935 ldr r1, [pc, #212] ; (8007428 <HAL_GPIO_Init+0x328>)
8007352: 69fb ldr r3, [r7, #28]
8007354: 089b lsrs r3, r3, #2
8007356: 3302 adds r3, #2
8007358: 69ba ldr r2, [r7, #24]
800735a: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
800735e: 4b3d ldr r3, [pc, #244] ; (8007454 <HAL_GPIO_Init+0x354>)
8007360: 681b ldr r3, [r3, #0]
8007362: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8007364: 693b ldr r3, [r7, #16]
8007366: 43db mvns r3, r3
8007368: 69ba ldr r2, [r7, #24]
800736a: 4013 ands r3, r2
800736c: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
800736e: 683b ldr r3, [r7, #0]
8007370: 685b ldr r3, [r3, #4]
8007372: f403 3380 and.w r3, r3, #65536 ; 0x10000
8007376: 2b00 cmp r3, #0
8007378: d003 beq.n 8007382 <HAL_GPIO_Init+0x282>
{
temp |= iocurrent;
800737a: 69ba ldr r2, [r7, #24]
800737c: 693b ldr r3, [r7, #16]
800737e: 4313 orrs r3, r2
8007380: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8007382: 4a34 ldr r2, [pc, #208] ; (8007454 <HAL_GPIO_Init+0x354>)
8007384: 69bb ldr r3, [r7, #24]
8007386: 6013 str r3, [r2, #0]
temp = EXTI->EMR;
8007388: 4b32 ldr r3, [pc, #200] ; (8007454 <HAL_GPIO_Init+0x354>)
800738a: 685b ldr r3, [r3, #4]
800738c: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800738e: 693b ldr r3, [r7, #16]
8007390: 43db mvns r3, r3
8007392: 69ba ldr r2, [r7, #24]
8007394: 4013 ands r3, r2
8007396: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8007398: 683b ldr r3, [r7, #0]
800739a: 685b ldr r3, [r3, #4]
800739c: f403 3300 and.w r3, r3, #131072 ; 0x20000
80073a0: 2b00 cmp r3, #0
80073a2: d003 beq.n 80073ac <HAL_GPIO_Init+0x2ac>
{
temp |= iocurrent;
80073a4: 69ba ldr r2, [r7, #24]
80073a6: 693b ldr r3, [r7, #16]
80073a8: 4313 orrs r3, r2
80073aa: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
80073ac: 4a29 ldr r2, [pc, #164] ; (8007454 <HAL_GPIO_Init+0x354>)
80073ae: 69bb ldr r3, [r7, #24]
80073b0: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
80073b2: 4b28 ldr r3, [pc, #160] ; (8007454 <HAL_GPIO_Init+0x354>)
80073b4: 689b ldr r3, [r3, #8]
80073b6: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80073b8: 693b ldr r3, [r7, #16]
80073ba: 43db mvns r3, r3
80073bc: 69ba ldr r2, [r7, #24]
80073be: 4013 ands r3, r2
80073c0: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
80073c2: 683b ldr r3, [r7, #0]
80073c4: 685b ldr r3, [r3, #4]
80073c6: f403 1380 and.w r3, r3, #1048576 ; 0x100000
80073ca: 2b00 cmp r3, #0
80073cc: d003 beq.n 80073d6 <HAL_GPIO_Init+0x2d6>
{
temp |= iocurrent;
80073ce: 69ba ldr r2, [r7, #24]
80073d0: 693b ldr r3, [r7, #16]
80073d2: 4313 orrs r3, r2
80073d4: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
80073d6: 4a1f ldr r2, [pc, #124] ; (8007454 <HAL_GPIO_Init+0x354>)
80073d8: 69bb ldr r3, [r7, #24]
80073da: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
80073dc: 4b1d ldr r3, [pc, #116] ; (8007454 <HAL_GPIO_Init+0x354>)
80073de: 68db ldr r3, [r3, #12]
80073e0: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80073e2: 693b ldr r3, [r7, #16]
80073e4: 43db mvns r3, r3
80073e6: 69ba ldr r2, [r7, #24]
80073e8: 4013 ands r3, r2
80073ea: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
80073ec: 683b ldr r3, [r7, #0]
80073ee: 685b ldr r3, [r3, #4]
80073f0: f403 1300 and.w r3, r3, #2097152 ; 0x200000
80073f4: 2b00 cmp r3, #0
80073f6: d003 beq.n 8007400 <HAL_GPIO_Init+0x300>
{
temp |= iocurrent;
80073f8: 69ba ldr r2, [r7, #24]
80073fa: 693b ldr r3, [r7, #16]
80073fc: 4313 orrs r3, r2
80073fe: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8007400: 4a14 ldr r2, [pc, #80] ; (8007454 <HAL_GPIO_Init+0x354>)
8007402: 69bb ldr r3, [r7, #24]
8007404: 60d3 str r3, [r2, #12]
for(position = 0; position < GPIO_NUMBER; position++)
8007406: 69fb ldr r3, [r7, #28]
8007408: 3301 adds r3, #1
800740a: 61fb str r3, [r7, #28]
800740c: 69fb ldr r3, [r7, #28]
800740e: 2b0f cmp r3, #15
8007410: f67f ae86 bls.w 8007120 <HAL_GPIO_Init+0x20>
}
}
}
}
8007414: bf00 nop
8007416: bf00 nop
8007418: 3724 adds r7, #36 ; 0x24
800741a: 46bd mov sp, r7
800741c: f85d 7b04 ldr.w r7, [sp], #4
8007420: 4770 bx lr
8007422: bf00 nop
8007424: 40023800 .word 0x40023800
8007428: 40013800 .word 0x40013800
800742c: 40020000 .word 0x40020000
8007430: 40020400 .word 0x40020400
8007434: 40020800 .word 0x40020800
8007438: 40020c00 .word 0x40020c00
800743c: 40021000 .word 0x40021000
8007440: 40021400 .word 0x40021400
8007444: 40021800 .word 0x40021800
8007448: 40021c00 .word 0x40021c00
800744c: 40022000 .word 0x40022000
8007450: 40022400 .word 0x40022400
8007454: 40013c00 .word 0x40013c00
08007458 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8007458: b480 push {r7}
800745a: b083 sub sp, #12
800745c: af00 add r7, sp, #0
800745e: 6078 str r0, [r7, #4]
8007460: 460b mov r3, r1
8007462: 807b strh r3, [r7, #2]
8007464: 4613 mov r3, r2
8007466: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8007468: 787b ldrb r3, [r7, #1]
800746a: 2b00 cmp r3, #0
800746c: d003 beq.n 8007476 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
800746e: 887a ldrh r2, [r7, #2]
8007470: 687b ldr r3, [r7, #4]
8007472: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
8007474: e003 b.n 800747e <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
8007476: 887b ldrh r3, [r7, #2]
8007478: 041a lsls r2, r3, #16
800747a: 687b ldr r3, [r7, #4]
800747c: 619a str r2, [r3, #24]
}
800747e: bf00 nop
8007480: 370c adds r7, #12
8007482: 46bd mov sp, r7
8007484: f85d 7b04 ldr.w r7, [sp], #4
8007488: 4770 bx lr
...
0800748c <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
800748c: b580 push {r7, lr}
800748e: b082 sub sp, #8
8007490: af00 add r7, sp, #0
8007492: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
8007494: 687b ldr r3, [r7, #4]
8007496: 2b00 cmp r3, #0
8007498: d101 bne.n 800749e <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
800749a: 2301 movs r3, #1
800749c: e07f b.n 800759e <HAL_I2C_Init+0x112>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
800749e: 687b ldr r3, [r7, #4]
80074a0: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
80074a4: b2db uxtb r3, r3
80074a6: 2b00 cmp r3, #0
80074a8: d106 bne.n 80074b8 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
80074aa: 687b ldr r3, [r7, #4]
80074ac: 2200 movs r2, #0
80074ae: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
80074b2: 6878 ldr r0, [r7, #4]
80074b4: f000 f8a9 bl 800760a <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
80074b8: 687b ldr r3, [r7, #4]
80074ba: 2224 movs r2, #36 ; 0x24
80074bc: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80074c0: 687b ldr r3, [r7, #4]
80074c2: 681b ldr r3, [r3, #0]
80074c4: 681a ldr r2, [r3, #0]
80074c6: 687b ldr r3, [r7, #4]
80074c8: 681b ldr r3, [r3, #0]
80074ca: f022 0201 bic.w r2, r2, #1
80074ce: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
80074d0: 687b ldr r3, [r7, #4]
80074d2: 685a ldr r2, [r3, #4]
80074d4: 687b ldr r3, [r7, #4]
80074d6: 681b ldr r3, [r3, #0]
80074d8: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
80074dc: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
80074de: 687b ldr r3, [r7, #4]
80074e0: 681b ldr r3, [r3, #0]
80074e2: 689a ldr r2, [r3, #8]
80074e4: 687b ldr r3, [r7, #4]
80074e6: 681b ldr r3, [r3, #0]
80074e8: f422 4200 bic.w r2, r2, #32768 ; 0x8000
80074ec: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
80074ee: 687b ldr r3, [r7, #4]
80074f0: 68db ldr r3, [r3, #12]
80074f2: 2b01 cmp r3, #1
80074f4: d107 bne.n 8007506 <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
80074f6: 687b ldr r3, [r7, #4]
80074f8: 689a ldr r2, [r3, #8]
80074fa: 687b ldr r3, [r7, #4]
80074fc: 681b ldr r3, [r3, #0]
80074fe: f442 4200 orr.w r2, r2, #32768 ; 0x8000
8007502: 609a str r2, [r3, #8]
8007504: e006 b.n 8007514 <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
8007506: 687b ldr r3, [r7, #4]
8007508: 689a ldr r2, [r3, #8]
800750a: 687b ldr r3, [r7, #4]
800750c: 681b ldr r3, [r3, #0]
800750e: f442 4204 orr.w r2, r2, #33792 ; 0x8400
8007512: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
8007514: 687b ldr r3, [r7, #4]
8007516: 68db ldr r3, [r3, #12]
8007518: 2b02 cmp r3, #2
800751a: d104 bne.n 8007526 <HAL_I2C_Init+0x9a>
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
800751c: 687b ldr r3, [r7, #4]
800751e: 681b ldr r3, [r3, #0]
8007520: f44f 6200 mov.w r2, #2048 ; 0x800
8007524: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
8007526: 687b ldr r3, [r7, #4]
8007528: 681b ldr r3, [r3, #0]
800752a: 6859 ldr r1, [r3, #4]
800752c: 687b ldr r3, [r7, #4]
800752e: 681a ldr r2, [r3, #0]
8007530: 4b1d ldr r3, [pc, #116] ; (80075a8 <HAL_I2C_Init+0x11c>)
8007532: 430b orrs r3, r1
8007534: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
8007536: 687b ldr r3, [r7, #4]
8007538: 681b ldr r3, [r3, #0]
800753a: 68da ldr r2, [r3, #12]
800753c: 687b ldr r3, [r7, #4]
800753e: 681b ldr r3, [r3, #0]
8007540: f422 4200 bic.w r2, r2, #32768 ; 0x8000
8007544: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
8007546: 687b ldr r3, [r7, #4]
8007548: 691a ldr r2, [r3, #16]
800754a: 687b ldr r3, [r7, #4]
800754c: 695b ldr r3, [r3, #20]
800754e: ea42 0103 orr.w r1, r2, r3
8007552: 687b ldr r3, [r7, #4]
8007554: 699b ldr r3, [r3, #24]
8007556: 021a lsls r2, r3, #8
8007558: 687b ldr r3, [r7, #4]
800755a: 681b ldr r3, [r3, #0]
800755c: 430a orrs r2, r1
800755e: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
8007560: 687b ldr r3, [r7, #4]
8007562: 69d9 ldr r1, [r3, #28]
8007564: 687b ldr r3, [r7, #4]
8007566: 6a1a ldr r2, [r3, #32]
8007568: 687b ldr r3, [r7, #4]
800756a: 681b ldr r3, [r3, #0]
800756c: 430a orrs r2, r1
800756e: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8007570: 687b ldr r3, [r7, #4]
8007572: 681b ldr r3, [r3, #0]
8007574: 681a ldr r2, [r3, #0]
8007576: 687b ldr r3, [r7, #4]
8007578: 681b ldr r3, [r3, #0]
800757a: f042 0201 orr.w r2, r2, #1
800757e: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8007580: 687b ldr r3, [r7, #4]
8007582: 2200 movs r2, #0
8007584: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007586: 687b ldr r3, [r7, #4]
8007588: 2220 movs r2, #32
800758a: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->PreviousState = I2C_STATE_NONE;
800758e: 687b ldr r3, [r7, #4]
8007590: 2200 movs r2, #0
8007592: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8007594: 687b ldr r3, [r7, #4]
8007596: 2200 movs r2, #0
8007598: f883 2042 strb.w r2, [r3, #66] ; 0x42
return HAL_OK;
800759c: 2300 movs r3, #0
}
800759e: 4618 mov r0, r3
80075a0: 3708 adds r7, #8
80075a2: 46bd mov sp, r7
80075a4: bd80 pop {r7, pc}
80075a6: bf00 nop
80075a8: 02008000 .word 0x02008000
080075ac <HAL_I2C_DeInit>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
{
80075ac: b580 push {r7, lr}
80075ae: b082 sub sp, #8
80075b0: af00 add r7, sp, #0
80075b2: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
80075b4: 687b ldr r3, [r7, #4]
80075b6: 2b00 cmp r3, #0
80075b8: d101 bne.n 80075be <HAL_I2C_DeInit+0x12>
{
return HAL_ERROR;
80075ba: 2301 movs r3, #1
80075bc: e021 b.n 8007602 <HAL_I2C_DeInit+0x56>
}
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
hi2c->State = HAL_I2C_STATE_BUSY;
80075be: 687b ldr r3, [r7, #4]
80075c0: 2224 movs r2, #36 ; 0x24
80075c2: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the I2C Peripheral Clock */
__HAL_I2C_DISABLE(hi2c);
80075c6: 687b ldr r3, [r7, #4]
80075c8: 681b ldr r3, [r3, #0]
80075ca: 681a ldr r2, [r3, #0]
80075cc: 687b ldr r3, [r7, #4]
80075ce: 681b ldr r3, [r3, #0]
80075d0: f022 0201 bic.w r2, r2, #1
80075d4: 601a str r2, [r3, #0]
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
hi2c->MspDeInitCallback(hi2c);
#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_I2C_MspDeInit(hi2c);
80075d6: 6878 ldr r0, [r7, #4]
80075d8: f000 f821 bl 800761e <HAL_I2C_MspDeInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80075dc: 687b ldr r3, [r7, #4]
80075de: 2200 movs r2, #0
80075e0: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_RESET;
80075e2: 687b ldr r3, [r7, #4]
80075e4: 2200 movs r2, #0
80075e6: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->PreviousState = I2C_STATE_NONE;
80075ea: 687b ldr r3, [r7, #4]
80075ec: 2200 movs r2, #0
80075ee: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
80075f0: 687b ldr r3, [r7, #4]
80075f2: 2200 movs r2, #0
80075f4: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Release Lock */
__HAL_UNLOCK(hi2c);
80075f8: 687b ldr r3, [r7, #4]
80075fa: 2200 movs r2, #0
80075fc: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8007600: 2300 movs r3, #0
}
8007602: 4618 mov r0, r3
8007604: 3708 adds r7, #8
8007606: 46bd mov sp, r7
8007608: bd80 pop {r7, pc}
0800760a <HAL_I2C_MspInit>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
{
800760a: b480 push {r7}
800760c: b083 sub sp, #12
800760e: af00 add r7, sp, #0
8007610: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspInit could be implemented in the user file
*/
}
8007612: bf00 nop
8007614: 370c adds r7, #12
8007616: 46bd mov sp, r7
8007618: f85d 7b04 ldr.w r7, [sp], #4
800761c: 4770 bx lr
0800761e <HAL_I2C_MspDeInit>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
{
800761e: b480 push {r7}
8007620: b083 sub sp, #12
8007622: af00 add r7, sp, #0
8007624: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspDeInit could be implemented in the user file
*/
}
8007626: bf00 nop
8007628: 370c adds r7, #12
800762a: 46bd mov sp, r7
800762c: f85d 7b04 ldr.w r7, [sp], #4
8007630: 4770 bx lr
...
08007634 <HAL_I2C_Mem_Write>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8007634: b580 push {r7, lr}
8007636: b088 sub sp, #32
8007638: af02 add r7, sp, #8
800763a: 60f8 str r0, [r7, #12]
800763c: 4608 mov r0, r1
800763e: 4611 mov r1, r2
8007640: 461a mov r2, r3
8007642: 4603 mov r3, r0
8007644: 817b strh r3, [r7, #10]
8007646: 460b mov r3, r1
8007648: 813b strh r3, [r7, #8]
800764a: 4613 mov r3, r2
800764c: 80fb strh r3, [r7, #6]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
800764e: 68fb ldr r3, [r7, #12]
8007650: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8007654: b2db uxtb r3, r3
8007656: 2b20 cmp r3, #32
8007658: f040 80f9 bne.w 800784e <HAL_I2C_Mem_Write+0x21a>
{
if ((pData == NULL) || (Size == 0U))
800765c: 6a3b ldr r3, [r7, #32]
800765e: 2b00 cmp r3, #0
8007660: d002 beq.n 8007668 <HAL_I2C_Mem_Write+0x34>
8007662: 8cbb ldrh r3, [r7, #36] ; 0x24
8007664: 2b00 cmp r3, #0
8007666: d105 bne.n 8007674 <HAL_I2C_Mem_Write+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
8007668: 68fb ldr r3, [r7, #12]
800766a: f44f 7200 mov.w r2, #512 ; 0x200
800766e: 645a str r2, [r3, #68] ; 0x44
return HAL_ERROR;
8007670: 2301 movs r3, #1
8007672: e0ed b.n 8007850 <HAL_I2C_Mem_Write+0x21c>
}
/* Process Locked */
__HAL_LOCK(hi2c);
8007674: 68fb ldr r3, [r7, #12]
8007676: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
800767a: 2b01 cmp r3, #1
800767c: d101 bne.n 8007682 <HAL_I2C_Mem_Write+0x4e>
800767e: 2302 movs r3, #2
8007680: e0e6 b.n 8007850 <HAL_I2C_Mem_Write+0x21c>
8007682: 68fb ldr r3, [r7, #12]
8007684: 2201 movs r2, #1
8007686: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
800768a: f7fd f8a1 bl 80047d0 <HAL_GetTick>
800768e: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
8007690: 697b ldr r3, [r7, #20]
8007692: 9300 str r3, [sp, #0]
8007694: 2319 movs r3, #25
8007696: 2201 movs r2, #1
8007698: f44f 4100 mov.w r1, #32768 ; 0x8000
800769c: 68f8 ldr r0, [r7, #12]
800769e: f000 fad1 bl 8007c44 <I2C_WaitOnFlagUntilTimeout>
80076a2: 4603 mov r3, r0
80076a4: 2b00 cmp r3, #0
80076a6: d001 beq.n 80076ac <HAL_I2C_Mem_Write+0x78>
{
return HAL_ERROR;
80076a8: 2301 movs r3, #1
80076aa: e0d1 b.n 8007850 <HAL_I2C_Mem_Write+0x21c>
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
80076ac: 68fb ldr r3, [r7, #12]
80076ae: 2221 movs r2, #33 ; 0x21
80076b0: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
80076b4: 68fb ldr r3, [r7, #12]
80076b6: 2240 movs r2, #64 ; 0x40
80076b8: f883 2042 strb.w r2, [r3, #66] ; 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80076bc: 68fb ldr r3, [r7, #12]
80076be: 2200 movs r2, #0
80076c0: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
80076c2: 68fb ldr r3, [r7, #12]
80076c4: 6a3a ldr r2, [r7, #32]
80076c6: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount = Size;
80076c8: 68fb ldr r3, [r7, #12]
80076ca: 8cba ldrh r2, [r7, #36] ; 0x24
80076cc: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferISR = NULL;
80076ce: 68fb ldr r3, [r7, #12]
80076d0: 2200 movs r2, #0
80076d2: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
80076d4: 88f8 ldrh r0, [r7, #6]
80076d6: 893a ldrh r2, [r7, #8]
80076d8: 8979 ldrh r1, [r7, #10]
80076da: 697b ldr r3, [r7, #20]
80076dc: 9301 str r3, [sp, #4]
80076de: 6abb ldr r3, [r7, #40] ; 0x28
80076e0: 9300 str r3, [sp, #0]
80076e2: 4603 mov r3, r0
80076e4: 68f8 ldr r0, [r7, #12]
80076e6: f000 f9e1 bl 8007aac <I2C_RequestMemoryWrite>
80076ea: 4603 mov r3, r0
80076ec: 2b00 cmp r3, #0
80076ee: d005 beq.n 80076fc <HAL_I2C_Mem_Write+0xc8>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80076f0: 68fb ldr r3, [r7, #12]
80076f2: 2200 movs r2, #0
80076f4: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
80076f8: 2301 movs r3, #1
80076fa: e0a9 b.n 8007850 <HAL_I2C_Mem_Write+0x21c>
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80076fc: 68fb ldr r3, [r7, #12]
80076fe: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007700: b29b uxth r3, r3
8007702: 2bff cmp r3, #255 ; 0xff
8007704: d90e bls.n 8007724 <HAL_I2C_Mem_Write+0xf0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8007706: 68fb ldr r3, [r7, #12]
8007708: 22ff movs r2, #255 ; 0xff
800770a: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
800770c: 68fb ldr r3, [r7, #12]
800770e: 8d1b ldrh r3, [r3, #40] ; 0x28
8007710: b2da uxtb r2, r3
8007712: 8979 ldrh r1, [r7, #10]
8007714: 2300 movs r3, #0
8007716: 9300 str r3, [sp, #0]
8007718: f04f 7380 mov.w r3, #16777216 ; 0x1000000
800771c: 68f8 ldr r0, [r7, #12]
800771e: f000 fbb3 bl 8007e88 <I2C_TransferConfig>
8007722: e00f b.n 8007744 <HAL_I2C_Mem_Write+0x110>
}
else
{
hi2c->XferSize = hi2c->XferCount;
8007724: 68fb ldr r3, [r7, #12]
8007726: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007728: b29a uxth r2, r3
800772a: 68fb ldr r3, [r7, #12]
800772c: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
800772e: 68fb ldr r3, [r7, #12]
8007730: 8d1b ldrh r3, [r3, #40] ; 0x28
8007732: b2da uxtb r2, r3
8007734: 8979 ldrh r1, [r7, #10]
8007736: 2300 movs r3, #0
8007738: 9300 str r3, [sp, #0]
800773a: f04f 7300 mov.w r3, #33554432 ; 0x2000000
800773e: 68f8 ldr r0, [r7, #12]
8007740: f000 fba2 bl 8007e88 <I2C_TransferConfig>
}
do
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8007744: 697a ldr r2, [r7, #20]
8007746: 6ab9 ldr r1, [r7, #40] ; 0x28
8007748: 68f8 ldr r0, [r7, #12]
800774a: f000 fabb bl 8007cc4 <I2C_WaitOnTXISFlagUntilTimeout>
800774e: 4603 mov r3, r0
8007750: 2b00 cmp r3, #0
8007752: d001 beq.n 8007758 <HAL_I2C_Mem_Write+0x124>
{
return HAL_ERROR;
8007754: 2301 movs r3, #1
8007756: e07b b.n 8007850 <HAL_I2C_Mem_Write+0x21c>
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
8007758: 68fb ldr r3, [r7, #12]
800775a: 6a5b ldr r3, [r3, #36] ; 0x24
800775c: 781a ldrb r2, [r3, #0]
800775e: 68fb ldr r3, [r7, #12]
8007760: 681b ldr r3, [r3, #0]
8007762: 629a str r2, [r3, #40] ; 0x28
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8007764: 68fb ldr r3, [r7, #12]
8007766: 6a5b ldr r3, [r3, #36] ; 0x24
8007768: 1c5a adds r2, r3, #1
800776a: 68fb ldr r3, [r7, #12]
800776c: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount--;
800776e: 68fb ldr r3, [r7, #12]
8007770: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007772: b29b uxth r3, r3
8007774: 3b01 subs r3, #1
8007776: b29a uxth r2, r3
8007778: 68fb ldr r3, [r7, #12]
800777a: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferSize--;
800777c: 68fb ldr r3, [r7, #12]
800777e: 8d1b ldrh r3, [r3, #40] ; 0x28
8007780: 3b01 subs r3, #1
8007782: b29a uxth r2, r3
8007784: 68fb ldr r3, [r7, #12]
8007786: 851a strh r2, [r3, #40] ; 0x28
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
8007788: 68fb ldr r3, [r7, #12]
800778a: 8d5b ldrh r3, [r3, #42] ; 0x2a
800778c: b29b uxth r3, r3
800778e: 2b00 cmp r3, #0
8007790: d034 beq.n 80077fc <HAL_I2C_Mem_Write+0x1c8>
8007792: 68fb ldr r3, [r7, #12]
8007794: 8d1b ldrh r3, [r3, #40] ; 0x28
8007796: 2b00 cmp r3, #0
8007798: d130 bne.n 80077fc <HAL_I2C_Mem_Write+0x1c8>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
800779a: 697b ldr r3, [r7, #20]
800779c: 9300 str r3, [sp, #0]
800779e: 6abb ldr r3, [r7, #40] ; 0x28
80077a0: 2200 movs r2, #0
80077a2: 2180 movs r1, #128 ; 0x80
80077a4: 68f8 ldr r0, [r7, #12]
80077a6: f000 fa4d bl 8007c44 <I2C_WaitOnFlagUntilTimeout>
80077aa: 4603 mov r3, r0
80077ac: 2b00 cmp r3, #0
80077ae: d001 beq.n 80077b4 <HAL_I2C_Mem_Write+0x180>
{
return HAL_ERROR;
80077b0: 2301 movs r3, #1
80077b2: e04d b.n 8007850 <HAL_I2C_Mem_Write+0x21c>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80077b4: 68fb ldr r3, [r7, #12]
80077b6: 8d5b ldrh r3, [r3, #42] ; 0x2a
80077b8: b29b uxth r3, r3
80077ba: 2bff cmp r3, #255 ; 0xff
80077bc: d90e bls.n 80077dc <HAL_I2C_Mem_Write+0x1a8>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
80077be: 68fb ldr r3, [r7, #12]
80077c0: 22ff movs r2, #255 ; 0xff
80077c2: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
80077c4: 68fb ldr r3, [r7, #12]
80077c6: 8d1b ldrh r3, [r3, #40] ; 0x28
80077c8: b2da uxtb r2, r3
80077ca: 8979 ldrh r1, [r7, #10]
80077cc: 2300 movs r3, #0
80077ce: 9300 str r3, [sp, #0]
80077d0: f04f 7380 mov.w r3, #16777216 ; 0x1000000
80077d4: 68f8 ldr r0, [r7, #12]
80077d6: f000 fb57 bl 8007e88 <I2C_TransferConfig>
80077da: e00f b.n 80077fc <HAL_I2C_Mem_Write+0x1c8>
}
else
{
hi2c->XferSize = hi2c->XferCount;
80077dc: 68fb ldr r3, [r7, #12]
80077de: 8d5b ldrh r3, [r3, #42] ; 0x2a
80077e0: b29a uxth r2, r3
80077e2: 68fb ldr r3, [r7, #12]
80077e4: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
80077e6: 68fb ldr r3, [r7, #12]
80077e8: 8d1b ldrh r3, [r3, #40] ; 0x28
80077ea: b2da uxtb r2, r3
80077ec: 8979 ldrh r1, [r7, #10]
80077ee: 2300 movs r3, #0
80077f0: 9300 str r3, [sp, #0]
80077f2: f04f 7300 mov.w r3, #33554432 ; 0x2000000
80077f6: 68f8 ldr r0, [r7, #12]
80077f8: f000 fb46 bl 8007e88 <I2C_TransferConfig>
}
}
} while (hi2c->XferCount > 0U);
80077fc: 68fb ldr r3, [r7, #12]
80077fe: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007800: b29b uxth r3, r3
8007802: 2b00 cmp r3, #0
8007804: d19e bne.n 8007744 <HAL_I2C_Mem_Write+0x110>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8007806: 697a ldr r2, [r7, #20]
8007808: 6ab9 ldr r1, [r7, #40] ; 0x28
800780a: 68f8 ldr r0, [r7, #12]
800780c: f000 fa9a bl 8007d44 <I2C_WaitOnSTOPFlagUntilTimeout>
8007810: 4603 mov r3, r0
8007812: 2b00 cmp r3, #0
8007814: d001 beq.n 800781a <HAL_I2C_Mem_Write+0x1e6>
{
return HAL_ERROR;
8007816: 2301 movs r3, #1
8007818: e01a b.n 8007850 <HAL_I2C_Mem_Write+0x21c>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
800781a: 68fb ldr r3, [r7, #12]
800781c: 681b ldr r3, [r3, #0]
800781e: 2220 movs r2, #32
8007820: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8007822: 68fb ldr r3, [r7, #12]
8007824: 681b ldr r3, [r3, #0]
8007826: 6859 ldr r1, [r3, #4]
8007828: 68fb ldr r3, [r7, #12]
800782a: 681a ldr r2, [r3, #0]
800782c: 4b0a ldr r3, [pc, #40] ; (8007858 <HAL_I2C_Mem_Write+0x224>)
800782e: 400b ands r3, r1
8007830: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
8007832: 68fb ldr r3, [r7, #12]
8007834: 2220 movs r2, #32
8007836: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
800783a: 68fb ldr r3, [r7, #12]
800783c: 2200 movs r2, #0
800783e: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007842: 68fb ldr r3, [r7, #12]
8007844: 2200 movs r2, #0
8007846: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
800784a: 2300 movs r3, #0
800784c: e000 b.n 8007850 <HAL_I2C_Mem_Write+0x21c>
}
else
{
return HAL_BUSY;
800784e: 2302 movs r3, #2
}
}
8007850: 4618 mov r0, r3
8007852: 3718 adds r7, #24
8007854: 46bd mov sp, r7
8007856: bd80 pop {r7, pc}
8007858: fe00e800 .word 0xfe00e800
0800785c <HAL_I2C_Mem_Read>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800785c: b580 push {r7, lr}
800785e: b088 sub sp, #32
8007860: af02 add r7, sp, #8
8007862: 60f8 str r0, [r7, #12]
8007864: 4608 mov r0, r1
8007866: 4611 mov r1, r2
8007868: 461a mov r2, r3
800786a: 4603 mov r3, r0
800786c: 817b strh r3, [r7, #10]
800786e: 460b mov r3, r1
8007870: 813b strh r3, [r7, #8]
8007872: 4613 mov r3, r2
8007874: 80fb strh r3, [r7, #6]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
8007876: 68fb ldr r3, [r7, #12]
8007878: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
800787c: b2db uxtb r3, r3
800787e: 2b20 cmp r3, #32
8007880: f040 80fd bne.w 8007a7e <HAL_I2C_Mem_Read+0x222>
{
if ((pData == NULL) || (Size == 0U))
8007884: 6a3b ldr r3, [r7, #32]
8007886: 2b00 cmp r3, #0
8007888: d002 beq.n 8007890 <HAL_I2C_Mem_Read+0x34>
800788a: 8cbb ldrh r3, [r7, #36] ; 0x24
800788c: 2b00 cmp r3, #0
800788e: d105 bne.n 800789c <HAL_I2C_Mem_Read+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
8007890: 68fb ldr r3, [r7, #12]
8007892: f44f 7200 mov.w r2, #512 ; 0x200
8007896: 645a str r2, [r3, #68] ; 0x44
return HAL_ERROR;
8007898: 2301 movs r3, #1
800789a: e0f1 b.n 8007a80 <HAL_I2C_Mem_Read+0x224>
}
/* Process Locked */
__HAL_LOCK(hi2c);
800789c: 68fb ldr r3, [r7, #12]
800789e: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
80078a2: 2b01 cmp r3, #1
80078a4: d101 bne.n 80078aa <HAL_I2C_Mem_Read+0x4e>
80078a6: 2302 movs r3, #2
80078a8: e0ea b.n 8007a80 <HAL_I2C_Mem_Read+0x224>
80078aa: 68fb ldr r3, [r7, #12]
80078ac: 2201 movs r2, #1
80078ae: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
80078b2: f7fc ff8d bl 80047d0 <HAL_GetTick>
80078b6: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
80078b8: 697b ldr r3, [r7, #20]
80078ba: 9300 str r3, [sp, #0]
80078bc: 2319 movs r3, #25
80078be: 2201 movs r2, #1
80078c0: f44f 4100 mov.w r1, #32768 ; 0x8000
80078c4: 68f8 ldr r0, [r7, #12]
80078c6: f000 f9bd bl 8007c44 <I2C_WaitOnFlagUntilTimeout>
80078ca: 4603 mov r3, r0
80078cc: 2b00 cmp r3, #0
80078ce: d001 beq.n 80078d4 <HAL_I2C_Mem_Read+0x78>
{
return HAL_ERROR;
80078d0: 2301 movs r3, #1
80078d2: e0d5 b.n 8007a80 <HAL_I2C_Mem_Read+0x224>
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
80078d4: 68fb ldr r3, [r7, #12]
80078d6: 2222 movs r2, #34 ; 0x22
80078d8: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
80078dc: 68fb ldr r3, [r7, #12]
80078de: 2240 movs r2, #64 ; 0x40
80078e0: f883 2042 strb.w r2, [r3, #66] ; 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80078e4: 68fb ldr r3, [r7, #12]
80078e6: 2200 movs r2, #0
80078e8: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
80078ea: 68fb ldr r3, [r7, #12]
80078ec: 6a3a ldr r2, [r7, #32]
80078ee: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount = Size;
80078f0: 68fb ldr r3, [r7, #12]
80078f2: 8cba ldrh r2, [r7, #36] ; 0x24
80078f4: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferISR = NULL;
80078f6: 68fb ldr r3, [r7, #12]
80078f8: 2200 movs r2, #0
80078fa: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
80078fc: 88f8 ldrh r0, [r7, #6]
80078fe: 893a ldrh r2, [r7, #8]
8007900: 8979 ldrh r1, [r7, #10]
8007902: 697b ldr r3, [r7, #20]
8007904: 9301 str r3, [sp, #4]
8007906: 6abb ldr r3, [r7, #40] ; 0x28
8007908: 9300 str r3, [sp, #0]
800790a: 4603 mov r3, r0
800790c: 68f8 ldr r0, [r7, #12]
800790e: f000 f921 bl 8007b54 <I2C_RequestMemoryRead>
8007912: 4603 mov r3, r0
8007914: 2b00 cmp r3, #0
8007916: d005 beq.n 8007924 <HAL_I2C_Mem_Read+0xc8>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007918: 68fb ldr r3, [r7, #12]
800791a: 2200 movs r2, #0
800791c: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007920: 2301 movs r3, #1
8007922: e0ad b.n 8007a80 <HAL_I2C_Mem_Read+0x224>
}
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8007924: 68fb ldr r3, [r7, #12]
8007926: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007928: b29b uxth r3, r3
800792a: 2bff cmp r3, #255 ; 0xff
800792c: d90e bls.n 800794c <HAL_I2C_Mem_Read+0xf0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
800792e: 68fb ldr r3, [r7, #12]
8007930: 22ff movs r2, #255 ; 0xff
8007932: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
8007934: 68fb ldr r3, [r7, #12]
8007936: 8d1b ldrh r3, [r3, #40] ; 0x28
8007938: b2da uxtb r2, r3
800793a: 8979 ldrh r1, [r7, #10]
800793c: 4b52 ldr r3, [pc, #328] ; (8007a88 <HAL_I2C_Mem_Read+0x22c>)
800793e: 9300 str r3, [sp, #0]
8007940: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8007944: 68f8 ldr r0, [r7, #12]
8007946: f000 fa9f bl 8007e88 <I2C_TransferConfig>
800794a: e00f b.n 800796c <HAL_I2C_Mem_Read+0x110>
}
else
{
hi2c->XferSize = hi2c->XferCount;
800794c: 68fb ldr r3, [r7, #12]
800794e: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007950: b29a uxth r2, r3
8007952: 68fb ldr r3, [r7, #12]
8007954: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
8007956: 68fb ldr r3, [r7, #12]
8007958: 8d1b ldrh r3, [r3, #40] ; 0x28
800795a: b2da uxtb r2, r3
800795c: 8979 ldrh r1, [r7, #10]
800795e: 4b4a ldr r3, [pc, #296] ; (8007a88 <HAL_I2C_Mem_Read+0x22c>)
8007960: 9300 str r3, [sp, #0]
8007962: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8007966: 68f8 ldr r0, [r7, #12]
8007968: f000 fa8e bl 8007e88 <I2C_TransferConfig>
}
do
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
800796c: 697b ldr r3, [r7, #20]
800796e: 9300 str r3, [sp, #0]
8007970: 6abb ldr r3, [r7, #40] ; 0x28
8007972: 2200 movs r2, #0
8007974: 2104 movs r1, #4
8007976: 68f8 ldr r0, [r7, #12]
8007978: f000 f964 bl 8007c44 <I2C_WaitOnFlagUntilTimeout>
800797c: 4603 mov r3, r0
800797e: 2b00 cmp r3, #0
8007980: d001 beq.n 8007986 <HAL_I2C_Mem_Read+0x12a>
{
return HAL_ERROR;
8007982: 2301 movs r3, #1
8007984: e07c b.n 8007a80 <HAL_I2C_Mem_Read+0x224>
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
8007986: 68fb ldr r3, [r7, #12]
8007988: 681b ldr r3, [r3, #0]
800798a: 6a5a ldr r2, [r3, #36] ; 0x24
800798c: 68fb ldr r3, [r7, #12]
800798e: 6a5b ldr r3, [r3, #36] ; 0x24
8007990: b2d2 uxtb r2, r2
8007992: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8007994: 68fb ldr r3, [r7, #12]
8007996: 6a5b ldr r3, [r3, #36] ; 0x24
8007998: 1c5a adds r2, r3, #1
800799a: 68fb ldr r3, [r7, #12]
800799c: 625a str r2, [r3, #36] ; 0x24
hi2c->XferSize--;
800799e: 68fb ldr r3, [r7, #12]
80079a0: 8d1b ldrh r3, [r3, #40] ; 0x28
80079a2: 3b01 subs r3, #1
80079a4: b29a uxth r2, r3
80079a6: 68fb ldr r3, [r7, #12]
80079a8: 851a strh r2, [r3, #40] ; 0x28
hi2c->XferCount--;
80079aa: 68fb ldr r3, [r7, #12]
80079ac: 8d5b ldrh r3, [r3, #42] ; 0x2a
80079ae: b29b uxth r3, r3
80079b0: 3b01 subs r3, #1
80079b2: b29a uxth r2, r3
80079b4: 68fb ldr r3, [r7, #12]
80079b6: 855a strh r2, [r3, #42] ; 0x2a
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
80079b8: 68fb ldr r3, [r7, #12]
80079ba: 8d5b ldrh r3, [r3, #42] ; 0x2a
80079bc: b29b uxth r3, r3
80079be: 2b00 cmp r3, #0
80079c0: d034 beq.n 8007a2c <HAL_I2C_Mem_Read+0x1d0>
80079c2: 68fb ldr r3, [r7, #12]
80079c4: 8d1b ldrh r3, [r3, #40] ; 0x28
80079c6: 2b00 cmp r3, #0
80079c8: d130 bne.n 8007a2c <HAL_I2C_Mem_Read+0x1d0>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
80079ca: 697b ldr r3, [r7, #20]
80079cc: 9300 str r3, [sp, #0]
80079ce: 6abb ldr r3, [r7, #40] ; 0x28
80079d0: 2200 movs r2, #0
80079d2: 2180 movs r1, #128 ; 0x80
80079d4: 68f8 ldr r0, [r7, #12]
80079d6: f000 f935 bl 8007c44 <I2C_WaitOnFlagUntilTimeout>
80079da: 4603 mov r3, r0
80079dc: 2b00 cmp r3, #0
80079de: d001 beq.n 80079e4 <HAL_I2C_Mem_Read+0x188>
{
return HAL_ERROR;
80079e0: 2301 movs r3, #1
80079e2: e04d b.n 8007a80 <HAL_I2C_Mem_Read+0x224>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80079e4: 68fb ldr r3, [r7, #12]
80079e6: 8d5b ldrh r3, [r3, #42] ; 0x2a
80079e8: b29b uxth r3, r3
80079ea: 2bff cmp r3, #255 ; 0xff
80079ec: d90e bls.n 8007a0c <HAL_I2C_Mem_Read+0x1b0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
80079ee: 68fb ldr r3, [r7, #12]
80079f0: 22ff movs r2, #255 ; 0xff
80079f2: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
80079f4: 68fb ldr r3, [r7, #12]
80079f6: 8d1b ldrh r3, [r3, #40] ; 0x28
80079f8: b2da uxtb r2, r3
80079fa: 8979 ldrh r1, [r7, #10]
80079fc: 2300 movs r3, #0
80079fe: 9300 str r3, [sp, #0]
8007a00: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8007a04: 68f8 ldr r0, [r7, #12]
8007a06: f000 fa3f bl 8007e88 <I2C_TransferConfig>
8007a0a: e00f b.n 8007a2c <HAL_I2C_Mem_Read+0x1d0>
}
else
{
hi2c->XferSize = hi2c->XferCount;
8007a0c: 68fb ldr r3, [r7, #12]
8007a0e: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007a10: b29a uxth r2, r3
8007a12: 68fb ldr r3, [r7, #12]
8007a14: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
8007a16: 68fb ldr r3, [r7, #12]
8007a18: 8d1b ldrh r3, [r3, #40] ; 0x28
8007a1a: b2da uxtb r2, r3
8007a1c: 8979 ldrh r1, [r7, #10]
8007a1e: 2300 movs r3, #0
8007a20: 9300 str r3, [sp, #0]
8007a22: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8007a26: 68f8 ldr r0, [r7, #12]
8007a28: f000 fa2e bl 8007e88 <I2C_TransferConfig>
}
}
} while (hi2c->XferCount > 0U);
8007a2c: 68fb ldr r3, [r7, #12]
8007a2e: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007a30: b29b uxth r3, r3
8007a32: 2b00 cmp r3, #0
8007a34: d19a bne.n 800796c <HAL_I2C_Mem_Read+0x110>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8007a36: 697a ldr r2, [r7, #20]
8007a38: 6ab9 ldr r1, [r7, #40] ; 0x28
8007a3a: 68f8 ldr r0, [r7, #12]
8007a3c: f000 f982 bl 8007d44 <I2C_WaitOnSTOPFlagUntilTimeout>
8007a40: 4603 mov r3, r0
8007a42: 2b00 cmp r3, #0
8007a44: d001 beq.n 8007a4a <HAL_I2C_Mem_Read+0x1ee>
{
return HAL_ERROR;
8007a46: 2301 movs r3, #1
8007a48: e01a b.n 8007a80 <HAL_I2C_Mem_Read+0x224>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8007a4a: 68fb ldr r3, [r7, #12]
8007a4c: 681b ldr r3, [r3, #0]
8007a4e: 2220 movs r2, #32
8007a50: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8007a52: 68fb ldr r3, [r7, #12]
8007a54: 681b ldr r3, [r3, #0]
8007a56: 6859 ldr r1, [r3, #4]
8007a58: 68fb ldr r3, [r7, #12]
8007a5a: 681a ldr r2, [r3, #0]
8007a5c: 4b0b ldr r3, [pc, #44] ; (8007a8c <HAL_I2C_Mem_Read+0x230>)
8007a5e: 400b ands r3, r1
8007a60: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
8007a62: 68fb ldr r3, [r7, #12]
8007a64: 2220 movs r2, #32
8007a66: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007a6a: 68fb ldr r3, [r7, #12]
8007a6c: 2200 movs r2, #0
8007a6e: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007a72: 68fb ldr r3, [r7, #12]
8007a74: 2200 movs r2, #0
8007a76: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8007a7a: 2300 movs r3, #0
8007a7c: e000 b.n 8007a80 <HAL_I2C_Mem_Read+0x224>
}
else
{
return HAL_BUSY;
8007a7e: 2302 movs r3, #2
}
}
8007a80: 4618 mov r0, r3
8007a82: 3718 adds r7, #24
8007a84: 46bd mov sp, r7
8007a86: bd80 pop {r7, pc}
8007a88: 80002400 .word 0x80002400
8007a8c: fe00e800 .word 0xfe00e800
08007a90 <HAL_I2C_GetState>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL state
*/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
{
8007a90: b480 push {r7}
8007a92: b083 sub sp, #12
8007a94: af00 add r7, sp, #0
8007a96: 6078 str r0, [r7, #4]
/* Return I2C handle state */
return hi2c->State;
8007a98: 687b ldr r3, [r7, #4]
8007a9a: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8007a9e: b2db uxtb r3, r3
}
8007aa0: 4618 mov r0, r3
8007aa2: 370c adds r7, #12
8007aa4: 46bd mov sp, r7
8007aa6: f85d 7b04 ldr.w r7, [sp], #4
8007aaa: 4770 bx lr
08007aac <I2C_RequestMemoryWrite>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
8007aac: b580 push {r7, lr}
8007aae: b086 sub sp, #24
8007ab0: af02 add r7, sp, #8
8007ab2: 60f8 str r0, [r7, #12]
8007ab4: 4608 mov r0, r1
8007ab6: 4611 mov r1, r2
8007ab8: 461a mov r2, r3
8007aba: 4603 mov r3, r0
8007abc: 817b strh r3, [r7, #10]
8007abe: 460b mov r3, r1
8007ac0: 813b strh r3, [r7, #8]
8007ac2: 4613 mov r3, r2
8007ac4: 80fb strh r3, [r7, #6]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
8007ac6: 88fb ldrh r3, [r7, #6]
8007ac8: b2da uxtb r2, r3
8007aca: 8979 ldrh r1, [r7, #10]
8007acc: 4b20 ldr r3, [pc, #128] ; (8007b50 <I2C_RequestMemoryWrite+0xa4>)
8007ace: 9300 str r3, [sp, #0]
8007ad0: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8007ad4: 68f8 ldr r0, [r7, #12]
8007ad6: f000 f9d7 bl 8007e88 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8007ada: 69fa ldr r2, [r7, #28]
8007adc: 69b9 ldr r1, [r7, #24]
8007ade: 68f8 ldr r0, [r7, #12]
8007ae0: f000 f8f0 bl 8007cc4 <I2C_WaitOnTXISFlagUntilTimeout>
8007ae4: 4603 mov r3, r0
8007ae6: 2b00 cmp r3, #0
8007ae8: d001 beq.n 8007aee <I2C_RequestMemoryWrite+0x42>
{
return HAL_ERROR;
8007aea: 2301 movs r3, #1
8007aec: e02c b.n 8007b48 <I2C_RequestMemoryWrite+0x9c>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
8007aee: 88fb ldrh r3, [r7, #6]
8007af0: 2b01 cmp r3, #1
8007af2: d105 bne.n 8007b00 <I2C_RequestMemoryWrite+0x54>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8007af4: 893b ldrh r3, [r7, #8]
8007af6: b2da uxtb r2, r3
8007af8: 68fb ldr r3, [r7, #12]
8007afa: 681b ldr r3, [r3, #0]
8007afc: 629a str r2, [r3, #40] ; 0x28
8007afe: e015 b.n 8007b2c <I2C_RequestMemoryWrite+0x80>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
8007b00: 893b ldrh r3, [r7, #8]
8007b02: 0a1b lsrs r3, r3, #8
8007b04: b29b uxth r3, r3
8007b06: b2da uxtb r2, r3
8007b08: 68fb ldr r3, [r7, #12]
8007b0a: 681b ldr r3, [r3, #0]
8007b0c: 629a str r2, [r3, #40] ; 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8007b0e: 69fa ldr r2, [r7, #28]
8007b10: 69b9 ldr r1, [r7, #24]
8007b12: 68f8 ldr r0, [r7, #12]
8007b14: f000 f8d6 bl 8007cc4 <I2C_WaitOnTXISFlagUntilTimeout>
8007b18: 4603 mov r3, r0
8007b1a: 2b00 cmp r3, #0
8007b1c: d001 beq.n 8007b22 <I2C_RequestMemoryWrite+0x76>
{
return HAL_ERROR;
8007b1e: 2301 movs r3, #1
8007b20: e012 b.n 8007b48 <I2C_RequestMemoryWrite+0x9c>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8007b22: 893b ldrh r3, [r7, #8]
8007b24: b2da uxtb r2, r3
8007b26: 68fb ldr r3, [r7, #12]
8007b28: 681b ldr r3, [r3, #0]
8007b2a: 629a str r2, [r3, #40] ; 0x28
}
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
8007b2c: 69fb ldr r3, [r7, #28]
8007b2e: 9300 str r3, [sp, #0]
8007b30: 69bb ldr r3, [r7, #24]
8007b32: 2200 movs r2, #0
8007b34: 2180 movs r1, #128 ; 0x80
8007b36: 68f8 ldr r0, [r7, #12]
8007b38: f000 f884 bl 8007c44 <I2C_WaitOnFlagUntilTimeout>
8007b3c: 4603 mov r3, r0
8007b3e: 2b00 cmp r3, #0
8007b40: d001 beq.n 8007b46 <I2C_RequestMemoryWrite+0x9a>
{
return HAL_ERROR;
8007b42: 2301 movs r3, #1
8007b44: e000 b.n 8007b48 <I2C_RequestMemoryWrite+0x9c>
}
return HAL_OK;
8007b46: 2300 movs r3, #0
}
8007b48: 4618 mov r0, r3
8007b4a: 3710 adds r7, #16
8007b4c: 46bd mov sp, r7
8007b4e: bd80 pop {r7, pc}
8007b50: 80002000 .word 0x80002000
08007b54 <I2C_RequestMemoryRead>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
8007b54: b580 push {r7, lr}
8007b56: b086 sub sp, #24
8007b58: af02 add r7, sp, #8
8007b5a: 60f8 str r0, [r7, #12]
8007b5c: 4608 mov r0, r1
8007b5e: 4611 mov r1, r2
8007b60: 461a mov r2, r3
8007b62: 4603 mov r3, r0
8007b64: 817b strh r3, [r7, #10]
8007b66: 460b mov r3, r1
8007b68: 813b strh r3, [r7, #8]
8007b6a: 4613 mov r3, r2
8007b6c: 80fb strh r3, [r7, #6]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
8007b6e: 88fb ldrh r3, [r7, #6]
8007b70: b2da uxtb r2, r3
8007b72: 8979 ldrh r1, [r7, #10]
8007b74: 4b20 ldr r3, [pc, #128] ; (8007bf8 <I2C_RequestMemoryRead+0xa4>)
8007b76: 9300 str r3, [sp, #0]
8007b78: 2300 movs r3, #0
8007b7a: 68f8 ldr r0, [r7, #12]
8007b7c: f000 f984 bl 8007e88 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8007b80: 69fa ldr r2, [r7, #28]
8007b82: 69b9 ldr r1, [r7, #24]
8007b84: 68f8 ldr r0, [r7, #12]
8007b86: f000 f89d bl 8007cc4 <I2C_WaitOnTXISFlagUntilTimeout>
8007b8a: 4603 mov r3, r0
8007b8c: 2b00 cmp r3, #0
8007b8e: d001 beq.n 8007b94 <I2C_RequestMemoryRead+0x40>
{
return HAL_ERROR;
8007b90: 2301 movs r3, #1
8007b92: e02c b.n 8007bee <I2C_RequestMemoryRead+0x9a>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
8007b94: 88fb ldrh r3, [r7, #6]
8007b96: 2b01 cmp r3, #1
8007b98: d105 bne.n 8007ba6 <I2C_RequestMemoryRead+0x52>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8007b9a: 893b ldrh r3, [r7, #8]
8007b9c: b2da uxtb r2, r3
8007b9e: 68fb ldr r3, [r7, #12]
8007ba0: 681b ldr r3, [r3, #0]
8007ba2: 629a str r2, [r3, #40] ; 0x28
8007ba4: e015 b.n 8007bd2 <I2C_RequestMemoryRead+0x7e>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
8007ba6: 893b ldrh r3, [r7, #8]
8007ba8: 0a1b lsrs r3, r3, #8
8007baa: b29b uxth r3, r3
8007bac: b2da uxtb r2, r3
8007bae: 68fb ldr r3, [r7, #12]
8007bb0: 681b ldr r3, [r3, #0]
8007bb2: 629a str r2, [r3, #40] ; 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8007bb4: 69fa ldr r2, [r7, #28]
8007bb6: 69b9 ldr r1, [r7, #24]
8007bb8: 68f8 ldr r0, [r7, #12]
8007bba: f000 f883 bl 8007cc4 <I2C_WaitOnTXISFlagUntilTimeout>
8007bbe: 4603 mov r3, r0
8007bc0: 2b00 cmp r3, #0
8007bc2: d001 beq.n 8007bc8 <I2C_RequestMemoryRead+0x74>
{
return HAL_ERROR;
8007bc4: 2301 movs r3, #1
8007bc6: e012 b.n 8007bee <I2C_RequestMemoryRead+0x9a>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8007bc8: 893b ldrh r3, [r7, #8]
8007bca: b2da uxtb r2, r3
8007bcc: 68fb ldr r3, [r7, #12]
8007bce: 681b ldr r3, [r3, #0]
8007bd0: 629a str r2, [r3, #40] ; 0x28
}
/* Wait until TC flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
8007bd2: 69fb ldr r3, [r7, #28]
8007bd4: 9300 str r3, [sp, #0]
8007bd6: 69bb ldr r3, [r7, #24]
8007bd8: 2200 movs r2, #0
8007bda: 2140 movs r1, #64 ; 0x40
8007bdc: 68f8 ldr r0, [r7, #12]
8007bde: f000 f831 bl 8007c44 <I2C_WaitOnFlagUntilTimeout>
8007be2: 4603 mov r3, r0
8007be4: 2b00 cmp r3, #0
8007be6: d001 beq.n 8007bec <I2C_RequestMemoryRead+0x98>
{
return HAL_ERROR;
8007be8: 2301 movs r3, #1
8007bea: e000 b.n 8007bee <I2C_RequestMemoryRead+0x9a>
}
return HAL_OK;
8007bec: 2300 movs r3, #0
}
8007bee: 4618 mov r0, r3
8007bf0: 3710 adds r7, #16
8007bf2: 46bd mov sp, r7
8007bf4: bd80 pop {r7, pc}
8007bf6: bf00 nop
8007bf8: 80002000 .word 0x80002000
08007bfc <I2C_Flush_TXDR>:
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
8007bfc: b480 push {r7}
8007bfe: b083 sub sp, #12
8007c00: af00 add r7, sp, #0
8007c02: 6078 str r0, [r7, #4]
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
8007c04: 687b ldr r3, [r7, #4]
8007c06: 681b ldr r3, [r3, #0]
8007c08: 699b ldr r3, [r3, #24]
8007c0a: f003 0302 and.w r3, r3, #2
8007c0e: 2b02 cmp r3, #2
8007c10: d103 bne.n 8007c1a <I2C_Flush_TXDR+0x1e>
{
hi2c->Instance->TXDR = 0x00U;
8007c12: 687b ldr r3, [r7, #4]
8007c14: 681b ldr r3, [r3, #0]
8007c16: 2200 movs r2, #0
8007c18: 629a str r2, [r3, #40] ; 0x28
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8007c1a: 687b ldr r3, [r7, #4]
8007c1c: 681b ldr r3, [r3, #0]
8007c1e: 699b ldr r3, [r3, #24]
8007c20: f003 0301 and.w r3, r3, #1
8007c24: 2b01 cmp r3, #1
8007c26: d007 beq.n 8007c38 <I2C_Flush_TXDR+0x3c>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
8007c28: 687b ldr r3, [r7, #4]
8007c2a: 681b ldr r3, [r3, #0]
8007c2c: 699a ldr r2, [r3, #24]
8007c2e: 687b ldr r3, [r7, #4]
8007c30: 681b ldr r3, [r3, #0]
8007c32: f042 0201 orr.w r2, r2, #1
8007c36: 619a str r2, [r3, #24]
}
}
8007c38: bf00 nop
8007c3a: 370c adds r7, #12
8007c3c: 46bd mov sp, r7
8007c3e: f85d 7b04 ldr.w r7, [sp], #4
8007c42: 4770 bx lr
08007c44 <I2C_WaitOnFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart)
{
8007c44: b580 push {r7, lr}
8007c46: b084 sub sp, #16
8007c48: af00 add r7, sp, #0
8007c4a: 60f8 str r0, [r7, #12]
8007c4c: 60b9 str r1, [r7, #8]
8007c4e: 603b str r3, [r7, #0]
8007c50: 4613 mov r3, r2
8007c52: 71fb strb r3, [r7, #7]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8007c54: e022 b.n 8007c9c <I2C_WaitOnFlagUntilTimeout+0x58>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8007c56: 683b ldr r3, [r7, #0]
8007c58: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8007c5c: d01e beq.n 8007c9c <I2C_WaitOnFlagUntilTimeout+0x58>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007c5e: f7fc fdb7 bl 80047d0 <HAL_GetTick>
8007c62: 4602 mov r2, r0
8007c64: 69bb ldr r3, [r7, #24]
8007c66: 1ad3 subs r3, r2, r3
8007c68: 683a ldr r2, [r7, #0]
8007c6a: 429a cmp r2, r3
8007c6c: d302 bcc.n 8007c74 <I2C_WaitOnFlagUntilTimeout+0x30>
8007c6e: 683b ldr r3, [r7, #0]
8007c70: 2b00 cmp r3, #0
8007c72: d113 bne.n 8007c9c <I2C_WaitOnFlagUntilTimeout+0x58>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8007c74: 68fb ldr r3, [r7, #12]
8007c76: 6c5b ldr r3, [r3, #68] ; 0x44
8007c78: f043 0220 orr.w r2, r3, #32
8007c7c: 68fb ldr r3, [r7, #12]
8007c7e: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007c80: 68fb ldr r3, [r7, #12]
8007c82: 2220 movs r2, #32
8007c84: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007c88: 68fb ldr r3, [r7, #12]
8007c8a: 2200 movs r2, #0
8007c8c: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007c90: 68fb ldr r3, [r7, #12]
8007c92: 2200 movs r2, #0
8007c94: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007c98: 2301 movs r3, #1
8007c9a: e00f b.n 8007cbc <I2C_WaitOnFlagUntilTimeout+0x78>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8007c9c: 68fb ldr r3, [r7, #12]
8007c9e: 681b ldr r3, [r3, #0]
8007ca0: 699a ldr r2, [r3, #24]
8007ca2: 68bb ldr r3, [r7, #8]
8007ca4: 4013 ands r3, r2
8007ca6: 68ba ldr r2, [r7, #8]
8007ca8: 429a cmp r2, r3
8007caa: bf0c ite eq
8007cac: 2301 moveq r3, #1
8007cae: 2300 movne r3, #0
8007cb0: b2db uxtb r3, r3
8007cb2: 461a mov r2, r3
8007cb4: 79fb ldrb r3, [r7, #7]
8007cb6: 429a cmp r2, r3
8007cb8: d0cd beq.n 8007c56 <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
8007cba: 2300 movs r3, #0
}
8007cbc: 4618 mov r0, r3
8007cbe: 3710 adds r7, #16
8007cc0: 46bd mov sp, r7
8007cc2: bd80 pop {r7, pc}
08007cc4 <I2C_WaitOnTXISFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8007cc4: b580 push {r7, lr}
8007cc6: b084 sub sp, #16
8007cc8: af00 add r7, sp, #0
8007cca: 60f8 str r0, [r7, #12]
8007ccc: 60b9 str r1, [r7, #8]
8007cce: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
8007cd0: e02c b.n 8007d2c <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
8007cd2: 687a ldr r2, [r7, #4]
8007cd4: 68b9 ldr r1, [r7, #8]
8007cd6: 68f8 ldr r0, [r7, #12]
8007cd8: f000 f870 bl 8007dbc <I2C_IsAcknowledgeFailed>
8007cdc: 4603 mov r3, r0
8007cde: 2b00 cmp r3, #0
8007ce0: d001 beq.n 8007ce6 <I2C_WaitOnTXISFlagUntilTimeout+0x22>
{
return HAL_ERROR;
8007ce2: 2301 movs r3, #1
8007ce4: e02a b.n 8007d3c <I2C_WaitOnTXISFlagUntilTimeout+0x78>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8007ce6: 68bb ldr r3, [r7, #8]
8007ce8: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8007cec: d01e beq.n 8007d2c <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007cee: f7fc fd6f bl 80047d0 <HAL_GetTick>
8007cf2: 4602 mov r2, r0
8007cf4: 687b ldr r3, [r7, #4]
8007cf6: 1ad3 subs r3, r2, r3
8007cf8: 68ba ldr r2, [r7, #8]
8007cfa: 429a cmp r2, r3
8007cfc: d302 bcc.n 8007d04 <I2C_WaitOnTXISFlagUntilTimeout+0x40>
8007cfe: 68bb ldr r3, [r7, #8]
8007d00: 2b00 cmp r3, #0
8007d02: d113 bne.n 8007d2c <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8007d04: 68fb ldr r3, [r7, #12]
8007d06: 6c5b ldr r3, [r3, #68] ; 0x44
8007d08: f043 0220 orr.w r2, r3, #32
8007d0c: 68fb ldr r3, [r7, #12]
8007d0e: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007d10: 68fb ldr r3, [r7, #12]
8007d12: 2220 movs r2, #32
8007d14: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007d18: 68fb ldr r3, [r7, #12]
8007d1a: 2200 movs r2, #0
8007d1c: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007d20: 68fb ldr r3, [r7, #12]
8007d22: 2200 movs r2, #0
8007d24: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007d28: 2301 movs r3, #1
8007d2a: e007 b.n 8007d3c <I2C_WaitOnTXISFlagUntilTimeout+0x78>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
8007d2c: 68fb ldr r3, [r7, #12]
8007d2e: 681b ldr r3, [r3, #0]
8007d30: 699b ldr r3, [r3, #24]
8007d32: f003 0302 and.w r3, r3, #2
8007d36: 2b02 cmp r3, #2
8007d38: d1cb bne.n 8007cd2 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
8007d3a: 2300 movs r3, #0
}
8007d3c: 4618 mov r0, r3
8007d3e: 3710 adds r7, #16
8007d40: 46bd mov sp, r7
8007d42: bd80 pop {r7, pc}
08007d44 <I2C_WaitOnSTOPFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8007d44: b580 push {r7, lr}
8007d46: b084 sub sp, #16
8007d48: af00 add r7, sp, #0
8007d4a: 60f8 str r0, [r7, #12]
8007d4c: 60b9 str r1, [r7, #8]
8007d4e: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8007d50: e028 b.n 8007da4 <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
8007d52: 687a ldr r2, [r7, #4]
8007d54: 68b9 ldr r1, [r7, #8]
8007d56: 68f8 ldr r0, [r7, #12]
8007d58: f000 f830 bl 8007dbc <I2C_IsAcknowledgeFailed>
8007d5c: 4603 mov r3, r0
8007d5e: 2b00 cmp r3, #0
8007d60: d001 beq.n 8007d66 <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
{
return HAL_ERROR;
8007d62: 2301 movs r3, #1
8007d64: e026 b.n 8007db4 <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007d66: f7fc fd33 bl 80047d0 <HAL_GetTick>
8007d6a: 4602 mov r2, r0
8007d6c: 687b ldr r3, [r7, #4]
8007d6e: 1ad3 subs r3, r2, r3
8007d70: 68ba ldr r2, [r7, #8]
8007d72: 429a cmp r2, r3
8007d74: d302 bcc.n 8007d7c <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
8007d76: 68bb ldr r3, [r7, #8]
8007d78: 2b00 cmp r3, #0
8007d7a: d113 bne.n 8007da4 <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8007d7c: 68fb ldr r3, [r7, #12]
8007d7e: 6c5b ldr r3, [r3, #68] ; 0x44
8007d80: f043 0220 orr.w r2, r3, #32
8007d84: 68fb ldr r3, [r7, #12]
8007d86: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007d88: 68fb ldr r3, [r7, #12]
8007d8a: 2220 movs r2, #32
8007d8c: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007d90: 68fb ldr r3, [r7, #12]
8007d92: 2200 movs r2, #0
8007d94: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007d98: 68fb ldr r3, [r7, #12]
8007d9a: 2200 movs r2, #0
8007d9c: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007da0: 2301 movs r3, #1
8007da2: e007 b.n 8007db4 <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8007da4: 68fb ldr r3, [r7, #12]
8007da6: 681b ldr r3, [r3, #0]
8007da8: 699b ldr r3, [r3, #24]
8007daa: f003 0320 and.w r3, r3, #32
8007dae: 2b20 cmp r3, #32
8007db0: d1cf bne.n 8007d52 <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
}
}
return HAL_OK;
8007db2: 2300 movs r3, #0
}
8007db4: 4618 mov r0, r3
8007db6: 3710 adds r7, #16
8007db8: 46bd mov sp, r7
8007dba: bd80 pop {r7, pc}
08007dbc <I2C_IsAcknowledgeFailed>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8007dbc: b580 push {r7, lr}
8007dbe: b084 sub sp, #16
8007dc0: af00 add r7, sp, #0
8007dc2: 60f8 str r0, [r7, #12]
8007dc4: 60b9 str r1, [r7, #8]
8007dc6: 607a str r2, [r7, #4]
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
8007dc8: 68fb ldr r3, [r7, #12]
8007dca: 681b ldr r3, [r3, #0]
8007dcc: 699b ldr r3, [r3, #24]
8007dce: f003 0310 and.w r3, r3, #16
8007dd2: 2b10 cmp r3, #16
8007dd4: d151 bne.n 8007e7a <I2C_IsAcknowledgeFailed+0xbe>
{
/* Wait until STOP Flag is reset */
/* AutoEnd should be initiate after AF */
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8007dd6: e022 b.n 8007e1e <I2C_IsAcknowledgeFailed+0x62>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8007dd8: 68bb ldr r3, [r7, #8]
8007dda: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8007dde: d01e beq.n 8007e1e <I2C_IsAcknowledgeFailed+0x62>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007de0: f7fc fcf6 bl 80047d0 <HAL_GetTick>
8007de4: 4602 mov r2, r0
8007de6: 687b ldr r3, [r7, #4]
8007de8: 1ad3 subs r3, r2, r3
8007dea: 68ba ldr r2, [r7, #8]
8007dec: 429a cmp r2, r3
8007dee: d302 bcc.n 8007df6 <I2C_IsAcknowledgeFailed+0x3a>
8007df0: 68bb ldr r3, [r7, #8]
8007df2: 2b00 cmp r3, #0
8007df4: d113 bne.n 8007e1e <I2C_IsAcknowledgeFailed+0x62>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8007df6: 68fb ldr r3, [r7, #12]
8007df8: 6c5b ldr r3, [r3, #68] ; 0x44
8007dfa: f043 0220 orr.w r2, r3, #32
8007dfe: 68fb ldr r3, [r7, #12]
8007e00: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007e02: 68fb ldr r3, [r7, #12]
8007e04: 2220 movs r2, #32
8007e06: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007e0a: 68fb ldr r3, [r7, #12]
8007e0c: 2200 movs r2, #0
8007e0e: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007e12: 68fb ldr r3, [r7, #12]
8007e14: 2200 movs r2, #0
8007e16: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007e1a: 2301 movs r3, #1
8007e1c: e02e b.n 8007e7c <I2C_IsAcknowledgeFailed+0xc0>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8007e1e: 68fb ldr r3, [r7, #12]
8007e20: 681b ldr r3, [r3, #0]
8007e22: 699b ldr r3, [r3, #24]
8007e24: f003 0320 and.w r3, r3, #32
8007e28: 2b20 cmp r3, #32
8007e2a: d1d5 bne.n 8007dd8 <I2C_IsAcknowledgeFailed+0x1c>
}
}
}
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8007e2c: 68fb ldr r3, [r7, #12]
8007e2e: 681b ldr r3, [r3, #0]
8007e30: 2210 movs r2, #16
8007e32: 61da str r2, [r3, #28]
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8007e34: 68fb ldr r3, [r7, #12]
8007e36: 681b ldr r3, [r3, #0]
8007e38: 2220 movs r2, #32
8007e3a: 61da str r2, [r3, #28]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8007e3c: 68f8 ldr r0, [r7, #12]
8007e3e: f7ff fedd bl 8007bfc <I2C_Flush_TXDR>
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8007e42: 68fb ldr r3, [r7, #12]
8007e44: 681b ldr r3, [r3, #0]
8007e46: 6859 ldr r1, [r3, #4]
8007e48: 68fb ldr r3, [r7, #12]
8007e4a: 681a ldr r2, [r3, #0]
8007e4c: 4b0d ldr r3, [pc, #52] ; (8007e84 <I2C_IsAcknowledgeFailed+0xc8>)
8007e4e: 400b ands r3, r1
8007e50: 6053 str r3, [r2, #4]
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8007e52: 68fb ldr r3, [r7, #12]
8007e54: 6c5b ldr r3, [r3, #68] ; 0x44
8007e56: f043 0204 orr.w r2, r3, #4
8007e5a: 68fb ldr r3, [r7, #12]
8007e5c: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007e5e: 68fb ldr r3, [r7, #12]
8007e60: 2220 movs r2, #32
8007e62: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007e66: 68fb ldr r3, [r7, #12]
8007e68: 2200 movs r2, #0
8007e6a: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007e6e: 68fb ldr r3, [r7, #12]
8007e70: 2200 movs r2, #0
8007e72: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007e76: 2301 movs r3, #1
8007e78: e000 b.n 8007e7c <I2C_IsAcknowledgeFailed+0xc0>
}
return HAL_OK;
8007e7a: 2300 movs r3, #0
}
8007e7c: 4618 mov r0, r3
8007e7e: 3710 adds r7, #16
8007e80: 46bd mov sp, r7
8007e82: bd80 pop {r7, pc}
8007e84: fe00e800 .word 0xfe00e800
08007e88 <I2C_TransferConfig>:
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request)
{
8007e88: b480 push {r7}
8007e8a: b085 sub sp, #20
8007e8c: af00 add r7, sp, #0
8007e8e: 60f8 str r0, [r7, #12]
8007e90: 607b str r3, [r7, #4]
8007e92: 460b mov r3, r1
8007e94: 817b strh r3, [r7, #10]
8007e96: 4613 mov r3, r2
8007e98: 727b strb r3, [r7, #9]
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2,
8007e9a: 68fb ldr r3, [r7, #12]
8007e9c: 681b ldr r3, [r3, #0]
8007e9e: 685a ldr r2, [r3, #4]
8007ea0: 69bb ldr r3, [r7, #24]
8007ea2: 0d5b lsrs r3, r3, #21
8007ea4: f403 6180 and.w r1, r3, #1024 ; 0x400
8007ea8: 4b0d ldr r3, [pc, #52] ; (8007ee0 <I2C_TransferConfig+0x58>)
8007eaa: 430b orrs r3, r1
8007eac: 43db mvns r3, r3
8007eae: ea02 0103 and.w r1, r2, r3
8007eb2: 897b ldrh r3, [r7, #10]
8007eb4: f3c3 0209 ubfx r2, r3, #0, #10
8007eb8: 7a7b ldrb r3, [r7, #9]
8007eba: 041b lsls r3, r3, #16
8007ebc: f403 037f and.w r3, r3, #16711680 ; 0xff0000
8007ec0: 431a orrs r2, r3
8007ec2: 687b ldr r3, [r7, #4]
8007ec4: 431a orrs r2, r3
8007ec6: 69bb ldr r3, [r7, #24]
8007ec8: 431a orrs r2, r3
8007eca: 68fb ldr r3, [r7, #12]
8007ecc: 681b ldr r3, [r3, #0]
8007ece: 430a orrs r2, r1
8007ed0: 605a str r2, [r3, #4]
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) |
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
8007ed2: bf00 nop
8007ed4: 3714 adds r7, #20
8007ed6: 46bd mov sp, r7
8007ed8: f85d 7b04 ldr.w r7, [sp], #4
8007edc: 4770 bx lr
8007ede: bf00 nop
8007ee0: 03ff63ff .word 0x03ff63ff
08007ee4 <HAL_LTDC_Init>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
{
8007ee4: b580 push {r7, lr}
8007ee6: b084 sub sp, #16
8007ee8: af00 add r7, sp, #0
8007eea: 6078 str r0, [r7, #4]
uint32_t tmp, tmp1;
/* Check the LTDC peripheral state */
if (hltdc == NULL)
8007eec: 687b ldr r3, [r7, #4]
8007eee: 2b00 cmp r3, #0
8007ef0: d101 bne.n 8007ef6 <HAL_LTDC_Init+0x12>
{
return HAL_ERROR;
8007ef2: 2301 movs r3, #1
8007ef4: e0bf b.n 8008076 <HAL_LTDC_Init+0x192>
}
/* Init the low level hardware */
hltdc->MspInitCallback(hltdc);
}
#else
if (hltdc->State == HAL_LTDC_STATE_RESET)
8007ef6: 687b ldr r3, [r7, #4]
8007ef8: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1
8007efc: b2db uxtb r3, r3
8007efe: 2b00 cmp r3, #0
8007f00: d106 bne.n 8007f10 <HAL_LTDC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hltdc->Lock = HAL_UNLOCKED;
8007f02: 687b ldr r3, [r7, #4]
8007f04: 2200 movs r2, #0
8007f06: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
/* Init the low level hardware */
HAL_LTDC_MspInit(hltdc);
8007f0a: 6878 ldr r0, [r7, #4]
8007f0c: f7fc f852 bl 8003fb4 <HAL_LTDC_MspInit>
}
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
8007f10: 687b ldr r3, [r7, #4]
8007f12: 2202 movs r2, #2
8007f14: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Configure the HS, VS, DE and PC polarity */
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
8007f18: 687b ldr r3, [r7, #4]
8007f1a: 681b ldr r3, [r3, #0]
8007f1c: 699a ldr r2, [r3, #24]
8007f1e: 687b ldr r3, [r7, #4]
8007f20: 681b ldr r3, [r3, #0]
8007f22: f022 4270 bic.w r2, r2, #4026531840 ; 0xf0000000
8007f26: 619a str r2, [r3, #24]
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8007f28: 687b ldr r3, [r7, #4]
8007f2a: 681b ldr r3, [r3, #0]
8007f2c: 6999 ldr r1, [r3, #24]
8007f2e: 687b ldr r3, [r7, #4]
8007f30: 685a ldr r2, [r3, #4]
8007f32: 687b ldr r3, [r7, #4]
8007f34: 689b ldr r3, [r3, #8]
8007f36: 431a orrs r2, r3
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
8007f38: 687b ldr r3, [r7, #4]
8007f3a: 68db ldr r3, [r3, #12]
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8007f3c: 431a orrs r2, r3
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
8007f3e: 687b ldr r3, [r7, #4]
8007f40: 691b ldr r3, [r3, #16]
8007f42: 431a orrs r2, r3
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8007f44: 687b ldr r3, [r7, #4]
8007f46: 681b ldr r3, [r3, #0]
8007f48: 430a orrs r2, r1
8007f4a: 619a str r2, [r3, #24]
/* Set Synchronization size */
hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
8007f4c: 687b ldr r3, [r7, #4]
8007f4e: 681b ldr r3, [r3, #0]
8007f50: 6899 ldr r1, [r3, #8]
8007f52: 687b ldr r3, [r7, #4]
8007f54: 681a ldr r2, [r3, #0]
8007f56: 4b4a ldr r3, [pc, #296] ; (8008080 <HAL_LTDC_Init+0x19c>)
8007f58: 400b ands r3, r1
8007f5a: 6093 str r3, [r2, #8]
tmp = (hltdc->Init.HorizontalSync << 16U);
8007f5c: 687b ldr r3, [r7, #4]
8007f5e: 695b ldr r3, [r3, #20]
8007f60: 041b lsls r3, r3, #16
8007f62: 60fb str r3, [r7, #12]
hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
8007f64: 687b ldr r3, [r7, #4]
8007f66: 681b ldr r3, [r3, #0]
8007f68: 6899 ldr r1, [r3, #8]
8007f6a: 687b ldr r3, [r7, #4]
8007f6c: 699a ldr r2, [r3, #24]
8007f6e: 68fb ldr r3, [r7, #12]
8007f70: 431a orrs r2, r3
8007f72: 687b ldr r3, [r7, #4]
8007f74: 681b ldr r3, [r3, #0]
8007f76: 430a orrs r2, r1
8007f78: 609a str r2, [r3, #8]
/* Set Accumulated Back porch */
hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
8007f7a: 687b ldr r3, [r7, #4]
8007f7c: 681b ldr r3, [r3, #0]
8007f7e: 68d9 ldr r1, [r3, #12]
8007f80: 687b ldr r3, [r7, #4]
8007f82: 681a ldr r2, [r3, #0]
8007f84: 4b3e ldr r3, [pc, #248] ; (8008080 <HAL_LTDC_Init+0x19c>)
8007f86: 400b ands r3, r1
8007f88: 60d3 str r3, [r2, #12]
tmp = (hltdc->Init.AccumulatedHBP << 16U);
8007f8a: 687b ldr r3, [r7, #4]
8007f8c: 69db ldr r3, [r3, #28]
8007f8e: 041b lsls r3, r3, #16
8007f90: 60fb str r3, [r7, #12]
hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
8007f92: 687b ldr r3, [r7, #4]
8007f94: 681b ldr r3, [r3, #0]
8007f96: 68d9 ldr r1, [r3, #12]
8007f98: 687b ldr r3, [r7, #4]
8007f9a: 6a1a ldr r2, [r3, #32]
8007f9c: 68fb ldr r3, [r7, #12]
8007f9e: 431a orrs r2, r3
8007fa0: 687b ldr r3, [r7, #4]
8007fa2: 681b ldr r3, [r3, #0]
8007fa4: 430a orrs r2, r1
8007fa6: 60da str r2, [r3, #12]
/* Set Accumulated Active Width */
hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
8007fa8: 687b ldr r3, [r7, #4]
8007faa: 681b ldr r3, [r3, #0]
8007fac: 6919 ldr r1, [r3, #16]
8007fae: 687b ldr r3, [r7, #4]
8007fb0: 681a ldr r2, [r3, #0]
8007fb2: 4b33 ldr r3, [pc, #204] ; (8008080 <HAL_LTDC_Init+0x19c>)
8007fb4: 400b ands r3, r1
8007fb6: 6113 str r3, [r2, #16]
tmp = (hltdc->Init.AccumulatedActiveW << 16U);
8007fb8: 687b ldr r3, [r7, #4]
8007fba: 6a5b ldr r3, [r3, #36] ; 0x24
8007fbc: 041b lsls r3, r3, #16
8007fbe: 60fb str r3, [r7, #12]
hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
8007fc0: 687b ldr r3, [r7, #4]
8007fc2: 681b ldr r3, [r3, #0]
8007fc4: 6919 ldr r1, [r3, #16]
8007fc6: 687b ldr r3, [r7, #4]
8007fc8: 6a9a ldr r2, [r3, #40] ; 0x28
8007fca: 68fb ldr r3, [r7, #12]
8007fcc: 431a orrs r2, r3
8007fce: 687b ldr r3, [r7, #4]
8007fd0: 681b ldr r3, [r3, #0]
8007fd2: 430a orrs r2, r1
8007fd4: 611a str r2, [r3, #16]
/* Set Total Width */
hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
8007fd6: 687b ldr r3, [r7, #4]
8007fd8: 681b ldr r3, [r3, #0]
8007fda: 6959 ldr r1, [r3, #20]
8007fdc: 687b ldr r3, [r7, #4]
8007fde: 681a ldr r2, [r3, #0]
8007fe0: 4b27 ldr r3, [pc, #156] ; (8008080 <HAL_LTDC_Init+0x19c>)
8007fe2: 400b ands r3, r1
8007fe4: 6153 str r3, [r2, #20]
tmp = (hltdc->Init.TotalWidth << 16U);
8007fe6: 687b ldr r3, [r7, #4]
8007fe8: 6adb ldr r3, [r3, #44] ; 0x2c
8007fea: 041b lsls r3, r3, #16
8007fec: 60fb str r3, [r7, #12]
hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
8007fee: 687b ldr r3, [r7, #4]
8007ff0: 681b ldr r3, [r3, #0]
8007ff2: 6959 ldr r1, [r3, #20]
8007ff4: 687b ldr r3, [r7, #4]
8007ff6: 6b1a ldr r2, [r3, #48] ; 0x30
8007ff8: 68fb ldr r3, [r7, #12]
8007ffa: 431a orrs r2, r3
8007ffc: 687b ldr r3, [r7, #4]
8007ffe: 681b ldr r3, [r3, #0]
8008000: 430a orrs r2, r1
8008002: 615a str r2, [r3, #20]
/* Set the background color value */
tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
8008004: 687b ldr r3, [r7, #4]
8008006: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
800800a: 021b lsls r3, r3, #8
800800c: 60fb str r3, [r7, #12]
tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
800800e: 687b ldr r3, [r7, #4]
8008010: f893 3036 ldrb.w r3, [r3, #54] ; 0x36
8008014: 041b lsls r3, r3, #16
8008016: 60bb str r3, [r7, #8]
hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
8008018: 687b ldr r3, [r7, #4]
800801a: 681b ldr r3, [r3, #0]
800801c: 6ada ldr r2, [r3, #44] ; 0x2c
800801e: 687b ldr r3, [r7, #4]
8008020: 681b ldr r3, [r3, #0]
8008022: f002 427f and.w r2, r2, #4278190080 ; 0xff000000
8008026: 62da str r2, [r3, #44] ; 0x2c
hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
8008028: 687b ldr r3, [r7, #4]
800802a: 681b ldr r3, [r3, #0]
800802c: 6ad9 ldr r1, [r3, #44] ; 0x2c
800802e: 68ba ldr r2, [r7, #8]
8008030: 68fb ldr r3, [r7, #12]
8008032: 4313 orrs r3, r2
8008034: 687a ldr r2, [r7, #4]
8008036: f892 2034 ldrb.w r2, [r2, #52] ; 0x34
800803a: 431a orrs r2, r3
800803c: 687b ldr r3, [r7, #4]
800803e: 681b ldr r3, [r3, #0]
8008040: 430a orrs r2, r1
8008042: 62da str r2, [r3, #44] ; 0x2c
/* Enable the Transfer Error and FIFO underrun interrupts */
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
8008044: 687b ldr r3, [r7, #4]
8008046: 681b ldr r3, [r3, #0]
8008048: 6b5a ldr r2, [r3, #52] ; 0x34
800804a: 687b ldr r3, [r7, #4]
800804c: 681b ldr r3, [r3, #0]
800804e: f042 0206 orr.w r2, r2, #6
8008052: 635a str r2, [r3, #52] ; 0x34
/* Enable LTDC by setting LTDCEN bit */
__HAL_LTDC_ENABLE(hltdc);
8008054: 687b ldr r3, [r7, #4]
8008056: 681b ldr r3, [r3, #0]
8008058: 699a ldr r2, [r3, #24]
800805a: 687b ldr r3, [r7, #4]
800805c: 681b ldr r3, [r3, #0]
800805e: f042 0201 orr.w r2, r2, #1
8008062: 619a str r2, [r3, #24]
/* Initialize the error code */
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
8008064: 687b ldr r3, [r7, #4]
8008066: 2200 movs r2, #0
8008068: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
800806c: 687b ldr r3, [r7, #4]
800806e: 2201 movs r2, #1
8008070: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
return HAL_OK;
8008074: 2300 movs r3, #0
}
8008076: 4618 mov r0, r3
8008078: 3710 adds r7, #16
800807a: 46bd mov sp, r7
800807c: bd80 pop {r7, pc}
800807e: bf00 nop
8008080: f000f800 .word 0xf000f800
08008084 <HAL_LTDC_IRQHandler>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
{
8008084: b580 push {r7, lr}
8008086: b084 sub sp, #16
8008088: af00 add r7, sp, #0
800808a: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
800808c: 687b ldr r3, [r7, #4]
800808e: 681b ldr r3, [r3, #0]
8008090: 6b9b ldr r3, [r3, #56] ; 0x38
8008092: 60fb str r3, [r7, #12]
uint32_t itsources = READ_REG(hltdc->Instance->IER);
8008094: 687b ldr r3, [r7, #4]
8008096: 681b ldr r3, [r3, #0]
8008098: 6b5b ldr r3, [r3, #52] ; 0x34
800809a: 60bb str r3, [r7, #8]
/* Transfer Error Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
800809c: 68fb ldr r3, [r7, #12]
800809e: f003 0304 and.w r3, r3, #4
80080a2: 2b00 cmp r3, #0
80080a4: d023 beq.n 80080ee <HAL_LTDC_IRQHandler+0x6a>
80080a6: 68bb ldr r3, [r7, #8]
80080a8: f003 0304 and.w r3, r3, #4
80080ac: 2b00 cmp r3, #0
80080ae: d01e beq.n 80080ee <HAL_LTDC_IRQHandler+0x6a>
{
/* Disable the transfer Error interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
80080b0: 687b ldr r3, [r7, #4]
80080b2: 681b ldr r3, [r3, #0]
80080b4: 6b5a ldr r2, [r3, #52] ; 0x34
80080b6: 687b ldr r3, [r7, #4]
80080b8: 681b ldr r3, [r3, #0]
80080ba: f022 0204 bic.w r2, r2, #4
80080be: 635a str r2, [r3, #52] ; 0x34
/* Clear the transfer error flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
80080c0: 687b ldr r3, [r7, #4]
80080c2: 681b ldr r3, [r3, #0]
80080c4: 2204 movs r2, #4
80080c6: 63da str r2, [r3, #60] ; 0x3c
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
80080c8: 687b ldr r3, [r7, #4]
80080ca: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
80080ce: f043 0201 orr.w r2, r3, #1
80080d2: 687b ldr r3, [r7, #4]
80080d4: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
80080d8: 687b ldr r3, [r7, #4]
80080da: 2204 movs r2, #4
80080dc: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
80080e0: 687b ldr r3, [r7, #4]
80080e2: 2200 movs r2, #0
80080e4: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
80080e8: 6878 ldr r0, [r7, #4]
80080ea: f000 f86f bl 80081cc <HAL_LTDC_ErrorCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* FIFO underrun Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
80080ee: 68fb ldr r3, [r7, #12]
80080f0: f003 0302 and.w r3, r3, #2
80080f4: 2b00 cmp r3, #0
80080f6: d023 beq.n 8008140 <HAL_LTDC_IRQHandler+0xbc>
80080f8: 68bb ldr r3, [r7, #8]
80080fa: f003 0302 and.w r3, r3, #2
80080fe: 2b00 cmp r3, #0
8008100: d01e beq.n 8008140 <HAL_LTDC_IRQHandler+0xbc>
{
/* Disable the FIFO underrun interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
8008102: 687b ldr r3, [r7, #4]
8008104: 681b ldr r3, [r3, #0]
8008106: 6b5a ldr r2, [r3, #52] ; 0x34
8008108: 687b ldr r3, [r7, #4]
800810a: 681b ldr r3, [r3, #0]
800810c: f022 0202 bic.w r2, r2, #2
8008110: 635a str r2, [r3, #52] ; 0x34
/* Clear the FIFO underrun flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
8008112: 687b ldr r3, [r7, #4]
8008114: 681b ldr r3, [r3, #0]
8008116: 2202 movs r2, #2
8008118: 63da str r2, [r3, #60] ; 0x3c
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
800811a: 687b ldr r3, [r7, #4]
800811c: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
8008120: f043 0202 orr.w r2, r3, #2
8008124: 687b ldr r3, [r7, #4]
8008126: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
800812a: 687b ldr r3, [r7, #4]
800812c: 2204 movs r2, #4
800812e: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8008132: 687b ldr r3, [r7, #4]
8008134: 2200 movs r2, #0
8008136: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
800813a: 6878 ldr r0, [r7, #4]
800813c: f000 f846 bl 80081cc <HAL_LTDC_ErrorCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Line Interrupt management ************************************************/
if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
8008140: 68fb ldr r3, [r7, #12]
8008142: f003 0301 and.w r3, r3, #1
8008146: 2b00 cmp r3, #0
8008148: d01b beq.n 8008182 <HAL_LTDC_IRQHandler+0xfe>
800814a: 68bb ldr r3, [r7, #8]
800814c: f003 0301 and.w r3, r3, #1
8008150: 2b00 cmp r3, #0
8008152: d016 beq.n 8008182 <HAL_LTDC_IRQHandler+0xfe>
{
/* Disable the Line interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
8008154: 687b ldr r3, [r7, #4]
8008156: 681b ldr r3, [r3, #0]
8008158: 6b5a ldr r2, [r3, #52] ; 0x34
800815a: 687b ldr r3, [r7, #4]
800815c: 681b ldr r3, [r3, #0]
800815e: f022 0201 bic.w r2, r2, #1
8008162: 635a str r2, [r3, #52] ; 0x34
/* Clear the Line interrupt flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
8008164: 687b ldr r3, [r7, #4]
8008166: 681b ldr r3, [r3, #0]
8008168: 2201 movs r2, #1
800816a: 63da str r2, [r3, #60] ; 0x3c
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
800816c: 687b ldr r3, [r7, #4]
800816e: 2201 movs r2, #1
8008170: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8008174: 687b ldr r3, [r7, #4]
8008176: 2200 movs r2, #0
8008178: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered Line Event callback */
hltdc->LineEventCallback(hltdc);
#else
/*Call Legacy Line Event callback */
HAL_LTDC_LineEventCallback(hltdc);
800817c: 6878 ldr r0, [r7, #4]
800817e: f000 f82f bl 80081e0 <HAL_LTDC_LineEventCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Register reload Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
8008182: 68fb ldr r3, [r7, #12]
8008184: f003 0308 and.w r3, r3, #8
8008188: 2b00 cmp r3, #0
800818a: d01b beq.n 80081c4 <HAL_LTDC_IRQHandler+0x140>
800818c: 68bb ldr r3, [r7, #8]
800818e: f003 0308 and.w r3, r3, #8
8008192: 2b00 cmp r3, #0
8008194: d016 beq.n 80081c4 <HAL_LTDC_IRQHandler+0x140>
{
/* Disable the register reload interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
8008196: 687b ldr r3, [r7, #4]
8008198: 681b ldr r3, [r3, #0]
800819a: 6b5a ldr r2, [r3, #52] ; 0x34
800819c: 687b ldr r3, [r7, #4]
800819e: 681b ldr r3, [r3, #0]
80081a0: f022 0208 bic.w r2, r2, #8
80081a4: 635a str r2, [r3, #52] ; 0x34
/* Clear the register reload flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
80081a6: 687b ldr r3, [r7, #4]
80081a8: 681b ldr r3, [r3, #0]
80081aa: 2208 movs r2, #8
80081ac: 63da str r2, [r3, #60] ; 0x3c
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
80081ae: 687b ldr r3, [r7, #4]
80081b0: 2201 movs r2, #1
80081b2: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
80081b6: 687b ldr r3, [r7, #4]
80081b8: 2200 movs r2, #0
80081ba: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered reload Event callback */
hltdc->ReloadEventCallback(hltdc);
#else
/*Call Legacy Reload Event callback */
HAL_LTDC_ReloadEventCallback(hltdc);
80081be: 6878 ldr r0, [r7, #4]
80081c0: f000 f818 bl 80081f4 <HAL_LTDC_ReloadEventCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
}
80081c4: bf00 nop
80081c6: 3710 adds r7, #16
80081c8: 46bd mov sp, r7
80081ca: bd80 pop {r7, pc}
080081cc <HAL_LTDC_ErrorCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
{
80081cc: b480 push {r7}
80081ce: b083 sub sp, #12
80081d0: af00 add r7, sp, #0
80081d2: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ErrorCallback could be implemented in the user file
*/
}
80081d4: bf00 nop
80081d6: 370c adds r7, #12
80081d8: 46bd mov sp, r7
80081da: f85d 7b04 ldr.w r7, [sp], #4
80081de: 4770 bx lr
080081e0 <HAL_LTDC_LineEventCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
{
80081e0: b480 push {r7}
80081e2: b083 sub sp, #12
80081e4: af00 add r7, sp, #0
80081e6: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_LineEventCallback could be implemented in the user file
*/
}
80081e8: bf00 nop
80081ea: 370c adds r7, #12
80081ec: 46bd mov sp, r7
80081ee: f85d 7b04 ldr.w r7, [sp], #4
80081f2: 4770 bx lr
080081f4 <HAL_LTDC_ReloadEventCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
{
80081f4: b480 push {r7}
80081f6: b083 sub sp, #12
80081f8: af00 add r7, sp, #0
80081fa: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
*/
}
80081fc: bf00 nop
80081fe: 370c adds r7, #12
8008200: 46bd mov sp, r7
8008202: f85d 7b04 ldr.w r7, [sp], #4
8008206: 4770 bx lr
08008208 <HAL_LTDC_ConfigLayer>:
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
8008208: b5b0 push {r4, r5, r7, lr}
800820a: b084 sub sp, #16
800820c: af00 add r7, sp, #0
800820e: 60f8 str r0, [r7, #12]
8008210: 60b9 str r1, [r7, #8]
8008212: 607a str r2, [r7, #4]
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
/* Process locked */
__HAL_LOCK(hltdc);
8008214: 68fb ldr r3, [r7, #12]
8008216: f893 30a0 ldrb.w r3, [r3, #160] ; 0xa0
800821a: 2b01 cmp r3, #1
800821c: d101 bne.n 8008222 <HAL_LTDC_ConfigLayer+0x1a>
800821e: 2302 movs r3, #2
8008220: e02c b.n 800827c <HAL_LTDC_ConfigLayer+0x74>
8008222: 68fb ldr r3, [r7, #12]
8008224: 2201 movs r2, #1
8008226: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
800822a: 68fb ldr r3, [r7, #12]
800822c: 2202 movs r2, #2
800822e: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Copy new layer configuration into handle structure */
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
8008232: 68fa ldr r2, [r7, #12]
8008234: 687b ldr r3, [r7, #4]
8008236: 2134 movs r1, #52 ; 0x34
8008238: fb01 f303 mul.w r3, r1, r3
800823c: 4413 add r3, r2
800823e: f103 0238 add.w r2, r3, #56 ; 0x38
8008242: 68bb ldr r3, [r7, #8]
8008244: 4614 mov r4, r2
8008246: 461d mov r5, r3
8008248: cd0f ldmia r5!, {r0, r1, r2, r3}
800824a: c40f stmia r4!, {r0, r1, r2, r3}
800824c: cd0f ldmia r5!, {r0, r1, r2, r3}
800824e: c40f stmia r4!, {r0, r1, r2, r3}
8008250: cd0f ldmia r5!, {r0, r1, r2, r3}
8008252: c40f stmia r4!, {r0, r1, r2, r3}
8008254: 682b ldr r3, [r5, #0]
8008256: 6023 str r3, [r4, #0]
/* Configure the LTDC Layer */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
8008258: 687a ldr r2, [r7, #4]
800825a: 68b9 ldr r1, [r7, #8]
800825c: 68f8 ldr r0, [r7, #12]
800825e: f000 f81f bl 80082a0 <LTDC_SetConfig>
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
8008262: 68fb ldr r3, [r7, #12]
8008264: 681b ldr r3, [r3, #0]
8008266: 2201 movs r2, #1
8008268: 625a str r2, [r3, #36] ; 0x24
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
800826a: 68fb ldr r3, [r7, #12]
800826c: 2201 movs r2, #1
800826e: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8008272: 68fb ldr r3, [r7, #12]
8008274: 2200 movs r2, #0
8008276: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
return HAL_OK;
800827a: 2300 movs r3, #0
}
800827c: 4618 mov r0, r3
800827e: 3710 adds r7, #16
8008280: 46bd mov sp, r7
8008282: bdb0 pop {r4, r5, r7, pc}
08008284 <HAL_LTDC_GetState>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL state
*/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
{
8008284: b480 push {r7}
8008286: b083 sub sp, #12
8008288: af00 add r7, sp, #0
800828a: 6078 str r0, [r7, #4]
return hltdc->State;
800828c: 687b ldr r3, [r7, #4]
800828e: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1
8008292: b2db uxtb r3, r3
}
8008294: 4618 mov r0, r3
8008296: 370c adds r7, #12
8008298: 46bd mov sp, r7
800829a: f85d 7b04 ldr.w r7, [sp], #4
800829e: 4770 bx lr
080082a0 <LTDC_SetConfig>:
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval None
*/
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
80082a0: b480 push {r7}
80082a2: b089 sub sp, #36 ; 0x24
80082a4: af00 add r7, sp, #0
80082a6: 60f8 str r0, [r7, #12]
80082a8: 60b9 str r1, [r7, #8]
80082aa: 607a str r2, [r7, #4]
uint32_t tmp;
uint32_t tmp1;
uint32_t tmp2;
/* Configure the horizontal start and stop position */
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
80082ac: 68bb ldr r3, [r7, #8]
80082ae: 685a ldr r2, [r3, #4]
80082b0: 68fb ldr r3, [r7, #12]
80082b2: 681b ldr r3, [r3, #0]
80082b4: 68db ldr r3, [r3, #12]
80082b6: 0c1b lsrs r3, r3, #16
80082b8: f3c3 030b ubfx r3, r3, #0, #12
80082bc: 4413 add r3, r2
80082be: 041b lsls r3, r3, #16
80082c0: 61fb str r3, [r7, #28]
LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
80082c2: 68fb ldr r3, [r7, #12]
80082c4: 681b ldr r3, [r3, #0]
80082c6: 461a mov r2, r3
80082c8: 687b ldr r3, [r7, #4]
80082ca: 01db lsls r3, r3, #7
80082cc: 4413 add r3, r2
80082ce: 3384 adds r3, #132 ; 0x84
80082d0: 685b ldr r3, [r3, #4]
80082d2: 68fa ldr r2, [r7, #12]
80082d4: 6812 ldr r2, [r2, #0]
80082d6: 4611 mov r1, r2
80082d8: 687a ldr r2, [r7, #4]
80082da: 01d2 lsls r2, r2, #7
80082dc: 440a add r2, r1
80082de: 3284 adds r2, #132 ; 0x84
80082e0: f403 4370 and.w r3, r3, #61440 ; 0xf000
80082e4: 6053 str r3, [r2, #4]
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
80082e6: 68bb ldr r3, [r7, #8]
80082e8: 681a ldr r2, [r3, #0]
80082ea: 68fb ldr r3, [r7, #12]
80082ec: 681b ldr r3, [r3, #0]
80082ee: 68db ldr r3, [r3, #12]
80082f0: 0c1b lsrs r3, r3, #16
80082f2: f3c3 030b ubfx r3, r3, #0, #12
80082f6: 4413 add r3, r2
80082f8: 1c5a adds r2, r3, #1
80082fa: 68fb ldr r3, [r7, #12]
80082fc: 681b ldr r3, [r3, #0]
80082fe: 4619 mov r1, r3
8008300: 687b ldr r3, [r7, #4]
8008302: 01db lsls r3, r3, #7
8008304: 440b add r3, r1
8008306: 3384 adds r3, #132 ; 0x84
8008308: 4619 mov r1, r3
800830a: 69fb ldr r3, [r7, #28]
800830c: 4313 orrs r3, r2
800830e: 604b str r3, [r1, #4]
/* Configure the vertical start and stop position */
tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
8008310: 68bb ldr r3, [r7, #8]
8008312: 68da ldr r2, [r3, #12]
8008314: 68fb ldr r3, [r7, #12]
8008316: 681b ldr r3, [r3, #0]
8008318: 68db ldr r3, [r3, #12]
800831a: f3c3 030a ubfx r3, r3, #0, #11
800831e: 4413 add r3, r2
8008320: 041b lsls r3, r3, #16
8008322: 61fb str r3, [r7, #28]
LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
8008324: 68fb ldr r3, [r7, #12]
8008326: 681b ldr r3, [r3, #0]
8008328: 461a mov r2, r3
800832a: 687b ldr r3, [r7, #4]
800832c: 01db lsls r3, r3, #7
800832e: 4413 add r3, r2
8008330: 3384 adds r3, #132 ; 0x84
8008332: 689b ldr r3, [r3, #8]
8008334: 68fa ldr r2, [r7, #12]
8008336: 6812 ldr r2, [r2, #0]
8008338: 4611 mov r1, r2
800833a: 687a ldr r2, [r7, #4]
800833c: 01d2 lsls r2, r2, #7
800833e: 440a add r2, r1
8008340: 3284 adds r2, #132 ; 0x84
8008342: f403 4370 and.w r3, r3, #61440 ; 0xf000
8008346: 6093 str r3, [r2, #8]
LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
8008348: 68bb ldr r3, [r7, #8]
800834a: 689a ldr r2, [r3, #8]
800834c: 68fb ldr r3, [r7, #12]
800834e: 681b ldr r3, [r3, #0]
8008350: 68db ldr r3, [r3, #12]
8008352: f3c3 030a ubfx r3, r3, #0, #11
8008356: 4413 add r3, r2
8008358: 1c5a adds r2, r3, #1
800835a: 68fb ldr r3, [r7, #12]
800835c: 681b ldr r3, [r3, #0]
800835e: 4619 mov r1, r3
8008360: 687b ldr r3, [r7, #4]
8008362: 01db lsls r3, r3, #7
8008364: 440b add r3, r1
8008366: 3384 adds r3, #132 ; 0x84
8008368: 4619 mov r1, r3
800836a: 69fb ldr r3, [r7, #28]
800836c: 4313 orrs r3, r2
800836e: 608b str r3, [r1, #8]
/* Specifies the pixel format */
LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
8008370: 68fb ldr r3, [r7, #12]
8008372: 681b ldr r3, [r3, #0]
8008374: 461a mov r2, r3
8008376: 687b ldr r3, [r7, #4]
8008378: 01db lsls r3, r3, #7
800837a: 4413 add r3, r2
800837c: 3384 adds r3, #132 ; 0x84
800837e: 691b ldr r3, [r3, #16]
8008380: 68fa ldr r2, [r7, #12]
8008382: 6812 ldr r2, [r2, #0]
8008384: 4611 mov r1, r2
8008386: 687a ldr r2, [r7, #4]
8008388: 01d2 lsls r2, r2, #7
800838a: 440a add r2, r1
800838c: 3284 adds r2, #132 ; 0x84
800838e: f023 0307 bic.w r3, r3, #7
8008392: 6113 str r3, [r2, #16]
LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
8008394: 68fb ldr r3, [r7, #12]
8008396: 681b ldr r3, [r3, #0]
8008398: 461a mov r2, r3
800839a: 687b ldr r3, [r7, #4]
800839c: 01db lsls r3, r3, #7
800839e: 4413 add r3, r2
80083a0: 3384 adds r3, #132 ; 0x84
80083a2: 461a mov r2, r3
80083a4: 68bb ldr r3, [r7, #8]
80083a6: 691b ldr r3, [r3, #16]
80083a8: 6113 str r3, [r2, #16]
/* Configure the default color values */
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
80083aa: 68bb ldr r3, [r7, #8]
80083ac: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
80083b0: 021b lsls r3, r3, #8
80083b2: 61fb str r3, [r7, #28]
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
80083b4: 68bb ldr r3, [r7, #8]
80083b6: f893 3032 ldrb.w r3, [r3, #50] ; 0x32
80083ba: 041b lsls r3, r3, #16
80083bc: 61bb str r3, [r7, #24]
tmp2 = (pLayerCfg->Alpha0 << 24U);
80083be: 68bb ldr r3, [r7, #8]
80083c0: 699b ldr r3, [r3, #24]
80083c2: 061b lsls r3, r3, #24
80083c4: 617b str r3, [r7, #20]
LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
80083c6: 68fb ldr r3, [r7, #12]
80083c8: 681b ldr r3, [r3, #0]
80083ca: 461a mov r2, r3
80083cc: 687b ldr r3, [r7, #4]
80083ce: 01db lsls r3, r3, #7
80083d0: 4413 add r3, r2
80083d2: 3384 adds r3, #132 ; 0x84
80083d4: 699b ldr r3, [r3, #24]
80083d6: 68fb ldr r3, [r7, #12]
80083d8: 681b ldr r3, [r3, #0]
80083da: 461a mov r2, r3
80083dc: 687b ldr r3, [r7, #4]
80083de: 01db lsls r3, r3, #7
80083e0: 4413 add r3, r2
80083e2: 3384 adds r3, #132 ; 0x84
80083e4: 461a mov r2, r3
80083e6: 2300 movs r3, #0
80083e8: 6193 str r3, [r2, #24]
LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
80083ea: 68bb ldr r3, [r7, #8]
80083ec: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
80083f0: 461a mov r2, r3
80083f2: 69fb ldr r3, [r7, #28]
80083f4: 431a orrs r2, r3
80083f6: 69bb ldr r3, [r7, #24]
80083f8: 431a orrs r2, r3
80083fa: 68fb ldr r3, [r7, #12]
80083fc: 681b ldr r3, [r3, #0]
80083fe: 4619 mov r1, r3
8008400: 687b ldr r3, [r7, #4]
8008402: 01db lsls r3, r3, #7
8008404: 440b add r3, r1
8008406: 3384 adds r3, #132 ; 0x84
8008408: 4619 mov r1, r3
800840a: 697b ldr r3, [r7, #20]
800840c: 4313 orrs r3, r2
800840e: 618b str r3, [r1, #24]
/* Specifies the constant alpha value */
LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
8008410: 68fb ldr r3, [r7, #12]
8008412: 681b ldr r3, [r3, #0]
8008414: 461a mov r2, r3
8008416: 687b ldr r3, [r7, #4]
8008418: 01db lsls r3, r3, #7
800841a: 4413 add r3, r2
800841c: 3384 adds r3, #132 ; 0x84
800841e: 695b ldr r3, [r3, #20]
8008420: 68fa ldr r2, [r7, #12]
8008422: 6812 ldr r2, [r2, #0]
8008424: 4611 mov r1, r2
8008426: 687a ldr r2, [r7, #4]
8008428: 01d2 lsls r2, r2, #7
800842a: 440a add r2, r1
800842c: 3284 adds r2, #132 ; 0x84
800842e: f023 03ff bic.w r3, r3, #255 ; 0xff
8008432: 6153 str r3, [r2, #20]
LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
8008434: 68fb ldr r3, [r7, #12]
8008436: 681b ldr r3, [r3, #0]
8008438: 461a mov r2, r3
800843a: 687b ldr r3, [r7, #4]
800843c: 01db lsls r3, r3, #7
800843e: 4413 add r3, r2
8008440: 3384 adds r3, #132 ; 0x84
8008442: 461a mov r2, r3
8008444: 68bb ldr r3, [r7, #8]
8008446: 695b ldr r3, [r3, #20]
8008448: 6153 str r3, [r2, #20]
/* Specifies the blending factors */
LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
800844a: 68fb ldr r3, [r7, #12]
800844c: 681b ldr r3, [r3, #0]
800844e: 461a mov r2, r3
8008450: 687b ldr r3, [r7, #4]
8008452: 01db lsls r3, r3, #7
8008454: 4413 add r3, r2
8008456: 3384 adds r3, #132 ; 0x84
8008458: 69da ldr r2, [r3, #28]
800845a: 68fb ldr r3, [r7, #12]
800845c: 681b ldr r3, [r3, #0]
800845e: 4619 mov r1, r3
8008460: 687b ldr r3, [r7, #4]
8008462: 01db lsls r3, r3, #7
8008464: 440b add r3, r1
8008466: 3384 adds r3, #132 ; 0x84
8008468: 4619 mov r1, r3
800846a: 4b58 ldr r3, [pc, #352] ; (80085cc <LTDC_SetConfig+0x32c>)
800846c: 4013 ands r3, r2
800846e: 61cb str r3, [r1, #28]
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
8008470: 68bb ldr r3, [r7, #8]
8008472: 69da ldr r2, [r3, #28]
8008474: 68bb ldr r3, [r7, #8]
8008476: 6a1b ldr r3, [r3, #32]
8008478: 68f9 ldr r1, [r7, #12]
800847a: 6809 ldr r1, [r1, #0]
800847c: 4608 mov r0, r1
800847e: 6879 ldr r1, [r7, #4]
8008480: 01c9 lsls r1, r1, #7
8008482: 4401 add r1, r0
8008484: 3184 adds r1, #132 ; 0x84
8008486: 4313 orrs r3, r2
8008488: 61cb str r3, [r1, #28]
/* Configure the color frame buffer start address */
LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
800848a: 68fb ldr r3, [r7, #12]
800848c: 681b ldr r3, [r3, #0]
800848e: 461a mov r2, r3
8008490: 687b ldr r3, [r7, #4]
8008492: 01db lsls r3, r3, #7
8008494: 4413 add r3, r2
8008496: 3384 adds r3, #132 ; 0x84
8008498: 6a9b ldr r3, [r3, #40] ; 0x28
800849a: 68fb ldr r3, [r7, #12]
800849c: 681b ldr r3, [r3, #0]
800849e: 461a mov r2, r3
80084a0: 687b ldr r3, [r7, #4]
80084a2: 01db lsls r3, r3, #7
80084a4: 4413 add r3, r2
80084a6: 3384 adds r3, #132 ; 0x84
80084a8: 461a mov r2, r3
80084aa: 2300 movs r3, #0
80084ac: 6293 str r3, [r2, #40] ; 0x28
LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
80084ae: 68fb ldr r3, [r7, #12]
80084b0: 681b ldr r3, [r3, #0]
80084b2: 461a mov r2, r3
80084b4: 687b ldr r3, [r7, #4]
80084b6: 01db lsls r3, r3, #7
80084b8: 4413 add r3, r2
80084ba: 3384 adds r3, #132 ; 0x84
80084bc: 461a mov r2, r3
80084be: 68bb ldr r3, [r7, #8]
80084c0: 6a5b ldr r3, [r3, #36] ; 0x24
80084c2: 6293 str r3, [r2, #40] ; 0x28
if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
80084c4: 68bb ldr r3, [r7, #8]
80084c6: 691b ldr r3, [r3, #16]
80084c8: 2b00 cmp r3, #0
80084ca: d102 bne.n 80084d2 <LTDC_SetConfig+0x232>
{
tmp = 4U;
80084cc: 2304 movs r3, #4
80084ce: 61fb str r3, [r7, #28]
80084d0: e01b b.n 800850a <LTDC_SetConfig+0x26a>
}
else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
80084d2: 68bb ldr r3, [r7, #8]
80084d4: 691b ldr r3, [r3, #16]
80084d6: 2b01 cmp r3, #1
80084d8: d102 bne.n 80084e0 <LTDC_SetConfig+0x240>
{
tmp = 3U;
80084da: 2303 movs r3, #3
80084dc: 61fb str r3, [r7, #28]
80084de: e014 b.n 800850a <LTDC_SetConfig+0x26a>
}
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
80084e0: 68bb ldr r3, [r7, #8]
80084e2: 691b ldr r3, [r3, #16]
80084e4: 2b04 cmp r3, #4
80084e6: d00b beq.n 8008500 <LTDC_SetConfig+0x260>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
80084e8: 68bb ldr r3, [r7, #8]
80084ea: 691b ldr r3, [r3, #16]
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
80084ec: 2b02 cmp r3, #2
80084ee: d007 beq.n 8008500 <LTDC_SetConfig+0x260>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
80084f0: 68bb ldr r3, [r7, #8]
80084f2: 691b ldr r3, [r3, #16]
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
80084f4: 2b03 cmp r3, #3
80084f6: d003 beq.n 8008500 <LTDC_SetConfig+0x260>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
80084f8: 68bb ldr r3, [r7, #8]
80084fa: 691b ldr r3, [r3, #16]
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
80084fc: 2b07 cmp r3, #7
80084fe: d102 bne.n 8008506 <LTDC_SetConfig+0x266>
{
tmp = 2U;
8008500: 2302 movs r3, #2
8008502: 61fb str r3, [r7, #28]
8008504: e001 b.n 800850a <LTDC_SetConfig+0x26a>
}
else
{
tmp = 1U;
8008506: 2301 movs r3, #1
8008508: 61fb str r3, [r7, #28]
}
/* Configure the color frame buffer pitch in byte */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
800850a: 68fb ldr r3, [r7, #12]
800850c: 681b ldr r3, [r3, #0]
800850e: 461a mov r2, r3
8008510: 687b ldr r3, [r7, #4]
8008512: 01db lsls r3, r3, #7
8008514: 4413 add r3, r2
8008516: 3384 adds r3, #132 ; 0x84
8008518: 6adb ldr r3, [r3, #44] ; 0x2c
800851a: 68fa ldr r2, [r7, #12]
800851c: 6812 ldr r2, [r2, #0]
800851e: 4611 mov r1, r2
8008520: 687a ldr r2, [r7, #4]
8008522: 01d2 lsls r2, r2, #7
8008524: 440a add r2, r1
8008526: 3284 adds r2, #132 ; 0x84
8008528: f003 23e0 and.w r3, r3, #3758153728 ; 0xe000e000
800852c: 62d3 str r3, [r2, #44] ; 0x2c
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
800852e: 68bb ldr r3, [r7, #8]
8008530: 6a9b ldr r3, [r3, #40] ; 0x28
8008532: 69fa ldr r2, [r7, #28]
8008534: fb02 f303 mul.w r3, r2, r3
8008538: 041a lsls r2, r3, #16
800853a: 68bb ldr r3, [r7, #8]
800853c: 6859 ldr r1, [r3, #4]
800853e: 68bb ldr r3, [r7, #8]
8008540: 681b ldr r3, [r3, #0]
8008542: 1acb subs r3, r1, r3
8008544: 69f9 ldr r1, [r7, #28]
8008546: fb01 f303 mul.w r3, r1, r3
800854a: 3303 adds r3, #3
800854c: 68f9 ldr r1, [r7, #12]
800854e: 6809 ldr r1, [r1, #0]
8008550: 4608 mov r0, r1
8008552: 6879 ldr r1, [r7, #4]
8008554: 01c9 lsls r1, r1, #7
8008556: 4401 add r1, r0
8008558: 3184 adds r1, #132 ; 0x84
800855a: 4313 orrs r3, r2
800855c: 62cb str r3, [r1, #44] ; 0x2c
/* Configure the frame buffer line number */
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
800855e: 68fb ldr r3, [r7, #12]
8008560: 681b ldr r3, [r3, #0]
8008562: 461a mov r2, r3
8008564: 687b ldr r3, [r7, #4]
8008566: 01db lsls r3, r3, #7
8008568: 4413 add r3, r2
800856a: 3384 adds r3, #132 ; 0x84
800856c: 6b1a ldr r2, [r3, #48] ; 0x30
800856e: 68fb ldr r3, [r7, #12]
8008570: 681b ldr r3, [r3, #0]
8008572: 4619 mov r1, r3
8008574: 687b ldr r3, [r7, #4]
8008576: 01db lsls r3, r3, #7
8008578: 440b add r3, r1
800857a: 3384 adds r3, #132 ; 0x84
800857c: 4619 mov r1, r3
800857e: 4b14 ldr r3, [pc, #80] ; (80085d0 <LTDC_SetConfig+0x330>)
8008580: 4013 ands r3, r2
8008582: 630b str r3, [r1, #48] ; 0x30
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
8008584: 68fb ldr r3, [r7, #12]
8008586: 681b ldr r3, [r3, #0]
8008588: 461a mov r2, r3
800858a: 687b ldr r3, [r7, #4]
800858c: 01db lsls r3, r3, #7
800858e: 4413 add r3, r2
8008590: 3384 adds r3, #132 ; 0x84
8008592: 461a mov r2, r3
8008594: 68bb ldr r3, [r7, #8]
8008596: 6adb ldr r3, [r3, #44] ; 0x2c
8008598: 6313 str r3, [r2, #48] ; 0x30
/* Enable LTDC_Layer by setting LEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
800859a: 68fb ldr r3, [r7, #12]
800859c: 681b ldr r3, [r3, #0]
800859e: 461a mov r2, r3
80085a0: 687b ldr r3, [r7, #4]
80085a2: 01db lsls r3, r3, #7
80085a4: 4413 add r3, r2
80085a6: 3384 adds r3, #132 ; 0x84
80085a8: 681b ldr r3, [r3, #0]
80085aa: 68fa ldr r2, [r7, #12]
80085ac: 6812 ldr r2, [r2, #0]
80085ae: 4611 mov r1, r2
80085b0: 687a ldr r2, [r7, #4]
80085b2: 01d2 lsls r2, r2, #7
80085b4: 440a add r2, r1
80085b6: 3284 adds r2, #132 ; 0x84
80085b8: f043 0301 orr.w r3, r3, #1
80085bc: 6013 str r3, [r2, #0]
}
80085be: bf00 nop
80085c0: 3724 adds r7, #36 ; 0x24
80085c2: 46bd mov sp, r7
80085c4: f85d 7b04 ldr.w r7, [sp], #4
80085c8: 4770 bx lr
80085ca: bf00 nop
80085cc: fffff8f8 .word 0xfffff8f8
80085d0: fffff800 .word 0xfffff800
080085d4 <HAL_PWR_EnableBkUpAccess>:
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
80085d4: b480 push {r7}
80085d6: af00 add r7, sp, #0
/* Enable access to RTC and backup registers */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80085d8: 4b05 ldr r3, [pc, #20] ; (80085f0 <HAL_PWR_EnableBkUpAccess+0x1c>)
80085da: 681b ldr r3, [r3, #0]
80085dc: 4a04 ldr r2, [pc, #16] ; (80085f0 <HAL_PWR_EnableBkUpAccess+0x1c>)
80085de: f443 7380 orr.w r3, r3, #256 ; 0x100
80085e2: 6013 str r3, [r2, #0]
}
80085e4: bf00 nop
80085e6: 46bd mov sp, r7
80085e8: f85d 7b04 ldr.w r7, [sp], #4
80085ec: 4770 bx lr
80085ee: bf00 nop
80085f0: 40007000 .word 0x40007000
080085f4 <HAL_PWREx_EnableOverDrive>:
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
80085f4: b580 push {r7, lr}
80085f6: b082 sub sp, #8
80085f8: af00 add r7, sp, #0
uint32_t tickstart = 0;
80085fa: 2300 movs r3, #0
80085fc: 607b str r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80085fe: 4b23 ldr r3, [pc, #140] ; (800868c <HAL_PWREx_EnableOverDrive+0x98>)
8008600: 6c1b ldr r3, [r3, #64] ; 0x40
8008602: 4a22 ldr r2, [pc, #136] ; (800868c <HAL_PWREx_EnableOverDrive+0x98>)
8008604: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8008608: 6413 str r3, [r2, #64] ; 0x40
800860a: 4b20 ldr r3, [pc, #128] ; (800868c <HAL_PWREx_EnableOverDrive+0x98>)
800860c: 6c1b ldr r3, [r3, #64] ; 0x40
800860e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8008612: 603b str r3, [r7, #0]
8008614: 683b ldr r3, [r7, #0]
/* Enable the Over-drive to extend the clock frequency to 216 MHz */
__HAL_PWR_OVERDRIVE_ENABLE();
8008616: 4b1e ldr r3, [pc, #120] ; (8008690 <HAL_PWREx_EnableOverDrive+0x9c>)
8008618: 681b ldr r3, [r3, #0]
800861a: 4a1d ldr r2, [pc, #116] ; (8008690 <HAL_PWREx_EnableOverDrive+0x9c>)
800861c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8008620: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8008622: f7fc f8d5 bl 80047d0 <HAL_GetTick>
8008626: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8008628: e009 b.n 800863e <HAL_PWREx_EnableOverDrive+0x4a>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
800862a: f7fc f8d1 bl 80047d0 <HAL_GetTick>
800862e: 4602 mov r2, r0
8008630: 687b ldr r3, [r7, #4]
8008632: 1ad3 subs r3, r2, r3
8008634: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
8008638: d901 bls.n 800863e <HAL_PWREx_EnableOverDrive+0x4a>
{
return HAL_TIMEOUT;
800863a: 2303 movs r3, #3
800863c: e022 b.n 8008684 <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
800863e: 4b14 ldr r3, [pc, #80] ; (8008690 <HAL_PWREx_EnableOverDrive+0x9c>)
8008640: 685b ldr r3, [r3, #4]
8008642: f403 3380 and.w r3, r3, #65536 ; 0x10000
8008646: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
800864a: d1ee bne.n 800862a <HAL_PWREx_EnableOverDrive+0x36>
}
}
/* Enable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
800864c: 4b10 ldr r3, [pc, #64] ; (8008690 <HAL_PWREx_EnableOverDrive+0x9c>)
800864e: 681b ldr r3, [r3, #0]
8008650: 4a0f ldr r2, [pc, #60] ; (8008690 <HAL_PWREx_EnableOverDrive+0x9c>)
8008652: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8008656: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8008658: f7fc f8ba bl 80047d0 <HAL_GetTick>
800865c: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
800865e: e009 b.n 8008674 <HAL_PWREx_EnableOverDrive+0x80>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8008660: f7fc f8b6 bl 80047d0 <HAL_GetTick>
8008664: 4602 mov r2, r0
8008666: 687b ldr r3, [r7, #4]
8008668: 1ad3 subs r3, r2, r3
800866a: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
800866e: d901 bls.n 8008674 <HAL_PWREx_EnableOverDrive+0x80>
{
return HAL_TIMEOUT;
8008670: 2303 movs r3, #3
8008672: e007 b.n 8008684 <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8008674: 4b06 ldr r3, [pc, #24] ; (8008690 <HAL_PWREx_EnableOverDrive+0x9c>)
8008676: 685b ldr r3, [r3, #4]
8008678: f403 3300 and.w r3, r3, #131072 ; 0x20000
800867c: f5b3 3f00 cmp.w r3, #131072 ; 0x20000
8008680: d1ee bne.n 8008660 <HAL_PWREx_EnableOverDrive+0x6c>
}
}
return HAL_OK;
8008682: 2300 movs r3, #0
}
8008684: 4618 mov r0, r3
8008686: 3708 adds r7, #8
8008688: 46bd mov sp, r7
800868a: bd80 pop {r7, pc}
800868c: 40023800 .word 0x40023800
8008690: 40007000 .word 0x40007000
08008694 <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8008694: b580 push {r7, lr}
8008696: b086 sub sp, #24
8008698: af00 add r7, sp, #0
800869a: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
FlagStatus pwrclkchanged = RESET;
800869c: 2300 movs r3, #0
800869e: 75fb strb r3, [r7, #23]
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
80086a0: 687b ldr r3, [r7, #4]
80086a2: 2b00 cmp r3, #0
80086a4: d101 bne.n 80086aa <HAL_RCC_OscConfig+0x16>
{
return HAL_ERROR;
80086a6: 2301 movs r3, #1
80086a8: e291 b.n 8008bce <HAL_RCC_OscConfig+0x53a>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80086aa: 687b ldr r3, [r7, #4]
80086ac: 681b ldr r3, [r3, #0]
80086ae: f003 0301 and.w r3, r3, #1
80086b2: 2b00 cmp r3, #0
80086b4: f000 8087 beq.w 80087c6 <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
80086b8: 4b96 ldr r3, [pc, #600] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80086ba: 689b ldr r3, [r3, #8]
80086bc: f003 030c and.w r3, r3, #12
80086c0: 2b04 cmp r3, #4
80086c2: d00c beq.n 80086de <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80086c4: 4b93 ldr r3, [pc, #588] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80086c6: 689b ldr r3, [r3, #8]
80086c8: f003 030c and.w r3, r3, #12
80086cc: 2b08 cmp r3, #8
80086ce: d112 bne.n 80086f6 <HAL_RCC_OscConfig+0x62>
80086d0: 4b90 ldr r3, [pc, #576] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80086d2: 685b ldr r3, [r3, #4]
80086d4: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80086d8: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
80086dc: d10b bne.n 80086f6 <HAL_RCC_OscConfig+0x62>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80086de: 4b8d ldr r3, [pc, #564] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80086e0: 681b ldr r3, [r3, #0]
80086e2: f403 3300 and.w r3, r3, #131072 ; 0x20000
80086e6: 2b00 cmp r3, #0
80086e8: d06c beq.n 80087c4 <HAL_RCC_OscConfig+0x130>
80086ea: 687b ldr r3, [r7, #4]
80086ec: 685b ldr r3, [r3, #4]
80086ee: 2b00 cmp r3, #0
80086f0: d168 bne.n 80087c4 <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
80086f2: 2301 movs r3, #1
80086f4: e26b b.n 8008bce <HAL_RCC_OscConfig+0x53a>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80086f6: 687b ldr r3, [r7, #4]
80086f8: 685b ldr r3, [r3, #4]
80086fa: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80086fe: d106 bne.n 800870e <HAL_RCC_OscConfig+0x7a>
8008700: 4b84 ldr r3, [pc, #528] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008702: 681b ldr r3, [r3, #0]
8008704: 4a83 ldr r2, [pc, #524] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008706: f443 3380 orr.w r3, r3, #65536 ; 0x10000
800870a: 6013 str r3, [r2, #0]
800870c: e02e b.n 800876c <HAL_RCC_OscConfig+0xd8>
800870e: 687b ldr r3, [r7, #4]
8008710: 685b ldr r3, [r3, #4]
8008712: 2b00 cmp r3, #0
8008714: d10c bne.n 8008730 <HAL_RCC_OscConfig+0x9c>
8008716: 4b7f ldr r3, [pc, #508] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008718: 681b ldr r3, [r3, #0]
800871a: 4a7e ldr r2, [pc, #504] ; (8008914 <HAL_RCC_OscConfig+0x280>)
800871c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8008720: 6013 str r3, [r2, #0]
8008722: 4b7c ldr r3, [pc, #496] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008724: 681b ldr r3, [r3, #0]
8008726: 4a7b ldr r2, [pc, #492] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008728: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800872c: 6013 str r3, [r2, #0]
800872e: e01d b.n 800876c <HAL_RCC_OscConfig+0xd8>
8008730: 687b ldr r3, [r7, #4]
8008732: 685b ldr r3, [r3, #4]
8008734: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8008738: d10c bne.n 8008754 <HAL_RCC_OscConfig+0xc0>
800873a: 4b76 ldr r3, [pc, #472] ; (8008914 <HAL_RCC_OscConfig+0x280>)
800873c: 681b ldr r3, [r3, #0]
800873e: 4a75 ldr r2, [pc, #468] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008740: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8008744: 6013 str r3, [r2, #0]
8008746: 4b73 ldr r3, [pc, #460] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008748: 681b ldr r3, [r3, #0]
800874a: 4a72 ldr r2, [pc, #456] ; (8008914 <HAL_RCC_OscConfig+0x280>)
800874c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8008750: 6013 str r3, [r2, #0]
8008752: e00b b.n 800876c <HAL_RCC_OscConfig+0xd8>
8008754: 4b6f ldr r3, [pc, #444] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008756: 681b ldr r3, [r3, #0]
8008758: 4a6e ldr r2, [pc, #440] ; (8008914 <HAL_RCC_OscConfig+0x280>)
800875a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
800875e: 6013 str r3, [r2, #0]
8008760: 4b6c ldr r3, [pc, #432] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008762: 681b ldr r3, [r3, #0]
8008764: 4a6b ldr r2, [pc, #428] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008766: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800876a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800876c: 687b ldr r3, [r7, #4]
800876e: 685b ldr r3, [r3, #4]
8008770: 2b00 cmp r3, #0
8008772: d013 beq.n 800879c <HAL_RCC_OscConfig+0x108>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008774: f7fc f82c bl 80047d0 <HAL_GetTick>
8008778: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800877a: e008 b.n 800878e <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800877c: f7fc f828 bl 80047d0 <HAL_GetTick>
8008780: 4602 mov r2, r0
8008782: 693b ldr r3, [r7, #16]
8008784: 1ad3 subs r3, r2, r3
8008786: 2b64 cmp r3, #100 ; 0x64
8008788: d901 bls.n 800878e <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
800878a: 2303 movs r3, #3
800878c: e21f b.n 8008bce <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800878e: 4b61 ldr r3, [pc, #388] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008790: 681b ldr r3, [r3, #0]
8008792: f403 3300 and.w r3, r3, #131072 ; 0x20000
8008796: 2b00 cmp r3, #0
8008798: d0f0 beq.n 800877c <HAL_RCC_OscConfig+0xe8>
800879a: e014 b.n 80087c6 <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800879c: f7fc f818 bl 80047d0 <HAL_GetTick>
80087a0: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80087a2: e008 b.n 80087b6 <HAL_RCC_OscConfig+0x122>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80087a4: f7fc f814 bl 80047d0 <HAL_GetTick>
80087a8: 4602 mov r2, r0
80087aa: 693b ldr r3, [r7, #16]
80087ac: 1ad3 subs r3, r2, r3
80087ae: 2b64 cmp r3, #100 ; 0x64
80087b0: d901 bls.n 80087b6 <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
80087b2: 2303 movs r3, #3
80087b4: e20b b.n 8008bce <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80087b6: 4b57 ldr r3, [pc, #348] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80087b8: 681b ldr r3, [r3, #0]
80087ba: f403 3300 and.w r3, r3, #131072 ; 0x20000
80087be: 2b00 cmp r3, #0
80087c0: d1f0 bne.n 80087a4 <HAL_RCC_OscConfig+0x110>
80087c2: e000 b.n 80087c6 <HAL_RCC_OscConfig+0x132>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80087c4: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80087c6: 687b ldr r3, [r7, #4]
80087c8: 681b ldr r3, [r3, #0]
80087ca: f003 0302 and.w r3, r3, #2
80087ce: 2b00 cmp r3, #0
80087d0: d069 beq.n 80088a6 <HAL_RCC_OscConfig+0x212>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
80087d2: 4b50 ldr r3, [pc, #320] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80087d4: 689b ldr r3, [r3, #8]
80087d6: f003 030c and.w r3, r3, #12
80087da: 2b00 cmp r3, #0
80087dc: d00b beq.n 80087f6 <HAL_RCC_OscConfig+0x162>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80087de: 4b4d ldr r3, [pc, #308] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80087e0: 689b ldr r3, [r3, #8]
80087e2: f003 030c and.w r3, r3, #12
80087e6: 2b08 cmp r3, #8
80087e8: d11c bne.n 8008824 <HAL_RCC_OscConfig+0x190>
80087ea: 4b4a ldr r3, [pc, #296] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80087ec: 685b ldr r3, [r3, #4]
80087ee: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80087f2: 2b00 cmp r3, #0
80087f4: d116 bne.n 8008824 <HAL_RCC_OscConfig+0x190>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80087f6: 4b47 ldr r3, [pc, #284] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80087f8: 681b ldr r3, [r3, #0]
80087fa: f003 0302 and.w r3, r3, #2
80087fe: 2b00 cmp r3, #0
8008800: d005 beq.n 800880e <HAL_RCC_OscConfig+0x17a>
8008802: 687b ldr r3, [r7, #4]
8008804: 68db ldr r3, [r3, #12]
8008806: 2b01 cmp r3, #1
8008808: d001 beq.n 800880e <HAL_RCC_OscConfig+0x17a>
{
return HAL_ERROR;
800880a: 2301 movs r3, #1
800880c: e1df b.n 8008bce <HAL_RCC_OscConfig+0x53a>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800880e: 4b41 ldr r3, [pc, #260] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008810: 681b ldr r3, [r3, #0]
8008812: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8008816: 687b ldr r3, [r7, #4]
8008818: 691b ldr r3, [r3, #16]
800881a: 00db lsls r3, r3, #3
800881c: 493d ldr r1, [pc, #244] ; (8008914 <HAL_RCC_OscConfig+0x280>)
800881e: 4313 orrs r3, r2
8008820: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8008822: e040 b.n 80088a6 <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
8008824: 687b ldr r3, [r7, #4]
8008826: 68db ldr r3, [r3, #12]
8008828: 2b00 cmp r3, #0
800882a: d023 beq.n 8008874 <HAL_RCC_OscConfig+0x1e0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
800882c: 4b39 ldr r3, [pc, #228] ; (8008914 <HAL_RCC_OscConfig+0x280>)
800882e: 681b ldr r3, [r3, #0]
8008830: 4a38 ldr r2, [pc, #224] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008832: f043 0301 orr.w r3, r3, #1
8008836: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008838: f7fb ffca bl 80047d0 <HAL_GetTick>
800883c: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800883e: e008 b.n 8008852 <HAL_RCC_OscConfig+0x1be>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8008840: f7fb ffc6 bl 80047d0 <HAL_GetTick>
8008844: 4602 mov r2, r0
8008846: 693b ldr r3, [r7, #16]
8008848: 1ad3 subs r3, r2, r3
800884a: 2b02 cmp r3, #2
800884c: d901 bls.n 8008852 <HAL_RCC_OscConfig+0x1be>
{
return HAL_TIMEOUT;
800884e: 2303 movs r3, #3
8008850: e1bd b.n 8008bce <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8008852: 4b30 ldr r3, [pc, #192] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008854: 681b ldr r3, [r3, #0]
8008856: f003 0302 and.w r3, r3, #2
800885a: 2b00 cmp r3, #0
800885c: d0f0 beq.n 8008840 <HAL_RCC_OscConfig+0x1ac>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800885e: 4b2d ldr r3, [pc, #180] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008860: 681b ldr r3, [r3, #0]
8008862: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8008866: 687b ldr r3, [r7, #4]
8008868: 691b ldr r3, [r3, #16]
800886a: 00db lsls r3, r3, #3
800886c: 4929 ldr r1, [pc, #164] ; (8008914 <HAL_RCC_OscConfig+0x280>)
800886e: 4313 orrs r3, r2
8008870: 600b str r3, [r1, #0]
8008872: e018 b.n 80088a6 <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8008874: 4b27 ldr r3, [pc, #156] ; (8008914 <HAL_RCC_OscConfig+0x280>)
8008876: 681b ldr r3, [r3, #0]
8008878: 4a26 ldr r2, [pc, #152] ; (8008914 <HAL_RCC_OscConfig+0x280>)
800887a: f023 0301 bic.w r3, r3, #1
800887e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008880: f7fb ffa6 bl 80047d0 <HAL_GetTick>
8008884: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8008886: e008 b.n 800889a <HAL_RCC_OscConfig+0x206>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8008888: f7fb ffa2 bl 80047d0 <HAL_GetTick>
800888c: 4602 mov r2, r0
800888e: 693b ldr r3, [r7, #16]
8008890: 1ad3 subs r3, r2, r3
8008892: 2b02 cmp r3, #2
8008894: d901 bls.n 800889a <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
8008896: 2303 movs r3, #3
8008898: e199 b.n 8008bce <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800889a: 4b1e ldr r3, [pc, #120] ; (8008914 <HAL_RCC_OscConfig+0x280>)
800889c: 681b ldr r3, [r3, #0]
800889e: f003 0302 and.w r3, r3, #2
80088a2: 2b00 cmp r3, #0
80088a4: d1f0 bne.n 8008888 <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80088a6: 687b ldr r3, [r7, #4]
80088a8: 681b ldr r3, [r3, #0]
80088aa: f003 0308 and.w r3, r3, #8
80088ae: 2b00 cmp r3, #0
80088b0: d038 beq.n 8008924 <HAL_RCC_OscConfig+0x290>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
80088b2: 687b ldr r3, [r7, #4]
80088b4: 695b ldr r3, [r3, #20]
80088b6: 2b00 cmp r3, #0
80088b8: d019 beq.n 80088ee <HAL_RCC_OscConfig+0x25a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80088ba: 4b16 ldr r3, [pc, #88] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80088bc: 6f5b ldr r3, [r3, #116] ; 0x74
80088be: 4a15 ldr r2, [pc, #84] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80088c0: f043 0301 orr.w r3, r3, #1
80088c4: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
80088c6: f7fb ff83 bl 80047d0 <HAL_GetTick>
80088ca: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80088cc: e008 b.n 80088e0 <HAL_RCC_OscConfig+0x24c>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80088ce: f7fb ff7f bl 80047d0 <HAL_GetTick>
80088d2: 4602 mov r2, r0
80088d4: 693b ldr r3, [r7, #16]
80088d6: 1ad3 subs r3, r2, r3
80088d8: 2b02 cmp r3, #2
80088da: d901 bls.n 80088e0 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
80088dc: 2303 movs r3, #3
80088de: e176 b.n 8008bce <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80088e0: 4b0c ldr r3, [pc, #48] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80088e2: 6f5b ldr r3, [r3, #116] ; 0x74
80088e4: f003 0302 and.w r3, r3, #2
80088e8: 2b00 cmp r3, #0
80088ea: d0f0 beq.n 80088ce <HAL_RCC_OscConfig+0x23a>
80088ec: e01a b.n 8008924 <HAL_RCC_OscConfig+0x290>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80088ee: 4b09 ldr r3, [pc, #36] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80088f0: 6f5b ldr r3, [r3, #116] ; 0x74
80088f2: 4a08 ldr r2, [pc, #32] ; (8008914 <HAL_RCC_OscConfig+0x280>)
80088f4: f023 0301 bic.w r3, r3, #1
80088f8: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
80088fa: f7fb ff69 bl 80047d0 <HAL_GetTick>
80088fe: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8008900: e00a b.n 8008918 <HAL_RCC_OscConfig+0x284>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8008902: f7fb ff65 bl 80047d0 <HAL_GetTick>
8008906: 4602 mov r2, r0
8008908: 693b ldr r3, [r7, #16]
800890a: 1ad3 subs r3, r2, r3
800890c: 2b02 cmp r3, #2
800890e: d903 bls.n 8008918 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
8008910: 2303 movs r3, #3
8008912: e15c b.n 8008bce <HAL_RCC_OscConfig+0x53a>
8008914: 40023800 .word 0x40023800
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8008918: 4b91 ldr r3, [pc, #580] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
800891a: 6f5b ldr r3, [r3, #116] ; 0x74
800891c: f003 0302 and.w r3, r3, #2
8008920: 2b00 cmp r3, #0
8008922: d1ee bne.n 8008902 <HAL_RCC_OscConfig+0x26e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8008924: 687b ldr r3, [r7, #4]
8008926: 681b ldr r3, [r3, #0]
8008928: f003 0304 and.w r3, r3, #4
800892c: 2b00 cmp r3, #0
800892e: f000 80a4 beq.w 8008a7a <HAL_RCC_OscConfig+0x3e6>
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8008932: 4b8b ldr r3, [pc, #556] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008934: 6c1b ldr r3, [r3, #64] ; 0x40
8008936: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800893a: 2b00 cmp r3, #0
800893c: d10d bne.n 800895a <HAL_RCC_OscConfig+0x2c6>
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
800893e: 4b88 ldr r3, [pc, #544] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008940: 6c1b ldr r3, [r3, #64] ; 0x40
8008942: 4a87 ldr r2, [pc, #540] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008944: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8008948: 6413 str r3, [r2, #64] ; 0x40
800894a: 4b85 ldr r3, [pc, #532] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
800894c: 6c1b ldr r3, [r3, #64] ; 0x40
800894e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8008952: 60bb str r3, [r7, #8]
8008954: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8008956: 2301 movs r3, #1
8008958: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
800895a: 4b82 ldr r3, [pc, #520] ; (8008b64 <HAL_RCC_OscConfig+0x4d0>)
800895c: 681b ldr r3, [r3, #0]
800895e: f403 7380 and.w r3, r3, #256 ; 0x100
8008962: 2b00 cmp r3, #0
8008964: d118 bne.n 8008998 <HAL_RCC_OscConfig+0x304>
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
8008966: 4b7f ldr r3, [pc, #508] ; (8008b64 <HAL_RCC_OscConfig+0x4d0>)
8008968: 681b ldr r3, [r3, #0]
800896a: 4a7e ldr r2, [pc, #504] ; (8008b64 <HAL_RCC_OscConfig+0x4d0>)
800896c: f443 7380 orr.w r3, r3, #256 ; 0x100
8008970: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8008972: f7fb ff2d bl 80047d0 <HAL_GetTick>
8008976: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8008978: e008 b.n 800898c <HAL_RCC_OscConfig+0x2f8>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800897a: f7fb ff29 bl 80047d0 <HAL_GetTick>
800897e: 4602 mov r2, r0
8008980: 693b ldr r3, [r7, #16]
8008982: 1ad3 subs r3, r2, r3
8008984: 2b64 cmp r3, #100 ; 0x64
8008986: d901 bls.n 800898c <HAL_RCC_OscConfig+0x2f8>
{
return HAL_TIMEOUT;
8008988: 2303 movs r3, #3
800898a: e120 b.n 8008bce <HAL_RCC_OscConfig+0x53a>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
800898c: 4b75 ldr r3, [pc, #468] ; (8008b64 <HAL_RCC_OscConfig+0x4d0>)
800898e: 681b ldr r3, [r3, #0]
8008990: f403 7380 and.w r3, r3, #256 ; 0x100
8008994: 2b00 cmp r3, #0
8008996: d0f0 beq.n 800897a <HAL_RCC_OscConfig+0x2e6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8008998: 687b ldr r3, [r7, #4]
800899a: 689b ldr r3, [r3, #8]
800899c: 2b01 cmp r3, #1
800899e: d106 bne.n 80089ae <HAL_RCC_OscConfig+0x31a>
80089a0: 4b6f ldr r3, [pc, #444] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
80089a2: 6f1b ldr r3, [r3, #112] ; 0x70
80089a4: 4a6e ldr r2, [pc, #440] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
80089a6: f043 0301 orr.w r3, r3, #1
80089aa: 6713 str r3, [r2, #112] ; 0x70
80089ac: e02d b.n 8008a0a <HAL_RCC_OscConfig+0x376>
80089ae: 687b ldr r3, [r7, #4]
80089b0: 689b ldr r3, [r3, #8]
80089b2: 2b00 cmp r3, #0
80089b4: d10c bne.n 80089d0 <HAL_RCC_OscConfig+0x33c>
80089b6: 4b6a ldr r3, [pc, #424] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
80089b8: 6f1b ldr r3, [r3, #112] ; 0x70
80089ba: 4a69 ldr r2, [pc, #420] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
80089bc: f023 0301 bic.w r3, r3, #1
80089c0: 6713 str r3, [r2, #112] ; 0x70
80089c2: 4b67 ldr r3, [pc, #412] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
80089c4: 6f1b ldr r3, [r3, #112] ; 0x70
80089c6: 4a66 ldr r2, [pc, #408] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
80089c8: f023 0304 bic.w r3, r3, #4
80089cc: 6713 str r3, [r2, #112] ; 0x70
80089ce: e01c b.n 8008a0a <HAL_RCC_OscConfig+0x376>
80089d0: 687b ldr r3, [r7, #4]
80089d2: 689b ldr r3, [r3, #8]
80089d4: 2b05 cmp r3, #5
80089d6: d10c bne.n 80089f2 <HAL_RCC_OscConfig+0x35e>
80089d8: 4b61 ldr r3, [pc, #388] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
80089da: 6f1b ldr r3, [r3, #112] ; 0x70
80089dc: 4a60 ldr r2, [pc, #384] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
80089de: f043 0304 orr.w r3, r3, #4
80089e2: 6713 str r3, [r2, #112] ; 0x70
80089e4: 4b5e ldr r3, [pc, #376] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
80089e6: 6f1b ldr r3, [r3, #112] ; 0x70
80089e8: 4a5d ldr r2, [pc, #372] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
80089ea: f043 0301 orr.w r3, r3, #1
80089ee: 6713 str r3, [r2, #112] ; 0x70
80089f0: e00b b.n 8008a0a <HAL_RCC_OscConfig+0x376>
80089f2: 4b5b ldr r3, [pc, #364] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
80089f4: 6f1b ldr r3, [r3, #112] ; 0x70
80089f6: 4a5a ldr r2, [pc, #360] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
80089f8: f023 0301 bic.w r3, r3, #1
80089fc: 6713 str r3, [r2, #112] ; 0x70
80089fe: 4b58 ldr r3, [pc, #352] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008a00: 6f1b ldr r3, [r3, #112] ; 0x70
8008a02: 4a57 ldr r2, [pc, #348] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008a04: f023 0304 bic.w r3, r3, #4
8008a08: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8008a0a: 687b ldr r3, [r7, #4]
8008a0c: 689b ldr r3, [r3, #8]
8008a0e: 2b00 cmp r3, #0
8008a10: d015 beq.n 8008a3e <HAL_RCC_OscConfig+0x3aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008a12: f7fb fedd bl 80047d0 <HAL_GetTick>
8008a16: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8008a18: e00a b.n 8008a30 <HAL_RCC_OscConfig+0x39c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8008a1a: f7fb fed9 bl 80047d0 <HAL_GetTick>
8008a1e: 4602 mov r2, r0
8008a20: 693b ldr r3, [r7, #16]
8008a22: 1ad3 subs r3, r2, r3
8008a24: f241 3288 movw r2, #5000 ; 0x1388
8008a28: 4293 cmp r3, r2
8008a2a: d901 bls.n 8008a30 <HAL_RCC_OscConfig+0x39c>
{
return HAL_TIMEOUT;
8008a2c: 2303 movs r3, #3
8008a2e: e0ce b.n 8008bce <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8008a30: 4b4b ldr r3, [pc, #300] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008a32: 6f1b ldr r3, [r3, #112] ; 0x70
8008a34: f003 0302 and.w r3, r3, #2
8008a38: 2b00 cmp r3, #0
8008a3a: d0ee beq.n 8008a1a <HAL_RCC_OscConfig+0x386>
8008a3c: e014 b.n 8008a68 <HAL_RCC_OscConfig+0x3d4>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008a3e: f7fb fec7 bl 80047d0 <HAL_GetTick>
8008a42: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8008a44: e00a b.n 8008a5c <HAL_RCC_OscConfig+0x3c8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8008a46: f7fb fec3 bl 80047d0 <HAL_GetTick>
8008a4a: 4602 mov r2, r0
8008a4c: 693b ldr r3, [r7, #16]
8008a4e: 1ad3 subs r3, r2, r3
8008a50: f241 3288 movw r2, #5000 ; 0x1388
8008a54: 4293 cmp r3, r2
8008a56: d901 bls.n 8008a5c <HAL_RCC_OscConfig+0x3c8>
{
return HAL_TIMEOUT;
8008a58: 2303 movs r3, #3
8008a5a: e0b8 b.n 8008bce <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8008a5c: 4b40 ldr r3, [pc, #256] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008a5e: 6f1b ldr r3, [r3, #112] ; 0x70
8008a60: f003 0302 and.w r3, r3, #2
8008a64: 2b00 cmp r3, #0
8008a66: d1ee bne.n 8008a46 <HAL_RCC_OscConfig+0x3b2>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8008a68: 7dfb ldrb r3, [r7, #23]
8008a6a: 2b01 cmp r3, #1
8008a6c: d105 bne.n 8008a7a <HAL_RCC_OscConfig+0x3e6>
{
__HAL_RCC_PWR_CLK_DISABLE();
8008a6e: 4b3c ldr r3, [pc, #240] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008a70: 6c1b ldr r3, [r3, #64] ; 0x40
8008a72: 4a3b ldr r2, [pc, #236] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008a74: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8008a78: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8008a7a: 687b ldr r3, [r7, #4]
8008a7c: 699b ldr r3, [r3, #24]
8008a7e: 2b00 cmp r3, #0
8008a80: f000 80a4 beq.w 8008bcc <HAL_RCC_OscConfig+0x538>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8008a84: 4b36 ldr r3, [pc, #216] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008a86: 689b ldr r3, [r3, #8]
8008a88: f003 030c and.w r3, r3, #12
8008a8c: 2b08 cmp r3, #8
8008a8e: d06b beq.n 8008b68 <HAL_RCC_OscConfig+0x4d4>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8008a90: 687b ldr r3, [r7, #4]
8008a92: 699b ldr r3, [r3, #24]
8008a94: 2b02 cmp r3, #2
8008a96: d149 bne.n 8008b2c <HAL_RCC_OscConfig+0x498>
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8008a98: 4b31 ldr r3, [pc, #196] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008a9a: 681b ldr r3, [r3, #0]
8008a9c: 4a30 ldr r2, [pc, #192] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008a9e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8008aa2: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008aa4: f7fb fe94 bl 80047d0 <HAL_GetTick>
8008aa8: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8008aaa: e008 b.n 8008abe <HAL_RCC_OscConfig+0x42a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8008aac: f7fb fe90 bl 80047d0 <HAL_GetTick>
8008ab0: 4602 mov r2, r0
8008ab2: 693b ldr r3, [r7, #16]
8008ab4: 1ad3 subs r3, r2, r3
8008ab6: 2b02 cmp r3, #2
8008ab8: d901 bls.n 8008abe <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
8008aba: 2303 movs r3, #3
8008abc: e087 b.n 8008bce <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8008abe: 4b28 ldr r3, [pc, #160] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008ac0: 681b ldr r3, [r3, #0]
8008ac2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8008ac6: 2b00 cmp r3, #0
8008ac8: d1f0 bne.n 8008aac <HAL_RCC_OscConfig+0x418>
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#else
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8008aca: 687b ldr r3, [r7, #4]
8008acc: 69da ldr r2, [r3, #28]
8008ace: 687b ldr r3, [r7, #4]
8008ad0: 6a1b ldr r3, [r3, #32]
8008ad2: 431a orrs r2, r3
8008ad4: 687b ldr r3, [r7, #4]
8008ad6: 6a5b ldr r3, [r3, #36] ; 0x24
8008ad8: 019b lsls r3, r3, #6
8008ada: 431a orrs r2, r3
8008adc: 687b ldr r3, [r7, #4]
8008ade: 6a9b ldr r3, [r3, #40] ; 0x28
8008ae0: 085b lsrs r3, r3, #1
8008ae2: 3b01 subs r3, #1
8008ae4: 041b lsls r3, r3, #16
8008ae6: 431a orrs r2, r3
8008ae8: 687b ldr r3, [r7, #4]
8008aea: 6adb ldr r3, [r3, #44] ; 0x2c
8008aec: 061b lsls r3, r3, #24
8008aee: 4313 orrs r3, r2
8008af0: 4a1b ldr r2, [pc, #108] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008af2: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
8008af6: 6053 str r3, [r2, #4]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8008af8: 4b19 ldr r3, [pc, #100] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008afa: 681b ldr r3, [r3, #0]
8008afc: 4a18 ldr r2, [pc, #96] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008afe: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
8008b02: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008b04: f7fb fe64 bl 80047d0 <HAL_GetTick>
8008b08: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8008b0a: e008 b.n 8008b1e <HAL_RCC_OscConfig+0x48a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8008b0c: f7fb fe60 bl 80047d0 <HAL_GetTick>
8008b10: 4602 mov r2, r0
8008b12: 693b ldr r3, [r7, #16]
8008b14: 1ad3 subs r3, r2, r3
8008b16: 2b02 cmp r3, #2
8008b18: d901 bls.n 8008b1e <HAL_RCC_OscConfig+0x48a>
{
return HAL_TIMEOUT;
8008b1a: 2303 movs r3, #3
8008b1c: e057 b.n 8008bce <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8008b1e: 4b10 ldr r3, [pc, #64] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008b20: 681b ldr r3, [r3, #0]
8008b22: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8008b26: 2b00 cmp r3, #0
8008b28: d0f0 beq.n 8008b0c <HAL_RCC_OscConfig+0x478>
8008b2a: e04f b.n 8008bcc <HAL_RCC_OscConfig+0x538>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8008b2c: 4b0c ldr r3, [pc, #48] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008b2e: 681b ldr r3, [r3, #0]
8008b30: 4a0b ldr r2, [pc, #44] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008b32: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8008b36: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008b38: f7fb fe4a bl 80047d0 <HAL_GetTick>
8008b3c: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8008b3e: e008 b.n 8008b52 <HAL_RCC_OscConfig+0x4be>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8008b40: f7fb fe46 bl 80047d0 <HAL_GetTick>
8008b44: 4602 mov r2, r0
8008b46: 693b ldr r3, [r7, #16]
8008b48: 1ad3 subs r3, r2, r3
8008b4a: 2b02 cmp r3, #2
8008b4c: d901 bls.n 8008b52 <HAL_RCC_OscConfig+0x4be>
{
return HAL_TIMEOUT;
8008b4e: 2303 movs r3, #3
8008b50: e03d b.n 8008bce <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8008b52: 4b03 ldr r3, [pc, #12] ; (8008b60 <HAL_RCC_OscConfig+0x4cc>)
8008b54: 681b ldr r3, [r3, #0]
8008b56: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8008b5a: 2b00 cmp r3, #0
8008b5c: d1f0 bne.n 8008b40 <HAL_RCC_OscConfig+0x4ac>
8008b5e: e035 b.n 8008bcc <HAL_RCC_OscConfig+0x538>
8008b60: 40023800 .word 0x40023800
8008b64: 40007000 .word 0x40007000
}
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8008b68: 4b1b ldr r3, [pc, #108] ; (8008bd8 <HAL_RCC_OscConfig+0x544>)
8008b6a: 685b ldr r3, [r3, #4]
8008b6c: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8008b6e: 687b ldr r3, [r7, #4]
8008b70: 699b ldr r3, [r3, #24]
8008b72: 2b01 cmp r3, #1
8008b74: d028 beq.n 8008bc8 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8008b76: 68fb ldr r3, [r7, #12]
8008b78: f403 0280 and.w r2, r3, #4194304 ; 0x400000
8008b7c: 687b ldr r3, [r7, #4]
8008b7e: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8008b80: 429a cmp r2, r3
8008b82: d121 bne.n 8008bc8 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8008b84: 68fb ldr r3, [r7, #12]
8008b86: f003 023f and.w r2, r3, #63 ; 0x3f
8008b8a: 687b ldr r3, [r7, #4]
8008b8c: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8008b8e: 429a cmp r2, r3
8008b90: d11a bne.n 8008bc8 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8008b92: 68fa ldr r2, [r7, #12]
8008b94: f647 73c0 movw r3, #32704 ; 0x7fc0
8008b98: 4013 ands r3, r2
8008b9a: 687a ldr r2, [r7, #4]
8008b9c: 6a52 ldr r2, [r2, #36] ; 0x24
8008b9e: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8008ba0: 4293 cmp r3, r2
8008ba2: d111 bne.n 8008bc8 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
8008ba4: 68fb ldr r3, [r7, #12]
8008ba6: f403 3240 and.w r2, r3, #196608 ; 0x30000
8008baa: 687b ldr r3, [r7, #4]
8008bac: 6a9b ldr r3, [r3, #40] ; 0x28
8008bae: 085b lsrs r3, r3, #1
8008bb0: 3b01 subs r3, #1
8008bb2: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8008bb4: 429a cmp r2, r3
8008bb6: d107 bne.n 8008bc8 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
8008bb8: 68fb ldr r3, [r7, #12]
8008bba: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
8008bbe: 687b ldr r3, [r7, #4]
8008bc0: 6adb ldr r3, [r3, #44] ; 0x2c
8008bc2: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
8008bc4: 429a cmp r2, r3
8008bc6: d001 beq.n 8008bcc <HAL_RCC_OscConfig+0x538>
#endif
{
return HAL_ERROR;
8008bc8: 2301 movs r3, #1
8008bca: e000 b.n 8008bce <HAL_RCC_OscConfig+0x53a>
}
}
}
return HAL_OK;
8008bcc: 2300 movs r3, #0
}
8008bce: 4618 mov r0, r3
8008bd0: 3718 adds r7, #24
8008bd2: 46bd mov sp, r7
8008bd4: bd80 pop {r7, pc}
8008bd6: bf00 nop
8008bd8: 40023800 .word 0x40023800
08008bdc <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8008bdc: b580 push {r7, lr}
8008bde: b084 sub sp, #16
8008be0: af00 add r7, sp, #0
8008be2: 6078 str r0, [r7, #4]
8008be4: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
8008be6: 2300 movs r3, #0
8008be8: 60fb str r3, [r7, #12]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8008bea: 687b ldr r3, [r7, #4]
8008bec: 2b00 cmp r3, #0
8008bee: d101 bne.n 8008bf4 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8008bf0: 2301 movs r3, #1
8008bf2: e0d0 b.n 8008d96 <HAL_RCC_ClockConfig+0x1ba>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8008bf4: 4b6a ldr r3, [pc, #424] ; (8008da0 <HAL_RCC_ClockConfig+0x1c4>)
8008bf6: 681b ldr r3, [r3, #0]
8008bf8: f003 030f and.w r3, r3, #15
8008bfc: 683a ldr r2, [r7, #0]
8008bfe: 429a cmp r2, r3
8008c00: d910 bls.n 8008c24 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8008c02: 4b67 ldr r3, [pc, #412] ; (8008da0 <HAL_RCC_ClockConfig+0x1c4>)
8008c04: 681b ldr r3, [r3, #0]
8008c06: f023 020f bic.w r2, r3, #15
8008c0a: 4965 ldr r1, [pc, #404] ; (8008da0 <HAL_RCC_ClockConfig+0x1c4>)
8008c0c: 683b ldr r3, [r7, #0]
8008c0e: 4313 orrs r3, r2
8008c10: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8008c12: 4b63 ldr r3, [pc, #396] ; (8008da0 <HAL_RCC_ClockConfig+0x1c4>)
8008c14: 681b ldr r3, [r3, #0]
8008c16: f003 030f and.w r3, r3, #15
8008c1a: 683a ldr r2, [r7, #0]
8008c1c: 429a cmp r2, r3
8008c1e: d001 beq.n 8008c24 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8008c20: 2301 movs r3, #1
8008c22: e0b8 b.n 8008d96 <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8008c24: 687b ldr r3, [r7, #4]
8008c26: 681b ldr r3, [r3, #0]
8008c28: f003 0302 and.w r3, r3, #2
8008c2c: 2b00 cmp r3, #0
8008c2e: d020 beq.n 8008c72 <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8008c30: 687b ldr r3, [r7, #4]
8008c32: 681b ldr r3, [r3, #0]
8008c34: f003 0304 and.w r3, r3, #4
8008c38: 2b00 cmp r3, #0
8008c3a: d005 beq.n 8008c48 <HAL_RCC_ClockConfig+0x6c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8008c3c: 4b59 ldr r3, [pc, #356] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008c3e: 689b ldr r3, [r3, #8]
8008c40: 4a58 ldr r2, [pc, #352] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008c42: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
8008c46: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8008c48: 687b ldr r3, [r7, #4]
8008c4a: 681b ldr r3, [r3, #0]
8008c4c: f003 0308 and.w r3, r3, #8
8008c50: 2b00 cmp r3, #0
8008c52: d005 beq.n 8008c60 <HAL_RCC_ClockConfig+0x84>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8008c54: 4b53 ldr r3, [pc, #332] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008c56: 689b ldr r3, [r3, #8]
8008c58: 4a52 ldr r2, [pc, #328] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008c5a: f443 4360 orr.w r3, r3, #57344 ; 0xe000
8008c5e: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8008c60: 4b50 ldr r3, [pc, #320] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008c62: 689b ldr r3, [r3, #8]
8008c64: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8008c68: 687b ldr r3, [r7, #4]
8008c6a: 689b ldr r3, [r3, #8]
8008c6c: 494d ldr r1, [pc, #308] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008c6e: 4313 orrs r3, r2
8008c70: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8008c72: 687b ldr r3, [r7, #4]
8008c74: 681b ldr r3, [r3, #0]
8008c76: f003 0301 and.w r3, r3, #1
8008c7a: 2b00 cmp r3, #0
8008c7c: d040 beq.n 8008d00 <HAL_RCC_ClockConfig+0x124>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8008c7e: 687b ldr r3, [r7, #4]
8008c80: 685b ldr r3, [r3, #4]
8008c82: 2b01 cmp r3, #1
8008c84: d107 bne.n 8008c96 <HAL_RCC_ClockConfig+0xba>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8008c86: 4b47 ldr r3, [pc, #284] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008c88: 681b ldr r3, [r3, #0]
8008c8a: f403 3300 and.w r3, r3, #131072 ; 0x20000
8008c8e: 2b00 cmp r3, #0
8008c90: d115 bne.n 8008cbe <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8008c92: 2301 movs r3, #1
8008c94: e07f b.n 8008d96 <HAL_RCC_ClockConfig+0x1ba>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8008c96: 687b ldr r3, [r7, #4]
8008c98: 685b ldr r3, [r3, #4]
8008c9a: 2b02 cmp r3, #2
8008c9c: d107 bne.n 8008cae <HAL_RCC_ClockConfig+0xd2>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8008c9e: 4b41 ldr r3, [pc, #260] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008ca0: 681b ldr r3, [r3, #0]
8008ca2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8008ca6: 2b00 cmp r3, #0
8008ca8: d109 bne.n 8008cbe <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8008caa: 2301 movs r3, #1
8008cac: e073 b.n 8008d96 <HAL_RCC_ClockConfig+0x1ba>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8008cae: 4b3d ldr r3, [pc, #244] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008cb0: 681b ldr r3, [r3, #0]
8008cb2: f003 0302 and.w r3, r3, #2
8008cb6: 2b00 cmp r3, #0
8008cb8: d101 bne.n 8008cbe <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8008cba: 2301 movs r3, #1
8008cbc: e06b b.n 8008d96 <HAL_RCC_ClockConfig+0x1ba>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8008cbe: 4b39 ldr r3, [pc, #228] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008cc0: 689b ldr r3, [r3, #8]
8008cc2: f023 0203 bic.w r2, r3, #3
8008cc6: 687b ldr r3, [r7, #4]
8008cc8: 685b ldr r3, [r3, #4]
8008cca: 4936 ldr r1, [pc, #216] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008ccc: 4313 orrs r3, r2
8008cce: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008cd0: f7fb fd7e bl 80047d0 <HAL_GetTick>
8008cd4: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8008cd6: e00a b.n 8008cee <HAL_RCC_ClockConfig+0x112>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8008cd8: f7fb fd7a bl 80047d0 <HAL_GetTick>
8008cdc: 4602 mov r2, r0
8008cde: 68fb ldr r3, [r7, #12]
8008ce0: 1ad3 subs r3, r2, r3
8008ce2: f241 3288 movw r2, #5000 ; 0x1388
8008ce6: 4293 cmp r3, r2
8008ce8: d901 bls.n 8008cee <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
8008cea: 2303 movs r3, #3
8008cec: e053 b.n 8008d96 <HAL_RCC_ClockConfig+0x1ba>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8008cee: 4b2d ldr r3, [pc, #180] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008cf0: 689b ldr r3, [r3, #8]
8008cf2: f003 020c and.w r2, r3, #12
8008cf6: 687b ldr r3, [r7, #4]
8008cf8: 685b ldr r3, [r3, #4]
8008cfa: 009b lsls r3, r3, #2
8008cfc: 429a cmp r2, r3
8008cfe: d1eb bne.n 8008cd8 <HAL_RCC_ClockConfig+0xfc>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8008d00: 4b27 ldr r3, [pc, #156] ; (8008da0 <HAL_RCC_ClockConfig+0x1c4>)
8008d02: 681b ldr r3, [r3, #0]
8008d04: f003 030f and.w r3, r3, #15
8008d08: 683a ldr r2, [r7, #0]
8008d0a: 429a cmp r2, r3
8008d0c: d210 bcs.n 8008d30 <HAL_RCC_ClockConfig+0x154>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8008d0e: 4b24 ldr r3, [pc, #144] ; (8008da0 <HAL_RCC_ClockConfig+0x1c4>)
8008d10: 681b ldr r3, [r3, #0]
8008d12: f023 020f bic.w r2, r3, #15
8008d16: 4922 ldr r1, [pc, #136] ; (8008da0 <HAL_RCC_ClockConfig+0x1c4>)
8008d18: 683b ldr r3, [r7, #0]
8008d1a: 4313 orrs r3, r2
8008d1c: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8008d1e: 4b20 ldr r3, [pc, #128] ; (8008da0 <HAL_RCC_ClockConfig+0x1c4>)
8008d20: 681b ldr r3, [r3, #0]
8008d22: f003 030f and.w r3, r3, #15
8008d26: 683a ldr r2, [r7, #0]
8008d28: 429a cmp r2, r3
8008d2a: d001 beq.n 8008d30 <HAL_RCC_ClockConfig+0x154>
{
return HAL_ERROR;
8008d2c: 2301 movs r3, #1
8008d2e: e032 b.n 8008d96 <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8008d30: 687b ldr r3, [r7, #4]
8008d32: 681b ldr r3, [r3, #0]
8008d34: f003 0304 and.w r3, r3, #4
8008d38: 2b00 cmp r3, #0
8008d3a: d008 beq.n 8008d4e <HAL_RCC_ClockConfig+0x172>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8008d3c: 4b19 ldr r3, [pc, #100] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008d3e: 689b ldr r3, [r3, #8]
8008d40: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
8008d44: 687b ldr r3, [r7, #4]
8008d46: 68db ldr r3, [r3, #12]
8008d48: 4916 ldr r1, [pc, #88] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008d4a: 4313 orrs r3, r2
8008d4c: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8008d4e: 687b ldr r3, [r7, #4]
8008d50: 681b ldr r3, [r3, #0]
8008d52: f003 0308 and.w r3, r3, #8
8008d56: 2b00 cmp r3, #0
8008d58: d009 beq.n 8008d6e <HAL_RCC_ClockConfig+0x192>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8008d5a: 4b12 ldr r3, [pc, #72] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008d5c: 689b ldr r3, [r3, #8]
8008d5e: f423 4260 bic.w r2, r3, #57344 ; 0xe000
8008d62: 687b ldr r3, [r7, #4]
8008d64: 691b ldr r3, [r3, #16]
8008d66: 00db lsls r3, r3, #3
8008d68: 490e ldr r1, [pc, #56] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008d6a: 4313 orrs r3, r2
8008d6c: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8008d6e: f000 f821 bl 8008db4 <HAL_RCC_GetSysClockFreq>
8008d72: 4602 mov r2, r0
8008d74: 4b0b ldr r3, [pc, #44] ; (8008da4 <HAL_RCC_ClockConfig+0x1c8>)
8008d76: 689b ldr r3, [r3, #8]
8008d78: 091b lsrs r3, r3, #4
8008d7a: f003 030f and.w r3, r3, #15
8008d7e: 490a ldr r1, [pc, #40] ; (8008da8 <HAL_RCC_ClockConfig+0x1cc>)
8008d80: 5ccb ldrb r3, [r1, r3]
8008d82: fa22 f303 lsr.w r3, r2, r3
8008d86: 4a09 ldr r2, [pc, #36] ; (8008dac <HAL_RCC_ClockConfig+0x1d0>)
8008d88: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8008d8a: 4b09 ldr r3, [pc, #36] ; (8008db0 <HAL_RCC_ClockConfig+0x1d4>)
8008d8c: 681b ldr r3, [r3, #0]
8008d8e: 4618 mov r0, r3
8008d90: f7fb fb5e bl 8004450 <HAL_InitTick>
return HAL_OK;
8008d94: 2300 movs r3, #0
}
8008d96: 4618 mov r0, r3
8008d98: 3710 adds r7, #16
8008d9a: 46bd mov sp, r7
8008d9c: bd80 pop {r7, pc}
8008d9e: bf00 nop
8008da0: 40023c00 .word 0x40023c00
8008da4: 40023800 .word 0x40023800
8008da8: 08020efc .word 0x08020efc
8008dac: 20000058 .word 0x20000058
8008db0: 2000005c .word 0x2000005c
08008db4 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8008db4: b5b0 push {r4, r5, r7, lr}
8008db6: b084 sub sp, #16
8008db8: af00 add r7, sp, #0
uint32_t pllm = 0, pllvco = 0, pllp = 0;
8008dba: 2100 movs r1, #0
8008dbc: 6079 str r1, [r7, #4]
8008dbe: 2100 movs r1, #0
8008dc0: 60f9 str r1, [r7, #12]
8008dc2: 2100 movs r1, #0
8008dc4: 6039 str r1, [r7, #0]
uint32_t sysclockfreq = 0;
8008dc6: 2100 movs r1, #0
8008dc8: 60b9 str r1, [r7, #8]
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8008dca: 4952 ldr r1, [pc, #328] ; (8008f14 <HAL_RCC_GetSysClockFreq+0x160>)
8008dcc: 6889 ldr r1, [r1, #8]
8008dce: f001 010c and.w r1, r1, #12
8008dd2: 2908 cmp r1, #8
8008dd4: d00d beq.n 8008df2 <HAL_RCC_GetSysClockFreq+0x3e>
8008dd6: 2908 cmp r1, #8
8008dd8: f200 8094 bhi.w 8008f04 <HAL_RCC_GetSysClockFreq+0x150>
8008ddc: 2900 cmp r1, #0
8008dde: d002 beq.n 8008de6 <HAL_RCC_GetSysClockFreq+0x32>
8008de0: 2904 cmp r1, #4
8008de2: d003 beq.n 8008dec <HAL_RCC_GetSysClockFreq+0x38>
8008de4: e08e b.n 8008f04 <HAL_RCC_GetSysClockFreq+0x150>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8008de6: 4b4c ldr r3, [pc, #304] ; (8008f18 <HAL_RCC_GetSysClockFreq+0x164>)
8008de8: 60bb str r3, [r7, #8]
break;
8008dea: e08e b.n 8008f0a <HAL_RCC_GetSysClockFreq+0x156>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8008dec: 4b4b ldr r3, [pc, #300] ; (8008f1c <HAL_RCC_GetSysClockFreq+0x168>)
8008dee: 60bb str r3, [r7, #8]
break;
8008df0: e08b b.n 8008f0a <HAL_RCC_GetSysClockFreq+0x156>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8008df2: 4948 ldr r1, [pc, #288] ; (8008f14 <HAL_RCC_GetSysClockFreq+0x160>)
8008df4: 6849 ldr r1, [r1, #4]
8008df6: f001 013f and.w r1, r1, #63 ; 0x3f
8008dfa: 6079 str r1, [r7, #4]
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
8008dfc: 4945 ldr r1, [pc, #276] ; (8008f14 <HAL_RCC_GetSysClockFreq+0x160>)
8008dfe: 6849 ldr r1, [r1, #4]
8008e00: f401 0180 and.w r1, r1, #4194304 ; 0x400000
8008e04: 2900 cmp r1, #0
8008e06: d024 beq.n 8008e52 <HAL_RCC_GetSysClockFreq+0x9e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8008e08: 4942 ldr r1, [pc, #264] ; (8008f14 <HAL_RCC_GetSysClockFreq+0x160>)
8008e0a: 6849 ldr r1, [r1, #4]
8008e0c: 0989 lsrs r1, r1, #6
8008e0e: 4608 mov r0, r1
8008e10: f04f 0100 mov.w r1, #0
8008e14: f240 14ff movw r4, #511 ; 0x1ff
8008e18: f04f 0500 mov.w r5, #0
8008e1c: ea00 0204 and.w r2, r0, r4
8008e20: ea01 0305 and.w r3, r1, r5
8008e24: 493d ldr r1, [pc, #244] ; (8008f1c <HAL_RCC_GetSysClockFreq+0x168>)
8008e26: fb01 f003 mul.w r0, r1, r3
8008e2a: 2100 movs r1, #0
8008e2c: fb01 f102 mul.w r1, r1, r2
8008e30: 1844 adds r4, r0, r1
8008e32: 493a ldr r1, [pc, #232] ; (8008f1c <HAL_RCC_GetSysClockFreq+0x168>)
8008e34: fba2 0101 umull r0, r1, r2, r1
8008e38: 1863 adds r3, r4, r1
8008e3a: 4619 mov r1, r3
8008e3c: 687b ldr r3, [r7, #4]
8008e3e: 461a mov r2, r3
8008e40: f04f 0300 mov.w r3, #0
8008e44: f7f7 fa34 bl 80002b0 <__aeabi_uldivmod>
8008e48: 4602 mov r2, r0
8008e4a: 460b mov r3, r1
8008e4c: 4613 mov r3, r2
8008e4e: 60fb str r3, [r7, #12]
8008e50: e04a b.n 8008ee8 <HAL_RCC_GetSysClockFreq+0x134>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8008e52: 4b30 ldr r3, [pc, #192] ; (8008f14 <HAL_RCC_GetSysClockFreq+0x160>)
8008e54: 685b ldr r3, [r3, #4]
8008e56: 099b lsrs r3, r3, #6
8008e58: 461a mov r2, r3
8008e5a: f04f 0300 mov.w r3, #0
8008e5e: f240 10ff movw r0, #511 ; 0x1ff
8008e62: f04f 0100 mov.w r1, #0
8008e66: ea02 0400 and.w r4, r2, r0
8008e6a: ea03 0501 and.w r5, r3, r1
8008e6e: 4620 mov r0, r4
8008e70: 4629 mov r1, r5
8008e72: f04f 0200 mov.w r2, #0
8008e76: f04f 0300 mov.w r3, #0
8008e7a: 014b lsls r3, r1, #5
8008e7c: ea43 63d0 orr.w r3, r3, r0, lsr #27
8008e80: 0142 lsls r2, r0, #5
8008e82: 4610 mov r0, r2
8008e84: 4619 mov r1, r3
8008e86: 1b00 subs r0, r0, r4
8008e88: eb61 0105 sbc.w r1, r1, r5
8008e8c: f04f 0200 mov.w r2, #0
8008e90: f04f 0300 mov.w r3, #0
8008e94: 018b lsls r3, r1, #6
8008e96: ea43 6390 orr.w r3, r3, r0, lsr #26
8008e9a: 0182 lsls r2, r0, #6
8008e9c: 1a12 subs r2, r2, r0
8008e9e: eb63 0301 sbc.w r3, r3, r1
8008ea2: f04f 0000 mov.w r0, #0
8008ea6: f04f 0100 mov.w r1, #0
8008eaa: 00d9 lsls r1, r3, #3
8008eac: ea41 7152 orr.w r1, r1, r2, lsr #29
8008eb0: 00d0 lsls r0, r2, #3
8008eb2: 4602 mov r2, r0
8008eb4: 460b mov r3, r1
8008eb6: 1912 adds r2, r2, r4
8008eb8: eb45 0303 adc.w r3, r5, r3
8008ebc: f04f 0000 mov.w r0, #0
8008ec0: f04f 0100 mov.w r1, #0
8008ec4: 0299 lsls r1, r3, #10
8008ec6: ea41 5192 orr.w r1, r1, r2, lsr #22
8008eca: 0290 lsls r0, r2, #10
8008ecc: 4602 mov r2, r0
8008ece: 460b mov r3, r1
8008ed0: 4610 mov r0, r2
8008ed2: 4619 mov r1, r3
8008ed4: 687b ldr r3, [r7, #4]
8008ed6: 461a mov r2, r3
8008ed8: f04f 0300 mov.w r3, #0
8008edc: f7f7 f9e8 bl 80002b0 <__aeabi_uldivmod>
8008ee0: 4602 mov r2, r0
8008ee2: 460b mov r3, r1
8008ee4: 4613 mov r3, r2
8008ee6: 60fb str r3, [r7, #12]
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
8008ee8: 4b0a ldr r3, [pc, #40] ; (8008f14 <HAL_RCC_GetSysClockFreq+0x160>)
8008eea: 685b ldr r3, [r3, #4]
8008eec: 0c1b lsrs r3, r3, #16
8008eee: f003 0303 and.w r3, r3, #3
8008ef2: 3301 adds r3, #1
8008ef4: 005b lsls r3, r3, #1
8008ef6: 603b str r3, [r7, #0]
sysclockfreq = pllvco / pllp;
8008ef8: 68fa ldr r2, [r7, #12]
8008efa: 683b ldr r3, [r7, #0]
8008efc: fbb2 f3f3 udiv r3, r2, r3
8008f00: 60bb str r3, [r7, #8]
break;
8008f02: e002 b.n 8008f0a <HAL_RCC_GetSysClockFreq+0x156>
}
default:
{
sysclockfreq = HSI_VALUE;
8008f04: 4b04 ldr r3, [pc, #16] ; (8008f18 <HAL_RCC_GetSysClockFreq+0x164>)
8008f06: 60bb str r3, [r7, #8]
break;
8008f08: bf00 nop
}
}
return sysclockfreq;
8008f0a: 68bb ldr r3, [r7, #8]
}
8008f0c: 4618 mov r0, r3
8008f0e: 3710 adds r7, #16
8008f10: 46bd mov sp, r7
8008f12: bdb0 pop {r4, r5, r7, pc}
8008f14: 40023800 .word 0x40023800
8008f18: 00f42400 .word 0x00f42400
8008f1c: 017d7840 .word 0x017d7840
08008f20 <HAL_RCC_GetHCLKFreq>:
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8008f20: b480 push {r7}
8008f22: af00 add r7, sp, #0
return SystemCoreClock;
8008f24: 4b03 ldr r3, [pc, #12] ; (8008f34 <HAL_RCC_GetHCLKFreq+0x14>)
8008f26: 681b ldr r3, [r3, #0]
}
8008f28: 4618 mov r0, r3
8008f2a: 46bd mov sp, r7
8008f2c: f85d 7b04 ldr.w r7, [sp], #4
8008f30: 4770 bx lr
8008f32: bf00 nop
8008f34: 20000058 .word 0x20000058
08008f38 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8008f38: b580 push {r7, lr}
8008f3a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8008f3c: f7ff fff0 bl 8008f20 <HAL_RCC_GetHCLKFreq>
8008f40: 4602 mov r2, r0
8008f42: 4b05 ldr r3, [pc, #20] ; (8008f58 <HAL_RCC_GetPCLK1Freq+0x20>)
8008f44: 689b ldr r3, [r3, #8]
8008f46: 0a9b lsrs r3, r3, #10
8008f48: f003 0307 and.w r3, r3, #7
8008f4c: 4903 ldr r1, [pc, #12] ; (8008f5c <HAL_RCC_GetPCLK1Freq+0x24>)
8008f4e: 5ccb ldrb r3, [r1, r3]
8008f50: fa22 f303 lsr.w r3, r2, r3
}
8008f54: 4618 mov r0, r3
8008f56: bd80 pop {r7, pc}
8008f58: 40023800 .word 0x40023800
8008f5c: 08020f0c .word 0x08020f0c
08008f60 <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
8008f60: b480 push {r7}
8008f62: b083 sub sp, #12
8008f64: af00 add r7, sp, #0
8008f66: 6078 str r0, [r7, #4]
8008f68: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
8008f6a: 687b ldr r3, [r7, #4]
8008f6c: 220f movs r2, #15
8008f6e: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
8008f70: 4b12 ldr r3, [pc, #72] ; (8008fbc <HAL_RCC_GetClockConfig+0x5c>)
8008f72: 689b ldr r3, [r3, #8]
8008f74: f003 0203 and.w r2, r3, #3
8008f78: 687b ldr r3, [r7, #4]
8008f7a: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
8008f7c: 4b0f ldr r3, [pc, #60] ; (8008fbc <HAL_RCC_GetClockConfig+0x5c>)
8008f7e: 689b ldr r3, [r3, #8]
8008f80: f003 02f0 and.w r2, r3, #240 ; 0xf0
8008f84: 687b ldr r3, [r7, #4]
8008f86: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
8008f88: 4b0c ldr r3, [pc, #48] ; (8008fbc <HAL_RCC_GetClockConfig+0x5c>)
8008f8a: 689b ldr r3, [r3, #8]
8008f8c: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
8008f90: 687b ldr r3, [r7, #4]
8008f92: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
8008f94: 4b09 ldr r3, [pc, #36] ; (8008fbc <HAL_RCC_GetClockConfig+0x5c>)
8008f96: 689b ldr r3, [r3, #8]
8008f98: 08db lsrs r3, r3, #3
8008f9a: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
8008f9e: 687b ldr r3, [r7, #4]
8008fa0: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
8008fa2: 4b07 ldr r3, [pc, #28] ; (8008fc0 <HAL_RCC_GetClockConfig+0x60>)
8008fa4: 681b ldr r3, [r3, #0]
8008fa6: f003 020f and.w r2, r3, #15
8008faa: 683b ldr r3, [r7, #0]
8008fac: 601a str r2, [r3, #0]
}
8008fae: bf00 nop
8008fb0: 370c adds r7, #12
8008fb2: 46bd mov sp, r7
8008fb4: f85d 7b04 ldr.w r7, [sp], #4
8008fb8: 4770 bx lr
8008fba: bf00 nop
8008fbc: 40023800 .word 0x40023800
8008fc0: 40023c00 .word 0x40023c00
08008fc4 <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8008fc4: b580 push {r7, lr}
8008fc6: b088 sub sp, #32
8008fc8: af00 add r7, sp, #0
8008fca: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
8008fcc: 2300 movs r3, #0
8008fce: 617b str r3, [r7, #20]
uint32_t tmpreg0 = 0;
8008fd0: 2300 movs r3, #0
8008fd2: 613b str r3, [r7, #16]
uint32_t tmpreg1 = 0;
8008fd4: 2300 movs r3, #0
8008fd6: 60fb str r3, [r7, #12]
uint32_t plli2sused = 0;
8008fd8: 2300 movs r3, #0
8008fda: 61fb str r3, [r7, #28]
uint32_t pllsaiused = 0;
8008fdc: 2300 movs r3, #0
8008fde: 61bb str r3, [r7, #24]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*----------------------------------- I2S configuration ----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
8008fe0: 687b ldr r3, [r7, #4]
8008fe2: 681b ldr r3, [r3, #0]
8008fe4: f003 0301 and.w r3, r3, #1
8008fe8: 2b00 cmp r3, #0
8008fea: d012 beq.n 8009012 <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure I2S Clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
8008fec: 4b69 ldr r3, [pc, #420] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8008fee: 689b ldr r3, [r3, #8]
8008ff0: 4a68 ldr r2, [pc, #416] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8008ff2: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
8008ff6: 6093 str r3, [r2, #8]
8008ff8: 4b66 ldr r3, [pc, #408] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8008ffa: 689a ldr r2, [r3, #8]
8008ffc: 687b ldr r3, [r7, #4]
8008ffe: 6b5b ldr r3, [r3, #52] ; 0x34
8009000: 4964 ldr r1, [pc, #400] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009002: 4313 orrs r3, r2
8009004: 608b str r3, [r1, #8]
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
8009006: 687b ldr r3, [r7, #4]
8009008: 6b5b ldr r3, [r3, #52] ; 0x34
800900a: 2b00 cmp r3, #0
800900c: d101 bne.n 8009012 <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
plli2sused = 1;
800900e: 2301 movs r3, #1
8009010: 61fb str r3, [r7, #28]
}
}
/*------------------------------------ SAI1 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
8009012: 687b ldr r3, [r7, #4]
8009014: 681b ldr r3, [r3, #0]
8009016: f403 2300 and.w r3, r3, #524288 ; 0x80000
800901a: 2b00 cmp r3, #0
800901c: d017 beq.n 800904e <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
800901e: 4b5d ldr r3, [pc, #372] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009020: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8009024: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
8009028: 687b ldr r3, [r7, #4]
800902a: 6bdb ldr r3, [r3, #60] ; 0x3c
800902c: 4959 ldr r1, [pc, #356] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800902e: 4313 orrs r3, r2
8009030: f8c1 308c str.w r3, [r1, #140] ; 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
8009034: 687b ldr r3, [r7, #4]
8009036: 6bdb ldr r3, [r3, #60] ; 0x3c
8009038: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
800903c: d101 bne.n 8009042 <HAL_RCCEx_PeriphCLKConfig+0x7e>
{
plli2sused = 1;
800903e: 2301 movs r3, #1
8009040: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
8009042: 687b ldr r3, [r7, #4]
8009044: 6bdb ldr r3, [r3, #60] ; 0x3c
8009046: 2b00 cmp r3, #0
8009048: d101 bne.n 800904e <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
pllsaiused = 1;
800904a: 2301 movs r3, #1
800904c: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ SAI2 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
800904e: 687b ldr r3, [r7, #4]
8009050: 681b ldr r3, [r3, #0]
8009052: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8009056: 2b00 cmp r3, #0
8009058: d017 beq.n 800908a <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
/* Configure SAI2 Clock source */
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
800905a: 4b4e ldr r3, [pc, #312] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800905c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8009060: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
8009064: 687b ldr r3, [r7, #4]
8009066: 6c1b ldr r3, [r3, #64] ; 0x40
8009068: 494a ldr r1, [pc, #296] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800906a: 4313 orrs r3, r2
800906c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
8009070: 687b ldr r3, [r7, #4]
8009072: 6c1b ldr r3, [r3, #64] ; 0x40
8009074: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8009078: d101 bne.n 800907e <HAL_RCCEx_PeriphCLKConfig+0xba>
{
plli2sused = 1;
800907a: 2301 movs r3, #1
800907c: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
800907e: 687b ldr r3, [r7, #4]
8009080: 6c1b ldr r3, [r3, #64] ; 0x40
8009082: 2b00 cmp r3, #0
8009084: d101 bne.n 800908a <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
pllsaiused = 1;
8009086: 2301 movs r3, #1
8009088: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
800908a: 687b ldr r3, [r7, #4]
800908c: 681b ldr r3, [r3, #0]
800908e: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8009092: 2b00 cmp r3, #0
8009094: d001 beq.n 800909a <HAL_RCCEx_PeriphCLKConfig+0xd6>
{
plli2sused = 1;
8009096: 2301 movs r3, #1
8009098: 61fb str r3, [r7, #28]
}
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
800909a: 687b ldr r3, [r7, #4]
800909c: 681b ldr r3, [r3, #0]
800909e: f003 0320 and.w r3, r3, #32
80090a2: 2b00 cmp r3, #0
80090a4: f000 808b beq.w 80091be <HAL_RCCEx_PeriphCLKConfig+0x1fa>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
80090a8: 4b3a ldr r3, [pc, #232] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80090aa: 6c1b ldr r3, [r3, #64] ; 0x40
80090ac: 4a39 ldr r2, [pc, #228] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80090ae: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80090b2: 6413 str r3, [r2, #64] ; 0x40
80090b4: 4b37 ldr r3, [pc, #220] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80090b6: 6c1b ldr r3, [r3, #64] ; 0x40
80090b8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80090bc: 60bb str r3, [r7, #8]
80090be: 68bb ldr r3, [r7, #8]
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
80090c0: 4b35 ldr r3, [pc, #212] ; (8009198 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
80090c2: 681b ldr r3, [r3, #0]
80090c4: 4a34 ldr r2, [pc, #208] ; (8009198 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
80090c6: f443 7380 orr.w r3, r3, #256 ; 0x100
80090ca: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80090cc: f7fb fb80 bl 80047d0 <HAL_GetTick>
80090d0: 6178 str r0, [r7, #20]
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
80090d2: e008 b.n 80090e6 <HAL_RCCEx_PeriphCLKConfig+0x122>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80090d4: f7fb fb7c bl 80047d0 <HAL_GetTick>
80090d8: 4602 mov r2, r0
80090da: 697b ldr r3, [r7, #20]
80090dc: 1ad3 subs r3, r2, r3
80090de: 2b64 cmp r3, #100 ; 0x64
80090e0: d901 bls.n 80090e6 <HAL_RCCEx_PeriphCLKConfig+0x122>
{
return HAL_TIMEOUT;
80090e2: 2303 movs r3, #3
80090e4: e357 b.n 8009796 <HAL_RCCEx_PeriphCLKConfig+0x7d2>
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
80090e6: 4b2c ldr r3, [pc, #176] ; (8009198 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
80090e8: 681b ldr r3, [r3, #0]
80090ea: f403 7380 and.w r3, r3, #256 ; 0x100
80090ee: 2b00 cmp r3, #0
80090f0: d0f0 beq.n 80090d4 <HAL_RCCEx_PeriphCLKConfig+0x110>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
80090f2: 4b28 ldr r3, [pc, #160] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80090f4: 6f1b ldr r3, [r3, #112] ; 0x70
80090f6: f403 7340 and.w r3, r3, #768 ; 0x300
80090fa: 613b str r3, [r7, #16]
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
80090fc: 693b ldr r3, [r7, #16]
80090fe: 2b00 cmp r3, #0
8009100: d035 beq.n 800916e <HAL_RCCEx_PeriphCLKConfig+0x1aa>
8009102: 687b ldr r3, [r7, #4]
8009104: 6b1b ldr r3, [r3, #48] ; 0x30
8009106: f403 7340 and.w r3, r3, #768 ; 0x300
800910a: 693a ldr r2, [r7, #16]
800910c: 429a cmp r2, r3
800910e: d02e beq.n 800916e <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8009110: 4b20 ldr r3, [pc, #128] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009112: 6f1b ldr r3, [r3, #112] ; 0x70
8009114: f423 7340 bic.w r3, r3, #768 ; 0x300
8009118: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
800911a: 4b1e ldr r3, [pc, #120] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800911c: 6f1b ldr r3, [r3, #112] ; 0x70
800911e: 4a1d ldr r2, [pc, #116] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009120: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8009124: 6713 str r3, [r2, #112] ; 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
8009126: 4b1b ldr r3, [pc, #108] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009128: 6f1b ldr r3, [r3, #112] ; 0x70
800912a: 4a1a ldr r2, [pc, #104] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800912c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8009130: 6713 str r3, [r2, #112] ; 0x70
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
8009132: 4a18 ldr r2, [pc, #96] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009134: 693b ldr r3, [r7, #16]
8009136: 6713 str r3, [r2, #112] ; 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
8009138: 4b16 ldr r3, [pc, #88] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800913a: 6f1b ldr r3, [r3, #112] ; 0x70
800913c: f003 0301 and.w r3, r3, #1
8009140: 2b01 cmp r3, #1
8009142: d114 bne.n 800916e <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8009144: f7fb fb44 bl 80047d0 <HAL_GetTick>
8009148: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800914a: e00a b.n 8009162 <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
800914c: f7fb fb40 bl 80047d0 <HAL_GetTick>
8009150: 4602 mov r2, r0
8009152: 697b ldr r3, [r7, #20]
8009154: 1ad3 subs r3, r2, r3
8009156: f241 3288 movw r2, #5000 ; 0x1388
800915a: 4293 cmp r3, r2
800915c: d901 bls.n 8009162 <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
return HAL_TIMEOUT;
800915e: 2303 movs r3, #3
8009160: e319 b.n 8009796 <HAL_RCCEx_PeriphCLKConfig+0x7d2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8009162: 4b0c ldr r3, [pc, #48] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009164: 6f1b ldr r3, [r3, #112] ; 0x70
8009166: f003 0302 and.w r3, r3, #2
800916a: 2b00 cmp r3, #0
800916c: d0ee beq.n 800914c <HAL_RCCEx_PeriphCLKConfig+0x188>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
800916e: 687b ldr r3, [r7, #4]
8009170: 6b1b ldr r3, [r3, #48] ; 0x30
8009172: f403 7340 and.w r3, r3, #768 ; 0x300
8009176: f5b3 7f40 cmp.w r3, #768 ; 0x300
800917a: d111 bne.n 80091a0 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
800917c: 4b05 ldr r3, [pc, #20] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800917e: 689b ldr r3, [r3, #8]
8009180: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
8009184: 687b ldr r3, [r7, #4]
8009186: 6b19 ldr r1, [r3, #48] ; 0x30
8009188: 4b04 ldr r3, [pc, #16] ; (800919c <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
800918a: 400b ands r3, r1
800918c: 4901 ldr r1, [pc, #4] ; (8009194 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800918e: 4313 orrs r3, r2
8009190: 608b str r3, [r1, #8]
8009192: e00b b.n 80091ac <HAL_RCCEx_PeriphCLKConfig+0x1e8>
8009194: 40023800 .word 0x40023800
8009198: 40007000 .word 0x40007000
800919c: 0ffffcff .word 0x0ffffcff
80091a0: 4bb1 ldr r3, [pc, #708] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80091a2: 689b ldr r3, [r3, #8]
80091a4: 4ab0 ldr r2, [pc, #704] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80091a6: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
80091aa: 6093 str r3, [r2, #8]
80091ac: 4bae ldr r3, [pc, #696] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80091ae: 6f1a ldr r2, [r3, #112] ; 0x70
80091b0: 687b ldr r3, [r7, #4]
80091b2: 6b1b ldr r3, [r3, #48] ; 0x30
80091b4: f3c3 030b ubfx r3, r3, #0, #12
80091b8: 49ab ldr r1, [pc, #684] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80091ba: 4313 orrs r3, r2
80091bc: 670b str r3, [r1, #112] ; 0x70
}
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
80091be: 687b ldr r3, [r7, #4]
80091c0: 681b ldr r3, [r3, #0]
80091c2: f003 0310 and.w r3, r3, #16
80091c6: 2b00 cmp r3, #0
80091c8: d010 beq.n 80091ec <HAL_RCCEx_PeriphCLKConfig+0x228>
{
/* Check the parameters */
assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
80091ca: 4ba7 ldr r3, [pc, #668] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80091cc: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80091d0: 4aa5 ldr r2, [pc, #660] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80091d2: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
80091d6: f8c2 308c str.w r3, [r2, #140] ; 0x8c
80091da: 4ba3 ldr r3, [pc, #652] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80091dc: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
80091e0: 687b ldr r3, [r7, #4]
80091e2: 6b9b ldr r3, [r3, #56] ; 0x38
80091e4: 49a0 ldr r1, [pc, #640] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80091e6: 4313 orrs r3, r2
80091e8: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*-------------------------------------- I2C1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
80091ec: 687b ldr r3, [r7, #4]
80091ee: 681b ldr r3, [r3, #0]
80091f0: f403 4380 and.w r3, r3, #16384 ; 0x4000
80091f4: 2b00 cmp r3, #0
80091f6: d00a beq.n 800920e <HAL_RCCEx_PeriphCLKConfig+0x24a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
80091f8: 4b9b ldr r3, [pc, #620] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80091fa: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80091fe: f423 3240 bic.w r2, r3, #196608 ; 0x30000
8009202: 687b ldr r3, [r7, #4]
8009204: 6e5b ldr r3, [r3, #100] ; 0x64
8009206: 4998 ldr r1, [pc, #608] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
8009208: 4313 orrs r3, r2
800920a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
800920e: 687b ldr r3, [r7, #4]
8009210: 681b ldr r3, [r3, #0]
8009212: f403 4300 and.w r3, r3, #32768 ; 0x8000
8009216: 2b00 cmp r3, #0
8009218: d00a beq.n 8009230 <HAL_RCCEx_PeriphCLKConfig+0x26c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
800921a: 4b93 ldr r3, [pc, #588] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
800921c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009220: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
8009224: 687b ldr r3, [r7, #4]
8009226: 6e9b ldr r3, [r3, #104] ; 0x68
8009228: 498f ldr r1, [pc, #572] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
800922a: 4313 orrs r3, r2
800922c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8009230: 687b ldr r3, [r7, #4]
8009232: 681b ldr r3, [r3, #0]
8009234: f403 3380 and.w r3, r3, #65536 ; 0x10000
8009238: 2b00 cmp r3, #0
800923a: d00a beq.n 8009252 <HAL_RCCEx_PeriphCLKConfig+0x28e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
800923c: 4b8a ldr r3, [pc, #552] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
800923e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009242: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
8009246: 687b ldr r3, [r7, #4]
8009248: 6edb ldr r3, [r3, #108] ; 0x6c
800924a: 4987 ldr r1, [pc, #540] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
800924c: 4313 orrs r3, r2
800924e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
8009252: 687b ldr r3, [r7, #4]
8009254: 681b ldr r3, [r3, #0]
8009256: f403 3300 and.w r3, r3, #131072 ; 0x20000
800925a: 2b00 cmp r3, #0
800925c: d00a beq.n 8009274 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
{
/* Check the parameters */
assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
/* Configure the I2C4 clock source */
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
800925e: 4b82 ldr r3, [pc, #520] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
8009260: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009264: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
8009268: 687b ldr r3, [r7, #4]
800926a: 6f1b ldr r3, [r3, #112] ; 0x70
800926c: 497e ldr r1, [pc, #504] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
800926e: 4313 orrs r3, r2
8009270: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8009274: 687b ldr r3, [r7, #4]
8009276: 681b ldr r3, [r3, #0]
8009278: f003 0340 and.w r3, r3, #64 ; 0x40
800927c: 2b00 cmp r3, #0
800927e: d00a beq.n 8009296 <HAL_RCCEx_PeriphCLKConfig+0x2d2>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8009280: 4b79 ldr r3, [pc, #484] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
8009282: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009286: f023 0203 bic.w r2, r3, #3
800928a: 687b ldr r3, [r7, #4]
800928c: 6c5b ldr r3, [r3, #68] ; 0x44
800928e: 4976 ldr r1, [pc, #472] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
8009290: 4313 orrs r3, r2
8009292: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8009296: 687b ldr r3, [r7, #4]
8009298: 681b ldr r3, [r3, #0]
800929a: f003 0380 and.w r3, r3, #128 ; 0x80
800929e: 2b00 cmp r3, #0
80092a0: d00a beq.n 80092b8 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
80092a2: 4b71 ldr r3, [pc, #452] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80092a4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80092a8: f023 020c bic.w r2, r3, #12
80092ac: 687b ldr r3, [r7, #4]
80092ae: 6c9b ldr r3, [r3, #72] ; 0x48
80092b0: 496d ldr r1, [pc, #436] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80092b2: 4313 orrs r3, r2
80092b4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
80092b8: 687b ldr r3, [r7, #4]
80092ba: 681b ldr r3, [r3, #0]
80092bc: f403 7380 and.w r3, r3, #256 ; 0x100
80092c0: 2b00 cmp r3, #0
80092c2: d00a beq.n 80092da <HAL_RCCEx_PeriphCLKConfig+0x316>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
80092c4: 4b68 ldr r3, [pc, #416] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80092c6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80092ca: f023 0230 bic.w r2, r3, #48 ; 0x30
80092ce: 687b ldr r3, [r7, #4]
80092d0: 6cdb ldr r3, [r3, #76] ; 0x4c
80092d2: 4965 ldr r1, [pc, #404] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80092d4: 4313 orrs r3, r2
80092d6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
80092da: 687b ldr r3, [r7, #4]
80092dc: 681b ldr r3, [r3, #0]
80092de: f403 7300 and.w r3, r3, #512 ; 0x200
80092e2: 2b00 cmp r3, #0
80092e4: d00a beq.n 80092fc <HAL_RCCEx_PeriphCLKConfig+0x338>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
80092e6: 4b60 ldr r3, [pc, #384] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80092e8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80092ec: f023 02c0 bic.w r2, r3, #192 ; 0xc0
80092f0: 687b ldr r3, [r7, #4]
80092f2: 6d1b ldr r3, [r3, #80] ; 0x50
80092f4: 495c ldr r1, [pc, #368] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80092f6: 4313 orrs r3, r2
80092f8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART5 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
80092fc: 687b ldr r3, [r7, #4]
80092fe: 681b ldr r3, [r3, #0]
8009300: f403 6380 and.w r3, r3, #1024 ; 0x400
8009304: 2b00 cmp r3, #0
8009306: d00a beq.n 800931e <HAL_RCCEx_PeriphCLKConfig+0x35a>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
8009308: 4b57 ldr r3, [pc, #348] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
800930a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800930e: f423 7240 bic.w r2, r3, #768 ; 0x300
8009312: 687b ldr r3, [r7, #4]
8009314: 6d5b ldr r3, [r3, #84] ; 0x54
8009316: 4954 ldr r1, [pc, #336] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
8009318: 4313 orrs r3, r2
800931a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART6 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
800931e: 687b ldr r3, [r7, #4]
8009320: 681b ldr r3, [r3, #0]
8009322: f403 6300 and.w r3, r3, #2048 ; 0x800
8009326: 2b00 cmp r3, #0
8009328: d00a beq.n 8009340 <HAL_RCCEx_PeriphCLKConfig+0x37c>
{
/* Check the parameters */
assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
/* Configure the USART6 clock source */
__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
800932a: 4b4f ldr r3, [pc, #316] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
800932c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009330: f423 6240 bic.w r2, r3, #3072 ; 0xc00
8009334: 687b ldr r3, [r7, #4]
8009336: 6d9b ldr r3, [r3, #88] ; 0x58
8009338: 494b ldr r1, [pc, #300] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
800933a: 4313 orrs r3, r2
800933c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART7 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
8009340: 687b ldr r3, [r7, #4]
8009342: 681b ldr r3, [r3, #0]
8009344: f403 5380 and.w r3, r3, #4096 ; 0x1000
8009348: 2b00 cmp r3, #0
800934a: d00a beq.n 8009362 <HAL_RCCEx_PeriphCLKConfig+0x39e>
{
/* Check the parameters */
assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
/* Configure the UART7 clock source */
__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
800934c: 4b46 ldr r3, [pc, #280] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
800934e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009352: f423 5240 bic.w r2, r3, #12288 ; 0x3000
8009356: 687b ldr r3, [r7, #4]
8009358: 6ddb ldr r3, [r3, #92] ; 0x5c
800935a: 4943 ldr r1, [pc, #268] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
800935c: 4313 orrs r3, r2
800935e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART8 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
8009362: 687b ldr r3, [r7, #4]
8009364: 681b ldr r3, [r3, #0]
8009366: f403 5300 and.w r3, r3, #8192 ; 0x2000
800936a: 2b00 cmp r3, #0
800936c: d00a beq.n 8009384 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
{
/* Check the parameters */
assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
/* Configure the UART8 clock source */
__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
800936e: 4b3e ldr r3, [pc, #248] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
8009370: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009374: f423 4240 bic.w r2, r3, #49152 ; 0xc000
8009378: 687b ldr r3, [r7, #4]
800937a: 6e1b ldr r3, [r3, #96] ; 0x60
800937c: 493a ldr r1, [pc, #232] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
800937e: 4313 orrs r3, r2
8009380: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*--------------------------------------- CEC Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
8009384: 687b ldr r3, [r7, #4]
8009386: 681b ldr r3, [r3, #0]
8009388: f403 0380 and.w r3, r3, #4194304 ; 0x400000
800938c: 2b00 cmp r3, #0
800938e: d00a beq.n 80093a6 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
{
/* Check the parameters */
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
/* Configure the CEC clock source */
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
8009390: 4b35 ldr r3, [pc, #212] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
8009392: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009396: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
800939a: 687b ldr r3, [r7, #4]
800939c: 6f9b ldr r3, [r3, #120] ; 0x78
800939e: 4932 ldr r1, [pc, #200] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80093a0: 4313 orrs r3, r2
80093a2: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- CK48 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
80093a6: 687b ldr r3, [r7, #4]
80093a8: 681b ldr r3, [r3, #0]
80093aa: f403 1300 and.w r3, r3, #2097152 ; 0x200000
80093ae: 2b00 cmp r3, #0
80093b0: d011 beq.n 80093d6 <HAL_RCCEx_PeriphCLKConfig+0x412>
{
/* Check the parameters */
assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
/* Configure the CLK48 source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
80093b2: 4b2d ldr r3, [pc, #180] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80093b4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80093b8: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
80093bc: 687b ldr r3, [r7, #4]
80093be: 6fdb ldr r3, [r3, #124] ; 0x7c
80093c0: 4929 ldr r1, [pc, #164] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80093c2: 4313 orrs r3, r2
80093c4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
/* Enable the PLLSAI when it's used as clock source for CK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
80093c8: 687b ldr r3, [r7, #4]
80093ca: 6fdb ldr r3, [r3, #124] ; 0x7c
80093cc: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
80093d0: d101 bne.n 80093d6 <HAL_RCCEx_PeriphCLKConfig+0x412>
{
pllsaiused = 1;
80093d2: 2301 movs r3, #1
80093d4: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- LTDC Configuration -----------------------------------*/
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
80093d6: 687b ldr r3, [r7, #4]
80093d8: 681b ldr r3, [r3, #0]
80093da: f003 0308 and.w r3, r3, #8
80093de: 2b00 cmp r3, #0
80093e0: d001 beq.n 80093e6 <HAL_RCCEx_PeriphCLKConfig+0x422>
{
pllsaiused = 1;
80093e2: 2301 movs r3, #1
80093e4: 61bb str r3, [r7, #24]
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
80093e6: 687b ldr r3, [r7, #4]
80093e8: 681b ldr r3, [r3, #0]
80093ea: f403 2380 and.w r3, r3, #262144 ; 0x40000
80093ee: 2b00 cmp r3, #0
80093f0: d00a beq.n 8009408 <HAL_RCCEx_PeriphCLKConfig+0x444>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LTPIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
80093f2: 4b1d ldr r3, [pc, #116] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
80093f4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80093f8: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
80093fc: 687b ldr r3, [r7, #4]
80093fe: 6f5b ldr r3, [r3, #116] ; 0x74
8009400: 4919 ldr r1, [pc, #100] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
8009402: 4313 orrs r3, r2
8009404: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*------------------------------------- SDMMC1 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
8009408: 687b ldr r3, [r7, #4]
800940a: 681b ldr r3, [r3, #0]
800940c: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8009410: 2b00 cmp r3, #0
8009412: d00b beq.n 800942c <HAL_RCCEx_PeriphCLKConfig+0x468>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
/* Configure the SDMMC1 clock source */
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
8009414: 4b14 ldr r3, [pc, #80] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
8009416: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800941a: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
800941e: 687b ldr r3, [r7, #4]
8009420: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8009424: 4910 ldr r1, [pc, #64] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
8009426: 4313 orrs r3, r2
8009428: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
800942c: 69fb ldr r3, [r7, #28]
800942e: 2b01 cmp r3, #1
8009430: d006 beq.n 8009440 <HAL_RCCEx_PeriphCLKConfig+0x47c>
8009432: 687b ldr r3, [r7, #4]
8009434: 681b ldr r3, [r3, #0]
8009436: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800943a: 2b00 cmp r3, #0
800943c: f000 80d9 beq.w 80095f2 <HAL_RCCEx_PeriphCLKConfig+0x62e>
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
8009440: 4b09 ldr r3, [pc, #36] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
8009442: 681b ldr r3, [r3, #0]
8009444: 4a08 ldr r2, [pc, #32] ; (8009468 <HAL_RCCEx_PeriphCLKConfig+0x4a4>)
8009446: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
800944a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800944c: f7fb f9c0 bl 80047d0 <HAL_GetTick>
8009450: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8009452: e00b b.n 800946c <HAL_RCCEx_PeriphCLKConfig+0x4a8>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8009454: f7fb f9bc bl 80047d0 <HAL_GetTick>
8009458: 4602 mov r2, r0
800945a: 697b ldr r3, [r7, #20]
800945c: 1ad3 subs r3, r2, r3
800945e: 2b64 cmp r3, #100 ; 0x64
8009460: d904 bls.n 800946c <HAL_RCCEx_PeriphCLKConfig+0x4a8>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8009462: 2303 movs r3, #3
8009464: e197 b.n 8009796 <HAL_RCCEx_PeriphCLKConfig+0x7d2>
8009466: bf00 nop
8009468: 40023800 .word 0x40023800
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
800946c: 4b6c ldr r3, [pc, #432] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
800946e: 681b ldr r3, [r3, #0]
8009470: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8009474: 2b00 cmp r3, #0
8009476: d1ed bne.n 8009454 <HAL_RCCEx_PeriphCLKConfig+0x490>
/* check for common PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
8009478: 687b ldr r3, [r7, #4]
800947a: 681b ldr r3, [r3, #0]
800947c: f003 0301 and.w r3, r3, #1
8009480: 2b00 cmp r3, #0
8009482: d021 beq.n 80094c8 <HAL_RCCEx_PeriphCLKConfig+0x504>
8009484: 687b ldr r3, [r7, #4]
8009486: 6b5b ldr r3, [r3, #52] ; 0x34
8009488: 2b00 cmp r3, #0
800948a: d11d bne.n 80094c8 <HAL_RCCEx_PeriphCLKConfig+0x504>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
800948c: 4b64 ldr r3, [pc, #400] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
800948e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8009492: 0c1b lsrs r3, r3, #16
8009494: f003 0303 and.w r3, r3, #3
8009498: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
800949a: 4b61 ldr r3, [pc, #388] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
800949c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
80094a0: 0e1b lsrs r3, r3, #24
80094a2: f003 030f and.w r3, r3, #15
80094a6: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
80094a8: 687b ldr r3, [r7, #4]
80094aa: 685b ldr r3, [r3, #4]
80094ac: 019a lsls r2, r3, #6
80094ae: 693b ldr r3, [r7, #16]
80094b0: 041b lsls r3, r3, #16
80094b2: 431a orrs r2, r3
80094b4: 68fb ldr r3, [r7, #12]
80094b6: 061b lsls r3, r3, #24
80094b8: 431a orrs r2, r3
80094ba: 687b ldr r3, [r7, #4]
80094bc: 689b ldr r3, [r3, #8]
80094be: 071b lsls r3, r3, #28
80094c0: 4957 ldr r1, [pc, #348] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
80094c2: 4313 orrs r3, r2
80094c4: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
80094c8: 687b ldr r3, [r7, #4]
80094ca: 681b ldr r3, [r3, #0]
80094cc: f403 2300 and.w r3, r3, #524288 ; 0x80000
80094d0: 2b00 cmp r3, #0
80094d2: d004 beq.n 80094de <HAL_RCCEx_PeriphCLKConfig+0x51a>
80094d4: 687b ldr r3, [r7, #4]
80094d6: 6bdb ldr r3, [r3, #60] ; 0x3c
80094d8: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
80094dc: d00a beq.n 80094f4 <HAL_RCCEx_PeriphCLKConfig+0x530>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
80094de: 687b ldr r3, [r7, #4]
80094e0: 681b ldr r3, [r3, #0]
80094e2: f403 1380 and.w r3, r3, #1048576 ; 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
80094e6: 2b00 cmp r3, #0
80094e8: d02e beq.n 8009548 <HAL_RCCEx_PeriphCLKConfig+0x584>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
80094ea: 687b ldr r3, [r7, #4]
80094ec: 6c1b ldr r3, [r3, #64] ; 0x40
80094ee: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
80094f2: d129 bne.n 8009548 <HAL_RCCEx_PeriphCLKConfig+0x584>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
80094f4: 4b4a ldr r3, [pc, #296] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
80094f6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
80094fa: 0c1b lsrs r3, r3, #16
80094fc: f003 0303 and.w r3, r3, #3
8009500: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
8009502: 4b47 ldr r3, [pc, #284] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
8009504: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8009508: 0f1b lsrs r3, r3, #28
800950a: f003 0307 and.w r3, r3, #7
800950e: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
8009510: 687b ldr r3, [r7, #4]
8009512: 685b ldr r3, [r3, #4]
8009514: 019a lsls r2, r3, #6
8009516: 693b ldr r3, [r7, #16]
8009518: 041b lsls r3, r3, #16
800951a: 431a orrs r2, r3
800951c: 687b ldr r3, [r7, #4]
800951e: 68db ldr r3, [r3, #12]
8009520: 061b lsls r3, r3, #24
8009522: 431a orrs r2, r3
8009524: 68fb ldr r3, [r7, #12]
8009526: 071b lsls r3, r3, #28
8009528: 493d ldr r1, [pc, #244] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
800952a: 4313 orrs r3, r2
800952c: f8c1 3084 str.w r3, [r1, #132] ; 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
8009530: 4b3b ldr r3, [pc, #236] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
8009532: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8009536: f023 021f bic.w r2, r3, #31
800953a: 687b ldr r3, [r7, #4]
800953c: 6a5b ldr r3, [r3, #36] ; 0x24
800953e: 3b01 subs r3, #1
8009540: 4937 ldr r1, [pc, #220] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
8009542: 4313 orrs r3, r2
8009544: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
8009548: 687b ldr r3, [r7, #4]
800954a: 681b ldr r3, [r3, #0]
800954c: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8009550: 2b00 cmp r3, #0
8009552: d01d beq.n 8009590 <HAL_RCCEx_PeriphCLKConfig+0x5cc>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
8009554: 4b32 ldr r3, [pc, #200] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
8009556: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
800955a: 0e1b lsrs r3, r3, #24
800955c: f003 030f and.w r3, r3, #15
8009560: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
8009562: 4b2f ldr r3, [pc, #188] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
8009564: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8009568: 0f1b lsrs r3, r3, #28
800956a: f003 0307 and.w r3, r3, #7
800956e: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
8009570: 687b ldr r3, [r7, #4]
8009572: 685b ldr r3, [r3, #4]
8009574: 019a lsls r2, r3, #6
8009576: 687b ldr r3, [r7, #4]
8009578: 691b ldr r3, [r3, #16]
800957a: 041b lsls r3, r3, #16
800957c: 431a orrs r2, r3
800957e: 693b ldr r3, [r7, #16]
8009580: 061b lsls r3, r3, #24
8009582: 431a orrs r2, r3
8009584: 68fb ldr r3, [r7, #12]
8009586: 071b lsls r3, r3, #28
8009588: 4925 ldr r1, [pc, #148] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
800958a: 4313 orrs r3, r2
800958c: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
8009590: 687b ldr r3, [r7, #4]
8009592: 681b ldr r3, [r3, #0]
8009594: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8009598: 2b00 cmp r3, #0
800959a: d011 beq.n 80095c0 <HAL_RCCEx_PeriphCLKConfig+0x5fc>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
800959c: 687b ldr r3, [r7, #4]
800959e: 685b ldr r3, [r3, #4]
80095a0: 019a lsls r2, r3, #6
80095a2: 687b ldr r3, [r7, #4]
80095a4: 691b ldr r3, [r3, #16]
80095a6: 041b lsls r3, r3, #16
80095a8: 431a orrs r2, r3
80095aa: 687b ldr r3, [r7, #4]
80095ac: 68db ldr r3, [r3, #12]
80095ae: 061b lsls r3, r3, #24
80095b0: 431a orrs r2, r3
80095b2: 687b ldr r3, [r7, #4]
80095b4: 689b ldr r3, [r3, #8]
80095b6: 071b lsls r3, r3, #28
80095b8: 4919 ldr r1, [pc, #100] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
80095ba: 4313 orrs r3, r2
80095bc: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
80095c0: 4b17 ldr r3, [pc, #92] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
80095c2: 681b ldr r3, [r3, #0]
80095c4: 4a16 ldr r2, [pc, #88] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
80095c6: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
80095ca: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80095cc: f7fb f900 bl 80047d0 <HAL_GetTick>
80095d0: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
80095d2: e008 b.n 80095e6 <HAL_RCCEx_PeriphCLKConfig+0x622>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
80095d4: f7fb f8fc bl 80047d0 <HAL_GetTick>
80095d8: 4602 mov r2, r0
80095da: 697b ldr r3, [r7, #20]
80095dc: 1ad3 subs r3, r2, r3
80095de: 2b64 cmp r3, #100 ; 0x64
80095e0: d901 bls.n 80095e6 <HAL_RCCEx_PeriphCLKConfig+0x622>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
80095e2: 2303 movs r3, #3
80095e4: e0d7 b.n 8009796 <HAL_RCCEx_PeriphCLKConfig+0x7d2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
80095e6: 4b0e ldr r3, [pc, #56] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
80095e8: 681b ldr r3, [r3, #0]
80095ea: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
80095ee: 2b00 cmp r3, #0
80095f0: d0f0 beq.n 80095d4 <HAL_RCCEx_PeriphCLKConfig+0x610>
}
}
/*-------------------------------------- PLLSAI Configuration ---------------------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
if(pllsaiused == 1)
80095f2: 69bb ldr r3, [r7, #24]
80095f4: 2b01 cmp r3, #1
80095f6: f040 80cd bne.w 8009794 <HAL_RCCEx_PeriphCLKConfig+0x7d0>
{
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
80095fa: 4b09 ldr r3, [pc, #36] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
80095fc: 681b ldr r3, [r3, #0]
80095fe: 4a08 ldr r2, [pc, #32] ; (8009620 <HAL_RCCEx_PeriphCLKConfig+0x65c>)
8009600: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8009604: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8009606: f7fb f8e3 bl 80047d0 <HAL_GetTick>
800960a: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
800960c: e00a b.n 8009624 <HAL_RCCEx_PeriphCLKConfig+0x660>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
800960e: f7fb f8df bl 80047d0 <HAL_GetTick>
8009612: 4602 mov r2, r0
8009614: 697b ldr r3, [r7, #20]
8009616: 1ad3 subs r3, r2, r3
8009618: 2b64 cmp r3, #100 ; 0x64
800961a: d903 bls.n 8009624 <HAL_RCCEx_PeriphCLKConfig+0x660>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
800961c: 2303 movs r3, #3
800961e: e0ba b.n 8009796 <HAL_RCCEx_PeriphCLKConfig+0x7d2>
8009620: 40023800 .word 0x40023800
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
8009624: 4b5e ldr r3, [pc, #376] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
8009626: 681b ldr r3, [r3, #0]
8009628: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
800962c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
8009630: d0ed beq.n 800960e <HAL_RCCEx_PeriphCLKConfig+0x64a>
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
8009632: 687b ldr r3, [r7, #4]
8009634: 681b ldr r3, [r3, #0]
8009636: f403 2300 and.w r3, r3, #524288 ; 0x80000
800963a: 2b00 cmp r3, #0
800963c: d003 beq.n 8009646 <HAL_RCCEx_PeriphCLKConfig+0x682>
800963e: 687b ldr r3, [r7, #4]
8009640: 6bdb ldr r3, [r3, #60] ; 0x3c
8009642: 2b00 cmp r3, #0
8009644: d009 beq.n 800965a <HAL_RCCEx_PeriphCLKConfig+0x696>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
8009646: 687b ldr r3, [r7, #4]
8009648: 681b ldr r3, [r3, #0]
800964a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
800964e: 2b00 cmp r3, #0
8009650: d02e beq.n 80096b0 <HAL_RCCEx_PeriphCLKConfig+0x6ec>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
8009652: 687b ldr r3, [r7, #4]
8009654: 6c1b ldr r3, [r3, #64] ; 0x40
8009656: 2b00 cmp r3, #0
8009658: d12a bne.n 80096b0 <HAL_RCCEx_PeriphCLKConfig+0x6ec>
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
/* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
800965a: 4b51 ldr r3, [pc, #324] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
800965c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8009660: 0c1b lsrs r3, r3, #16
8009662: f003 0303 and.w r3, r3, #3
8009666: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
8009668: 4b4d ldr r3, [pc, #308] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
800966a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800966e: 0f1b lsrs r3, r3, #28
8009670: f003 0307 and.w r3, r3, #7
8009674: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
8009676: 687b ldr r3, [r7, #4]
8009678: 695b ldr r3, [r3, #20]
800967a: 019a lsls r2, r3, #6
800967c: 693b ldr r3, [r7, #16]
800967e: 041b lsls r3, r3, #16
8009680: 431a orrs r2, r3
8009682: 687b ldr r3, [r7, #4]
8009684: 699b ldr r3, [r3, #24]
8009686: 061b lsls r3, r3, #24
8009688: 431a orrs r2, r3
800968a: 68fb ldr r3, [r7, #12]
800968c: 071b lsls r3, r3, #28
800968e: 4944 ldr r1, [pc, #272] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
8009690: 4313 orrs r3, r2
8009692: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
8009696: 4b42 ldr r3, [pc, #264] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
8009698: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
800969c: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
80096a0: 687b ldr r3, [r7, #4]
80096a2: 6a9b ldr r3, [r3, #40] ; 0x28
80096a4: 3b01 subs r3, #1
80096a6: 021b lsls r3, r3, #8
80096a8: 493d ldr r1, [pc, #244] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
80096aa: 4313 orrs r3, r2
80096ac: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
/* In Case of PLLI2S is selected as source clock for CK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
80096b0: 687b ldr r3, [r7, #4]
80096b2: 681b ldr r3, [r3, #0]
80096b4: f403 1300 and.w r3, r3, #2097152 ; 0x200000
80096b8: 2b00 cmp r3, #0
80096ba: d022 beq.n 8009702 <HAL_RCCEx_PeriphCLKConfig+0x73e>
80096bc: 687b ldr r3, [r7, #4]
80096be: 6fdb ldr r3, [r3, #124] ; 0x7c
80096c0: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
80096c4: d11d bne.n 8009702 <HAL_RCCEx_PeriphCLKConfig+0x73e>
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
80096c6: 4b36 ldr r3, [pc, #216] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
80096c8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80096cc: 0e1b lsrs r3, r3, #24
80096ce: f003 030f and.w r3, r3, #15
80096d2: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
80096d4: 4b32 ldr r3, [pc, #200] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
80096d6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80096da: 0f1b lsrs r3, r3, #28
80096dc: f003 0307 and.w r3, r3, #7
80096e0: 60fb str r3, [r7, #12]
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
80096e2: 687b ldr r3, [r7, #4]
80096e4: 695b ldr r3, [r3, #20]
80096e6: 019a lsls r2, r3, #6
80096e8: 687b ldr r3, [r7, #4]
80096ea: 6a1b ldr r3, [r3, #32]
80096ec: 041b lsls r3, r3, #16
80096ee: 431a orrs r2, r3
80096f0: 693b ldr r3, [r7, #16]
80096f2: 061b lsls r3, r3, #24
80096f4: 431a orrs r2, r3
80096f6: 68fb ldr r3, [r7, #12]
80096f8: 071b lsls r3, r3, #28
80096fa: 4929 ldr r1, [pc, #164] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
80096fc: 4313 orrs r3, r2
80096fe: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/*---------------------------- LTDC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
8009702: 687b ldr r3, [r7, #4]
8009704: 681b ldr r3, [r3, #0]
8009706: f003 0308 and.w r3, r3, #8
800970a: 2b00 cmp r3, #0
800970c: d028 beq.n 8009760 <HAL_RCCEx_PeriphCLKConfig+0x79c>
{
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
/* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
800970e: 4b24 ldr r3, [pc, #144] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
8009710: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8009714: 0e1b lsrs r3, r3, #24
8009716: f003 030f and.w r3, r3, #15
800971a: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
800971c: 4b20 ldr r3, [pc, #128] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
800971e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8009722: 0c1b lsrs r3, r3, #16
8009724: f003 0303 and.w r3, r3, #3
8009728: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
800972a: 687b ldr r3, [r7, #4]
800972c: 695b ldr r3, [r3, #20]
800972e: 019a lsls r2, r3, #6
8009730: 68fb ldr r3, [r7, #12]
8009732: 041b lsls r3, r3, #16
8009734: 431a orrs r2, r3
8009736: 693b ldr r3, [r7, #16]
8009738: 061b lsls r3, r3, #24
800973a: 431a orrs r2, r3
800973c: 687b ldr r3, [r7, #4]
800973e: 69db ldr r3, [r3, #28]
8009740: 071b lsls r3, r3, #28
8009742: 4917 ldr r1, [pc, #92] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
8009744: 4313 orrs r3, r2
8009746: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
800974a: 4b15 ldr r3, [pc, #84] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
800974c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8009750: f423 3240 bic.w r2, r3, #196608 ; 0x30000
8009754: 687b ldr r3, [r7, #4]
8009756: 6adb ldr r3, [r3, #44] ; 0x2c
8009758: 4911 ldr r1, [pc, #68] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
800975a: 4313 orrs r3, r2
800975c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
8009760: 4b0f ldr r3, [pc, #60] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
8009762: 681b ldr r3, [r3, #0]
8009764: 4a0e ldr r2, [pc, #56] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
8009766: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
800976a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800976c: f7fb f830 bl 80047d0 <HAL_GetTick>
8009770: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8009772: e008 b.n 8009786 <HAL_RCCEx_PeriphCLKConfig+0x7c2>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
8009774: f7fb f82c bl 80047d0 <HAL_GetTick>
8009778: 4602 mov r2, r0
800977a: 697b ldr r3, [r7, #20]
800977c: 1ad3 subs r3, r2, r3
800977e: 2b64 cmp r3, #100 ; 0x64
8009780: d901 bls.n 8009786 <HAL_RCCEx_PeriphCLKConfig+0x7c2>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8009782: 2303 movs r3, #3
8009784: e007 b.n 8009796 <HAL_RCCEx_PeriphCLKConfig+0x7d2>
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8009786: 4b06 ldr r3, [pc, #24] ; (80097a0 <HAL_RCCEx_PeriphCLKConfig+0x7dc>)
8009788: 681b ldr r3, [r3, #0]
800978a: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
800978e: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
8009792: d1ef bne.n 8009774 <HAL_RCCEx_PeriphCLKConfig+0x7b0>
}
}
}
return HAL_OK;
8009794: 2300 movs r3, #0
}
8009796: 4618 mov r0, r3
8009798: 3720 adds r7, #32
800979a: 46bd mov sp, r7
800979c: bd80 pop {r7, pc}
800979e: bf00 nop
80097a0: 40023800 .word 0x40023800
080097a4 <HAL_RNG_Init>:
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
80097a4: b580 push {r7, lr}
80097a6: b082 sub sp, #8
80097a8: af00 add r7, sp, #0
80097aa: 6078 str r0, [r7, #4]
/* Check the RNG handle allocation */
if (hrng == NULL)
80097ac: 687b ldr r3, [r7, #4]
80097ae: 2b00 cmp r3, #0
80097b0: d101 bne.n 80097b6 <HAL_RNG_Init+0x12>
{
return HAL_ERROR;
80097b2: 2301 movs r3, #1
80097b4: e01c b.n 80097f0 <HAL_RNG_Init+0x4c>
/* Init the low level hardware */
hrng->MspInitCallback(hrng);
}
#else
if (hrng->State == HAL_RNG_STATE_RESET)
80097b6: 687b ldr r3, [r7, #4]
80097b8: 795b ldrb r3, [r3, #5]
80097ba: b2db uxtb r3, r3
80097bc: 2b00 cmp r3, #0
80097be: d105 bne.n 80097cc <HAL_RNG_Init+0x28>
{
/* Allocate lock resource and initialize it */
hrng->Lock = HAL_UNLOCKED;
80097c0: 687b ldr r3, [r7, #4]
80097c2: 2200 movs r2, #0
80097c4: 711a strb r2, [r3, #4]
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
80097c6: 6878 ldr r0, [r7, #4]
80097c8: f7fa fcbc bl 8004144 <HAL_RNG_MspInit>
}
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
80097cc: 687b ldr r3, [r7, #4]
80097ce: 2202 movs r2, #2
80097d0: 715a strb r2, [r3, #5]
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
80097d2: 687b ldr r3, [r7, #4]
80097d4: 681b ldr r3, [r3, #0]
80097d6: 681a ldr r2, [r3, #0]
80097d8: 687b ldr r3, [r7, #4]
80097da: 681b ldr r3, [r3, #0]
80097dc: f042 0204 orr.w r2, r2, #4
80097e0: 601a str r2, [r3, #0]
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
80097e2: 687b ldr r3, [r7, #4]
80097e4: 2201 movs r2, #1
80097e6: 715a strb r2, [r3, #5]
/* Initialise the error code */
hrng->ErrorCode = HAL_RNG_ERROR_NONE;
80097e8: 687b ldr r3, [r7, #4]
80097ea: 2200 movs r2, #0
80097ec: 609a str r2, [r3, #8]
/* Return function status */
return HAL_OK;
80097ee: 2300 movs r3, #0
}
80097f0: 4618 mov r0, r3
80097f2: 3708 adds r7, #8
80097f4: 46bd mov sp, r7
80097f6: bd80 pop {r7, pc}
080097f8 <HAL_RNG_GenerateRandomNumber>:
* @param random32bit pointer to generated random number variable if successful.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
{
80097f8: b580 push {r7, lr}
80097fa: b084 sub sp, #16
80097fc: af00 add r7, sp, #0
80097fe: 6078 str r0, [r7, #4]
8009800: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
8009802: 2300 movs r3, #0
8009804: 73fb strb r3, [r7, #15]
/* Process Locked */
__HAL_LOCK(hrng);
8009806: 687b ldr r3, [r7, #4]
8009808: 791b ldrb r3, [r3, #4]
800980a: 2b01 cmp r3, #1
800980c: d101 bne.n 8009812 <HAL_RNG_GenerateRandomNumber+0x1a>
800980e: 2302 movs r3, #2
8009810: e03d b.n 800988e <HAL_RNG_GenerateRandomNumber+0x96>
8009812: 687b ldr r3, [r7, #4]
8009814: 2201 movs r2, #1
8009816: 711a strb r2, [r3, #4]
/* Check RNG peripheral state */
if (hrng->State == HAL_RNG_STATE_READY)
8009818: 687b ldr r3, [r7, #4]
800981a: 795b ldrb r3, [r3, #5]
800981c: b2db uxtb r3, r3
800981e: 2b01 cmp r3, #1
8009820: d12c bne.n 800987c <HAL_RNG_GenerateRandomNumber+0x84>
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
8009822: 687b ldr r3, [r7, #4]
8009824: 2202 movs r2, #2
8009826: 715a strb r2, [r3, #5]
/* Get tick */
tickstart = HAL_GetTick();
8009828: f7fa ffd2 bl 80047d0 <HAL_GetTick>
800982c: 60b8 str r0, [r7, #8]
/* Check if data register contains valid random data */
while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
800982e: e011 b.n 8009854 <HAL_RNG_GenerateRandomNumber+0x5c>
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
8009830: f7fa ffce bl 80047d0 <HAL_GetTick>
8009834: 4602 mov r2, r0
8009836: 68bb ldr r3, [r7, #8]
8009838: 1ad3 subs r3, r2, r3
800983a: 2b02 cmp r3, #2
800983c: d90a bls.n 8009854 <HAL_RNG_GenerateRandomNumber+0x5c>
{
hrng->State = HAL_RNG_STATE_READY;
800983e: 687b ldr r3, [r7, #4]
8009840: 2201 movs r2, #1
8009842: 715a strb r2, [r3, #5]
hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
8009844: 687b ldr r3, [r7, #4]
8009846: 2202 movs r2, #2
8009848: 609a str r2, [r3, #8]
/* Process Unlocked */
__HAL_UNLOCK(hrng);
800984a: 687b ldr r3, [r7, #4]
800984c: 2200 movs r2, #0
800984e: 711a strb r2, [r3, #4]
return HAL_ERROR;
8009850: 2301 movs r3, #1
8009852: e01c b.n 800988e <HAL_RNG_GenerateRandomNumber+0x96>
while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
8009854: 687b ldr r3, [r7, #4]
8009856: 681b ldr r3, [r3, #0]
8009858: 685b ldr r3, [r3, #4]
800985a: f003 0301 and.w r3, r3, #1
800985e: 2b01 cmp r3, #1
8009860: d1e6 bne.n 8009830 <HAL_RNG_GenerateRandomNumber+0x38>
}
}
/* Get a 32bit Random number */
hrng->RandomNumber = hrng->Instance->DR;
8009862: 687b ldr r3, [r7, #4]
8009864: 681b ldr r3, [r3, #0]
8009866: 689a ldr r2, [r3, #8]
8009868: 687b ldr r3, [r7, #4]
800986a: 60da str r2, [r3, #12]
*random32bit = hrng->RandomNumber;
800986c: 687b ldr r3, [r7, #4]
800986e: 68da ldr r2, [r3, #12]
8009870: 683b ldr r3, [r7, #0]
8009872: 601a str r2, [r3, #0]
hrng->State = HAL_RNG_STATE_READY;
8009874: 687b ldr r3, [r7, #4]
8009876: 2201 movs r2, #1
8009878: 715a strb r2, [r3, #5]
800987a: e004 b.n 8009886 <HAL_RNG_GenerateRandomNumber+0x8e>
}
else
{
hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
800987c: 687b ldr r3, [r7, #4]
800987e: 2204 movs r2, #4
8009880: 609a str r2, [r3, #8]
status = HAL_ERROR;
8009882: 2301 movs r3, #1
8009884: 73fb strb r3, [r7, #15]
}
/* Process Unlocked */
__HAL_UNLOCK(hrng);
8009886: 687b ldr r3, [r7, #4]
8009888: 2200 movs r2, #0
800988a: 711a strb r2, [r3, #4]
return status;
800988c: 7bfb ldrb r3, [r7, #15]
}
800988e: 4618 mov r0, r3
8009890: 3710 adds r7, #16
8009892: 46bd mov sp, r7
8009894: bd80 pop {r7, pc}
08009896 <HAL_SDRAM_Init>:
* the configuration information for SDRAM module.
* @param Timing Pointer to SDRAM control timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
{
8009896: b580 push {r7, lr}
8009898: b082 sub sp, #8
800989a: af00 add r7, sp, #0
800989c: 6078 str r0, [r7, #4]
800989e: 6039 str r1, [r7, #0]
/* Check the SDRAM handle parameter */
if(hsdram == NULL)
80098a0: 687b ldr r3, [r7, #4]
80098a2: 2b00 cmp r3, #0
80098a4: d101 bne.n 80098aa <HAL_SDRAM_Init+0x14>
{
return HAL_ERROR;
80098a6: 2301 movs r3, #1
80098a8: e025 b.n 80098f6 <HAL_SDRAM_Init+0x60>
}
if(hsdram->State == HAL_SDRAM_STATE_RESET)
80098aa: 687b ldr r3, [r7, #4]
80098ac: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
80098b0: b2db uxtb r3, r3
80098b2: 2b00 cmp r3, #0
80098b4: d106 bne.n 80098c4 <HAL_SDRAM_Init+0x2e>
{
/* Allocate lock resource and initialize it */
hsdram->Lock = HAL_UNLOCKED;
80098b6: 687b ldr r3, [r7, #4]
80098b8: 2200 movs r2, #0
80098ba: f883 202d strb.w r2, [r3, #45] ; 0x2d
/* Init the low level hardware */
hsdram->MspInitCallback(hsdram);
#else
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
80098be: 6878 ldr r0, [r7, #4]
80098c0: f7fa fdbc bl 800443c <HAL_SDRAM_MspInit>
#endif
}
/* Initialize the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
80098c4: 687b ldr r3, [r7, #4]
80098c6: 2202 movs r2, #2
80098c8: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Initialize SDRAM control Interface */
FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
80098cc: 687b ldr r3, [r7, #4]
80098ce: 681a ldr r2, [r3, #0]
80098d0: 687b ldr r3, [r7, #4]
80098d2: 3304 adds r3, #4
80098d4: 4619 mov r1, r3
80098d6: 4610 mov r0, r2
80098d8: f001 fa3e bl 800ad58 <FMC_SDRAM_Init>
/* Initialize SDRAM timing Interface */
FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
80098dc: 687b ldr r3, [r7, #4]
80098de: 6818 ldr r0, [r3, #0]
80098e0: 687b ldr r3, [r7, #4]
80098e2: 685b ldr r3, [r3, #4]
80098e4: 461a mov r2, r3
80098e6: 6839 ldr r1, [r7, #0]
80098e8: f001 faa8 bl 800ae3c <FMC_SDRAM_Timing_Init>
/* Update the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_READY;
80098ec: 687b ldr r3, [r7, #4]
80098ee: 2201 movs r2, #1
80098f0: f883 202c strb.w r2, [r3, #44] ; 0x2c
return HAL_OK;
80098f4: 2300 movs r3, #0
}
80098f6: 4618 mov r0, r3
80098f8: 3708 adds r7, #8
80098fa: 46bd mov sp, r7
80098fc: bd80 pop {r7, pc}
080098fe <HAL_SDRAM_SendCommand>:
* @param Command SDRAM command structure
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
{
80098fe: b580 push {r7, lr}
8009900: b084 sub sp, #16
8009902: af00 add r7, sp, #0
8009904: 60f8 str r0, [r7, #12]
8009906: 60b9 str r1, [r7, #8]
8009908: 607a str r2, [r7, #4]
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
800990a: 68fb ldr r3, [r7, #12]
800990c: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
8009910: b2db uxtb r3, r3
8009912: 2b02 cmp r3, #2
8009914: d101 bne.n 800991a <HAL_SDRAM_SendCommand+0x1c>
{
return HAL_BUSY;
8009916: 2302 movs r3, #2
8009918: e018 b.n 800994c <HAL_SDRAM_SendCommand+0x4e>
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
800991a: 68fb ldr r3, [r7, #12]
800991c: 2202 movs r2, #2
800991e: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Send SDRAM command */
FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
8009922: 68fb ldr r3, [r7, #12]
8009924: 681b ldr r3, [r3, #0]
8009926: 687a ldr r2, [r7, #4]
8009928: 68b9 ldr r1, [r7, #8]
800992a: 4618 mov r0, r3
800992c: f001 fb06 bl 800af3c <FMC_SDRAM_SendCommand>
/* Update the SDRAM controller state state */
if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
8009930: 68bb ldr r3, [r7, #8]
8009932: 681b ldr r3, [r3, #0]
8009934: 2b02 cmp r3, #2
8009936: d104 bne.n 8009942 <HAL_SDRAM_SendCommand+0x44>
{
hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
8009938: 68fb ldr r3, [r7, #12]
800993a: 2205 movs r2, #5
800993c: f883 202c strb.w r2, [r3, #44] ; 0x2c
8009940: e003 b.n 800994a <HAL_SDRAM_SendCommand+0x4c>
}
else
{
hsdram->State = HAL_SDRAM_STATE_READY;
8009942: 68fb ldr r3, [r7, #12]
8009944: 2201 movs r2, #1
8009946: f883 202c strb.w r2, [r3, #44] ; 0x2c
}
return HAL_OK;
800994a: 2300 movs r3, #0
}
800994c: 4618 mov r0, r3
800994e: 3710 adds r7, #16
8009950: 46bd mov sp, r7
8009952: bd80 pop {r7, pc}
08009954 <HAL_SDRAM_ProgramRefreshRate>:
* the configuration information for SDRAM module.
* @param RefreshRate The SDRAM refresh rate value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
{
8009954: b580 push {r7, lr}
8009956: b082 sub sp, #8
8009958: af00 add r7, sp, #0
800995a: 6078 str r0, [r7, #4]
800995c: 6039 str r1, [r7, #0]
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
800995e: 687b ldr r3, [r7, #4]
8009960: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
8009964: b2db uxtb r3, r3
8009966: 2b02 cmp r3, #2
8009968: d101 bne.n 800996e <HAL_SDRAM_ProgramRefreshRate+0x1a>
{
return HAL_BUSY;
800996a: 2302 movs r3, #2
800996c: e00e b.n 800998c <HAL_SDRAM_ProgramRefreshRate+0x38>
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
800996e: 687b ldr r3, [r7, #4]
8009970: 2202 movs r2, #2
8009972: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Program the refresh rate */
FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
8009976: 687b ldr r3, [r7, #4]
8009978: 681b ldr r3, [r3, #0]
800997a: 6839 ldr r1, [r7, #0]
800997c: 4618 mov r0, r3
800997e: f001 fb01 bl 800af84 <FMC_SDRAM_ProgramRefreshRate>
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_READY;
8009982: 687b ldr r3, [r7, #4]
8009984: 2201 movs r2, #1
8009986: f883 202c strb.w r2, [r3, #44] ; 0x2c
return HAL_OK;
800998a: 2300 movs r3, #0
}
800998c: 4618 mov r0, r3
800998e: 3708 adds r7, #8
8009990: 46bd mov sp, r7
8009992: bd80 pop {r7, pc}
08009994 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8009994: b580 push {r7, lr}
8009996: b082 sub sp, #8
8009998: af00 add r7, sp, #0
800999a: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
800999c: 687b ldr r3, [r7, #4]
800999e: 2b00 cmp r3, #0
80099a0: d101 bne.n 80099a6 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
80099a2: 2301 movs r3, #1
80099a4: e049 b.n 8009a3a <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80099a6: 687b ldr r3, [r7, #4]
80099a8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80099ac: b2db uxtb r3, r3
80099ae: 2b00 cmp r3, #0
80099b0: d106 bne.n 80099c0 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80099b2: 687b ldr r3, [r7, #4]
80099b4: 2200 movs r2, #0
80099b6: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
80099ba: 6878 ldr r0, [r7, #4]
80099bc: f7fa fbe2 bl 8004184 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80099c0: 687b ldr r3, [r7, #4]
80099c2: 2202 movs r2, #2
80099c4: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80099c8: 687b ldr r3, [r7, #4]
80099ca: 681a ldr r2, [r3, #0]
80099cc: 687b ldr r3, [r7, #4]
80099ce: 3304 adds r3, #4
80099d0: 4619 mov r1, r3
80099d2: 4610 mov r0, r2
80099d4: f000 fc6e bl 800a2b4 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80099d8: 687b ldr r3, [r7, #4]
80099da: 2201 movs r2, #1
80099dc: f883 2048 strb.w r2, [r3, #72] ; 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80099e0: 687b ldr r3, [r7, #4]
80099e2: 2201 movs r2, #1
80099e4: f883 203e strb.w r2, [r3, #62] ; 0x3e
80099e8: 687b ldr r3, [r7, #4]
80099ea: 2201 movs r2, #1
80099ec: f883 203f strb.w r2, [r3, #63] ; 0x3f
80099f0: 687b ldr r3, [r7, #4]
80099f2: 2201 movs r2, #1
80099f4: f883 2040 strb.w r2, [r3, #64] ; 0x40
80099f8: 687b ldr r3, [r7, #4]
80099fa: 2201 movs r2, #1
80099fc: f883 2041 strb.w r2, [r3, #65] ; 0x41
8009a00: 687b ldr r3, [r7, #4]
8009a02: 2201 movs r2, #1
8009a04: f883 2042 strb.w r2, [r3, #66] ; 0x42
8009a08: 687b ldr r3, [r7, #4]
8009a0a: 2201 movs r2, #1
8009a0c: f883 2043 strb.w r2, [r3, #67] ; 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8009a10: 687b ldr r3, [r7, #4]
8009a12: 2201 movs r2, #1
8009a14: f883 2044 strb.w r2, [r3, #68] ; 0x44
8009a18: 687b ldr r3, [r7, #4]
8009a1a: 2201 movs r2, #1
8009a1c: f883 2045 strb.w r2, [r3, #69] ; 0x45
8009a20: 687b ldr r3, [r7, #4]
8009a22: 2201 movs r2, #1
8009a24: f883 2046 strb.w r2, [r3, #70] ; 0x46
8009a28: 687b ldr r3, [r7, #4]
8009a2a: 2201 movs r2, #1
8009a2c: f883 2047 strb.w r2, [r3, #71] ; 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8009a30: 687b ldr r3, [r7, #4]
8009a32: 2201 movs r2, #1
8009a34: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8009a38: 2300 movs r3, #0
}
8009a3a: 4618 mov r0, r3
8009a3c: 3708 adds r7, #8
8009a3e: 46bd mov sp, r7
8009a40: bd80 pop {r7, pc}
...
08009a44 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8009a44: b480 push {r7}
8009a46: b085 sub sp, #20
8009a48: af00 add r7, sp, #0
8009a4a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8009a4c: 687b ldr r3, [r7, #4]
8009a4e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8009a52: b2db uxtb r3, r3
8009a54: 2b01 cmp r3, #1
8009a56: d001 beq.n 8009a5c <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
8009a58: 2301 movs r3, #1
8009a5a: e054 b.n 8009b06 <HAL_TIM_Base_Start_IT+0xc2>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8009a5c: 687b ldr r3, [r7, #4]
8009a5e: 2202 movs r2, #2
8009a60: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8009a64: 687b ldr r3, [r7, #4]
8009a66: 681b ldr r3, [r3, #0]
8009a68: 68da ldr r2, [r3, #12]
8009a6a: 687b ldr r3, [r7, #4]
8009a6c: 681b ldr r3, [r3, #0]
8009a6e: f042 0201 orr.w r2, r2, #1
8009a72: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8009a74: 687b ldr r3, [r7, #4]
8009a76: 681b ldr r3, [r3, #0]
8009a78: 4a26 ldr r2, [pc, #152] ; (8009b14 <HAL_TIM_Base_Start_IT+0xd0>)
8009a7a: 4293 cmp r3, r2
8009a7c: d022 beq.n 8009ac4 <HAL_TIM_Base_Start_IT+0x80>
8009a7e: 687b ldr r3, [r7, #4]
8009a80: 681b ldr r3, [r3, #0]
8009a82: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8009a86: d01d beq.n 8009ac4 <HAL_TIM_Base_Start_IT+0x80>
8009a88: 687b ldr r3, [r7, #4]
8009a8a: 681b ldr r3, [r3, #0]
8009a8c: 4a22 ldr r2, [pc, #136] ; (8009b18 <HAL_TIM_Base_Start_IT+0xd4>)
8009a8e: 4293 cmp r3, r2
8009a90: d018 beq.n 8009ac4 <HAL_TIM_Base_Start_IT+0x80>
8009a92: 687b ldr r3, [r7, #4]
8009a94: 681b ldr r3, [r3, #0]
8009a96: 4a21 ldr r2, [pc, #132] ; (8009b1c <HAL_TIM_Base_Start_IT+0xd8>)
8009a98: 4293 cmp r3, r2
8009a9a: d013 beq.n 8009ac4 <HAL_TIM_Base_Start_IT+0x80>
8009a9c: 687b ldr r3, [r7, #4]
8009a9e: 681b ldr r3, [r3, #0]
8009aa0: 4a1f ldr r2, [pc, #124] ; (8009b20 <HAL_TIM_Base_Start_IT+0xdc>)
8009aa2: 4293 cmp r3, r2
8009aa4: d00e beq.n 8009ac4 <HAL_TIM_Base_Start_IT+0x80>
8009aa6: 687b ldr r3, [r7, #4]
8009aa8: 681b ldr r3, [r3, #0]
8009aaa: 4a1e ldr r2, [pc, #120] ; (8009b24 <HAL_TIM_Base_Start_IT+0xe0>)
8009aac: 4293 cmp r3, r2
8009aae: d009 beq.n 8009ac4 <HAL_TIM_Base_Start_IT+0x80>
8009ab0: 687b ldr r3, [r7, #4]
8009ab2: 681b ldr r3, [r3, #0]
8009ab4: 4a1c ldr r2, [pc, #112] ; (8009b28 <HAL_TIM_Base_Start_IT+0xe4>)
8009ab6: 4293 cmp r3, r2
8009ab8: d004 beq.n 8009ac4 <HAL_TIM_Base_Start_IT+0x80>
8009aba: 687b ldr r3, [r7, #4]
8009abc: 681b ldr r3, [r3, #0]
8009abe: 4a1b ldr r2, [pc, #108] ; (8009b2c <HAL_TIM_Base_Start_IT+0xe8>)
8009ac0: 4293 cmp r3, r2
8009ac2: d115 bne.n 8009af0 <HAL_TIM_Base_Start_IT+0xac>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8009ac4: 687b ldr r3, [r7, #4]
8009ac6: 681b ldr r3, [r3, #0]
8009ac8: 689a ldr r2, [r3, #8]
8009aca: 4b19 ldr r3, [pc, #100] ; (8009b30 <HAL_TIM_Base_Start_IT+0xec>)
8009acc: 4013 ands r3, r2
8009ace: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8009ad0: 68fb ldr r3, [r7, #12]
8009ad2: 2b06 cmp r3, #6
8009ad4: d015 beq.n 8009b02 <HAL_TIM_Base_Start_IT+0xbe>
8009ad6: 68fb ldr r3, [r7, #12]
8009ad8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8009adc: d011 beq.n 8009b02 <HAL_TIM_Base_Start_IT+0xbe>
{
__HAL_TIM_ENABLE(htim);
8009ade: 687b ldr r3, [r7, #4]
8009ae0: 681b ldr r3, [r3, #0]
8009ae2: 681a ldr r2, [r3, #0]
8009ae4: 687b ldr r3, [r7, #4]
8009ae6: 681b ldr r3, [r3, #0]
8009ae8: f042 0201 orr.w r2, r2, #1
8009aec: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8009aee: e008 b.n 8009b02 <HAL_TIM_Base_Start_IT+0xbe>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8009af0: 687b ldr r3, [r7, #4]
8009af2: 681b ldr r3, [r3, #0]
8009af4: 681a ldr r2, [r3, #0]
8009af6: 687b ldr r3, [r7, #4]
8009af8: 681b ldr r3, [r3, #0]
8009afa: f042 0201 orr.w r2, r2, #1
8009afe: 601a str r2, [r3, #0]
8009b00: e000 b.n 8009b04 <HAL_TIM_Base_Start_IT+0xc0>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8009b02: bf00 nop
}
/* Return function status */
return HAL_OK;
8009b04: 2300 movs r3, #0
}
8009b06: 4618 mov r0, r3
8009b08: 3714 adds r7, #20
8009b0a: 46bd mov sp, r7
8009b0c: f85d 7b04 ldr.w r7, [sp], #4
8009b10: 4770 bx lr
8009b12: bf00 nop
8009b14: 40010000 .word 0x40010000
8009b18: 40000400 .word 0x40000400
8009b1c: 40000800 .word 0x40000800
8009b20: 40000c00 .word 0x40000c00
8009b24: 40010400 .word 0x40010400
8009b28: 40014000 .word 0x40014000
8009b2c: 40001800 .word 0x40001800
8009b30: 00010007 .word 0x00010007
08009b34 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8009b34: b580 push {r7, lr}
8009b36: b082 sub sp, #8
8009b38: af00 add r7, sp, #0
8009b3a: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8009b3c: 687b ldr r3, [r7, #4]
8009b3e: 2b00 cmp r3, #0
8009b40: d101 bne.n 8009b46 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8009b42: 2301 movs r3, #1
8009b44: e049 b.n 8009bda <HAL_TIM_PWM_Init+0xa6>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8009b46: 687b ldr r3, [r7, #4]
8009b48: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8009b4c: b2db uxtb r3, r3
8009b4e: 2b00 cmp r3, #0
8009b50: d106 bne.n 8009b60 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8009b52: 687b ldr r3, [r7, #4]
8009b54: 2200 movs r2, #0
8009b56: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8009b5a: 6878 ldr r0, [r7, #4]
8009b5c: f000 f841 bl 8009be2 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8009b60: 687b ldr r3, [r7, #4]
8009b62: 2202 movs r2, #2
8009b64: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8009b68: 687b ldr r3, [r7, #4]
8009b6a: 681a ldr r2, [r3, #0]
8009b6c: 687b ldr r3, [r7, #4]
8009b6e: 3304 adds r3, #4
8009b70: 4619 mov r1, r3
8009b72: 4610 mov r0, r2
8009b74: f000 fb9e bl 800a2b4 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8009b78: 687b ldr r3, [r7, #4]
8009b7a: 2201 movs r2, #1
8009b7c: f883 2048 strb.w r2, [r3, #72] ; 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8009b80: 687b ldr r3, [r7, #4]
8009b82: 2201 movs r2, #1
8009b84: f883 203e strb.w r2, [r3, #62] ; 0x3e
8009b88: 687b ldr r3, [r7, #4]
8009b8a: 2201 movs r2, #1
8009b8c: f883 203f strb.w r2, [r3, #63] ; 0x3f
8009b90: 687b ldr r3, [r7, #4]
8009b92: 2201 movs r2, #1
8009b94: f883 2040 strb.w r2, [r3, #64] ; 0x40
8009b98: 687b ldr r3, [r7, #4]
8009b9a: 2201 movs r2, #1
8009b9c: f883 2041 strb.w r2, [r3, #65] ; 0x41
8009ba0: 687b ldr r3, [r7, #4]
8009ba2: 2201 movs r2, #1
8009ba4: f883 2042 strb.w r2, [r3, #66] ; 0x42
8009ba8: 687b ldr r3, [r7, #4]
8009baa: 2201 movs r2, #1
8009bac: f883 2043 strb.w r2, [r3, #67] ; 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8009bb0: 687b ldr r3, [r7, #4]
8009bb2: 2201 movs r2, #1
8009bb4: f883 2044 strb.w r2, [r3, #68] ; 0x44
8009bb8: 687b ldr r3, [r7, #4]
8009bba: 2201 movs r2, #1
8009bbc: f883 2045 strb.w r2, [r3, #69] ; 0x45
8009bc0: 687b ldr r3, [r7, #4]
8009bc2: 2201 movs r2, #1
8009bc4: f883 2046 strb.w r2, [r3, #70] ; 0x46
8009bc8: 687b ldr r3, [r7, #4]
8009bca: 2201 movs r2, #1
8009bcc: f883 2047 strb.w r2, [r3, #71] ; 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8009bd0: 687b ldr r3, [r7, #4]
8009bd2: 2201 movs r2, #1
8009bd4: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8009bd8: 2300 movs r3, #0
}
8009bda: 4618 mov r0, r3
8009bdc: 3708 adds r7, #8
8009bde: 46bd mov sp, r7
8009be0: bd80 pop {r7, pc}
08009be2 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8009be2: b480 push {r7}
8009be4: b083 sub sp, #12
8009be6: af00 add r7, sp, #0
8009be8: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8009bea: bf00 nop
8009bec: 370c adds r7, #12
8009bee: 46bd mov sp, r7
8009bf0: f85d 7b04 ldr.w r7, [sp], #4
8009bf4: 4770 bx lr
08009bf6 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8009bf6: b580 push {r7, lr}
8009bf8: b082 sub sp, #8
8009bfa: af00 add r7, sp, #0
8009bfc: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8009bfe: 687b ldr r3, [r7, #4]
8009c00: 681b ldr r3, [r3, #0]
8009c02: 691b ldr r3, [r3, #16]
8009c04: f003 0302 and.w r3, r3, #2
8009c08: 2b02 cmp r3, #2
8009c0a: d122 bne.n 8009c52 <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
8009c0c: 687b ldr r3, [r7, #4]
8009c0e: 681b ldr r3, [r3, #0]
8009c10: 68db ldr r3, [r3, #12]
8009c12: f003 0302 and.w r3, r3, #2
8009c16: 2b02 cmp r3, #2
8009c18: d11b bne.n 8009c52 <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8009c1a: 687b ldr r3, [r7, #4]
8009c1c: 681b ldr r3, [r3, #0]
8009c1e: f06f 0202 mvn.w r2, #2
8009c22: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8009c24: 687b ldr r3, [r7, #4]
8009c26: 2201 movs r2, #1
8009c28: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8009c2a: 687b ldr r3, [r7, #4]
8009c2c: 681b ldr r3, [r3, #0]
8009c2e: 699b ldr r3, [r3, #24]
8009c30: f003 0303 and.w r3, r3, #3
8009c34: 2b00 cmp r3, #0
8009c36: d003 beq.n 8009c40 <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8009c38: 6878 ldr r0, [r7, #4]
8009c3a: f000 fb1d bl 800a278 <HAL_TIM_IC_CaptureCallback>
8009c3e: e005 b.n 8009c4c <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8009c40: 6878 ldr r0, [r7, #4]
8009c42: f000 fb0f bl 800a264 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8009c46: 6878 ldr r0, [r7, #4]
8009c48: f000 fb20 bl 800a28c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8009c4c: 687b ldr r3, [r7, #4]
8009c4e: 2200 movs r2, #0
8009c50: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8009c52: 687b ldr r3, [r7, #4]
8009c54: 681b ldr r3, [r3, #0]
8009c56: 691b ldr r3, [r3, #16]
8009c58: f003 0304 and.w r3, r3, #4
8009c5c: 2b04 cmp r3, #4
8009c5e: d122 bne.n 8009ca6 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8009c60: 687b ldr r3, [r7, #4]
8009c62: 681b ldr r3, [r3, #0]
8009c64: 68db ldr r3, [r3, #12]
8009c66: f003 0304 and.w r3, r3, #4
8009c6a: 2b04 cmp r3, #4
8009c6c: d11b bne.n 8009ca6 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8009c6e: 687b ldr r3, [r7, #4]
8009c70: 681b ldr r3, [r3, #0]
8009c72: f06f 0204 mvn.w r2, #4
8009c76: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8009c78: 687b ldr r3, [r7, #4]
8009c7a: 2202 movs r2, #2
8009c7c: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8009c7e: 687b ldr r3, [r7, #4]
8009c80: 681b ldr r3, [r3, #0]
8009c82: 699b ldr r3, [r3, #24]
8009c84: f403 7340 and.w r3, r3, #768 ; 0x300
8009c88: 2b00 cmp r3, #0
8009c8a: d003 beq.n 8009c94 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8009c8c: 6878 ldr r0, [r7, #4]
8009c8e: f000 faf3 bl 800a278 <HAL_TIM_IC_CaptureCallback>
8009c92: e005 b.n 8009ca0 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8009c94: 6878 ldr r0, [r7, #4]
8009c96: f000 fae5 bl 800a264 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8009c9a: 6878 ldr r0, [r7, #4]
8009c9c: f000 faf6 bl 800a28c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8009ca0: 687b ldr r3, [r7, #4]
8009ca2: 2200 movs r2, #0
8009ca4: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8009ca6: 687b ldr r3, [r7, #4]
8009ca8: 681b ldr r3, [r3, #0]
8009caa: 691b ldr r3, [r3, #16]
8009cac: f003 0308 and.w r3, r3, #8
8009cb0: 2b08 cmp r3, #8
8009cb2: d122 bne.n 8009cfa <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8009cb4: 687b ldr r3, [r7, #4]
8009cb6: 681b ldr r3, [r3, #0]
8009cb8: 68db ldr r3, [r3, #12]
8009cba: f003 0308 and.w r3, r3, #8
8009cbe: 2b08 cmp r3, #8
8009cc0: d11b bne.n 8009cfa <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
8009cc2: 687b ldr r3, [r7, #4]
8009cc4: 681b ldr r3, [r3, #0]
8009cc6: f06f 0208 mvn.w r2, #8
8009cca: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8009ccc: 687b ldr r3, [r7, #4]
8009cce: 2204 movs r2, #4
8009cd0: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8009cd2: 687b ldr r3, [r7, #4]
8009cd4: 681b ldr r3, [r3, #0]
8009cd6: 69db ldr r3, [r3, #28]
8009cd8: f003 0303 and.w r3, r3, #3
8009cdc: 2b00 cmp r3, #0
8009cde: d003 beq.n 8009ce8 <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8009ce0: 6878 ldr r0, [r7, #4]
8009ce2: f000 fac9 bl 800a278 <HAL_TIM_IC_CaptureCallback>
8009ce6: e005 b.n 8009cf4 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8009ce8: 6878 ldr r0, [r7, #4]
8009cea: f000 fabb bl 800a264 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8009cee: 6878 ldr r0, [r7, #4]
8009cf0: f000 facc bl 800a28c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8009cf4: 687b ldr r3, [r7, #4]
8009cf6: 2200 movs r2, #0
8009cf8: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8009cfa: 687b ldr r3, [r7, #4]
8009cfc: 681b ldr r3, [r3, #0]
8009cfe: 691b ldr r3, [r3, #16]
8009d00: f003 0310 and.w r3, r3, #16
8009d04: 2b10 cmp r3, #16
8009d06: d122 bne.n 8009d4e <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8009d08: 687b ldr r3, [r7, #4]
8009d0a: 681b ldr r3, [r3, #0]
8009d0c: 68db ldr r3, [r3, #12]
8009d0e: f003 0310 and.w r3, r3, #16
8009d12: 2b10 cmp r3, #16
8009d14: d11b bne.n 8009d4e <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8009d16: 687b ldr r3, [r7, #4]
8009d18: 681b ldr r3, [r3, #0]
8009d1a: f06f 0210 mvn.w r2, #16
8009d1e: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8009d20: 687b ldr r3, [r7, #4]
8009d22: 2208 movs r2, #8
8009d24: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8009d26: 687b ldr r3, [r7, #4]
8009d28: 681b ldr r3, [r3, #0]
8009d2a: 69db ldr r3, [r3, #28]
8009d2c: f403 7340 and.w r3, r3, #768 ; 0x300
8009d30: 2b00 cmp r3, #0
8009d32: d003 beq.n 8009d3c <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8009d34: 6878 ldr r0, [r7, #4]
8009d36: f000 fa9f bl 800a278 <HAL_TIM_IC_CaptureCallback>
8009d3a: e005 b.n 8009d48 <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8009d3c: 6878 ldr r0, [r7, #4]
8009d3e: f000 fa91 bl 800a264 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8009d42: 6878 ldr r0, [r7, #4]
8009d44: f000 faa2 bl 800a28c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8009d48: 687b ldr r3, [r7, #4]
8009d4a: 2200 movs r2, #0
8009d4c: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8009d4e: 687b ldr r3, [r7, #4]
8009d50: 681b ldr r3, [r3, #0]
8009d52: 691b ldr r3, [r3, #16]
8009d54: f003 0301 and.w r3, r3, #1
8009d58: 2b01 cmp r3, #1
8009d5a: d10e bne.n 8009d7a <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
8009d5c: 687b ldr r3, [r7, #4]
8009d5e: 681b ldr r3, [r3, #0]
8009d60: 68db ldr r3, [r3, #12]
8009d62: f003 0301 and.w r3, r3, #1
8009d66: 2b01 cmp r3, #1
8009d68: d107 bne.n 8009d7a <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8009d6a: 687b ldr r3, [r7, #4]
8009d6c: 681b ldr r3, [r3, #0]
8009d6e: f06f 0201 mvn.w r2, #1
8009d72: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8009d74: 6878 ldr r0, [r7, #4]
8009d76: f7f8 fc6f bl 8002658 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8009d7a: 687b ldr r3, [r7, #4]
8009d7c: 681b ldr r3, [r3, #0]
8009d7e: 691b ldr r3, [r3, #16]
8009d80: f003 0380 and.w r3, r3, #128 ; 0x80
8009d84: 2b80 cmp r3, #128 ; 0x80
8009d86: d10e bne.n 8009da6 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8009d88: 687b ldr r3, [r7, #4]
8009d8a: 681b ldr r3, [r3, #0]
8009d8c: 68db ldr r3, [r3, #12]
8009d8e: f003 0380 and.w r3, r3, #128 ; 0x80
8009d92: 2b80 cmp r3, #128 ; 0x80
8009d94: d107 bne.n 8009da6 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8009d96: 687b ldr r3, [r7, #4]
8009d98: 681b ldr r3, [r3, #0]
8009d9a: f06f 0280 mvn.w r2, #128 ; 0x80
8009d9e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8009da0: 6878 ldr r0, [r7, #4]
8009da2: f000 ffc5 bl 800ad30 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
8009da6: 687b ldr r3, [r7, #4]
8009da8: 681b ldr r3, [r3, #0]
8009daa: 691b ldr r3, [r3, #16]
8009dac: f403 7380 and.w r3, r3, #256 ; 0x100
8009db0: f5b3 7f80 cmp.w r3, #256 ; 0x100
8009db4: d10e bne.n 8009dd4 <HAL_TIM_IRQHandler+0x1de>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8009db6: 687b ldr r3, [r7, #4]
8009db8: 681b ldr r3, [r3, #0]
8009dba: 68db ldr r3, [r3, #12]
8009dbc: f003 0380 and.w r3, r3, #128 ; 0x80
8009dc0: 2b80 cmp r3, #128 ; 0x80
8009dc2: d107 bne.n 8009dd4 <HAL_TIM_IRQHandler+0x1de>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8009dc4: 687b ldr r3, [r7, #4]
8009dc6: 681b ldr r3, [r3, #0]
8009dc8: f46f 7280 mvn.w r2, #256 ; 0x100
8009dcc: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
8009dce: 6878 ldr r0, [r7, #4]
8009dd0: f000 ffb8 bl 800ad44 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8009dd4: 687b ldr r3, [r7, #4]
8009dd6: 681b ldr r3, [r3, #0]
8009dd8: 691b ldr r3, [r3, #16]
8009dda: f003 0340 and.w r3, r3, #64 ; 0x40
8009dde: 2b40 cmp r3, #64 ; 0x40
8009de0: d10e bne.n 8009e00 <HAL_TIM_IRQHandler+0x20a>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
8009de2: 687b ldr r3, [r7, #4]
8009de4: 681b ldr r3, [r3, #0]
8009de6: 68db ldr r3, [r3, #12]
8009de8: f003 0340 and.w r3, r3, #64 ; 0x40
8009dec: 2b40 cmp r3, #64 ; 0x40
8009dee: d107 bne.n 8009e00 <HAL_TIM_IRQHandler+0x20a>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
8009df0: 687b ldr r3, [r7, #4]
8009df2: 681b ldr r3, [r3, #0]
8009df4: f06f 0240 mvn.w r2, #64 ; 0x40
8009df8: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8009dfa: 6878 ldr r0, [r7, #4]
8009dfc: f000 fa50 bl 800a2a0 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8009e00: 687b ldr r3, [r7, #4]
8009e02: 681b ldr r3, [r3, #0]
8009e04: 691b ldr r3, [r3, #16]
8009e06: f003 0320 and.w r3, r3, #32
8009e0a: 2b20 cmp r3, #32
8009e0c: d10e bne.n 8009e2c <HAL_TIM_IRQHandler+0x236>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
8009e0e: 687b ldr r3, [r7, #4]
8009e10: 681b ldr r3, [r3, #0]
8009e12: 68db ldr r3, [r3, #12]
8009e14: f003 0320 and.w r3, r3, #32
8009e18: 2b20 cmp r3, #32
8009e1a: d107 bne.n 8009e2c <HAL_TIM_IRQHandler+0x236>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8009e1c: 687b ldr r3, [r7, #4]
8009e1e: 681b ldr r3, [r3, #0]
8009e20: f06f 0220 mvn.w r2, #32
8009e24: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8009e26: 6878 ldr r0, [r7, #4]
8009e28: f000 ff78 bl 800ad1c <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8009e2c: bf00 nop
8009e2e: 3708 adds r7, #8
8009e30: 46bd mov sp, r7
8009e32: bd80 pop {r7, pc}
08009e34 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8009e34: b580 push {r7, lr}
8009e36: b084 sub sp, #16
8009e38: af00 add r7, sp, #0
8009e3a: 60f8 str r0, [r7, #12]
8009e3c: 60b9 str r1, [r7, #8]
8009e3e: 607a str r2, [r7, #4]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8009e40: 68fb ldr r3, [r7, #12]
8009e42: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8009e46: 2b01 cmp r3, #1
8009e48: d101 bne.n 8009e4e <HAL_TIM_PWM_ConfigChannel+0x1a>
8009e4a: 2302 movs r3, #2
8009e4c: e0fd b.n 800a04a <HAL_TIM_PWM_ConfigChannel+0x216>
8009e4e: 68fb ldr r3, [r7, #12]
8009e50: 2201 movs r2, #1
8009e52: f883 203c strb.w r2, [r3, #60] ; 0x3c
8009e56: 687b ldr r3, [r7, #4]
8009e58: 2b14 cmp r3, #20
8009e5a: f200 80f0 bhi.w 800a03e <HAL_TIM_PWM_ConfigChannel+0x20a>
8009e5e: a201 add r2, pc, #4 ; (adr r2, 8009e64 <HAL_TIM_PWM_ConfigChannel+0x30>)
8009e60: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8009e64: 08009eb9 .word 0x08009eb9
8009e68: 0800a03f .word 0x0800a03f
8009e6c: 0800a03f .word 0x0800a03f
8009e70: 0800a03f .word 0x0800a03f
8009e74: 08009ef9 .word 0x08009ef9
8009e78: 0800a03f .word 0x0800a03f
8009e7c: 0800a03f .word 0x0800a03f
8009e80: 0800a03f .word 0x0800a03f
8009e84: 08009f3b .word 0x08009f3b
8009e88: 0800a03f .word 0x0800a03f
8009e8c: 0800a03f .word 0x0800a03f
8009e90: 0800a03f .word 0x0800a03f
8009e94: 08009f7b .word 0x08009f7b
8009e98: 0800a03f .word 0x0800a03f
8009e9c: 0800a03f .word 0x0800a03f
8009ea0: 0800a03f .word 0x0800a03f
8009ea4: 08009fbd .word 0x08009fbd
8009ea8: 0800a03f .word 0x0800a03f
8009eac: 0800a03f .word 0x0800a03f
8009eb0: 0800a03f .word 0x0800a03f
8009eb4: 08009ffd .word 0x08009ffd
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8009eb8: 68fb ldr r3, [r7, #12]
8009eba: 681b ldr r3, [r3, #0]
8009ebc: 68b9 ldr r1, [r7, #8]
8009ebe: 4618 mov r0, r3
8009ec0: f000 fa98 bl 800a3f4 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8009ec4: 68fb ldr r3, [r7, #12]
8009ec6: 681b ldr r3, [r3, #0]
8009ec8: 699a ldr r2, [r3, #24]
8009eca: 68fb ldr r3, [r7, #12]
8009ecc: 681b ldr r3, [r3, #0]
8009ece: f042 0208 orr.w r2, r2, #8
8009ed2: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8009ed4: 68fb ldr r3, [r7, #12]
8009ed6: 681b ldr r3, [r3, #0]
8009ed8: 699a ldr r2, [r3, #24]
8009eda: 68fb ldr r3, [r7, #12]
8009edc: 681b ldr r3, [r3, #0]
8009ede: f022 0204 bic.w r2, r2, #4
8009ee2: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8009ee4: 68fb ldr r3, [r7, #12]
8009ee6: 681b ldr r3, [r3, #0]
8009ee8: 6999 ldr r1, [r3, #24]
8009eea: 68bb ldr r3, [r7, #8]
8009eec: 691a ldr r2, [r3, #16]
8009eee: 68fb ldr r3, [r7, #12]
8009ef0: 681b ldr r3, [r3, #0]
8009ef2: 430a orrs r2, r1
8009ef4: 619a str r2, [r3, #24]
break;
8009ef6: e0a3 b.n 800a040 <HAL_TIM_PWM_ConfigChannel+0x20c>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8009ef8: 68fb ldr r3, [r7, #12]
8009efa: 681b ldr r3, [r3, #0]
8009efc: 68b9 ldr r1, [r7, #8]
8009efe: 4618 mov r0, r3
8009f00: f000 faea bl 800a4d8 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8009f04: 68fb ldr r3, [r7, #12]
8009f06: 681b ldr r3, [r3, #0]
8009f08: 699a ldr r2, [r3, #24]
8009f0a: 68fb ldr r3, [r7, #12]
8009f0c: 681b ldr r3, [r3, #0]
8009f0e: f442 6200 orr.w r2, r2, #2048 ; 0x800
8009f12: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8009f14: 68fb ldr r3, [r7, #12]
8009f16: 681b ldr r3, [r3, #0]
8009f18: 699a ldr r2, [r3, #24]
8009f1a: 68fb ldr r3, [r7, #12]
8009f1c: 681b ldr r3, [r3, #0]
8009f1e: f422 6280 bic.w r2, r2, #1024 ; 0x400
8009f22: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8009f24: 68fb ldr r3, [r7, #12]
8009f26: 681b ldr r3, [r3, #0]
8009f28: 6999 ldr r1, [r3, #24]
8009f2a: 68bb ldr r3, [r7, #8]
8009f2c: 691b ldr r3, [r3, #16]
8009f2e: 021a lsls r2, r3, #8
8009f30: 68fb ldr r3, [r7, #12]
8009f32: 681b ldr r3, [r3, #0]
8009f34: 430a orrs r2, r1
8009f36: 619a str r2, [r3, #24]
break;
8009f38: e082 b.n 800a040 <HAL_TIM_PWM_ConfigChannel+0x20c>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8009f3a: 68fb ldr r3, [r7, #12]
8009f3c: 681b ldr r3, [r3, #0]
8009f3e: 68b9 ldr r1, [r7, #8]
8009f40: 4618 mov r0, r3
8009f42: f000 fb41 bl 800a5c8 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8009f46: 68fb ldr r3, [r7, #12]
8009f48: 681b ldr r3, [r3, #0]
8009f4a: 69da ldr r2, [r3, #28]
8009f4c: 68fb ldr r3, [r7, #12]
8009f4e: 681b ldr r3, [r3, #0]
8009f50: f042 0208 orr.w r2, r2, #8
8009f54: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8009f56: 68fb ldr r3, [r7, #12]
8009f58: 681b ldr r3, [r3, #0]
8009f5a: 69da ldr r2, [r3, #28]
8009f5c: 68fb ldr r3, [r7, #12]
8009f5e: 681b ldr r3, [r3, #0]
8009f60: f022 0204 bic.w r2, r2, #4
8009f64: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8009f66: 68fb ldr r3, [r7, #12]
8009f68: 681b ldr r3, [r3, #0]
8009f6a: 69d9 ldr r1, [r3, #28]
8009f6c: 68bb ldr r3, [r7, #8]
8009f6e: 691a ldr r2, [r3, #16]
8009f70: 68fb ldr r3, [r7, #12]
8009f72: 681b ldr r3, [r3, #0]
8009f74: 430a orrs r2, r1
8009f76: 61da str r2, [r3, #28]
break;
8009f78: e062 b.n 800a040 <HAL_TIM_PWM_ConfigChannel+0x20c>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8009f7a: 68fb ldr r3, [r7, #12]
8009f7c: 681b ldr r3, [r3, #0]
8009f7e: 68b9 ldr r1, [r7, #8]
8009f80: 4618 mov r0, r3
8009f82: f000 fb97 bl 800a6b4 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8009f86: 68fb ldr r3, [r7, #12]
8009f88: 681b ldr r3, [r3, #0]
8009f8a: 69da ldr r2, [r3, #28]
8009f8c: 68fb ldr r3, [r7, #12]
8009f8e: 681b ldr r3, [r3, #0]
8009f90: f442 6200 orr.w r2, r2, #2048 ; 0x800
8009f94: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8009f96: 68fb ldr r3, [r7, #12]
8009f98: 681b ldr r3, [r3, #0]
8009f9a: 69da ldr r2, [r3, #28]
8009f9c: 68fb ldr r3, [r7, #12]
8009f9e: 681b ldr r3, [r3, #0]
8009fa0: f422 6280 bic.w r2, r2, #1024 ; 0x400
8009fa4: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8009fa6: 68fb ldr r3, [r7, #12]
8009fa8: 681b ldr r3, [r3, #0]
8009faa: 69d9 ldr r1, [r3, #28]
8009fac: 68bb ldr r3, [r7, #8]
8009fae: 691b ldr r3, [r3, #16]
8009fb0: 021a lsls r2, r3, #8
8009fb2: 68fb ldr r3, [r7, #12]
8009fb4: 681b ldr r3, [r3, #0]
8009fb6: 430a orrs r2, r1
8009fb8: 61da str r2, [r3, #28]
break;
8009fba: e041 b.n 800a040 <HAL_TIM_PWM_ConfigChannel+0x20c>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
8009fbc: 68fb ldr r3, [r7, #12]
8009fbe: 681b ldr r3, [r3, #0]
8009fc0: 68b9 ldr r1, [r7, #8]
8009fc2: 4618 mov r0, r3
8009fc4: f000 fbce bl 800a764 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
8009fc8: 68fb ldr r3, [r7, #12]
8009fca: 681b ldr r3, [r3, #0]
8009fcc: 6d5a ldr r2, [r3, #84] ; 0x54
8009fce: 68fb ldr r3, [r7, #12]
8009fd0: 681b ldr r3, [r3, #0]
8009fd2: f042 0208 orr.w r2, r2, #8
8009fd6: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
8009fd8: 68fb ldr r3, [r7, #12]
8009fda: 681b ldr r3, [r3, #0]
8009fdc: 6d5a ldr r2, [r3, #84] ; 0x54
8009fde: 68fb ldr r3, [r7, #12]
8009fe0: 681b ldr r3, [r3, #0]
8009fe2: f022 0204 bic.w r2, r2, #4
8009fe6: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
8009fe8: 68fb ldr r3, [r7, #12]
8009fea: 681b ldr r3, [r3, #0]
8009fec: 6d59 ldr r1, [r3, #84] ; 0x54
8009fee: 68bb ldr r3, [r7, #8]
8009ff0: 691a ldr r2, [r3, #16]
8009ff2: 68fb ldr r3, [r7, #12]
8009ff4: 681b ldr r3, [r3, #0]
8009ff6: 430a orrs r2, r1
8009ff8: 655a str r2, [r3, #84] ; 0x54
break;
8009ffa: e021 b.n 800a040 <HAL_TIM_PWM_ConfigChannel+0x20c>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
8009ffc: 68fb ldr r3, [r7, #12]
8009ffe: 681b ldr r3, [r3, #0]
800a000: 68b9 ldr r1, [r7, #8]
800a002: 4618 mov r0, r3
800a004: f000 fc00 bl 800a808 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
800a008: 68fb ldr r3, [r7, #12]
800a00a: 681b ldr r3, [r3, #0]
800a00c: 6d5a ldr r2, [r3, #84] ; 0x54
800a00e: 68fb ldr r3, [r7, #12]
800a010: 681b ldr r3, [r3, #0]
800a012: f442 6200 orr.w r2, r2, #2048 ; 0x800
800a016: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
800a018: 68fb ldr r3, [r7, #12]
800a01a: 681b ldr r3, [r3, #0]
800a01c: 6d5a ldr r2, [r3, #84] ; 0x54
800a01e: 68fb ldr r3, [r7, #12]
800a020: 681b ldr r3, [r3, #0]
800a022: f422 6280 bic.w r2, r2, #1024 ; 0x400
800a026: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
800a028: 68fb ldr r3, [r7, #12]
800a02a: 681b ldr r3, [r3, #0]
800a02c: 6d59 ldr r1, [r3, #84] ; 0x54
800a02e: 68bb ldr r3, [r7, #8]
800a030: 691b ldr r3, [r3, #16]
800a032: 021a lsls r2, r3, #8
800a034: 68fb ldr r3, [r7, #12]
800a036: 681b ldr r3, [r3, #0]
800a038: 430a orrs r2, r1
800a03a: 655a str r2, [r3, #84] ; 0x54
break;
800a03c: e000 b.n 800a040 <HAL_TIM_PWM_ConfigChannel+0x20c>
}
default:
break;
800a03e: bf00 nop
}
__HAL_UNLOCK(htim);
800a040: 68fb ldr r3, [r7, #12]
800a042: 2200 movs r2, #0
800a044: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800a048: 2300 movs r3, #0
}
800a04a: 4618 mov r0, r3
800a04c: 3710 adds r7, #16
800a04e: 46bd mov sp, r7
800a050: bd80 pop {r7, pc}
800a052: bf00 nop
0800a054 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
800a054: b580 push {r7, lr}
800a056: b084 sub sp, #16
800a058: af00 add r7, sp, #0
800a05a: 6078 str r0, [r7, #4]
800a05c: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
800a05e: 687b ldr r3, [r7, #4]
800a060: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800a064: 2b01 cmp r3, #1
800a066: d101 bne.n 800a06c <HAL_TIM_ConfigClockSource+0x18>
800a068: 2302 movs r3, #2
800a06a: e0b3 b.n 800a1d4 <HAL_TIM_ConfigClockSource+0x180>
800a06c: 687b ldr r3, [r7, #4]
800a06e: 2201 movs r2, #1
800a070: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
800a074: 687b ldr r3, [r7, #4]
800a076: 2202 movs r2, #2
800a078: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
800a07c: 687b ldr r3, [r7, #4]
800a07e: 681b ldr r3, [r3, #0]
800a080: 689b ldr r3, [r3, #8]
800a082: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
800a084: 68fa ldr r2, [r7, #12]
800a086: 4b55 ldr r3, [pc, #340] ; (800a1dc <HAL_TIM_ConfigClockSource+0x188>)
800a088: 4013 ands r3, r2
800a08a: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800a08c: 68fb ldr r3, [r7, #12]
800a08e: f423 437f bic.w r3, r3, #65280 ; 0xff00
800a092: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
800a094: 687b ldr r3, [r7, #4]
800a096: 681b ldr r3, [r3, #0]
800a098: 68fa ldr r2, [r7, #12]
800a09a: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
800a09c: 683b ldr r3, [r7, #0]
800a09e: 681b ldr r3, [r3, #0]
800a0a0: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800a0a4: d03e beq.n 800a124 <HAL_TIM_ConfigClockSource+0xd0>
800a0a6: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800a0aa: f200 8087 bhi.w 800a1bc <HAL_TIM_ConfigClockSource+0x168>
800a0ae: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800a0b2: f000 8085 beq.w 800a1c0 <HAL_TIM_ConfigClockSource+0x16c>
800a0b6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800a0ba: d87f bhi.n 800a1bc <HAL_TIM_ConfigClockSource+0x168>
800a0bc: 2b70 cmp r3, #112 ; 0x70
800a0be: d01a beq.n 800a0f6 <HAL_TIM_ConfigClockSource+0xa2>
800a0c0: 2b70 cmp r3, #112 ; 0x70
800a0c2: d87b bhi.n 800a1bc <HAL_TIM_ConfigClockSource+0x168>
800a0c4: 2b60 cmp r3, #96 ; 0x60
800a0c6: d050 beq.n 800a16a <HAL_TIM_ConfigClockSource+0x116>
800a0c8: 2b60 cmp r3, #96 ; 0x60
800a0ca: d877 bhi.n 800a1bc <HAL_TIM_ConfigClockSource+0x168>
800a0cc: 2b50 cmp r3, #80 ; 0x50
800a0ce: d03c beq.n 800a14a <HAL_TIM_ConfigClockSource+0xf6>
800a0d0: 2b50 cmp r3, #80 ; 0x50
800a0d2: d873 bhi.n 800a1bc <HAL_TIM_ConfigClockSource+0x168>
800a0d4: 2b40 cmp r3, #64 ; 0x40
800a0d6: d058 beq.n 800a18a <HAL_TIM_ConfigClockSource+0x136>
800a0d8: 2b40 cmp r3, #64 ; 0x40
800a0da: d86f bhi.n 800a1bc <HAL_TIM_ConfigClockSource+0x168>
800a0dc: 2b30 cmp r3, #48 ; 0x30
800a0de: d064 beq.n 800a1aa <HAL_TIM_ConfigClockSource+0x156>
800a0e0: 2b30 cmp r3, #48 ; 0x30
800a0e2: d86b bhi.n 800a1bc <HAL_TIM_ConfigClockSource+0x168>
800a0e4: 2b20 cmp r3, #32
800a0e6: d060 beq.n 800a1aa <HAL_TIM_ConfigClockSource+0x156>
800a0e8: 2b20 cmp r3, #32
800a0ea: d867 bhi.n 800a1bc <HAL_TIM_ConfigClockSource+0x168>
800a0ec: 2b00 cmp r3, #0
800a0ee: d05c beq.n 800a1aa <HAL_TIM_ConfigClockSource+0x156>
800a0f0: 2b10 cmp r3, #16
800a0f2: d05a beq.n 800a1aa <HAL_TIM_ConfigClockSource+0x156>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
break;
}
default:
break;
800a0f4: e062 b.n 800a1bc <HAL_TIM_ConfigClockSource+0x168>
TIM_ETR_SetConfig(htim->Instance,
800a0f6: 687b ldr r3, [r7, #4]
800a0f8: 6818 ldr r0, [r3, #0]
800a0fa: 683b ldr r3, [r7, #0]
800a0fc: 6899 ldr r1, [r3, #8]
800a0fe: 683b ldr r3, [r7, #0]
800a100: 685a ldr r2, [r3, #4]
800a102: 683b ldr r3, [r7, #0]
800a104: 68db ldr r3, [r3, #12]
800a106: f000 fcdd bl 800aac4 <TIM_ETR_SetConfig>
tmpsmcr = htim->Instance->SMCR;
800a10a: 687b ldr r3, [r7, #4]
800a10c: 681b ldr r3, [r3, #0]
800a10e: 689b ldr r3, [r3, #8]
800a110: 60fb str r3, [r7, #12]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
800a112: 68fb ldr r3, [r7, #12]
800a114: f043 0377 orr.w r3, r3, #119 ; 0x77
800a118: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
800a11a: 687b ldr r3, [r7, #4]
800a11c: 681b ldr r3, [r3, #0]
800a11e: 68fa ldr r2, [r7, #12]
800a120: 609a str r2, [r3, #8]
break;
800a122: e04e b.n 800a1c2 <HAL_TIM_ConfigClockSource+0x16e>
TIM_ETR_SetConfig(htim->Instance,
800a124: 687b ldr r3, [r7, #4]
800a126: 6818 ldr r0, [r3, #0]
800a128: 683b ldr r3, [r7, #0]
800a12a: 6899 ldr r1, [r3, #8]
800a12c: 683b ldr r3, [r7, #0]
800a12e: 685a ldr r2, [r3, #4]
800a130: 683b ldr r3, [r7, #0]
800a132: 68db ldr r3, [r3, #12]
800a134: f000 fcc6 bl 800aac4 <TIM_ETR_SetConfig>
htim->Instance->SMCR |= TIM_SMCR_ECE;
800a138: 687b ldr r3, [r7, #4]
800a13a: 681b ldr r3, [r3, #0]
800a13c: 689a ldr r2, [r3, #8]
800a13e: 687b ldr r3, [r7, #4]
800a140: 681b ldr r3, [r3, #0]
800a142: f442 4280 orr.w r2, r2, #16384 ; 0x4000
800a146: 609a str r2, [r3, #8]
break;
800a148: e03b b.n 800a1c2 <HAL_TIM_ConfigClockSource+0x16e>
TIM_TI1_ConfigInputStage(htim->Instance,
800a14a: 687b ldr r3, [r7, #4]
800a14c: 6818 ldr r0, [r3, #0]
800a14e: 683b ldr r3, [r7, #0]
800a150: 6859 ldr r1, [r3, #4]
800a152: 683b ldr r3, [r7, #0]
800a154: 68db ldr r3, [r3, #12]
800a156: 461a mov r2, r3
800a158: f000 fc3a bl 800a9d0 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
800a15c: 687b ldr r3, [r7, #4]
800a15e: 681b ldr r3, [r3, #0]
800a160: 2150 movs r1, #80 ; 0x50
800a162: 4618 mov r0, r3
800a164: f000 fc93 bl 800aa8e <TIM_ITRx_SetConfig>
break;
800a168: e02b b.n 800a1c2 <HAL_TIM_ConfigClockSource+0x16e>
TIM_TI2_ConfigInputStage(htim->Instance,
800a16a: 687b ldr r3, [r7, #4]
800a16c: 6818 ldr r0, [r3, #0]
800a16e: 683b ldr r3, [r7, #0]
800a170: 6859 ldr r1, [r3, #4]
800a172: 683b ldr r3, [r7, #0]
800a174: 68db ldr r3, [r3, #12]
800a176: 461a mov r2, r3
800a178: f000 fc59 bl 800aa2e <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
800a17c: 687b ldr r3, [r7, #4]
800a17e: 681b ldr r3, [r3, #0]
800a180: 2160 movs r1, #96 ; 0x60
800a182: 4618 mov r0, r3
800a184: f000 fc83 bl 800aa8e <TIM_ITRx_SetConfig>
break;
800a188: e01b b.n 800a1c2 <HAL_TIM_ConfigClockSource+0x16e>
TIM_TI1_ConfigInputStage(htim->Instance,
800a18a: 687b ldr r3, [r7, #4]
800a18c: 6818 ldr r0, [r3, #0]
800a18e: 683b ldr r3, [r7, #0]
800a190: 6859 ldr r1, [r3, #4]
800a192: 683b ldr r3, [r7, #0]
800a194: 68db ldr r3, [r3, #12]
800a196: 461a mov r2, r3
800a198: f000 fc1a bl 800a9d0 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
800a19c: 687b ldr r3, [r7, #4]
800a19e: 681b ldr r3, [r3, #0]
800a1a0: 2140 movs r1, #64 ; 0x40
800a1a2: 4618 mov r0, r3
800a1a4: f000 fc73 bl 800aa8e <TIM_ITRx_SetConfig>
break;
800a1a8: e00b b.n 800a1c2 <HAL_TIM_ConfigClockSource+0x16e>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
800a1aa: 687b ldr r3, [r7, #4]
800a1ac: 681a ldr r2, [r3, #0]
800a1ae: 683b ldr r3, [r7, #0]
800a1b0: 681b ldr r3, [r3, #0]
800a1b2: 4619 mov r1, r3
800a1b4: 4610 mov r0, r2
800a1b6: f000 fc6a bl 800aa8e <TIM_ITRx_SetConfig>
break;
800a1ba: e002 b.n 800a1c2 <HAL_TIM_ConfigClockSource+0x16e>
break;
800a1bc: bf00 nop
800a1be: e000 b.n 800a1c2 <HAL_TIM_ConfigClockSource+0x16e>
break;
800a1c0: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
800a1c2: 687b ldr r3, [r7, #4]
800a1c4: 2201 movs r2, #1
800a1c6: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800a1ca: 687b ldr r3, [r7, #4]
800a1cc: 2200 movs r2, #0
800a1ce: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800a1d2: 2300 movs r3, #0
}
800a1d4: 4618 mov r0, r3
800a1d6: 3710 adds r7, #16
800a1d8: 46bd mov sp, r7
800a1da: bd80 pop {r7, pc}
800a1dc: fffeff88 .word 0xfffeff88
0800a1e0 <HAL_TIM_SlaveConfigSynchro>:
* timer input or external trigger input) and the Slave mode
* (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
{
800a1e0: b580 push {r7, lr}
800a1e2: b082 sub sp, #8
800a1e4: af00 add r7, sp, #0
800a1e6: 6078 str r0, [r7, #4]
800a1e8: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
__HAL_LOCK(htim);
800a1ea: 687b ldr r3, [r7, #4]
800a1ec: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800a1f0: 2b01 cmp r3, #1
800a1f2: d101 bne.n 800a1f8 <HAL_TIM_SlaveConfigSynchro+0x18>
800a1f4: 2302 movs r3, #2
800a1f6: e031 b.n 800a25c <HAL_TIM_SlaveConfigSynchro+0x7c>
800a1f8: 687b ldr r3, [r7, #4]
800a1fa: 2201 movs r2, #1
800a1fc: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
800a200: 687b ldr r3, [r7, #4]
800a202: 2202 movs r2, #2
800a204: f883 203d strb.w r2, [r3, #61] ; 0x3d
if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
800a208: 6839 ldr r1, [r7, #0]
800a20a: 6878 ldr r0, [r7, #4]
800a20c: f000 fb50 bl 800a8b0 <TIM_SlaveTimer_SetConfig>
800a210: 4603 mov r3, r0
800a212: 2b00 cmp r3, #0
800a214: d009 beq.n 800a22a <HAL_TIM_SlaveConfigSynchro+0x4a>
{
htim->State = HAL_TIM_STATE_READY;
800a216: 687b ldr r3, [r7, #4]
800a218: 2201 movs r2, #1
800a21a: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800a21e: 687b ldr r3, [r7, #4]
800a220: 2200 movs r2, #0
800a222: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_ERROR;
800a226: 2301 movs r3, #1
800a228: e018 b.n 800a25c <HAL_TIM_SlaveConfigSynchro+0x7c>
}
/* Disable Trigger Interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
800a22a: 687b ldr r3, [r7, #4]
800a22c: 681b ldr r3, [r3, #0]
800a22e: 68da ldr r2, [r3, #12]
800a230: 687b ldr r3, [r7, #4]
800a232: 681b ldr r3, [r3, #0]
800a234: f022 0240 bic.w r2, r2, #64 ; 0x40
800a238: 60da str r2, [r3, #12]
/* Disable Trigger DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
800a23a: 687b ldr r3, [r7, #4]
800a23c: 681b ldr r3, [r3, #0]
800a23e: 68da ldr r2, [r3, #12]
800a240: 687b ldr r3, [r7, #4]
800a242: 681b ldr r3, [r3, #0]
800a244: f422 4280 bic.w r2, r2, #16384 ; 0x4000
800a248: 60da str r2, [r3, #12]
htim->State = HAL_TIM_STATE_READY;
800a24a: 687b ldr r3, [r7, #4]
800a24c: 2201 movs r2, #1
800a24e: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800a252: 687b ldr r3, [r7, #4]
800a254: 2200 movs r2, #0
800a256: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800a25a: 2300 movs r3, #0
}
800a25c: 4618 mov r0, r3
800a25e: 3708 adds r7, #8
800a260: 46bd mov sp, r7
800a262: bd80 pop {r7, pc}
0800a264 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
800a264: b480 push {r7}
800a266: b083 sub sp, #12
800a268: af00 add r7, sp, #0
800a26a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
800a26c: bf00 nop
800a26e: 370c adds r7, #12
800a270: 46bd mov sp, r7
800a272: f85d 7b04 ldr.w r7, [sp], #4
800a276: 4770 bx lr
0800a278 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
800a278: b480 push {r7}
800a27a: b083 sub sp, #12
800a27c: af00 add r7, sp, #0
800a27e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
800a280: bf00 nop
800a282: 370c adds r7, #12
800a284: 46bd mov sp, r7
800a286: f85d 7b04 ldr.w r7, [sp], #4
800a28a: 4770 bx lr
0800a28c <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
800a28c: b480 push {r7}
800a28e: b083 sub sp, #12
800a290: af00 add r7, sp, #0
800a292: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
800a294: bf00 nop
800a296: 370c adds r7, #12
800a298: 46bd mov sp, r7
800a29a: f85d 7b04 ldr.w r7, [sp], #4
800a29e: 4770 bx lr
0800a2a0 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
800a2a0: b480 push {r7}
800a2a2: b083 sub sp, #12
800a2a4: af00 add r7, sp, #0
800a2a6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
800a2a8: bf00 nop
800a2aa: 370c adds r7, #12
800a2ac: 46bd mov sp, r7
800a2ae: f85d 7b04 ldr.w r7, [sp], #4
800a2b2: 4770 bx lr
0800a2b4 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
800a2b4: b480 push {r7}
800a2b6: b085 sub sp, #20
800a2b8: af00 add r7, sp, #0
800a2ba: 6078 str r0, [r7, #4]
800a2bc: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
800a2be: 687b ldr r3, [r7, #4]
800a2c0: 681b ldr r3, [r3, #0]
800a2c2: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
800a2c4: 687b ldr r3, [r7, #4]
800a2c6: 4a40 ldr r2, [pc, #256] ; (800a3c8 <TIM_Base_SetConfig+0x114>)
800a2c8: 4293 cmp r3, r2
800a2ca: d013 beq.n 800a2f4 <TIM_Base_SetConfig+0x40>
800a2cc: 687b ldr r3, [r7, #4]
800a2ce: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
800a2d2: d00f beq.n 800a2f4 <TIM_Base_SetConfig+0x40>
800a2d4: 687b ldr r3, [r7, #4]
800a2d6: 4a3d ldr r2, [pc, #244] ; (800a3cc <TIM_Base_SetConfig+0x118>)
800a2d8: 4293 cmp r3, r2
800a2da: d00b beq.n 800a2f4 <TIM_Base_SetConfig+0x40>
800a2dc: 687b ldr r3, [r7, #4]
800a2de: 4a3c ldr r2, [pc, #240] ; (800a3d0 <TIM_Base_SetConfig+0x11c>)
800a2e0: 4293 cmp r3, r2
800a2e2: d007 beq.n 800a2f4 <TIM_Base_SetConfig+0x40>
800a2e4: 687b ldr r3, [r7, #4]
800a2e6: 4a3b ldr r2, [pc, #236] ; (800a3d4 <TIM_Base_SetConfig+0x120>)
800a2e8: 4293 cmp r3, r2
800a2ea: d003 beq.n 800a2f4 <TIM_Base_SetConfig+0x40>
800a2ec: 687b ldr r3, [r7, #4]
800a2ee: 4a3a ldr r2, [pc, #232] ; (800a3d8 <TIM_Base_SetConfig+0x124>)
800a2f0: 4293 cmp r3, r2
800a2f2: d108 bne.n 800a306 <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
800a2f4: 68fb ldr r3, [r7, #12]
800a2f6: f023 0370 bic.w r3, r3, #112 ; 0x70
800a2fa: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
800a2fc: 683b ldr r3, [r7, #0]
800a2fe: 685b ldr r3, [r3, #4]
800a300: 68fa ldr r2, [r7, #12]
800a302: 4313 orrs r3, r2
800a304: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800a306: 687b ldr r3, [r7, #4]
800a308: 4a2f ldr r2, [pc, #188] ; (800a3c8 <TIM_Base_SetConfig+0x114>)
800a30a: 4293 cmp r3, r2
800a30c: d02b beq.n 800a366 <TIM_Base_SetConfig+0xb2>
800a30e: 687b ldr r3, [r7, #4]
800a310: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
800a314: d027 beq.n 800a366 <TIM_Base_SetConfig+0xb2>
800a316: 687b ldr r3, [r7, #4]
800a318: 4a2c ldr r2, [pc, #176] ; (800a3cc <TIM_Base_SetConfig+0x118>)
800a31a: 4293 cmp r3, r2
800a31c: d023 beq.n 800a366 <TIM_Base_SetConfig+0xb2>
800a31e: 687b ldr r3, [r7, #4]
800a320: 4a2b ldr r2, [pc, #172] ; (800a3d0 <TIM_Base_SetConfig+0x11c>)
800a322: 4293 cmp r3, r2
800a324: d01f beq.n 800a366 <TIM_Base_SetConfig+0xb2>
800a326: 687b ldr r3, [r7, #4]
800a328: 4a2a ldr r2, [pc, #168] ; (800a3d4 <TIM_Base_SetConfig+0x120>)
800a32a: 4293 cmp r3, r2
800a32c: d01b beq.n 800a366 <TIM_Base_SetConfig+0xb2>
800a32e: 687b ldr r3, [r7, #4]
800a330: 4a29 ldr r2, [pc, #164] ; (800a3d8 <TIM_Base_SetConfig+0x124>)
800a332: 4293 cmp r3, r2
800a334: d017 beq.n 800a366 <TIM_Base_SetConfig+0xb2>
800a336: 687b ldr r3, [r7, #4]
800a338: 4a28 ldr r2, [pc, #160] ; (800a3dc <TIM_Base_SetConfig+0x128>)
800a33a: 4293 cmp r3, r2
800a33c: d013 beq.n 800a366 <TIM_Base_SetConfig+0xb2>
800a33e: 687b ldr r3, [r7, #4]
800a340: 4a27 ldr r2, [pc, #156] ; (800a3e0 <TIM_Base_SetConfig+0x12c>)
800a342: 4293 cmp r3, r2
800a344: d00f beq.n 800a366 <TIM_Base_SetConfig+0xb2>
800a346: 687b ldr r3, [r7, #4]
800a348: 4a26 ldr r2, [pc, #152] ; (800a3e4 <TIM_Base_SetConfig+0x130>)
800a34a: 4293 cmp r3, r2
800a34c: d00b beq.n 800a366 <TIM_Base_SetConfig+0xb2>
800a34e: 687b ldr r3, [r7, #4]
800a350: 4a25 ldr r2, [pc, #148] ; (800a3e8 <TIM_Base_SetConfig+0x134>)
800a352: 4293 cmp r3, r2
800a354: d007 beq.n 800a366 <TIM_Base_SetConfig+0xb2>
800a356: 687b ldr r3, [r7, #4]
800a358: 4a24 ldr r2, [pc, #144] ; (800a3ec <TIM_Base_SetConfig+0x138>)
800a35a: 4293 cmp r3, r2
800a35c: d003 beq.n 800a366 <TIM_Base_SetConfig+0xb2>
800a35e: 687b ldr r3, [r7, #4]
800a360: 4a23 ldr r2, [pc, #140] ; (800a3f0 <TIM_Base_SetConfig+0x13c>)
800a362: 4293 cmp r3, r2
800a364: d108 bne.n 800a378 <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800a366: 68fb ldr r3, [r7, #12]
800a368: f423 7340 bic.w r3, r3, #768 ; 0x300
800a36c: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
800a36e: 683b ldr r3, [r7, #0]
800a370: 68db ldr r3, [r3, #12]
800a372: 68fa ldr r2, [r7, #12]
800a374: 4313 orrs r3, r2
800a376: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800a378: 68fb ldr r3, [r7, #12]
800a37a: f023 0280 bic.w r2, r3, #128 ; 0x80
800a37e: 683b ldr r3, [r7, #0]
800a380: 695b ldr r3, [r3, #20]
800a382: 4313 orrs r3, r2
800a384: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
800a386: 687b ldr r3, [r7, #4]
800a388: 68fa ldr r2, [r7, #12]
800a38a: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
800a38c: 683b ldr r3, [r7, #0]
800a38e: 689a ldr r2, [r3, #8]
800a390: 687b ldr r3, [r7, #4]
800a392: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
800a394: 683b ldr r3, [r7, #0]
800a396: 681a ldr r2, [r3, #0]
800a398: 687b ldr r3, [r7, #4]
800a39a: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
800a39c: 687b ldr r3, [r7, #4]
800a39e: 4a0a ldr r2, [pc, #40] ; (800a3c8 <TIM_Base_SetConfig+0x114>)
800a3a0: 4293 cmp r3, r2
800a3a2: d003 beq.n 800a3ac <TIM_Base_SetConfig+0xf8>
800a3a4: 687b ldr r3, [r7, #4]
800a3a6: 4a0c ldr r2, [pc, #48] ; (800a3d8 <TIM_Base_SetConfig+0x124>)
800a3a8: 4293 cmp r3, r2
800a3aa: d103 bne.n 800a3b4 <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
800a3ac: 683b ldr r3, [r7, #0]
800a3ae: 691a ldr r2, [r3, #16]
800a3b0: 687b ldr r3, [r7, #4]
800a3b2: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
800a3b4: 687b ldr r3, [r7, #4]
800a3b6: 2201 movs r2, #1
800a3b8: 615a str r2, [r3, #20]
}
800a3ba: bf00 nop
800a3bc: 3714 adds r7, #20
800a3be: 46bd mov sp, r7
800a3c0: f85d 7b04 ldr.w r7, [sp], #4
800a3c4: 4770 bx lr
800a3c6: bf00 nop
800a3c8: 40010000 .word 0x40010000
800a3cc: 40000400 .word 0x40000400
800a3d0: 40000800 .word 0x40000800
800a3d4: 40000c00 .word 0x40000c00
800a3d8: 40010400 .word 0x40010400
800a3dc: 40014000 .word 0x40014000
800a3e0: 40014400 .word 0x40014400
800a3e4: 40014800 .word 0x40014800
800a3e8: 40001800 .word 0x40001800
800a3ec: 40001c00 .word 0x40001c00
800a3f0: 40002000 .word 0x40002000
0800a3f4 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800a3f4: b480 push {r7}
800a3f6: b087 sub sp, #28
800a3f8: af00 add r7, sp, #0
800a3fa: 6078 str r0, [r7, #4]
800a3fc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
800a3fe: 687b ldr r3, [r7, #4]
800a400: 6a1b ldr r3, [r3, #32]
800a402: f023 0201 bic.w r2, r3, #1
800a406: 687b ldr r3, [r7, #4]
800a408: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a40a: 687b ldr r3, [r7, #4]
800a40c: 6a1b ldr r3, [r3, #32]
800a40e: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a410: 687b ldr r3, [r7, #4]
800a412: 685b ldr r3, [r3, #4]
800a414: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800a416: 687b ldr r3, [r7, #4]
800a418: 699b ldr r3, [r3, #24]
800a41a: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
800a41c: 68fa ldr r2, [r7, #12]
800a41e: 4b2b ldr r3, [pc, #172] ; (800a4cc <TIM_OC1_SetConfig+0xd8>)
800a420: 4013 ands r3, r2
800a422: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
800a424: 68fb ldr r3, [r7, #12]
800a426: f023 0303 bic.w r3, r3, #3
800a42a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800a42c: 683b ldr r3, [r7, #0]
800a42e: 681b ldr r3, [r3, #0]
800a430: 68fa ldr r2, [r7, #12]
800a432: 4313 orrs r3, r2
800a434: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
800a436: 697b ldr r3, [r7, #20]
800a438: f023 0302 bic.w r3, r3, #2
800a43c: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
800a43e: 683b ldr r3, [r7, #0]
800a440: 689b ldr r3, [r3, #8]
800a442: 697a ldr r2, [r7, #20]
800a444: 4313 orrs r3, r2
800a446: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
800a448: 687b ldr r3, [r7, #4]
800a44a: 4a21 ldr r2, [pc, #132] ; (800a4d0 <TIM_OC1_SetConfig+0xdc>)
800a44c: 4293 cmp r3, r2
800a44e: d003 beq.n 800a458 <TIM_OC1_SetConfig+0x64>
800a450: 687b ldr r3, [r7, #4]
800a452: 4a20 ldr r2, [pc, #128] ; (800a4d4 <TIM_OC1_SetConfig+0xe0>)
800a454: 4293 cmp r3, r2
800a456: d10c bne.n 800a472 <TIM_OC1_SetConfig+0x7e>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
800a458: 697b ldr r3, [r7, #20]
800a45a: f023 0308 bic.w r3, r3, #8
800a45e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
800a460: 683b ldr r3, [r7, #0]
800a462: 68db ldr r3, [r3, #12]
800a464: 697a ldr r2, [r7, #20]
800a466: 4313 orrs r3, r2
800a468: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
800a46a: 697b ldr r3, [r7, #20]
800a46c: f023 0304 bic.w r3, r3, #4
800a470: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a472: 687b ldr r3, [r7, #4]
800a474: 4a16 ldr r2, [pc, #88] ; (800a4d0 <TIM_OC1_SetConfig+0xdc>)
800a476: 4293 cmp r3, r2
800a478: d003 beq.n 800a482 <TIM_OC1_SetConfig+0x8e>
800a47a: 687b ldr r3, [r7, #4]
800a47c: 4a15 ldr r2, [pc, #84] ; (800a4d4 <TIM_OC1_SetConfig+0xe0>)
800a47e: 4293 cmp r3, r2
800a480: d111 bne.n 800a4a6 <TIM_OC1_SetConfig+0xb2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
800a482: 693b ldr r3, [r7, #16]
800a484: f423 7380 bic.w r3, r3, #256 ; 0x100
800a488: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
800a48a: 693b ldr r3, [r7, #16]
800a48c: f423 7300 bic.w r3, r3, #512 ; 0x200
800a490: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
800a492: 683b ldr r3, [r7, #0]
800a494: 695b ldr r3, [r3, #20]
800a496: 693a ldr r2, [r7, #16]
800a498: 4313 orrs r3, r2
800a49a: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
800a49c: 683b ldr r3, [r7, #0]
800a49e: 699b ldr r3, [r3, #24]
800a4a0: 693a ldr r2, [r7, #16]
800a4a2: 4313 orrs r3, r2
800a4a4: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a4a6: 687b ldr r3, [r7, #4]
800a4a8: 693a ldr r2, [r7, #16]
800a4aa: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800a4ac: 687b ldr r3, [r7, #4]
800a4ae: 68fa ldr r2, [r7, #12]
800a4b0: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
800a4b2: 683b ldr r3, [r7, #0]
800a4b4: 685a ldr r2, [r3, #4]
800a4b6: 687b ldr r3, [r7, #4]
800a4b8: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a4ba: 687b ldr r3, [r7, #4]
800a4bc: 697a ldr r2, [r7, #20]
800a4be: 621a str r2, [r3, #32]
}
800a4c0: bf00 nop
800a4c2: 371c adds r7, #28
800a4c4: 46bd mov sp, r7
800a4c6: f85d 7b04 ldr.w r7, [sp], #4
800a4ca: 4770 bx lr
800a4cc: fffeff8f .word 0xfffeff8f
800a4d0: 40010000 .word 0x40010000
800a4d4: 40010400 .word 0x40010400
0800a4d8 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800a4d8: b480 push {r7}
800a4da: b087 sub sp, #28
800a4dc: af00 add r7, sp, #0
800a4de: 6078 str r0, [r7, #4]
800a4e0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
800a4e2: 687b ldr r3, [r7, #4]
800a4e4: 6a1b ldr r3, [r3, #32]
800a4e6: f023 0210 bic.w r2, r3, #16
800a4ea: 687b ldr r3, [r7, #4]
800a4ec: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a4ee: 687b ldr r3, [r7, #4]
800a4f0: 6a1b ldr r3, [r3, #32]
800a4f2: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a4f4: 687b ldr r3, [r7, #4]
800a4f6: 685b ldr r3, [r3, #4]
800a4f8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800a4fa: 687b ldr r3, [r7, #4]
800a4fc: 699b ldr r3, [r3, #24]
800a4fe: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
800a500: 68fa ldr r2, [r7, #12]
800a502: 4b2e ldr r3, [pc, #184] ; (800a5bc <TIM_OC2_SetConfig+0xe4>)
800a504: 4013 ands r3, r2
800a506: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
800a508: 68fb ldr r3, [r7, #12]
800a50a: f423 7340 bic.w r3, r3, #768 ; 0x300
800a50e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800a510: 683b ldr r3, [r7, #0]
800a512: 681b ldr r3, [r3, #0]
800a514: 021b lsls r3, r3, #8
800a516: 68fa ldr r2, [r7, #12]
800a518: 4313 orrs r3, r2
800a51a: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
800a51c: 697b ldr r3, [r7, #20]
800a51e: f023 0320 bic.w r3, r3, #32
800a522: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
800a524: 683b ldr r3, [r7, #0]
800a526: 689b ldr r3, [r3, #8]
800a528: 011b lsls r3, r3, #4
800a52a: 697a ldr r2, [r7, #20]
800a52c: 4313 orrs r3, r2
800a52e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
800a530: 687b ldr r3, [r7, #4]
800a532: 4a23 ldr r2, [pc, #140] ; (800a5c0 <TIM_OC2_SetConfig+0xe8>)
800a534: 4293 cmp r3, r2
800a536: d003 beq.n 800a540 <TIM_OC2_SetConfig+0x68>
800a538: 687b ldr r3, [r7, #4]
800a53a: 4a22 ldr r2, [pc, #136] ; (800a5c4 <TIM_OC2_SetConfig+0xec>)
800a53c: 4293 cmp r3, r2
800a53e: d10d bne.n 800a55c <TIM_OC2_SetConfig+0x84>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
800a540: 697b ldr r3, [r7, #20]
800a542: f023 0380 bic.w r3, r3, #128 ; 0x80
800a546: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
800a548: 683b ldr r3, [r7, #0]
800a54a: 68db ldr r3, [r3, #12]
800a54c: 011b lsls r3, r3, #4
800a54e: 697a ldr r2, [r7, #20]
800a550: 4313 orrs r3, r2
800a552: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
800a554: 697b ldr r3, [r7, #20]
800a556: f023 0340 bic.w r3, r3, #64 ; 0x40
800a55a: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a55c: 687b ldr r3, [r7, #4]
800a55e: 4a18 ldr r2, [pc, #96] ; (800a5c0 <TIM_OC2_SetConfig+0xe8>)
800a560: 4293 cmp r3, r2
800a562: d003 beq.n 800a56c <TIM_OC2_SetConfig+0x94>
800a564: 687b ldr r3, [r7, #4]
800a566: 4a17 ldr r2, [pc, #92] ; (800a5c4 <TIM_OC2_SetConfig+0xec>)
800a568: 4293 cmp r3, r2
800a56a: d113 bne.n 800a594 <TIM_OC2_SetConfig+0xbc>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
800a56c: 693b ldr r3, [r7, #16]
800a56e: f423 6380 bic.w r3, r3, #1024 ; 0x400
800a572: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
800a574: 693b ldr r3, [r7, #16]
800a576: f423 6300 bic.w r3, r3, #2048 ; 0x800
800a57a: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
800a57c: 683b ldr r3, [r7, #0]
800a57e: 695b ldr r3, [r3, #20]
800a580: 009b lsls r3, r3, #2
800a582: 693a ldr r2, [r7, #16]
800a584: 4313 orrs r3, r2
800a586: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
800a588: 683b ldr r3, [r7, #0]
800a58a: 699b ldr r3, [r3, #24]
800a58c: 009b lsls r3, r3, #2
800a58e: 693a ldr r2, [r7, #16]
800a590: 4313 orrs r3, r2
800a592: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a594: 687b ldr r3, [r7, #4]
800a596: 693a ldr r2, [r7, #16]
800a598: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800a59a: 687b ldr r3, [r7, #4]
800a59c: 68fa ldr r2, [r7, #12]
800a59e: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
800a5a0: 683b ldr r3, [r7, #0]
800a5a2: 685a ldr r2, [r3, #4]
800a5a4: 687b ldr r3, [r7, #4]
800a5a6: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a5a8: 687b ldr r3, [r7, #4]
800a5aa: 697a ldr r2, [r7, #20]
800a5ac: 621a str r2, [r3, #32]
}
800a5ae: bf00 nop
800a5b0: 371c adds r7, #28
800a5b2: 46bd mov sp, r7
800a5b4: f85d 7b04 ldr.w r7, [sp], #4
800a5b8: 4770 bx lr
800a5ba: bf00 nop
800a5bc: feff8fff .word 0xfeff8fff
800a5c0: 40010000 .word 0x40010000
800a5c4: 40010400 .word 0x40010400
0800a5c8 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800a5c8: b480 push {r7}
800a5ca: b087 sub sp, #28
800a5cc: af00 add r7, sp, #0
800a5ce: 6078 str r0, [r7, #4]
800a5d0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
800a5d2: 687b ldr r3, [r7, #4]
800a5d4: 6a1b ldr r3, [r3, #32]
800a5d6: f423 7280 bic.w r2, r3, #256 ; 0x100
800a5da: 687b ldr r3, [r7, #4]
800a5dc: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a5de: 687b ldr r3, [r7, #4]
800a5e0: 6a1b ldr r3, [r3, #32]
800a5e2: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a5e4: 687b ldr r3, [r7, #4]
800a5e6: 685b ldr r3, [r3, #4]
800a5e8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800a5ea: 687b ldr r3, [r7, #4]
800a5ec: 69db ldr r3, [r3, #28]
800a5ee: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
800a5f0: 68fa ldr r2, [r7, #12]
800a5f2: 4b2d ldr r3, [pc, #180] ; (800a6a8 <TIM_OC3_SetConfig+0xe0>)
800a5f4: 4013 ands r3, r2
800a5f6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
800a5f8: 68fb ldr r3, [r7, #12]
800a5fa: f023 0303 bic.w r3, r3, #3
800a5fe: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800a600: 683b ldr r3, [r7, #0]
800a602: 681b ldr r3, [r3, #0]
800a604: 68fa ldr r2, [r7, #12]
800a606: 4313 orrs r3, r2
800a608: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
800a60a: 697b ldr r3, [r7, #20]
800a60c: f423 7300 bic.w r3, r3, #512 ; 0x200
800a610: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
800a612: 683b ldr r3, [r7, #0]
800a614: 689b ldr r3, [r3, #8]
800a616: 021b lsls r3, r3, #8
800a618: 697a ldr r2, [r7, #20]
800a61a: 4313 orrs r3, r2
800a61c: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
800a61e: 687b ldr r3, [r7, #4]
800a620: 4a22 ldr r2, [pc, #136] ; (800a6ac <TIM_OC3_SetConfig+0xe4>)
800a622: 4293 cmp r3, r2
800a624: d003 beq.n 800a62e <TIM_OC3_SetConfig+0x66>
800a626: 687b ldr r3, [r7, #4]
800a628: 4a21 ldr r2, [pc, #132] ; (800a6b0 <TIM_OC3_SetConfig+0xe8>)
800a62a: 4293 cmp r3, r2
800a62c: d10d bne.n 800a64a <TIM_OC3_SetConfig+0x82>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
800a62e: 697b ldr r3, [r7, #20]
800a630: f423 6300 bic.w r3, r3, #2048 ; 0x800
800a634: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
800a636: 683b ldr r3, [r7, #0]
800a638: 68db ldr r3, [r3, #12]
800a63a: 021b lsls r3, r3, #8
800a63c: 697a ldr r2, [r7, #20]
800a63e: 4313 orrs r3, r2
800a640: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
800a642: 697b ldr r3, [r7, #20]
800a644: f423 6380 bic.w r3, r3, #1024 ; 0x400
800a648: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a64a: 687b ldr r3, [r7, #4]
800a64c: 4a17 ldr r2, [pc, #92] ; (800a6ac <TIM_OC3_SetConfig+0xe4>)
800a64e: 4293 cmp r3, r2
800a650: d003 beq.n 800a65a <TIM_OC3_SetConfig+0x92>
800a652: 687b ldr r3, [r7, #4]
800a654: 4a16 ldr r2, [pc, #88] ; (800a6b0 <TIM_OC3_SetConfig+0xe8>)
800a656: 4293 cmp r3, r2
800a658: d113 bne.n 800a682 <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
800a65a: 693b ldr r3, [r7, #16]
800a65c: f423 5380 bic.w r3, r3, #4096 ; 0x1000
800a660: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
800a662: 693b ldr r3, [r7, #16]
800a664: f423 5300 bic.w r3, r3, #8192 ; 0x2000
800a668: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
800a66a: 683b ldr r3, [r7, #0]
800a66c: 695b ldr r3, [r3, #20]
800a66e: 011b lsls r3, r3, #4
800a670: 693a ldr r2, [r7, #16]
800a672: 4313 orrs r3, r2
800a674: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
800a676: 683b ldr r3, [r7, #0]
800a678: 699b ldr r3, [r3, #24]
800a67a: 011b lsls r3, r3, #4
800a67c: 693a ldr r2, [r7, #16]
800a67e: 4313 orrs r3, r2
800a680: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a682: 687b ldr r3, [r7, #4]
800a684: 693a ldr r2, [r7, #16]
800a686: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800a688: 687b ldr r3, [r7, #4]
800a68a: 68fa ldr r2, [r7, #12]
800a68c: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800a68e: 683b ldr r3, [r7, #0]
800a690: 685a ldr r2, [r3, #4]
800a692: 687b ldr r3, [r7, #4]
800a694: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a696: 687b ldr r3, [r7, #4]
800a698: 697a ldr r2, [r7, #20]
800a69a: 621a str r2, [r3, #32]
}
800a69c: bf00 nop
800a69e: 371c adds r7, #28
800a6a0: 46bd mov sp, r7
800a6a2: f85d 7b04 ldr.w r7, [sp], #4
800a6a6: 4770 bx lr
800a6a8: fffeff8f .word 0xfffeff8f
800a6ac: 40010000 .word 0x40010000
800a6b0: 40010400 .word 0x40010400
0800a6b4 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800a6b4: b480 push {r7}
800a6b6: b087 sub sp, #28
800a6b8: af00 add r7, sp, #0
800a6ba: 6078 str r0, [r7, #4]
800a6bc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
800a6be: 687b ldr r3, [r7, #4]
800a6c0: 6a1b ldr r3, [r3, #32]
800a6c2: f423 5280 bic.w r2, r3, #4096 ; 0x1000
800a6c6: 687b ldr r3, [r7, #4]
800a6c8: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a6ca: 687b ldr r3, [r7, #4]
800a6cc: 6a1b ldr r3, [r3, #32]
800a6ce: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a6d0: 687b ldr r3, [r7, #4]
800a6d2: 685b ldr r3, [r3, #4]
800a6d4: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800a6d6: 687b ldr r3, [r7, #4]
800a6d8: 69db ldr r3, [r3, #28]
800a6da: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
800a6dc: 68fa ldr r2, [r7, #12]
800a6de: 4b1e ldr r3, [pc, #120] ; (800a758 <TIM_OC4_SetConfig+0xa4>)
800a6e0: 4013 ands r3, r2
800a6e2: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
800a6e4: 68fb ldr r3, [r7, #12]
800a6e6: f423 7340 bic.w r3, r3, #768 ; 0x300
800a6ea: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800a6ec: 683b ldr r3, [r7, #0]
800a6ee: 681b ldr r3, [r3, #0]
800a6f0: 021b lsls r3, r3, #8
800a6f2: 68fa ldr r2, [r7, #12]
800a6f4: 4313 orrs r3, r2
800a6f6: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
800a6f8: 693b ldr r3, [r7, #16]
800a6fa: f423 5300 bic.w r3, r3, #8192 ; 0x2000
800a6fe: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
800a700: 683b ldr r3, [r7, #0]
800a702: 689b ldr r3, [r3, #8]
800a704: 031b lsls r3, r3, #12
800a706: 693a ldr r2, [r7, #16]
800a708: 4313 orrs r3, r2
800a70a: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a70c: 687b ldr r3, [r7, #4]
800a70e: 4a13 ldr r2, [pc, #76] ; (800a75c <TIM_OC4_SetConfig+0xa8>)
800a710: 4293 cmp r3, r2
800a712: d003 beq.n 800a71c <TIM_OC4_SetConfig+0x68>
800a714: 687b ldr r3, [r7, #4]
800a716: 4a12 ldr r2, [pc, #72] ; (800a760 <TIM_OC4_SetConfig+0xac>)
800a718: 4293 cmp r3, r2
800a71a: d109 bne.n 800a730 <TIM_OC4_SetConfig+0x7c>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
800a71c: 697b ldr r3, [r7, #20]
800a71e: f423 4380 bic.w r3, r3, #16384 ; 0x4000
800a722: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
800a724: 683b ldr r3, [r7, #0]
800a726: 695b ldr r3, [r3, #20]
800a728: 019b lsls r3, r3, #6
800a72a: 697a ldr r2, [r7, #20]
800a72c: 4313 orrs r3, r2
800a72e: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a730: 687b ldr r3, [r7, #4]
800a732: 697a ldr r2, [r7, #20]
800a734: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800a736: 687b ldr r3, [r7, #4]
800a738: 68fa ldr r2, [r7, #12]
800a73a: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
800a73c: 683b ldr r3, [r7, #0]
800a73e: 685a ldr r2, [r3, #4]
800a740: 687b ldr r3, [r7, #4]
800a742: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a744: 687b ldr r3, [r7, #4]
800a746: 693a ldr r2, [r7, #16]
800a748: 621a str r2, [r3, #32]
}
800a74a: bf00 nop
800a74c: 371c adds r7, #28
800a74e: 46bd mov sp, r7
800a750: f85d 7b04 ldr.w r7, [sp], #4
800a754: 4770 bx lr
800a756: bf00 nop
800a758: feff8fff .word 0xfeff8fff
800a75c: 40010000 .word 0x40010000
800a760: 40010400 .word 0x40010400
0800a764 <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
800a764: b480 push {r7}
800a766: b087 sub sp, #28
800a768: af00 add r7, sp, #0
800a76a: 6078 str r0, [r7, #4]
800a76c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
800a76e: 687b ldr r3, [r7, #4]
800a770: 6a1b ldr r3, [r3, #32]
800a772: f423 3280 bic.w r2, r3, #65536 ; 0x10000
800a776: 687b ldr r3, [r7, #4]
800a778: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a77a: 687b ldr r3, [r7, #4]
800a77c: 6a1b ldr r3, [r3, #32]
800a77e: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a780: 687b ldr r3, [r7, #4]
800a782: 685b ldr r3, [r3, #4]
800a784: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800a786: 687b ldr r3, [r7, #4]
800a788: 6d5b ldr r3, [r3, #84] ; 0x54
800a78a: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
800a78c: 68fa ldr r2, [r7, #12]
800a78e: 4b1b ldr r3, [pc, #108] ; (800a7fc <TIM_OC5_SetConfig+0x98>)
800a790: 4013 ands r3, r2
800a792: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800a794: 683b ldr r3, [r7, #0]
800a796: 681b ldr r3, [r3, #0]
800a798: 68fa ldr r2, [r7, #12]
800a79a: 4313 orrs r3, r2
800a79c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
800a79e: 693b ldr r3, [r7, #16]
800a7a0: f423 3300 bic.w r3, r3, #131072 ; 0x20000
800a7a4: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
800a7a6: 683b ldr r3, [r7, #0]
800a7a8: 689b ldr r3, [r3, #8]
800a7aa: 041b lsls r3, r3, #16
800a7ac: 693a ldr r2, [r7, #16]
800a7ae: 4313 orrs r3, r2
800a7b0: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a7b2: 687b ldr r3, [r7, #4]
800a7b4: 4a12 ldr r2, [pc, #72] ; (800a800 <TIM_OC5_SetConfig+0x9c>)
800a7b6: 4293 cmp r3, r2
800a7b8: d003 beq.n 800a7c2 <TIM_OC5_SetConfig+0x5e>
800a7ba: 687b ldr r3, [r7, #4]
800a7bc: 4a11 ldr r2, [pc, #68] ; (800a804 <TIM_OC5_SetConfig+0xa0>)
800a7be: 4293 cmp r3, r2
800a7c0: d109 bne.n 800a7d6 <TIM_OC5_SetConfig+0x72>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
800a7c2: 697b ldr r3, [r7, #20]
800a7c4: f423 3380 bic.w r3, r3, #65536 ; 0x10000
800a7c8: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
800a7ca: 683b ldr r3, [r7, #0]
800a7cc: 695b ldr r3, [r3, #20]
800a7ce: 021b lsls r3, r3, #8
800a7d0: 697a ldr r2, [r7, #20]
800a7d2: 4313 orrs r3, r2
800a7d4: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a7d6: 687b ldr r3, [r7, #4]
800a7d8: 697a ldr r2, [r7, #20]
800a7da: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
800a7dc: 687b ldr r3, [r7, #4]
800a7de: 68fa ldr r2, [r7, #12]
800a7e0: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
800a7e2: 683b ldr r3, [r7, #0]
800a7e4: 685a ldr r2, [r3, #4]
800a7e6: 687b ldr r3, [r7, #4]
800a7e8: 659a str r2, [r3, #88] ; 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a7ea: 687b ldr r3, [r7, #4]
800a7ec: 693a ldr r2, [r7, #16]
800a7ee: 621a str r2, [r3, #32]
}
800a7f0: bf00 nop
800a7f2: 371c adds r7, #28
800a7f4: 46bd mov sp, r7
800a7f6: f85d 7b04 ldr.w r7, [sp], #4
800a7fa: 4770 bx lr
800a7fc: fffeff8f .word 0xfffeff8f
800a800: 40010000 .word 0x40010000
800a804: 40010400 .word 0x40010400
0800a808 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
800a808: b480 push {r7}
800a80a: b087 sub sp, #28
800a80c: af00 add r7, sp, #0
800a80e: 6078 str r0, [r7, #4]
800a810: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
800a812: 687b ldr r3, [r7, #4]
800a814: 6a1b ldr r3, [r3, #32]
800a816: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
800a81a: 687b ldr r3, [r7, #4]
800a81c: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a81e: 687b ldr r3, [r7, #4]
800a820: 6a1b ldr r3, [r3, #32]
800a822: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a824: 687b ldr r3, [r7, #4]
800a826: 685b ldr r3, [r3, #4]
800a828: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800a82a: 687b ldr r3, [r7, #4]
800a82c: 6d5b ldr r3, [r3, #84] ; 0x54
800a82e: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
800a830: 68fa ldr r2, [r7, #12]
800a832: 4b1c ldr r3, [pc, #112] ; (800a8a4 <TIM_OC6_SetConfig+0x9c>)
800a834: 4013 ands r3, r2
800a836: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800a838: 683b ldr r3, [r7, #0]
800a83a: 681b ldr r3, [r3, #0]
800a83c: 021b lsls r3, r3, #8
800a83e: 68fa ldr r2, [r7, #12]
800a840: 4313 orrs r3, r2
800a842: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
800a844: 693b ldr r3, [r7, #16]
800a846: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
800a84a: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
800a84c: 683b ldr r3, [r7, #0]
800a84e: 689b ldr r3, [r3, #8]
800a850: 051b lsls r3, r3, #20
800a852: 693a ldr r2, [r7, #16]
800a854: 4313 orrs r3, r2
800a856: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a858: 687b ldr r3, [r7, #4]
800a85a: 4a13 ldr r2, [pc, #76] ; (800a8a8 <TIM_OC6_SetConfig+0xa0>)
800a85c: 4293 cmp r3, r2
800a85e: d003 beq.n 800a868 <TIM_OC6_SetConfig+0x60>
800a860: 687b ldr r3, [r7, #4]
800a862: 4a12 ldr r2, [pc, #72] ; (800a8ac <TIM_OC6_SetConfig+0xa4>)
800a864: 4293 cmp r3, r2
800a866: d109 bne.n 800a87c <TIM_OC6_SetConfig+0x74>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
800a868: 697b ldr r3, [r7, #20]
800a86a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800a86e: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
800a870: 683b ldr r3, [r7, #0]
800a872: 695b ldr r3, [r3, #20]
800a874: 029b lsls r3, r3, #10
800a876: 697a ldr r2, [r7, #20]
800a878: 4313 orrs r3, r2
800a87a: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a87c: 687b ldr r3, [r7, #4]
800a87e: 697a ldr r2, [r7, #20]
800a880: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
800a882: 687b ldr r3, [r7, #4]
800a884: 68fa ldr r2, [r7, #12]
800a886: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
800a888: 683b ldr r3, [r7, #0]
800a88a: 685a ldr r2, [r3, #4]
800a88c: 687b ldr r3, [r7, #4]
800a88e: 65da str r2, [r3, #92] ; 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a890: 687b ldr r3, [r7, #4]
800a892: 693a ldr r2, [r7, #16]
800a894: 621a str r2, [r3, #32]
}
800a896: bf00 nop
800a898: 371c adds r7, #28
800a89a: 46bd mov sp, r7
800a89c: f85d 7b04 ldr.w r7, [sp], #4
800a8a0: 4770 bx lr
800a8a2: bf00 nop
800a8a4: feff8fff .word 0xfeff8fff
800a8a8: 40010000 .word 0x40010000
800a8ac: 40010400 .word 0x40010400
0800a8b0 <TIM_SlaveTimer_SetConfig>:
* @param sSlaveConfig Slave timer configuration
* @retval None
*/
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig)
{
800a8b0: b580 push {r7, lr}
800a8b2: b086 sub sp, #24
800a8b4: af00 add r7, sp, #0
800a8b6: 6078 str r0, [r7, #4]
800a8b8: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
800a8ba: 687b ldr r3, [r7, #4]
800a8bc: 681b ldr r3, [r3, #0]
800a8be: 689b ldr r3, [r3, #8]
800a8c0: 617b str r3, [r7, #20]
/* Reset the Trigger Selection Bits */
tmpsmcr &= ~TIM_SMCR_TS;
800a8c2: 697b ldr r3, [r7, #20]
800a8c4: f023 0370 bic.w r3, r3, #112 ; 0x70
800a8c8: 617b str r3, [r7, #20]
/* Set the Input Trigger source */
tmpsmcr |= sSlaveConfig->InputTrigger;
800a8ca: 683b ldr r3, [r7, #0]
800a8cc: 685b ldr r3, [r3, #4]
800a8ce: 697a ldr r2, [r7, #20]
800a8d0: 4313 orrs r3, r2
800a8d2: 617b str r3, [r7, #20]
/* Reset the slave mode Bits */
tmpsmcr &= ~TIM_SMCR_SMS;
800a8d4: 697a ldr r2, [r7, #20]
800a8d6: 4b3d ldr r3, [pc, #244] ; (800a9cc <TIM_SlaveTimer_SetConfig+0x11c>)
800a8d8: 4013 ands r3, r2
800a8da: 617b str r3, [r7, #20]
/* Set the slave mode */
tmpsmcr |= sSlaveConfig->SlaveMode;
800a8dc: 683b ldr r3, [r7, #0]
800a8de: 681b ldr r3, [r3, #0]
800a8e0: 697a ldr r2, [r7, #20]
800a8e2: 4313 orrs r3, r2
800a8e4: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800a8e6: 687b ldr r3, [r7, #4]
800a8e8: 681b ldr r3, [r3, #0]
800a8ea: 697a ldr r2, [r7, #20]
800a8ec: 609a str r2, [r3, #8]
/* Configure the trigger prescaler, filter, and polarity */
switch (sSlaveConfig->InputTrigger)
800a8ee: 683b ldr r3, [r7, #0]
800a8f0: 685b ldr r3, [r3, #4]
800a8f2: 2b70 cmp r3, #112 ; 0x70
800a8f4: d01a beq.n 800a92c <TIM_SlaveTimer_SetConfig+0x7c>
800a8f6: 2b70 cmp r3, #112 ; 0x70
800a8f8: d860 bhi.n 800a9bc <TIM_SlaveTimer_SetConfig+0x10c>
800a8fa: 2b60 cmp r3, #96 ; 0x60
800a8fc: d054 beq.n 800a9a8 <TIM_SlaveTimer_SetConfig+0xf8>
800a8fe: 2b60 cmp r3, #96 ; 0x60
800a900: d85c bhi.n 800a9bc <TIM_SlaveTimer_SetConfig+0x10c>
800a902: 2b50 cmp r3, #80 ; 0x50
800a904: d046 beq.n 800a994 <TIM_SlaveTimer_SetConfig+0xe4>
800a906: 2b50 cmp r3, #80 ; 0x50
800a908: d858 bhi.n 800a9bc <TIM_SlaveTimer_SetConfig+0x10c>
800a90a: 2b40 cmp r3, #64 ; 0x40
800a90c: d019 beq.n 800a942 <TIM_SlaveTimer_SetConfig+0x92>
800a90e: 2b40 cmp r3, #64 ; 0x40
800a910: d854 bhi.n 800a9bc <TIM_SlaveTimer_SetConfig+0x10c>
800a912: 2b30 cmp r3, #48 ; 0x30
800a914: d054 beq.n 800a9c0 <TIM_SlaveTimer_SetConfig+0x110>
800a916: 2b30 cmp r3, #48 ; 0x30
800a918: d850 bhi.n 800a9bc <TIM_SlaveTimer_SetConfig+0x10c>
800a91a: 2b20 cmp r3, #32
800a91c: d050 beq.n 800a9c0 <TIM_SlaveTimer_SetConfig+0x110>
800a91e: 2b20 cmp r3, #32
800a920: d84c bhi.n 800a9bc <TIM_SlaveTimer_SetConfig+0x10c>
800a922: 2b00 cmp r3, #0
800a924: d04c beq.n 800a9c0 <TIM_SlaveTimer_SetConfig+0x110>
800a926: 2b10 cmp r3, #16
800a928: d04a beq.n 800a9c0 <TIM_SlaveTimer_SetConfig+0x110>
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
break;
}
default:
break;
800a92a: e047 b.n 800a9bc <TIM_SlaveTimer_SetConfig+0x10c>
TIM_ETR_SetConfig(htim->Instance,
800a92c: 687b ldr r3, [r7, #4]
800a92e: 6818 ldr r0, [r3, #0]
800a930: 683b ldr r3, [r7, #0]
800a932: 68d9 ldr r1, [r3, #12]
800a934: 683b ldr r3, [r7, #0]
800a936: 689a ldr r2, [r3, #8]
800a938: 683b ldr r3, [r7, #0]
800a93a: 691b ldr r3, [r3, #16]
800a93c: f000 f8c2 bl 800aac4 <TIM_ETR_SetConfig>
break;
800a940: e03f b.n 800a9c2 <TIM_SlaveTimer_SetConfig+0x112>
if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
800a942: 683b ldr r3, [r7, #0]
800a944: 681b ldr r3, [r3, #0]
800a946: 2b05 cmp r3, #5
800a948: d101 bne.n 800a94e <TIM_SlaveTimer_SetConfig+0x9e>
return HAL_ERROR;
800a94a: 2301 movs r3, #1
800a94c: e03a b.n 800a9c4 <TIM_SlaveTimer_SetConfig+0x114>
tmpccer = htim->Instance->CCER;
800a94e: 687b ldr r3, [r7, #4]
800a950: 681b ldr r3, [r3, #0]
800a952: 6a1b ldr r3, [r3, #32]
800a954: 613b str r3, [r7, #16]
htim->Instance->CCER &= ~TIM_CCER_CC1E;
800a956: 687b ldr r3, [r7, #4]
800a958: 681b ldr r3, [r3, #0]
800a95a: 6a1a ldr r2, [r3, #32]
800a95c: 687b ldr r3, [r7, #4]
800a95e: 681b ldr r3, [r3, #0]
800a960: f022 0201 bic.w r2, r2, #1
800a964: 621a str r2, [r3, #32]
tmpccmr1 = htim->Instance->CCMR1;
800a966: 687b ldr r3, [r7, #4]
800a968: 681b ldr r3, [r3, #0]
800a96a: 699b ldr r3, [r3, #24]
800a96c: 60fb str r3, [r7, #12]
tmpccmr1 &= ~TIM_CCMR1_IC1F;
800a96e: 68fb ldr r3, [r7, #12]
800a970: f023 03f0 bic.w r3, r3, #240 ; 0xf0
800a974: 60fb str r3, [r7, #12]
tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
800a976: 683b ldr r3, [r7, #0]
800a978: 691b ldr r3, [r3, #16]
800a97a: 011b lsls r3, r3, #4
800a97c: 68fa ldr r2, [r7, #12]
800a97e: 4313 orrs r3, r2
800a980: 60fb str r3, [r7, #12]
htim->Instance->CCMR1 = tmpccmr1;
800a982: 687b ldr r3, [r7, #4]
800a984: 681b ldr r3, [r3, #0]
800a986: 68fa ldr r2, [r7, #12]
800a988: 619a str r2, [r3, #24]
htim->Instance->CCER = tmpccer;
800a98a: 687b ldr r3, [r7, #4]
800a98c: 681b ldr r3, [r3, #0]
800a98e: 693a ldr r2, [r7, #16]
800a990: 621a str r2, [r3, #32]
break;
800a992: e016 b.n 800a9c2 <TIM_SlaveTimer_SetConfig+0x112>
TIM_TI1_ConfigInputStage(htim->Instance,
800a994: 687b ldr r3, [r7, #4]
800a996: 6818 ldr r0, [r3, #0]
800a998: 683b ldr r3, [r7, #0]
800a99a: 6899 ldr r1, [r3, #8]
800a99c: 683b ldr r3, [r7, #0]
800a99e: 691b ldr r3, [r3, #16]
800a9a0: 461a mov r2, r3
800a9a2: f000 f815 bl 800a9d0 <TIM_TI1_ConfigInputStage>
break;
800a9a6: e00c b.n 800a9c2 <TIM_SlaveTimer_SetConfig+0x112>
TIM_TI2_ConfigInputStage(htim->Instance,
800a9a8: 687b ldr r3, [r7, #4]
800a9aa: 6818 ldr r0, [r3, #0]
800a9ac: 683b ldr r3, [r7, #0]
800a9ae: 6899 ldr r1, [r3, #8]
800a9b0: 683b ldr r3, [r7, #0]
800a9b2: 691b ldr r3, [r3, #16]
800a9b4: 461a mov r2, r3
800a9b6: f000 f83a bl 800aa2e <TIM_TI2_ConfigInputStage>
break;
800a9ba: e002 b.n 800a9c2 <TIM_SlaveTimer_SetConfig+0x112>
break;
800a9bc: bf00 nop
800a9be: e000 b.n 800a9c2 <TIM_SlaveTimer_SetConfig+0x112>
break;
800a9c0: bf00 nop
}
return HAL_OK;
800a9c2: 2300 movs r3, #0
}
800a9c4: 4618 mov r0, r3
800a9c6: 3718 adds r7, #24
800a9c8: 46bd mov sp, r7
800a9ca: bd80 pop {r7, pc}
800a9cc: fffefff8 .word 0xfffefff8
0800a9d0 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
800a9d0: b480 push {r7}
800a9d2: b087 sub sp, #28
800a9d4: af00 add r7, sp, #0
800a9d6: 60f8 str r0, [r7, #12]
800a9d8: 60b9 str r1, [r7, #8]
800a9da: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
800a9dc: 68fb ldr r3, [r7, #12]
800a9de: 6a1b ldr r3, [r3, #32]
800a9e0: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
800a9e2: 68fb ldr r3, [r7, #12]
800a9e4: 6a1b ldr r3, [r3, #32]
800a9e6: f023 0201 bic.w r2, r3, #1
800a9ea: 68fb ldr r3, [r7, #12]
800a9ec: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800a9ee: 68fb ldr r3, [r7, #12]
800a9f0: 699b ldr r3, [r3, #24]
800a9f2: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
800a9f4: 693b ldr r3, [r7, #16]
800a9f6: f023 03f0 bic.w r3, r3, #240 ; 0xf0
800a9fa: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
800a9fc: 687b ldr r3, [r7, #4]
800a9fe: 011b lsls r3, r3, #4
800aa00: 693a ldr r2, [r7, #16]
800aa02: 4313 orrs r3, r2
800aa04: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
800aa06: 697b ldr r3, [r7, #20]
800aa08: f023 030a bic.w r3, r3, #10
800aa0c: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
800aa0e: 697a ldr r2, [r7, #20]
800aa10: 68bb ldr r3, [r7, #8]
800aa12: 4313 orrs r3, r2
800aa14: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
800aa16: 68fb ldr r3, [r7, #12]
800aa18: 693a ldr r2, [r7, #16]
800aa1a: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
800aa1c: 68fb ldr r3, [r7, #12]
800aa1e: 697a ldr r2, [r7, #20]
800aa20: 621a str r2, [r3, #32]
}
800aa22: bf00 nop
800aa24: 371c adds r7, #28
800aa26: 46bd mov sp, r7
800aa28: f85d 7b04 ldr.w r7, [sp], #4
800aa2c: 4770 bx lr
0800aa2e <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
800aa2e: b480 push {r7}
800aa30: b087 sub sp, #28
800aa32: af00 add r7, sp, #0
800aa34: 60f8 str r0, [r7, #12]
800aa36: 60b9 str r1, [r7, #8]
800aa38: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
800aa3a: 68fb ldr r3, [r7, #12]
800aa3c: 6a1b ldr r3, [r3, #32]
800aa3e: f023 0210 bic.w r2, r3, #16
800aa42: 68fb ldr r3, [r7, #12]
800aa44: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800aa46: 68fb ldr r3, [r7, #12]
800aa48: 699b ldr r3, [r3, #24]
800aa4a: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
800aa4c: 68fb ldr r3, [r7, #12]
800aa4e: 6a1b ldr r3, [r3, #32]
800aa50: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
800aa52: 697b ldr r3, [r7, #20]
800aa54: f423 4370 bic.w r3, r3, #61440 ; 0xf000
800aa58: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
800aa5a: 687b ldr r3, [r7, #4]
800aa5c: 031b lsls r3, r3, #12
800aa5e: 697a ldr r2, [r7, #20]
800aa60: 4313 orrs r3, r2
800aa62: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
800aa64: 693b ldr r3, [r7, #16]
800aa66: f023 03a0 bic.w r3, r3, #160 ; 0xa0
800aa6a: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
800aa6c: 68bb ldr r3, [r7, #8]
800aa6e: 011b lsls r3, r3, #4
800aa70: 693a ldr r2, [r7, #16]
800aa72: 4313 orrs r3, r2
800aa74: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
800aa76: 68fb ldr r3, [r7, #12]
800aa78: 697a ldr r2, [r7, #20]
800aa7a: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
800aa7c: 68fb ldr r3, [r7, #12]
800aa7e: 693a ldr r2, [r7, #16]
800aa80: 621a str r2, [r3, #32]
}
800aa82: bf00 nop
800aa84: 371c adds r7, #28
800aa86: 46bd mov sp, r7
800aa88: f85d 7b04 ldr.w r7, [sp], #4
800aa8c: 4770 bx lr
0800aa8e <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
800aa8e: b480 push {r7}
800aa90: b085 sub sp, #20
800aa92: af00 add r7, sp, #0
800aa94: 6078 str r0, [r7, #4]
800aa96: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
800aa98: 687b ldr r3, [r7, #4]
800aa9a: 689b ldr r3, [r3, #8]
800aa9c: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
800aa9e: 68fb ldr r3, [r7, #12]
800aaa0: f023 0370 bic.w r3, r3, #112 ; 0x70
800aaa4: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
800aaa6: 683a ldr r2, [r7, #0]
800aaa8: 68fb ldr r3, [r7, #12]
800aaaa: 4313 orrs r3, r2
800aaac: f043 0307 orr.w r3, r3, #7
800aab0: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
800aab2: 687b ldr r3, [r7, #4]
800aab4: 68fa ldr r2, [r7, #12]
800aab6: 609a str r2, [r3, #8]
}
800aab8: bf00 nop
800aaba: 3714 adds r7, #20
800aabc: 46bd mov sp, r7
800aabe: f85d 7b04 ldr.w r7, [sp], #4
800aac2: 4770 bx lr
0800aac4 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
800aac4: b480 push {r7}
800aac6: b087 sub sp, #28
800aac8: af00 add r7, sp, #0
800aaca: 60f8 str r0, [r7, #12]
800aacc: 60b9 str r1, [r7, #8]
800aace: 607a str r2, [r7, #4]
800aad0: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
800aad2: 68fb ldr r3, [r7, #12]
800aad4: 689b ldr r3, [r3, #8]
800aad6: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800aad8: 697b ldr r3, [r7, #20]
800aada: f423 437f bic.w r3, r3, #65280 ; 0xff00
800aade: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
800aae0: 683b ldr r3, [r7, #0]
800aae2: 021a lsls r2, r3, #8
800aae4: 687b ldr r3, [r7, #4]
800aae6: 431a orrs r2, r3
800aae8: 68bb ldr r3, [r7, #8]
800aaea: 4313 orrs r3, r2
800aaec: 697a ldr r2, [r7, #20]
800aaee: 4313 orrs r3, r2
800aaf0: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
800aaf2: 68fb ldr r3, [r7, #12]
800aaf4: 697a ldr r2, [r7, #20]
800aaf6: 609a str r2, [r3, #8]
}
800aaf8: bf00 nop
800aafa: 371c adds r7, #28
800aafc: 46bd mov sp, r7
800aafe: f85d 7b04 ldr.w r7, [sp], #4
800ab02: 4770 bx lr
0800ab04 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
800ab04: b480 push {r7}
800ab06: b085 sub sp, #20
800ab08: af00 add r7, sp, #0
800ab0a: 6078 str r0, [r7, #4]
800ab0c: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
800ab0e: 687b ldr r3, [r7, #4]
800ab10: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800ab14: 2b01 cmp r3, #1
800ab16: d101 bne.n 800ab1c <HAL_TIMEx_MasterConfigSynchronization+0x18>
800ab18: 2302 movs r3, #2
800ab1a: e06d b.n 800abf8 <HAL_TIMEx_MasterConfigSynchronization+0xf4>
800ab1c: 687b ldr r3, [r7, #4]
800ab1e: 2201 movs r2, #1
800ab20: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
800ab24: 687b ldr r3, [r7, #4]
800ab26: 2202 movs r2, #2
800ab28: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
800ab2c: 687b ldr r3, [r7, #4]
800ab2e: 681b ldr r3, [r3, #0]
800ab30: 685b ldr r3, [r3, #4]
800ab32: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
800ab34: 687b ldr r3, [r7, #4]
800ab36: 681b ldr r3, [r3, #0]
800ab38: 689b ldr r3, [r3, #8]
800ab3a: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
800ab3c: 687b ldr r3, [r7, #4]
800ab3e: 681b ldr r3, [r3, #0]
800ab40: 4a30 ldr r2, [pc, #192] ; (800ac04 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
800ab42: 4293 cmp r3, r2
800ab44: d004 beq.n 800ab50 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
800ab46: 687b ldr r3, [r7, #4]
800ab48: 681b ldr r3, [r3, #0]
800ab4a: 4a2f ldr r2, [pc, #188] ; (800ac08 <HAL_TIMEx_MasterConfigSynchronization+0x104>)
800ab4c: 4293 cmp r3, r2
800ab4e: d108 bne.n 800ab62 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
800ab50: 68fb ldr r3, [r7, #12]
800ab52: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
800ab56: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
800ab58: 683b ldr r3, [r7, #0]
800ab5a: 685b ldr r3, [r3, #4]
800ab5c: 68fa ldr r2, [r7, #12]
800ab5e: 4313 orrs r3, r2
800ab60: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
800ab62: 68fb ldr r3, [r7, #12]
800ab64: f023 0370 bic.w r3, r3, #112 ; 0x70
800ab68: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
800ab6a: 683b ldr r3, [r7, #0]
800ab6c: 681b ldr r3, [r3, #0]
800ab6e: 68fa ldr r2, [r7, #12]
800ab70: 4313 orrs r3, r2
800ab72: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
800ab74: 687b ldr r3, [r7, #4]
800ab76: 681b ldr r3, [r3, #0]
800ab78: 68fa ldr r2, [r7, #12]
800ab7a: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800ab7c: 687b ldr r3, [r7, #4]
800ab7e: 681b ldr r3, [r3, #0]
800ab80: 4a20 ldr r2, [pc, #128] ; (800ac04 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
800ab82: 4293 cmp r3, r2
800ab84: d022 beq.n 800abcc <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800ab86: 687b ldr r3, [r7, #4]
800ab88: 681b ldr r3, [r3, #0]
800ab8a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
800ab8e: d01d beq.n 800abcc <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800ab90: 687b ldr r3, [r7, #4]
800ab92: 681b ldr r3, [r3, #0]
800ab94: 4a1d ldr r2, [pc, #116] ; (800ac0c <HAL_TIMEx_MasterConfigSynchronization+0x108>)
800ab96: 4293 cmp r3, r2
800ab98: d018 beq.n 800abcc <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800ab9a: 687b ldr r3, [r7, #4]
800ab9c: 681b ldr r3, [r3, #0]
800ab9e: 4a1c ldr r2, [pc, #112] ; (800ac10 <HAL_TIMEx_MasterConfigSynchronization+0x10c>)
800aba0: 4293 cmp r3, r2
800aba2: d013 beq.n 800abcc <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800aba4: 687b ldr r3, [r7, #4]
800aba6: 681b ldr r3, [r3, #0]
800aba8: 4a1a ldr r2, [pc, #104] ; (800ac14 <HAL_TIMEx_MasterConfigSynchronization+0x110>)
800abaa: 4293 cmp r3, r2
800abac: d00e beq.n 800abcc <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800abae: 687b ldr r3, [r7, #4]
800abb0: 681b ldr r3, [r3, #0]
800abb2: 4a15 ldr r2, [pc, #84] ; (800ac08 <HAL_TIMEx_MasterConfigSynchronization+0x104>)
800abb4: 4293 cmp r3, r2
800abb6: d009 beq.n 800abcc <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800abb8: 687b ldr r3, [r7, #4]
800abba: 681b ldr r3, [r3, #0]
800abbc: 4a16 ldr r2, [pc, #88] ; (800ac18 <HAL_TIMEx_MasterConfigSynchronization+0x114>)
800abbe: 4293 cmp r3, r2
800abc0: d004 beq.n 800abcc <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800abc2: 687b ldr r3, [r7, #4]
800abc4: 681b ldr r3, [r3, #0]
800abc6: 4a15 ldr r2, [pc, #84] ; (800ac1c <HAL_TIMEx_MasterConfigSynchronization+0x118>)
800abc8: 4293 cmp r3, r2
800abca: d10c bne.n 800abe6 <HAL_TIMEx_MasterConfigSynchronization+0xe2>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800abcc: 68bb ldr r3, [r7, #8]
800abce: f023 0380 bic.w r3, r3, #128 ; 0x80
800abd2: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
800abd4: 683b ldr r3, [r7, #0]
800abd6: 689b ldr r3, [r3, #8]
800abd8: 68ba ldr r2, [r7, #8]
800abda: 4313 orrs r3, r2
800abdc: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800abde: 687b ldr r3, [r7, #4]
800abe0: 681b ldr r3, [r3, #0]
800abe2: 68ba ldr r2, [r7, #8]
800abe4: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
800abe6: 687b ldr r3, [r7, #4]
800abe8: 2201 movs r2, #1
800abea: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800abee: 687b ldr r3, [r7, #4]
800abf0: 2200 movs r2, #0
800abf2: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800abf6: 2300 movs r3, #0
}
800abf8: 4618 mov r0, r3
800abfa: 3714 adds r7, #20
800abfc: 46bd mov sp, r7
800abfe: f85d 7b04 ldr.w r7, [sp], #4
800ac02: 4770 bx lr
800ac04: 40010000 .word 0x40010000
800ac08: 40010400 .word 0x40010400
800ac0c: 40000400 .word 0x40000400
800ac10: 40000800 .word 0x40000800
800ac14: 40000c00 .word 0x40000c00
800ac18: 40014000 .word 0x40014000
800ac1c: 40001800 .word 0x40001800
0800ac20 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
800ac20: b480 push {r7}
800ac22: b085 sub sp, #20
800ac24: af00 add r7, sp, #0
800ac26: 6078 str r0, [r7, #4]
800ac28: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
800ac2a: 2300 movs r3, #0
800ac2c: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
800ac2e: 687b ldr r3, [r7, #4]
800ac30: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800ac34: 2b01 cmp r3, #1
800ac36: d101 bne.n 800ac3c <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
800ac38: 2302 movs r3, #2
800ac3a: e065 b.n 800ad08 <HAL_TIMEx_ConfigBreakDeadTime+0xe8>
800ac3c: 687b ldr r3, [r7, #4]
800ac3e: 2201 movs r2, #1
800ac40: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
800ac44: 68fb ldr r3, [r7, #12]
800ac46: f023 02ff bic.w r2, r3, #255 ; 0xff
800ac4a: 683b ldr r3, [r7, #0]
800ac4c: 68db ldr r3, [r3, #12]
800ac4e: 4313 orrs r3, r2
800ac50: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
800ac52: 68fb ldr r3, [r7, #12]
800ac54: f423 7240 bic.w r2, r3, #768 ; 0x300
800ac58: 683b ldr r3, [r7, #0]
800ac5a: 689b ldr r3, [r3, #8]
800ac5c: 4313 orrs r3, r2
800ac5e: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
800ac60: 68fb ldr r3, [r7, #12]
800ac62: f423 6280 bic.w r2, r3, #1024 ; 0x400
800ac66: 683b ldr r3, [r7, #0]
800ac68: 685b ldr r3, [r3, #4]
800ac6a: 4313 orrs r3, r2
800ac6c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
800ac6e: 68fb ldr r3, [r7, #12]
800ac70: f423 6200 bic.w r2, r3, #2048 ; 0x800
800ac74: 683b ldr r3, [r7, #0]
800ac76: 681b ldr r3, [r3, #0]
800ac78: 4313 orrs r3, r2
800ac7a: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
800ac7c: 68fb ldr r3, [r7, #12]
800ac7e: f423 5280 bic.w r2, r3, #4096 ; 0x1000
800ac82: 683b ldr r3, [r7, #0]
800ac84: 691b ldr r3, [r3, #16]
800ac86: 4313 orrs r3, r2
800ac88: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
800ac8a: 68fb ldr r3, [r7, #12]
800ac8c: f423 5200 bic.w r2, r3, #8192 ; 0x2000
800ac90: 683b ldr r3, [r7, #0]
800ac92: 695b ldr r3, [r3, #20]
800ac94: 4313 orrs r3, r2
800ac96: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
800ac98: 68fb ldr r3, [r7, #12]
800ac9a: f423 4280 bic.w r2, r3, #16384 ; 0x4000
800ac9e: 683b ldr r3, [r7, #0]
800aca0: 6a9b ldr r3, [r3, #40] ; 0x28
800aca2: 4313 orrs r3, r2
800aca4: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
800aca6: 68fb ldr r3, [r7, #12]
800aca8: f423 2270 bic.w r2, r3, #983040 ; 0xf0000
800acac: 683b ldr r3, [r7, #0]
800acae: 699b ldr r3, [r3, #24]
800acb0: 041b lsls r3, r3, #16
800acb2: 4313 orrs r3, r2
800acb4: 60fb str r3, [r7, #12]
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
800acb6: 687b ldr r3, [r7, #4]
800acb8: 681b ldr r3, [r3, #0]
800acba: 4a16 ldr r2, [pc, #88] ; (800ad14 <HAL_TIMEx_ConfigBreakDeadTime+0xf4>)
800acbc: 4293 cmp r3, r2
800acbe: d004 beq.n 800acca <HAL_TIMEx_ConfigBreakDeadTime+0xaa>
800acc0: 687b ldr r3, [r7, #4]
800acc2: 681b ldr r3, [r3, #0]
800acc4: 4a14 ldr r2, [pc, #80] ; (800ad18 <HAL_TIMEx_ConfigBreakDeadTime+0xf8>)
800acc6: 4293 cmp r3, r2
800acc8: d115 bne.n 800acf6 <HAL_TIMEx_ConfigBreakDeadTime+0xd6>
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
800acca: 68fb ldr r3, [r7, #12]
800accc: f423 0270 bic.w r2, r3, #15728640 ; 0xf00000
800acd0: 683b ldr r3, [r7, #0]
800acd2: 6a5b ldr r3, [r3, #36] ; 0x24
800acd4: 051b lsls r3, r3, #20
800acd6: 4313 orrs r3, r2
800acd8: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
800acda: 68fb ldr r3, [r7, #12]
800acdc: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000
800ace0: 683b ldr r3, [r7, #0]
800ace2: 69db ldr r3, [r3, #28]
800ace4: 4313 orrs r3, r2
800ace6: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
800ace8: 68fb ldr r3, [r7, #12]
800acea: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
800acee: 683b ldr r3, [r7, #0]
800acf0: 6a1b ldr r3, [r3, #32]
800acf2: 4313 orrs r3, r2
800acf4: 60fb str r3, [r7, #12]
}
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
800acf6: 687b ldr r3, [r7, #4]
800acf8: 681b ldr r3, [r3, #0]
800acfa: 68fa ldr r2, [r7, #12]
800acfc: 645a str r2, [r3, #68] ; 0x44
__HAL_UNLOCK(htim);
800acfe: 687b ldr r3, [r7, #4]
800ad00: 2200 movs r2, #0
800ad02: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800ad06: 2300 movs r3, #0
}
800ad08: 4618 mov r0, r3
800ad0a: 3714 adds r7, #20
800ad0c: 46bd mov sp, r7
800ad0e: f85d 7b04 ldr.w r7, [sp], #4
800ad12: 4770 bx lr
800ad14: 40010000 .word 0x40010000
800ad18: 40010400 .word 0x40010400
0800ad1c <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
800ad1c: b480 push {r7}
800ad1e: b083 sub sp, #12
800ad20: af00 add r7, sp, #0
800ad22: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
800ad24: bf00 nop
800ad26: 370c adds r7, #12
800ad28: 46bd mov sp, r7
800ad2a: f85d 7b04 ldr.w r7, [sp], #4
800ad2e: 4770 bx lr
0800ad30 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
800ad30: b480 push {r7}
800ad32: b083 sub sp, #12
800ad34: af00 add r7, sp, #0
800ad36: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
800ad38: bf00 nop
800ad3a: 370c adds r7, #12
800ad3c: 46bd mov sp, r7
800ad3e: f85d 7b04 ldr.w r7, [sp], #4
800ad42: 4770 bx lr
0800ad44 <HAL_TIMEx_Break2Callback>:
* @brief Hall Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
800ad44: b480 push {r7}
800ad46: b083 sub sp, #12
800ad48: af00 add r7, sp, #0
800ad4a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
800ad4c: bf00 nop
800ad4e: 370c adds r7, #12
800ad50: 46bd mov sp, r7
800ad52: f85d 7b04 ldr.w r7, [sp], #4
800ad56: 4770 bx lr
0800ad58 <FMC_SDRAM_Init>:
* @param Device Pointer to SDRAM device instance
* @param Init Pointer to SDRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
{
800ad58: b480 push {r7}
800ad5a: b085 sub sp, #20
800ad5c: af00 add r7, sp, #0
800ad5e: 6078 str r0, [r7, #4]
800ad60: 6039 str r1, [r7, #0]
uint32_t tmpr1 = 0;
800ad62: 2300 movs r3, #0
800ad64: 60fb str r3, [r7, #12]
uint32_t tmpr2 = 0;
800ad66: 2300 movs r3, #0
800ad68: 60bb str r3, [r7, #8]
assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
/* Set SDRAM bank configuration parameters */
if (Init->SDBank != FMC_SDRAM_BANK2)
800ad6a: 683b ldr r3, [r7, #0]
800ad6c: 681b ldr r3, [r3, #0]
800ad6e: 2b01 cmp r3, #1
800ad70: d027 beq.n 800adc2 <FMC_SDRAM_Init+0x6a>
{
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
800ad72: 687b ldr r3, [r7, #4]
800ad74: 681b ldr r3, [r3, #0]
800ad76: 60fb str r3, [r7, #12]
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
800ad78: 68fa ldr r2, [r7, #12]
800ad7a: 4b2f ldr r3, [pc, #188] ; (800ae38 <FMC_SDRAM_Init+0xe0>)
800ad7c: 4013 ands r3, r2
800ad7e: 60fb str r3, [r7, #12]
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800ad80: 683b ldr r3, [r7, #0]
800ad82: 685a ldr r2, [r3, #4]
Init->RowBitsNumber |\
800ad84: 683b ldr r3, [r7, #0]
800ad86: 689b ldr r3, [r3, #8]
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800ad88: 431a orrs r2, r3
Init->MemoryDataWidth |\
800ad8a: 683b ldr r3, [r7, #0]
800ad8c: 68db ldr r3, [r3, #12]
Init->RowBitsNumber |\
800ad8e: 431a orrs r2, r3
Init->InternalBankNumber |\
800ad90: 683b ldr r3, [r7, #0]
800ad92: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth |\
800ad94: 431a orrs r2, r3
Init->CASLatency |\
800ad96: 683b ldr r3, [r7, #0]
800ad98: 695b ldr r3, [r3, #20]
Init->InternalBankNumber |\
800ad9a: 431a orrs r2, r3
Init->WriteProtection |\
800ad9c: 683b ldr r3, [r7, #0]
800ad9e: 699b ldr r3, [r3, #24]
Init->CASLatency |\
800ada0: 431a orrs r2, r3
Init->SDClockPeriod |\
800ada2: 683b ldr r3, [r7, #0]
800ada4: 69db ldr r3, [r3, #28]
Init->WriteProtection |\
800ada6: 431a orrs r2, r3
Init->ReadBurst |\
800ada8: 683b ldr r3, [r7, #0]
800adaa: 6a1b ldr r3, [r3, #32]
Init->SDClockPeriod |\
800adac: 431a orrs r2, r3
Init->ReadPipeDelay
800adae: 683b ldr r3, [r7, #0]
800adb0: 6a5b ldr r3, [r3, #36] ; 0x24
Init->ReadBurst |\
800adb2: 4313 orrs r3, r2
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800adb4: 68fa ldr r2, [r7, #12]
800adb6: 4313 orrs r3, r2
800adb8: 60fb str r3, [r7, #12]
);
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
800adba: 687b ldr r3, [r7, #4]
800adbc: 68fa ldr r2, [r7, #12]
800adbe: 601a str r2, [r3, #0]
800adc0: e032 b.n 800ae28 <FMC_SDRAM_Init+0xd0>
}
else /* FMC_Bank2_SDRAM */
{
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
800adc2: 687b ldr r3, [r7, #4]
800adc4: 681b ldr r3, [r3, #0]
800adc6: 60fb str r3, [r7, #12]
/* Clear SDCLK, RBURST, and RPIPE bits */
tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
800adc8: 68fb ldr r3, [r7, #12]
800adca: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
800adce: 60fb str r3, [r7, #12]
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
800add0: 683b ldr r3, [r7, #0]
800add2: 69da ldr r2, [r3, #28]
Init->ReadBurst |\
800add4: 683b ldr r3, [r7, #0]
800add6: 6a1b ldr r3, [r3, #32]
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
800add8: 431a orrs r2, r3
Init->ReadPipeDelay);
800adda: 683b ldr r3, [r7, #0]
800addc: 6a5b ldr r3, [r3, #36] ; 0x24
Init->ReadBurst |\
800adde: 4313 orrs r3, r2
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
800ade0: 68fa ldr r2, [r7, #12]
800ade2: 4313 orrs r3, r2
800ade4: 60fb str r3, [r7, #12]
tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
800ade6: 687b ldr r3, [r7, #4]
800ade8: 685b ldr r3, [r3, #4]
800adea: 60bb str r3, [r7, #8]
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
800adec: 68ba ldr r2, [r7, #8]
800adee: 4b12 ldr r3, [pc, #72] ; (800ae38 <FMC_SDRAM_Init+0xe0>)
800adf0: 4013 ands r3, r2
800adf2: 60bb str r3, [r7, #8]
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
800adf4: 683b ldr r3, [r7, #0]
800adf6: 685a ldr r2, [r3, #4]
Init->RowBitsNumber |\
800adf8: 683b ldr r3, [r7, #0]
800adfa: 689b ldr r3, [r3, #8]
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
800adfc: 431a orrs r2, r3
Init->MemoryDataWidth |\
800adfe: 683b ldr r3, [r7, #0]
800ae00: 68db ldr r3, [r3, #12]
Init->RowBitsNumber |\
800ae02: 431a orrs r2, r3
Init->InternalBankNumber |\
800ae04: 683b ldr r3, [r7, #0]
800ae06: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth |\
800ae08: 431a orrs r2, r3
Init->CASLatency |\
800ae0a: 683b ldr r3, [r7, #0]
800ae0c: 695b ldr r3, [r3, #20]
Init->InternalBankNumber |\
800ae0e: 431a orrs r2, r3
Init->WriteProtection);
800ae10: 683b ldr r3, [r7, #0]
800ae12: 699b ldr r3, [r3, #24]
Init->CASLatency |\
800ae14: 4313 orrs r3, r2
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
800ae16: 68ba ldr r2, [r7, #8]
800ae18: 4313 orrs r3, r2
800ae1a: 60bb str r3, [r7, #8]
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
800ae1c: 687b ldr r3, [r7, #4]
800ae1e: 68fa ldr r2, [r7, #12]
800ae20: 601a str r2, [r3, #0]
Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
800ae22: 687b ldr r3, [r7, #4]
800ae24: 68ba ldr r2, [r7, #8]
800ae26: 605a str r2, [r3, #4]
}
return HAL_OK;
800ae28: 2300 movs r3, #0
}
800ae2a: 4618 mov r0, r3
800ae2c: 3714 adds r7, #20
800ae2e: 46bd mov sp, r7
800ae30: f85d 7b04 ldr.w r7, [sp], #4
800ae34: 4770 bx lr
800ae36: bf00 nop
800ae38: ffff8000 .word 0xffff8000
0800ae3c <FMC_SDRAM_Timing_Init>:
* @param Timing Pointer to SDRAM Timing structure
* @param Bank SDRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
{
800ae3c: b480 push {r7}
800ae3e: b087 sub sp, #28
800ae40: af00 add r7, sp, #0
800ae42: 60f8 str r0, [r7, #12]
800ae44: 60b9 str r1, [r7, #8]
800ae46: 607a str r2, [r7, #4]
uint32_t tmpr1 = 0;
800ae48: 2300 movs r3, #0
800ae4a: 617b str r3, [r7, #20]
uint32_t tmpr2 = 0;
800ae4c: 2300 movs r3, #0
800ae4e: 613b str r3, [r7, #16]
assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
assert_param(IS_FMC_SDRAM_BANK(Bank));
/* Set SDRAM device timing parameters */
if (Bank != FMC_SDRAM_BANK2)
800ae50: 687b ldr r3, [r7, #4]
800ae52: 2b01 cmp r3, #1
800ae54: d02e beq.n 800aeb4 <FMC_SDRAM_Timing_Init+0x78>
{
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
800ae56: 68fb ldr r3, [r7, #12]
800ae58: 689b ldr r3, [r3, #8]
800ae5a: 617b str r3, [r7, #20]
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
800ae5c: 697b ldr r3, [r7, #20]
800ae5e: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
800ae62: 617b str r3, [r7, #20]
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800ae64: 68bb ldr r3, [r7, #8]
800ae66: 681b ldr r3, [r3, #0]
800ae68: 1e5a subs r2, r3, #1
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800ae6a: 68bb ldr r3, [r7, #8]
800ae6c: 685b ldr r3, [r3, #4]
800ae6e: 3b01 subs r3, #1
800ae70: 011b lsls r3, r3, #4
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800ae72: 431a orrs r2, r3
(((Timing->SelfRefreshTime)-1) << 8) |\
800ae74: 68bb ldr r3, [r7, #8]
800ae76: 689b ldr r3, [r3, #8]
800ae78: 3b01 subs r3, #1
800ae7a: 021b lsls r3, r3, #8
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800ae7c: 431a orrs r2, r3
(((Timing->RowCycleDelay)-1) << 12) |\
800ae7e: 68bb ldr r3, [r7, #8]
800ae80: 68db ldr r3, [r3, #12]
800ae82: 3b01 subs r3, #1
800ae84: 031b lsls r3, r3, #12
(((Timing->SelfRefreshTime)-1) << 8) |\
800ae86: 431a orrs r2, r3
(((Timing->WriteRecoveryTime)-1) <<16) |\
800ae88: 68bb ldr r3, [r7, #8]
800ae8a: 691b ldr r3, [r3, #16]
800ae8c: 3b01 subs r3, #1
800ae8e: 041b lsls r3, r3, #16
(((Timing->RowCycleDelay)-1) << 12) |\
800ae90: 431a orrs r2, r3
(((Timing->RPDelay)-1) << 20) |\
800ae92: 68bb ldr r3, [r7, #8]
800ae94: 695b ldr r3, [r3, #20]
800ae96: 3b01 subs r3, #1
800ae98: 051b lsls r3, r3, #20
(((Timing->WriteRecoveryTime)-1) <<16) |\
800ae9a: 431a orrs r2, r3
(((Timing->RCDDelay)-1) << 24));
800ae9c: 68bb ldr r3, [r7, #8]
800ae9e: 699b ldr r3, [r3, #24]
800aea0: 3b01 subs r3, #1
800aea2: 061b lsls r3, r3, #24
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800aea4: 4313 orrs r3, r2
800aea6: 697a ldr r2, [r7, #20]
800aea8: 4313 orrs r3, r2
800aeaa: 617b str r3, [r7, #20]
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
800aeac: 68fb ldr r3, [r7, #12]
800aeae: 697a ldr r2, [r7, #20]
800aeb0: 609a str r2, [r3, #8]
800aeb2: e039 b.n 800af28 <FMC_SDRAM_Timing_Init+0xec>
}
else /* FMC_Bank2_SDRAM */
{
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
800aeb4: 68fb ldr r3, [r7, #12]
800aeb6: 689b ldr r3, [r3, #8]
800aeb8: 617b str r3, [r7, #20]
/* Clear TRC and TRP bits */
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
800aeba: 697a ldr r2, [r7, #20]
800aebc: 4b1e ldr r3, [pc, #120] ; (800af38 <FMC_SDRAM_Timing_Init+0xfc>)
800aebe: 4013 ands r3, r2
800aec0: 617b str r3, [r7, #20]
tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
800aec2: 68bb ldr r3, [r7, #8]
800aec4: 68db ldr r3, [r3, #12]
800aec6: 3b01 subs r3, #1
800aec8: 031a lsls r2, r3, #12
(((Timing->RPDelay)-1) << 20));
800aeca: 68bb ldr r3, [r7, #8]
800aecc: 695b ldr r3, [r3, #20]
800aece: 3b01 subs r3, #1
800aed0: 051b lsls r3, r3, #20
tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
800aed2: 4313 orrs r3, r2
800aed4: 697a ldr r2, [r7, #20]
800aed6: 4313 orrs r3, r2
800aed8: 617b str r3, [r7, #20]
tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
800aeda: 68fb ldr r3, [r7, #12]
800aedc: 68db ldr r3, [r3, #12]
800aede: 613b str r3, [r7, #16]
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
800aee0: 693b ldr r3, [r7, #16]
800aee2: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
800aee6: 613b str r3, [r7, #16]
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800aee8: 68bb ldr r3, [r7, #8]
800aeea: 681b ldr r3, [r3, #0]
800aeec: 1e5a subs r2, r3, #1
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800aeee: 68bb ldr r3, [r7, #8]
800aef0: 685b ldr r3, [r3, #4]
800aef2: 3b01 subs r3, #1
800aef4: 011b lsls r3, r3, #4
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800aef6: 431a orrs r2, r3
(((Timing->SelfRefreshTime)-1) << 8) |\
800aef8: 68bb ldr r3, [r7, #8]
800aefa: 689b ldr r3, [r3, #8]
800aefc: 3b01 subs r3, #1
800aefe: 021b lsls r3, r3, #8
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800af00: 431a orrs r2, r3
(((Timing->WriteRecoveryTime)-1) <<16) |\
800af02: 68bb ldr r3, [r7, #8]
800af04: 691b ldr r3, [r3, #16]
800af06: 3b01 subs r3, #1
800af08: 041b lsls r3, r3, #16
(((Timing->SelfRefreshTime)-1) << 8) |\
800af0a: 431a orrs r2, r3
(((Timing->RCDDelay)-1) << 24));
800af0c: 68bb ldr r3, [r7, #8]
800af0e: 699b ldr r3, [r3, #24]
800af10: 3b01 subs r3, #1
800af12: 061b lsls r3, r3, #24
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800af14: 4313 orrs r3, r2
800af16: 693a ldr r2, [r7, #16]
800af18: 4313 orrs r3, r2
800af1a: 613b str r3, [r7, #16]
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
800af1c: 68fb ldr r3, [r7, #12]
800af1e: 697a ldr r2, [r7, #20]
800af20: 609a str r2, [r3, #8]
Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
800af22: 68fb ldr r3, [r7, #12]
800af24: 693a ldr r2, [r7, #16]
800af26: 60da str r2, [r3, #12]
}
return HAL_OK;
800af28: 2300 movs r3, #0
}
800af2a: 4618 mov r0, r3
800af2c: 371c adds r7, #28
800af2e: 46bd mov sp, r7
800af30: f85d 7b04 ldr.w r7, [sp], #4
800af34: 4770 bx lr
800af36: bf00 nop
800af38: ff0f0fff .word 0xff0f0fff
0800af3c <FMC_SDRAM_SendCommand>:
* @param Timing Pointer to SDRAM Timing structure
* @param Timeout Timeout wait value
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
{
800af3c: b480 push {r7}
800af3e: b085 sub sp, #20
800af40: af00 add r7, sp, #0
800af42: 60f8 str r0, [r7, #12]
800af44: 60b9 str r1, [r7, #8]
800af46: 607a str r2, [r7, #4]
assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
/* Set command register */
MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 |
800af48: 68fb ldr r3, [r7, #12]
800af4a: 691a ldr r2, [r3, #16]
800af4c: 4b0c ldr r3, [pc, #48] ; (800af80 <FMC_SDRAM_SendCommand+0x44>)
800af4e: 4013 ands r3, r2
800af50: 68ba ldr r2, [r7, #8]
800af52: 6811 ldr r1, [r2, #0]
800af54: 68ba ldr r2, [r7, #8]
800af56: 6852 ldr r2, [r2, #4]
800af58: 4311 orrs r1, r2
800af5a: 68ba ldr r2, [r7, #8]
800af5c: 6892 ldr r2, [r2, #8]
800af5e: 3a01 subs r2, #1
800af60: 0152 lsls r2, r2, #5
800af62: 4311 orrs r1, r2
800af64: 68ba ldr r2, [r7, #8]
800af66: 68d2 ldr r2, [r2, #12]
800af68: 0252 lsls r2, r2, #9
800af6a: 430a orrs r2, r1
800af6c: 431a orrs r2, r3
800af6e: 68fb ldr r3, [r7, #12]
800af70: 611a str r2, [r3, #16]
FMC_SDCMR_NRFS | FMC_SDCMR_MRD), ((Command->CommandMode) |
(Command->CommandTarget) | (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
return HAL_OK;
800af72: 2300 movs r3, #0
}
800af74: 4618 mov r0, r3
800af76: 3714 adds r7, #20
800af78: 46bd mov sp, r7
800af7a: f85d 7b04 ldr.w r7, [sp], #4
800af7e: 4770 bx lr
800af80: ffc00000 .word 0xffc00000
0800af84 <FMC_SDRAM_ProgramRefreshRate>:
* @param Device Pointer to SDRAM device instance
* @param RefreshRate The SDRAM refresh rate value.
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
{
800af84: b480 push {r7}
800af86: b083 sub sp, #12
800af88: af00 add r7, sp, #0
800af8a: 6078 str r0, [r7, #4]
800af8c: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_FMC_SDRAM_DEVICE(Device));
assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
/* Set the refresh rate in command register */
Device->SDRTR |= (RefreshRate<<1);
800af8e: 687b ldr r3, [r7, #4]
800af90: 695a ldr r2, [r3, #20]
800af92: 683b ldr r3, [r7, #0]
800af94: 005b lsls r3, r3, #1
800af96: 431a orrs r2, r3
800af98: 687b ldr r3, [r7, #4]
800af9a: 615a str r2, [r3, #20]
return HAL_OK;
800af9c: 2300 movs r3, #0
}
800af9e: 4618 mov r0, r3
800afa0: 370c adds r7, #12
800afa2: 46bd mov sp, r7
800afa4: f85d 7b04 ldr.w r7, [sp], #4
800afa8: 4770 bx lr
...
0800afac <MX_LWIP_Init>:
/**
* LwIP initialization function
*/
void MX_LWIP_Init(void)
{
800afac: b5b0 push {r4, r5, r7, lr}
800afae: b08e sub sp, #56 ; 0x38
800afb0: af04 add r7, sp, #16
/* Initilialize the LwIP stack with RTOS */
tcpip_init( NULL, NULL );
800afb2: 2100 movs r1, #0
800afb4: 2000 movs r0, #0
800afb6: f003 fef7 bl 800eda8 <tcpip_init>
/* IP addresses initialization with DHCP (IPv4) */
ipaddr.addr = 0;
800afba: 4b2a ldr r3, [pc, #168] ; (800b064 <MX_LWIP_Init+0xb8>)
800afbc: 2200 movs r2, #0
800afbe: 601a str r2, [r3, #0]
netmask.addr = 0;
800afc0: 4b29 ldr r3, [pc, #164] ; (800b068 <MX_LWIP_Init+0xbc>)
800afc2: 2200 movs r2, #0
800afc4: 601a str r2, [r3, #0]
gw.addr = 0;
800afc6: 4b29 ldr r3, [pc, #164] ; (800b06c <MX_LWIP_Init+0xc0>)
800afc8: 2200 movs r2, #0
800afca: 601a str r2, [r3, #0]
/* add the network interface (IPv4/IPv6) with RTOS */
netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, &ethernetif_init, &tcpip_input);
800afcc: 4b28 ldr r3, [pc, #160] ; (800b070 <MX_LWIP_Init+0xc4>)
800afce: 9302 str r3, [sp, #8]
800afd0: 4b28 ldr r3, [pc, #160] ; (800b074 <MX_LWIP_Init+0xc8>)
800afd2: 9301 str r3, [sp, #4]
800afd4: 2300 movs r3, #0
800afd6: 9300 str r3, [sp, #0]
800afd8: 4b24 ldr r3, [pc, #144] ; (800b06c <MX_LWIP_Init+0xc0>)
800afda: 4a23 ldr r2, [pc, #140] ; (800b068 <MX_LWIP_Init+0xbc>)
800afdc: 4921 ldr r1, [pc, #132] ; (800b064 <MX_LWIP_Init+0xb8>)
800afde: 4826 ldr r0, [pc, #152] ; (800b078 <MX_LWIP_Init+0xcc>)
800afe0: f004 fc66 bl 800f8b0 <netif_add>
/* Registers the default network interface */
netif_set_default(&gnetif);
800afe4: 4824 ldr r0, [pc, #144] ; (800b078 <MX_LWIP_Init+0xcc>)
800afe6: f004 fe1d bl 800fc24 <netif_set_default>
if (netif_is_link_up(&gnetif))
800afea: 4b23 ldr r3, [pc, #140] ; (800b078 <MX_LWIP_Init+0xcc>)
800afec: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800aff0: 089b lsrs r3, r3, #2
800aff2: f003 0301 and.w r3, r3, #1
800aff6: b2db uxtb r3, r3
800aff8: 2b00 cmp r3, #0
800affa: d003 beq.n 800b004 <MX_LWIP_Init+0x58>
{
/* When the netif is fully configured this function must be called */
netif_set_up(&gnetif);
800affc: 481e ldr r0, [pc, #120] ; (800b078 <MX_LWIP_Init+0xcc>)
800affe: f004 fe21 bl 800fc44 <netif_set_up>
800b002: e002 b.n 800b00a <MX_LWIP_Init+0x5e>
}
else
{
/* When the netif link is down this function must be called */
netif_set_down(&gnetif);
800b004: 481c ldr r0, [pc, #112] ; (800b078 <MX_LWIP_Init+0xcc>)
800b006: f004 fe89 bl 800fd1c <netif_set_down>
}
/* Set the link callback function, this function is called on change of link status*/
netif_set_link_callback(&gnetif, ethernetif_update_config);
800b00a: 491c ldr r1, [pc, #112] ; (800b07c <MX_LWIP_Init+0xd0>)
800b00c: 481a ldr r0, [pc, #104] ; (800b078 <MX_LWIP_Init+0xcc>)
800b00e: f004 ff1f bl 800fe50 <netif_set_link_callback>
/* create a binary semaphore used for informing ethernetif of frame reception */
osSemaphoreDef(Netif_SEM);
800b012: 2300 movs r3, #0
800b014: 623b str r3, [r7, #32]
800b016: 2300 movs r3, #0
800b018: 627b str r3, [r7, #36] ; 0x24
Netif_LinkSemaphore = osSemaphoreCreate(osSemaphore(Netif_SEM) , 1 );
800b01a: f107 0320 add.w r3, r7, #32
800b01e: 2101 movs r1, #1
800b020: 4618 mov r0, r3
800b022: f000 fd75 bl 800bb10 <osSemaphoreCreate>
800b026: 4603 mov r3, r0
800b028: 4a15 ldr r2, [pc, #84] ; (800b080 <MX_LWIP_Init+0xd4>)
800b02a: 6013 str r3, [r2, #0]
link_arg.netif = &gnetif;
800b02c: 4b15 ldr r3, [pc, #84] ; (800b084 <MX_LWIP_Init+0xd8>)
800b02e: 4a12 ldr r2, [pc, #72] ; (800b078 <MX_LWIP_Init+0xcc>)
800b030: 601a str r2, [r3, #0]
link_arg.semaphore = Netif_LinkSemaphore;
800b032: 4b13 ldr r3, [pc, #76] ; (800b080 <MX_LWIP_Init+0xd4>)
800b034: 681b ldr r3, [r3, #0]
800b036: 4a13 ldr r2, [pc, #76] ; (800b084 <MX_LWIP_Init+0xd8>)
800b038: 6053 str r3, [r2, #4]
/* Create the Ethernet link handler thread */
/* USER CODE BEGIN OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
osThreadDef(LinkThr, ethernetif_set_link, osPriorityBelowNormal, 0, configMINIMAL_STACK_SIZE * 2);
800b03a: 4b13 ldr r3, [pc, #76] ; (800b088 <MX_LWIP_Init+0xdc>)
800b03c: 1d3c adds r4, r7, #4
800b03e: 461d mov r5, r3
800b040: cd0f ldmia r5!, {r0, r1, r2, r3}
800b042: c40f stmia r4!, {r0, r1, r2, r3}
800b044: e895 0007 ldmia.w r5, {r0, r1, r2}
800b048: e884 0007 stmia.w r4, {r0, r1, r2}
osThreadCreate (osThread(LinkThr), &link_arg);
800b04c: 1d3b adds r3, r7, #4
800b04e: 490d ldr r1, [pc, #52] ; (800b084 <MX_LWIP_Init+0xd8>)
800b050: 4618 mov r0, r3
800b052: f000 fc60 bl 800b916 <osThreadCreate>
/* USER CODE END OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
/* Start DHCP negotiation for a network interface (IPv4) */
dhcp_start(&gnetif);
800b056: 4808 ldr r0, [pc, #32] ; (800b078 <MX_LWIP_Init+0xcc>)
800b058: f00c f85e bl 8017118 <dhcp_start>
/* USER CODE BEGIN 3 */
/* USER CODE END 3 */
}
800b05c: bf00 nop
800b05e: 3728 adds r7, #40 ; 0x28
800b060: 46bd mov sp, r7
800b062: bdb0 pop {r4, r5, r7, pc}
800b064: 20009010 .word 0x20009010
800b068: 20009014 .word 0x20009014
800b06c: 20009018 .word 0x20009018
800b070: 0800ece5 .word 0x0800ece5
800b074: 0800b6a5 .word 0x0800b6a5
800b078: 20008fd8 .word 0x20008fd8
800b07c: 0800b789 .word 0x0800b789
800b080: 20000578 .word 0x20000578
800b084: 20008fd0 .word 0x20008fd0
800b088: 0801c10c .word 0x0801c10c
0800b08c <HAL_ETH_MspInit>:
/* USER CODE END 3 */
/* Private functions ---------------------------------------------------------*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle)
{
800b08c: b580 push {r7, lr}
800b08e: b08e sub sp, #56 ; 0x38
800b090: af00 add r7, sp, #0
800b092: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800b094: f107 0324 add.w r3, r7, #36 ; 0x24
800b098: 2200 movs r2, #0
800b09a: 601a str r2, [r3, #0]
800b09c: 605a str r2, [r3, #4]
800b09e: 609a str r2, [r3, #8]
800b0a0: 60da str r2, [r3, #12]
800b0a2: 611a str r2, [r3, #16]
if(ethHandle->Instance==ETH)
800b0a4: 687b ldr r3, [r7, #4]
800b0a6: 681b ldr r3, [r3, #0]
800b0a8: 4a44 ldr r2, [pc, #272] ; (800b1bc <HAL_ETH_MspInit+0x130>)
800b0aa: 4293 cmp r3, r2
800b0ac: f040 8081 bne.w 800b1b2 <HAL_ETH_MspInit+0x126>
{
/* USER CODE BEGIN ETH_MspInit 0 */
/* USER CODE END ETH_MspInit 0 */
/* Enable Peripheral clock */
__HAL_RCC_ETH_CLK_ENABLE();
800b0b0: 4b43 ldr r3, [pc, #268] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b0b2: 6b1b ldr r3, [r3, #48] ; 0x30
800b0b4: 4a42 ldr r2, [pc, #264] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b0b6: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
800b0ba: 6313 str r3, [r2, #48] ; 0x30
800b0bc: 4b40 ldr r3, [pc, #256] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b0be: 6b1b ldr r3, [r3, #48] ; 0x30
800b0c0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800b0c4: 623b str r3, [r7, #32]
800b0c6: 6a3b ldr r3, [r7, #32]
800b0c8: 4b3d ldr r3, [pc, #244] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b0ca: 6b1b ldr r3, [r3, #48] ; 0x30
800b0cc: 4a3c ldr r2, [pc, #240] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b0ce: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
800b0d2: 6313 str r3, [r2, #48] ; 0x30
800b0d4: 4b3a ldr r3, [pc, #232] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b0d6: 6b1b ldr r3, [r3, #48] ; 0x30
800b0d8: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
800b0dc: 61fb str r3, [r7, #28]
800b0de: 69fb ldr r3, [r7, #28]
800b0e0: 4b37 ldr r3, [pc, #220] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b0e2: 6b1b ldr r3, [r3, #48] ; 0x30
800b0e4: 4a36 ldr r2, [pc, #216] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b0e6: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000
800b0ea: 6313 str r3, [r2, #48] ; 0x30
800b0ec: 4b34 ldr r3, [pc, #208] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b0ee: 6b1b ldr r3, [r3, #48] ; 0x30
800b0f0: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
800b0f4: 61bb str r3, [r7, #24]
800b0f6: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOG_CLK_ENABLE();
800b0f8: 4b31 ldr r3, [pc, #196] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b0fa: 6b1b ldr r3, [r3, #48] ; 0x30
800b0fc: 4a30 ldr r2, [pc, #192] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b0fe: f043 0340 orr.w r3, r3, #64 ; 0x40
800b102: 6313 str r3, [r2, #48] ; 0x30
800b104: 4b2e ldr r3, [pc, #184] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b106: 6b1b ldr r3, [r3, #48] ; 0x30
800b108: f003 0340 and.w r3, r3, #64 ; 0x40
800b10c: 617b str r3, [r7, #20]
800b10e: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOC_CLK_ENABLE();
800b110: 4b2b ldr r3, [pc, #172] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b112: 6b1b ldr r3, [r3, #48] ; 0x30
800b114: 4a2a ldr r2, [pc, #168] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b116: f043 0304 orr.w r3, r3, #4
800b11a: 6313 str r3, [r2, #48] ; 0x30
800b11c: 4b28 ldr r3, [pc, #160] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b11e: 6b1b ldr r3, [r3, #48] ; 0x30
800b120: f003 0304 and.w r3, r3, #4
800b124: 613b str r3, [r7, #16]
800b126: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800b128: 4b25 ldr r3, [pc, #148] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b12a: 6b1b ldr r3, [r3, #48] ; 0x30
800b12c: 4a24 ldr r2, [pc, #144] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b12e: f043 0301 orr.w r3, r3, #1
800b132: 6313 str r3, [r2, #48] ; 0x30
800b134: 4b22 ldr r3, [pc, #136] ; (800b1c0 <HAL_ETH_MspInit+0x134>)
800b136: 6b1b ldr r3, [r3, #48] ; 0x30
800b138: f003 0301 and.w r3, r3, #1
800b13c: 60fb str r3, [r7, #12]
800b13e: 68fb ldr r3, [r7, #12]
PC4 ------> ETH_RXD0
PA2 ------> ETH_MDIO
PC5 ------> ETH_RXD1
PA7 ------> ETH_CRS_DV
*/
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_11;
800b140: f44f 43d0 mov.w r3, #26624 ; 0x6800
800b144: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800b146: 2302 movs r3, #2
800b148: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800b14a: 2300 movs r3, #0
800b14c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800b14e: 2303 movs r3, #3
800b150: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
800b152: 230b movs r3, #11
800b154: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
800b156: f107 0324 add.w r3, r7, #36 ; 0x24
800b15a: 4619 mov r1, r3
800b15c: 4819 ldr r0, [pc, #100] ; (800b1c4 <HAL_ETH_MspInit+0x138>)
800b15e: f7fb ffcf bl 8007100 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
800b162: 2332 movs r3, #50 ; 0x32
800b164: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800b166: 2302 movs r3, #2
800b168: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800b16a: 2300 movs r3, #0
800b16c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800b16e: 2303 movs r3, #3
800b170: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
800b172: 230b movs r3, #11
800b174: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800b176: f107 0324 add.w r3, r7, #36 ; 0x24
800b17a: 4619 mov r1, r3
800b17c: 4812 ldr r0, [pc, #72] ; (800b1c8 <HAL_ETH_MspInit+0x13c>)
800b17e: f7fb ffbf bl 8007100 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
800b182: 2386 movs r3, #134 ; 0x86
800b184: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800b186: 2302 movs r3, #2
800b188: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800b18a: 2300 movs r3, #0
800b18c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800b18e: 2303 movs r3, #3
800b190: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
800b192: 230b movs r3, #11
800b194: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800b196: f107 0324 add.w r3, r7, #36 ; 0x24
800b19a: 4619 mov r1, r3
800b19c: 480b ldr r0, [pc, #44] ; (800b1cc <HAL_ETH_MspInit+0x140>)
800b19e: f7fb ffaf bl 8007100 <HAL_GPIO_Init>
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(ETH_IRQn, 5, 0);
800b1a2: 2200 movs r2, #0
800b1a4: 2105 movs r1, #5
800b1a6: 203d movs r0, #61 ; 0x3d
800b1a8: f7f9 ffe8 bl 800517c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(ETH_IRQn);
800b1ac: 203d movs r0, #61 ; 0x3d
800b1ae: f7fa f801 bl 80051b4 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN ETH_MspInit 1 */
/* USER CODE END ETH_MspInit 1 */
}
}
800b1b2: bf00 nop
800b1b4: 3738 adds r7, #56 ; 0x38
800b1b6: 46bd mov sp, r7
800b1b8: bd80 pop {r7, pc}
800b1ba: bf00 nop
800b1bc: 40028000 .word 0x40028000
800b1c0: 40023800 .word 0x40023800
800b1c4: 40021800 .word 0x40021800
800b1c8: 40020800 .word 0x40020800
800b1cc: 40020000 .word 0x40020000
0800b1d0 <HAL_ETH_RxCpltCallback>:
* @brief Ethernet Rx Transfer completed callback
* @param heth: ETH handle
* @retval None
*/
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
{
800b1d0: b580 push {r7, lr}
800b1d2: b082 sub sp, #8
800b1d4: af00 add r7, sp, #0
800b1d6: 6078 str r0, [r7, #4]
osSemaphoreRelease(s_xSemaphore);
800b1d8: 4b04 ldr r3, [pc, #16] ; (800b1ec <HAL_ETH_RxCpltCallback+0x1c>)
800b1da: 681b ldr r3, [r3, #0]
800b1dc: 4618 mov r0, r3
800b1de: f000 fd25 bl 800bc2c <osSemaphoreRelease>
}
800b1e2: bf00 nop
800b1e4: 3708 adds r7, #8
800b1e6: 46bd mov sp, r7
800b1e8: bd80 pop {r7, pc}
800b1ea: bf00 nop
800b1ec: 2000057c .word 0x2000057c
0800b1f0 <low_level_init>:
*
* @param netif the already initialized lwip network interface structure
* for this ethernetif
*/
static void low_level_init(struct netif *netif)
{
800b1f0: b5b0 push {r4, r5, r7, lr}
800b1f2: b090 sub sp, #64 ; 0x40
800b1f4: af00 add r7, sp, #0
800b1f6: 6078 str r0, [r7, #4]
uint32_t regvalue = 0;
800b1f8: 2300 movs r3, #0
800b1fa: 63bb str r3, [r7, #56] ; 0x38
HAL_StatusTypeDef hal_eth_init_status;
/* Init ETH */
uint8_t MACAddr[6] ;
heth.Instance = ETH;
800b1fc: 4b60 ldr r3, [pc, #384] ; (800b380 <low_level_init+0x190>)
800b1fe: 4a61 ldr r2, [pc, #388] ; (800b384 <low_level_init+0x194>)
800b200: 601a str r2, [r3, #0]
heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
800b202: 4b5f ldr r3, [pc, #380] ; (800b380 <low_level_init+0x190>)
800b204: 2201 movs r2, #1
800b206: 605a str r2, [r3, #4]
heth.Init.Speed = ETH_SPEED_100M;
800b208: 4b5d ldr r3, [pc, #372] ; (800b380 <low_level_init+0x190>)
800b20a: f44f 4280 mov.w r2, #16384 ; 0x4000
800b20e: 609a str r2, [r3, #8]
heth.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
800b210: 4b5b ldr r3, [pc, #364] ; (800b380 <low_level_init+0x190>)
800b212: f44f 6200 mov.w r2, #2048 ; 0x800
800b216: 60da str r2, [r3, #12]
heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
800b218: 4b59 ldr r3, [pc, #356] ; (800b380 <low_level_init+0x190>)
800b21a: 2201 movs r2, #1
800b21c: 821a strh r2, [r3, #16]
MACAddr[0] = 0x00;
800b21e: 2300 movs r3, #0
800b220: f887 3030 strb.w r3, [r7, #48] ; 0x30
MACAddr[1] = 0x80;
800b224: 2380 movs r3, #128 ; 0x80
800b226: f887 3031 strb.w r3, [r7, #49] ; 0x31
MACAddr[2] = 0xE1;
800b22a: 23e1 movs r3, #225 ; 0xe1
800b22c: f887 3032 strb.w r3, [r7, #50] ; 0x32
MACAddr[3] = 0x00;
800b230: 2300 movs r3, #0
800b232: f887 3033 strb.w r3, [r7, #51] ; 0x33
MACAddr[4] = 0xE0;
800b236: 23e0 movs r3, #224 ; 0xe0
800b238: f887 3034 strb.w r3, [r7, #52] ; 0x34
MACAddr[5] = 0x00;
800b23c: 2300 movs r3, #0
800b23e: f887 3035 strb.w r3, [r7, #53] ; 0x35
heth.Init.MACAddr = &MACAddr[0];
800b242: 4a4f ldr r2, [pc, #316] ; (800b380 <low_level_init+0x190>)
800b244: f107 0330 add.w r3, r7, #48 ; 0x30
800b248: 6153 str r3, [r2, #20]
heth.Init.RxMode = ETH_RXINTERRUPT_MODE;
800b24a: 4b4d ldr r3, [pc, #308] ; (800b380 <low_level_init+0x190>)
800b24c: 2201 movs r2, #1
800b24e: 619a str r2, [r3, #24]
heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
800b250: 4b4b ldr r3, [pc, #300] ; (800b380 <low_level_init+0x190>)
800b252: 2200 movs r2, #0
800b254: 61da str r2, [r3, #28]
heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
800b256: 4b4a ldr r3, [pc, #296] ; (800b380 <low_level_init+0x190>)
800b258: f44f 0200 mov.w r2, #8388608 ; 0x800000
800b25c: 621a str r2, [r3, #32]
/* USER CODE BEGIN MACADDRESS */
/* USER CODE END MACADDRESS */
hal_eth_init_status = HAL_ETH_Init(&heth);
800b25e: 4848 ldr r0, [pc, #288] ; (800b380 <low_level_init+0x190>)
800b260: f7fa fdca bl 8005df8 <HAL_ETH_Init>
800b264: 4603 mov r3, r0
800b266: f887 303f strb.w r3, [r7, #63] ; 0x3f
if (hal_eth_init_status == HAL_OK)
800b26a: f897 303f ldrb.w r3, [r7, #63] ; 0x3f
800b26e: 2b00 cmp r3, #0
800b270: d108 bne.n 800b284 <low_level_init+0x94>
{
/* Set netif link flag */
netif->flags |= NETIF_FLAG_LINK_UP;
800b272: 687b ldr r3, [r7, #4]
800b274: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b278: f043 0304 orr.w r3, r3, #4
800b27c: b2da uxtb r2, r3
800b27e: 687b ldr r3, [r7, #4]
800b280: f883 2031 strb.w r2, [r3, #49] ; 0x31
}
/* Initialize Tx Descriptors list: Chain Mode */
HAL_ETH_DMATxDescListInit(&heth, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
800b284: 2304 movs r3, #4
800b286: 4a40 ldr r2, [pc, #256] ; (800b388 <low_level_init+0x198>)
800b288: 4940 ldr r1, [pc, #256] ; (800b38c <low_level_init+0x19c>)
800b28a: 483d ldr r0, [pc, #244] ; (800b380 <low_level_init+0x190>)
800b28c: f7fa ff4e bl 800612c <HAL_ETH_DMATxDescListInit>
/* Initialize Rx Descriptors list: Chain Mode */
HAL_ETH_DMARxDescListInit(&heth, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
800b290: 2304 movs r3, #4
800b292: 4a3f ldr r2, [pc, #252] ; (800b390 <low_level_init+0x1a0>)
800b294: 493f ldr r1, [pc, #252] ; (800b394 <low_level_init+0x1a4>)
800b296: 483a ldr r0, [pc, #232] ; (800b380 <low_level_init+0x190>)
800b298: f7fa ffb1 bl 80061fe <HAL_ETH_DMARxDescListInit>
#if LWIP_ARP || LWIP_ETHERNET
/* set MAC hardware address length */
netif->hwaddr_len = ETH_HWADDR_LEN;
800b29c: 687b ldr r3, [r7, #4]
800b29e: 2206 movs r2, #6
800b2a0: f883 2030 strb.w r2, [r3, #48] ; 0x30
/* set MAC hardware address */
netif->hwaddr[0] = heth.Init.MACAddr[0];
800b2a4: 4b36 ldr r3, [pc, #216] ; (800b380 <low_level_init+0x190>)
800b2a6: 695b ldr r3, [r3, #20]
800b2a8: 781a ldrb r2, [r3, #0]
800b2aa: 687b ldr r3, [r7, #4]
800b2ac: f883 202a strb.w r2, [r3, #42] ; 0x2a
netif->hwaddr[1] = heth.Init.MACAddr[1];
800b2b0: 4b33 ldr r3, [pc, #204] ; (800b380 <low_level_init+0x190>)
800b2b2: 695b ldr r3, [r3, #20]
800b2b4: 785a ldrb r2, [r3, #1]
800b2b6: 687b ldr r3, [r7, #4]
800b2b8: f883 202b strb.w r2, [r3, #43] ; 0x2b
netif->hwaddr[2] = heth.Init.MACAddr[2];
800b2bc: 4b30 ldr r3, [pc, #192] ; (800b380 <low_level_init+0x190>)
800b2be: 695b ldr r3, [r3, #20]
800b2c0: 789a ldrb r2, [r3, #2]
800b2c2: 687b ldr r3, [r7, #4]
800b2c4: f883 202c strb.w r2, [r3, #44] ; 0x2c
netif->hwaddr[3] = heth.Init.MACAddr[3];
800b2c8: 4b2d ldr r3, [pc, #180] ; (800b380 <low_level_init+0x190>)
800b2ca: 695b ldr r3, [r3, #20]
800b2cc: 78da ldrb r2, [r3, #3]
800b2ce: 687b ldr r3, [r7, #4]
800b2d0: f883 202d strb.w r2, [r3, #45] ; 0x2d
netif->hwaddr[4] = heth.Init.MACAddr[4];
800b2d4: 4b2a ldr r3, [pc, #168] ; (800b380 <low_level_init+0x190>)
800b2d6: 695b ldr r3, [r3, #20]
800b2d8: 791a ldrb r2, [r3, #4]
800b2da: 687b ldr r3, [r7, #4]
800b2dc: f883 202e strb.w r2, [r3, #46] ; 0x2e
netif->hwaddr[5] = heth.Init.MACAddr[5];
800b2e0: 4b27 ldr r3, [pc, #156] ; (800b380 <low_level_init+0x190>)
800b2e2: 695b ldr r3, [r3, #20]
800b2e4: 795a ldrb r2, [r3, #5]
800b2e6: 687b ldr r3, [r7, #4]
800b2e8: f883 202f strb.w r2, [r3, #47] ; 0x2f
/* maximum transfer unit */
netif->mtu = 1500;
800b2ec: 687b ldr r3, [r7, #4]
800b2ee: f240 52dc movw r2, #1500 ; 0x5dc
800b2f2: 851a strh r2, [r3, #40] ; 0x28
/* Accept broadcast address and ARP traffic */
/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
#if LWIP_ARP
netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
800b2f4: 687b ldr r3, [r7, #4]
800b2f6: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b2fa: f043 030a orr.w r3, r3, #10
800b2fe: b2da uxtb r2, r3
800b300: 687b ldr r3, [r7, #4]
800b302: f883 2031 strb.w r2, [r3, #49] ; 0x31
#else
netif->flags |= NETIF_FLAG_BROADCAST;
#endif /* LWIP_ARP */
/* create a binary semaphore used for informing ethernetif of frame reception */
osSemaphoreDef(SEM);
800b306: 2300 movs r3, #0
800b308: 62bb str r3, [r7, #40] ; 0x28
800b30a: 2300 movs r3, #0
800b30c: 62fb str r3, [r7, #44] ; 0x2c
s_xSemaphore = osSemaphoreCreate(osSemaphore(SEM), 1);
800b30e: f107 0328 add.w r3, r7, #40 ; 0x28
800b312: 2101 movs r1, #1
800b314: 4618 mov r0, r3
800b316: f000 fbfb bl 800bb10 <osSemaphoreCreate>
800b31a: 4603 mov r3, r0
800b31c: 4a1e ldr r2, [pc, #120] ; (800b398 <low_level_init+0x1a8>)
800b31e: 6013 str r3, [r2, #0]
/* create the task that handles the ETH_MAC */
/* USER CODE BEGIN OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
osThreadDef(EthIf, ethernetif_input, osPriorityRealtime, 0, INTERFACE_THREAD_STACK_SIZE);
800b320: 4b1e ldr r3, [pc, #120] ; (800b39c <low_level_init+0x1ac>)
800b322: f107 040c add.w r4, r7, #12
800b326: 461d mov r5, r3
800b328: cd0f ldmia r5!, {r0, r1, r2, r3}
800b32a: c40f stmia r4!, {r0, r1, r2, r3}
800b32c: e895 0007 ldmia.w r5, {r0, r1, r2}
800b330: e884 0007 stmia.w r4, {r0, r1, r2}
osThreadCreate (osThread(EthIf), netif);
800b334: f107 030c add.w r3, r7, #12
800b338: 6879 ldr r1, [r7, #4]
800b33a: 4618 mov r0, r3
800b33c: f000 faeb bl 800b916 <osThreadCreate>
/* USER CODE END OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
/* Enable MAC and DMA transmission and reception */
HAL_ETH_Start(&heth);
800b340: 480f ldr r0, [pc, #60] ; (800b380 <low_level_init+0x190>)
800b342: f7fb fa84 bl 800684e <HAL_ETH_Start>
/* USER CODE BEGIN PHY_PRE_CONFIG */
/* USER CODE END PHY_PRE_CONFIG */
/* Read Register Configuration */
HAL_ETH_ReadPHYRegister(&heth, PHY_ISFR, &regvalue);
800b346: f107 0338 add.w r3, r7, #56 ; 0x38
800b34a: 461a mov r2, r3
800b34c: 211d movs r1, #29
800b34e: 480c ldr r0, [pc, #48] ; (800b380 <low_level_init+0x190>)
800b350: f7fb f9af bl 80066b2 <HAL_ETH_ReadPHYRegister>
regvalue |= (PHY_ISFR_INT4);
800b354: 6bbb ldr r3, [r7, #56] ; 0x38
800b356: f043 030b orr.w r3, r3, #11
800b35a: 63bb str r3, [r7, #56] ; 0x38
/* Enable Interrupt on change of link status */
HAL_ETH_WritePHYRegister(&heth, PHY_ISFR , regvalue );
800b35c: 6bbb ldr r3, [r7, #56] ; 0x38
800b35e: 461a mov r2, r3
800b360: 211d movs r1, #29
800b362: 4807 ldr r0, [pc, #28] ; (800b380 <low_level_init+0x190>)
800b364: f7fb fa0d bl 8006782 <HAL_ETH_WritePHYRegister>
/* Read Register Configuration */
HAL_ETH_ReadPHYRegister(&heth, PHY_ISFR , &regvalue);
800b368: f107 0338 add.w r3, r7, #56 ; 0x38
800b36c: 461a mov r2, r3
800b36e: 211d movs r1, #29
800b370: 4803 ldr r0, [pc, #12] ; (800b380 <low_level_init+0x190>)
800b372: f7fb f99e bl 80066b2 <HAL_ETH_ReadPHYRegister>
#endif /* LWIP_ARP || LWIP_ETHERNET */
/* USER CODE BEGIN LOW_LEVEL_INIT */
/* USER CODE END LOW_LEVEL_INIT */
}
800b376: bf00 nop
800b378: 3740 adds r7, #64 ; 0x40
800b37a: 46bd mov sp, r7
800b37c: bdb0 pop {r4, r5, r7, pc}
800b37e: bf00 nop
800b380: 2000a8ec .word 0x2000a8ec
800b384: 40028000 .word 0x40028000
800b388: 2000a934 .word 0x2000a934
800b38c: 2000901c .word 0x2000901c
800b390: 2000909c .word 0x2000909c
800b394: 2000a86c .word 0x2000a86c
800b398: 2000057c .word 0x2000057c
800b39c: 0801c130 .word 0x0801c130
0800b3a0 <low_level_output>:
* to become available since the stack doesn't retry to send a packet
* dropped because of memory failure (except for the TCP timers).
*/
static err_t low_level_output(struct netif *netif, struct pbuf *p)
{
800b3a0: b580 push {r7, lr}
800b3a2: b08a sub sp, #40 ; 0x28
800b3a4: af00 add r7, sp, #0
800b3a6: 6078 str r0, [r7, #4]
800b3a8: 6039 str r1, [r7, #0]
err_t errval;
struct pbuf *q;
uint8_t *buffer = (uint8_t *)(heth.TxDesc->Buffer1Addr);
800b3aa: 4b4b ldr r3, [pc, #300] ; (800b4d8 <low_level_output+0x138>)
800b3ac: 6adb ldr r3, [r3, #44] ; 0x2c
800b3ae: 689b ldr r3, [r3, #8]
800b3b0: 61fb str r3, [r7, #28]
__IO ETH_DMADescTypeDef *DmaTxDesc;
uint32_t framelength = 0;
800b3b2: 2300 movs r3, #0
800b3b4: 617b str r3, [r7, #20]
uint32_t bufferoffset = 0;
800b3b6: 2300 movs r3, #0
800b3b8: 613b str r3, [r7, #16]
uint32_t byteslefttocopy = 0;
800b3ba: 2300 movs r3, #0
800b3bc: 60fb str r3, [r7, #12]
uint32_t payloadoffset = 0;
800b3be: 2300 movs r3, #0
800b3c0: 60bb str r3, [r7, #8]
DmaTxDesc = heth.TxDesc;
800b3c2: 4b45 ldr r3, [pc, #276] ; (800b4d8 <low_level_output+0x138>)
800b3c4: 6adb ldr r3, [r3, #44] ; 0x2c
800b3c6: 61bb str r3, [r7, #24]
bufferoffset = 0;
800b3c8: 2300 movs r3, #0
800b3ca: 613b str r3, [r7, #16]
/* copy frame from pbufs to driver buffers */
for(q = p; q != NULL; q = q->next)
800b3cc: 683b ldr r3, [r7, #0]
800b3ce: 623b str r3, [r7, #32]
800b3d0: e05a b.n 800b488 <low_level_output+0xe8>
{
/* Is this buffer available? If not, goto error */
if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
800b3d2: 69bb ldr r3, [r7, #24]
800b3d4: 681b ldr r3, [r3, #0]
800b3d6: 2b00 cmp r3, #0
800b3d8: da03 bge.n 800b3e2 <low_level_output+0x42>
{
errval = ERR_USE;
800b3da: 23f8 movs r3, #248 ; 0xf8
800b3dc: f887 3027 strb.w r3, [r7, #39] ; 0x27
goto error;
800b3e0: e05c b.n 800b49c <low_level_output+0xfc>
}
/* Get bytes in current lwIP buffer */
byteslefttocopy = q->len;
800b3e2: 6a3b ldr r3, [r7, #32]
800b3e4: 895b ldrh r3, [r3, #10]
800b3e6: 60fb str r3, [r7, #12]
payloadoffset = 0;
800b3e8: 2300 movs r3, #0
800b3ea: 60bb str r3, [r7, #8]
/* Check if the length of data to copy is bigger than Tx buffer size*/
while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
800b3ec: e02f b.n 800b44e <low_level_output+0xae>
{
/* Copy data to Tx buffer*/
memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset) );
800b3ee: 69fa ldr r2, [r7, #28]
800b3f0: 693b ldr r3, [r7, #16]
800b3f2: 18d0 adds r0, r2, r3
800b3f4: 6a3b ldr r3, [r7, #32]
800b3f6: 685a ldr r2, [r3, #4]
800b3f8: 68bb ldr r3, [r7, #8]
800b3fa: 18d1 adds r1, r2, r3
800b3fc: 693a ldr r2, [r7, #16]
800b3fe: f240 53f4 movw r3, #1524 ; 0x5f4
800b402: 1a9b subs r3, r3, r2
800b404: 461a mov r2, r3
800b406: f00f fdc7 bl 801af98 <memcpy>
/* Point to next descriptor */
DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
800b40a: 69bb ldr r3, [r7, #24]
800b40c: 68db ldr r3, [r3, #12]
800b40e: 61bb str r3, [r7, #24]
/* Check if the buffer is available */
if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
800b410: 69bb ldr r3, [r7, #24]
800b412: 681b ldr r3, [r3, #0]
800b414: 2b00 cmp r3, #0
800b416: da03 bge.n 800b420 <low_level_output+0x80>
{
errval = ERR_USE;
800b418: 23f8 movs r3, #248 ; 0xf8
800b41a: f887 3027 strb.w r3, [r7, #39] ; 0x27
goto error;
800b41e: e03d b.n 800b49c <low_level_output+0xfc>
}
buffer = (uint8_t *)(DmaTxDesc->Buffer1Addr);
800b420: 69bb ldr r3, [r7, #24]
800b422: 689b ldr r3, [r3, #8]
800b424: 61fb str r3, [r7, #28]
byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
800b426: 693a ldr r2, [r7, #16]
800b428: 68fb ldr r3, [r7, #12]
800b42a: 4413 add r3, r2
800b42c: f2a3 53f4 subw r3, r3, #1524 ; 0x5f4
800b430: 60fb str r3, [r7, #12]
payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
800b432: 68ba ldr r2, [r7, #8]
800b434: 693b ldr r3, [r7, #16]
800b436: 1ad3 subs r3, r2, r3
800b438: f203 53f4 addw r3, r3, #1524 ; 0x5f4
800b43c: 60bb str r3, [r7, #8]
framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
800b43e: 697a ldr r2, [r7, #20]
800b440: 693b ldr r3, [r7, #16]
800b442: 1ad3 subs r3, r2, r3
800b444: f203 53f4 addw r3, r3, #1524 ; 0x5f4
800b448: 617b str r3, [r7, #20]
bufferoffset = 0;
800b44a: 2300 movs r3, #0
800b44c: 613b str r3, [r7, #16]
while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
800b44e: 68fa ldr r2, [r7, #12]
800b450: 693b ldr r3, [r7, #16]
800b452: 4413 add r3, r2
800b454: f240 52f4 movw r2, #1524 ; 0x5f4
800b458: 4293 cmp r3, r2
800b45a: d8c8 bhi.n 800b3ee <low_level_output+0x4e>
}
/* Copy the remaining bytes */
memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), byteslefttocopy );
800b45c: 69fa ldr r2, [r7, #28]
800b45e: 693b ldr r3, [r7, #16]
800b460: 18d0 adds r0, r2, r3
800b462: 6a3b ldr r3, [r7, #32]
800b464: 685a ldr r2, [r3, #4]
800b466: 68bb ldr r3, [r7, #8]
800b468: 4413 add r3, r2
800b46a: 68fa ldr r2, [r7, #12]
800b46c: 4619 mov r1, r3
800b46e: f00f fd93 bl 801af98 <memcpy>
bufferoffset = bufferoffset + byteslefttocopy;
800b472: 693a ldr r2, [r7, #16]
800b474: 68fb ldr r3, [r7, #12]
800b476: 4413 add r3, r2
800b478: 613b str r3, [r7, #16]
framelength = framelength + byteslefttocopy;
800b47a: 697a ldr r2, [r7, #20]
800b47c: 68fb ldr r3, [r7, #12]
800b47e: 4413 add r3, r2
800b480: 617b str r3, [r7, #20]
for(q = p; q != NULL; q = q->next)
800b482: 6a3b ldr r3, [r7, #32]
800b484: 681b ldr r3, [r3, #0]
800b486: 623b str r3, [r7, #32]
800b488: 6a3b ldr r3, [r7, #32]
800b48a: 2b00 cmp r3, #0
800b48c: d1a1 bne.n 800b3d2 <low_level_output+0x32>
}
/* Prepare transmit descriptors to give to DMA */
HAL_ETH_TransmitFrame(&heth, framelength);
800b48e: 6979 ldr r1, [r7, #20]
800b490: 4811 ldr r0, [pc, #68] ; (800b4d8 <low_level_output+0x138>)
800b492: f7fa ff21 bl 80062d8 <HAL_ETH_TransmitFrame>
errval = ERR_OK;
800b496: 2300 movs r3, #0
800b498: f887 3027 strb.w r3, [r7, #39] ; 0x27
error:
/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
if ((heth.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET)
800b49c: 4b0e ldr r3, [pc, #56] ; (800b4d8 <low_level_output+0x138>)
800b49e: 681a ldr r2, [r3, #0]
800b4a0: f241 0314 movw r3, #4116 ; 0x1014
800b4a4: 4413 add r3, r2
800b4a6: 681b ldr r3, [r3, #0]
800b4a8: f003 0320 and.w r3, r3, #32
800b4ac: 2b00 cmp r3, #0
800b4ae: d00d beq.n 800b4cc <low_level_output+0x12c>
{
/* Clear TUS ETHERNET DMA flag */
heth.Instance->DMASR = ETH_DMASR_TUS;
800b4b0: 4b09 ldr r3, [pc, #36] ; (800b4d8 <low_level_output+0x138>)
800b4b2: 681a ldr r2, [r3, #0]
800b4b4: f241 0314 movw r3, #4116 ; 0x1014
800b4b8: 4413 add r3, r2
800b4ba: 2220 movs r2, #32
800b4bc: 601a str r2, [r3, #0]
/* Resume DMA transmission*/
heth.Instance->DMATPDR = 0;
800b4be: 4b06 ldr r3, [pc, #24] ; (800b4d8 <low_level_output+0x138>)
800b4c0: 681a ldr r2, [r3, #0]
800b4c2: f241 0304 movw r3, #4100 ; 0x1004
800b4c6: 4413 add r3, r2
800b4c8: 2200 movs r2, #0
800b4ca: 601a str r2, [r3, #0]
}
return errval;
800b4cc: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
}
800b4d0: 4618 mov r0, r3
800b4d2: 3728 adds r7, #40 ; 0x28
800b4d4: 46bd mov sp, r7
800b4d6: bd80 pop {r7, pc}
800b4d8: 2000a8ec .word 0x2000a8ec
0800b4dc <low_level_input>:
* @param netif the lwip network interface structure for this ethernetif
* @return a pbuf filled with the received packet (including MAC header)
* NULL on memory error
*/
static struct pbuf * low_level_input(struct netif *netif)
{
800b4dc: b580 push {r7, lr}
800b4de: b08c sub sp, #48 ; 0x30
800b4e0: af00 add r7, sp, #0
800b4e2: 6078 str r0, [r7, #4]
struct pbuf *p = NULL;
800b4e4: 2300 movs r3, #0
800b4e6: 62fb str r3, [r7, #44] ; 0x2c
struct pbuf *q = NULL;
800b4e8: 2300 movs r3, #0
800b4ea: 62bb str r3, [r7, #40] ; 0x28
uint16_t len = 0;
800b4ec: 2300 movs r3, #0
800b4ee: 81fb strh r3, [r7, #14]
uint8_t *buffer;
__IO ETH_DMADescTypeDef *dmarxdesc;
uint32_t bufferoffset = 0;
800b4f0: 2300 movs r3, #0
800b4f2: 61fb str r3, [r7, #28]
uint32_t payloadoffset = 0;
800b4f4: 2300 movs r3, #0
800b4f6: 61bb str r3, [r7, #24]
uint32_t byteslefttocopy = 0;
800b4f8: 2300 movs r3, #0
800b4fa: 617b str r3, [r7, #20]
uint32_t i=0;
800b4fc: 2300 movs r3, #0
800b4fe: 613b str r3, [r7, #16]
/* get received frame */
if (HAL_ETH_GetReceivedFrame_IT(&heth) != HAL_OK)
800b500: 484f ldr r0, [pc, #316] ; (800b640 <low_level_input+0x164>)
800b502: f7fa ffd3 bl 80064ac <HAL_ETH_GetReceivedFrame_IT>
800b506: 4603 mov r3, r0
800b508: 2b00 cmp r3, #0
800b50a: d001 beq.n 800b510 <low_level_input+0x34>
return NULL;
800b50c: 2300 movs r3, #0
800b50e: e092 b.n 800b636 <low_level_input+0x15a>
/* Obtain the size of the packet and put it into the "len" variable. */
len = heth.RxFrameInfos.length;
800b510: 4b4b ldr r3, [pc, #300] ; (800b640 <low_level_input+0x164>)
800b512: 6bdb ldr r3, [r3, #60] ; 0x3c
800b514: 81fb strh r3, [r7, #14]
buffer = (uint8_t *)heth.RxFrameInfos.buffer;
800b516: 4b4a ldr r3, [pc, #296] ; (800b640 <low_level_input+0x164>)
800b518: 6c1b ldr r3, [r3, #64] ; 0x40
800b51a: 627b str r3, [r7, #36] ; 0x24
if (len > 0)
800b51c: 89fb ldrh r3, [r7, #14]
800b51e: 2b00 cmp r3, #0
800b520: d007 beq.n 800b532 <low_level_input+0x56>
{
/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
800b522: 89fb ldrh r3, [r7, #14]
800b524: f44f 72c1 mov.w r2, #386 ; 0x182
800b528: 4619 mov r1, r3
800b52a: 2000 movs r0, #0
800b52c: f004 fd5a bl 800ffe4 <pbuf_alloc>
800b530: 62f8 str r0, [r7, #44] ; 0x2c
}
if (p != NULL)
800b532: 6afb ldr r3, [r7, #44] ; 0x2c
800b534: 2b00 cmp r3, #0
800b536: d04b beq.n 800b5d0 <low_level_input+0xf4>
{
dmarxdesc = heth.RxFrameInfos.FSRxDesc;
800b538: 4b41 ldr r3, [pc, #260] ; (800b640 <low_level_input+0x164>)
800b53a: 6b1b ldr r3, [r3, #48] ; 0x30
800b53c: 623b str r3, [r7, #32]
bufferoffset = 0;
800b53e: 2300 movs r3, #0
800b540: 61fb str r3, [r7, #28]
for(q = p; q != NULL; q = q->next)
800b542: 6afb ldr r3, [r7, #44] ; 0x2c
800b544: 62bb str r3, [r7, #40] ; 0x28
800b546: e040 b.n 800b5ca <low_level_input+0xee>
{
byteslefttocopy = q->len;
800b548: 6abb ldr r3, [r7, #40] ; 0x28
800b54a: 895b ldrh r3, [r3, #10]
800b54c: 617b str r3, [r7, #20]
payloadoffset = 0;
800b54e: 2300 movs r3, #0
800b550: 61bb str r3, [r7, #24]
/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
800b552: e021 b.n 800b598 <low_level_input+0xbc>
{
/* Copy data to pbuf */
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
800b554: 6abb ldr r3, [r7, #40] ; 0x28
800b556: 685a ldr r2, [r3, #4]
800b558: 69bb ldr r3, [r7, #24]
800b55a: 18d0 adds r0, r2, r3
800b55c: 6a7a ldr r2, [r7, #36] ; 0x24
800b55e: 69fb ldr r3, [r7, #28]
800b560: 18d1 adds r1, r2, r3
800b562: 69fa ldr r2, [r7, #28]
800b564: f240 53f4 movw r3, #1524 ; 0x5f4
800b568: 1a9b subs r3, r3, r2
800b56a: 461a mov r2, r3
800b56c: f00f fd14 bl 801af98 <memcpy>
/* Point to next descriptor */
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
800b570: 6a3b ldr r3, [r7, #32]
800b572: 68db ldr r3, [r3, #12]
800b574: 623b str r3, [r7, #32]
buffer = (uint8_t *)(dmarxdesc->Buffer1Addr);
800b576: 6a3b ldr r3, [r7, #32]
800b578: 689b ldr r3, [r3, #8]
800b57a: 627b str r3, [r7, #36] ; 0x24
byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
800b57c: 69fa ldr r2, [r7, #28]
800b57e: 697b ldr r3, [r7, #20]
800b580: 4413 add r3, r2
800b582: f2a3 53f4 subw r3, r3, #1524 ; 0x5f4
800b586: 617b str r3, [r7, #20]
payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
800b588: 69ba ldr r2, [r7, #24]
800b58a: 69fb ldr r3, [r7, #28]
800b58c: 1ad3 subs r3, r2, r3
800b58e: f203 53f4 addw r3, r3, #1524 ; 0x5f4
800b592: 61bb str r3, [r7, #24]
bufferoffset = 0;
800b594: 2300 movs r3, #0
800b596: 61fb str r3, [r7, #28]
while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
800b598: 697a ldr r2, [r7, #20]
800b59a: 69fb ldr r3, [r7, #28]
800b59c: 4413 add r3, r2
800b59e: f240 52f4 movw r2, #1524 ; 0x5f4
800b5a2: 4293 cmp r3, r2
800b5a4: d8d6 bhi.n 800b554 <low_level_input+0x78>
}
/* Copy remaining data in pbuf */
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), byteslefttocopy);
800b5a6: 6abb ldr r3, [r7, #40] ; 0x28
800b5a8: 685a ldr r2, [r3, #4]
800b5aa: 69bb ldr r3, [r7, #24]
800b5ac: 18d0 adds r0, r2, r3
800b5ae: 6a7a ldr r2, [r7, #36] ; 0x24
800b5b0: 69fb ldr r3, [r7, #28]
800b5b2: 4413 add r3, r2
800b5b4: 697a ldr r2, [r7, #20]
800b5b6: 4619 mov r1, r3
800b5b8: f00f fcee bl 801af98 <memcpy>
bufferoffset = bufferoffset + byteslefttocopy;
800b5bc: 69fa ldr r2, [r7, #28]
800b5be: 697b ldr r3, [r7, #20]
800b5c0: 4413 add r3, r2
800b5c2: 61fb str r3, [r7, #28]
for(q = p; q != NULL; q = q->next)
800b5c4: 6abb ldr r3, [r7, #40] ; 0x28
800b5c6: 681b ldr r3, [r3, #0]
800b5c8: 62bb str r3, [r7, #40] ; 0x28
800b5ca: 6abb ldr r3, [r7, #40] ; 0x28
800b5cc: 2b00 cmp r3, #0
800b5ce: d1bb bne.n 800b548 <low_level_input+0x6c>
}
}
/* Release descriptors to DMA */
/* Point to first descriptor */
dmarxdesc = heth.RxFrameInfos.FSRxDesc;
800b5d0: 4b1b ldr r3, [pc, #108] ; (800b640 <low_level_input+0x164>)
800b5d2: 6b1b ldr r3, [r3, #48] ; 0x30
800b5d4: 623b str r3, [r7, #32]
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
for (i=0; i< heth.RxFrameInfos.SegCount; i++)
800b5d6: 2300 movs r3, #0
800b5d8: 613b str r3, [r7, #16]
800b5da: e00b b.n 800b5f4 <low_level_input+0x118>
{
dmarxdesc->Status |= ETH_DMARXDESC_OWN;
800b5dc: 6a3b ldr r3, [r7, #32]
800b5de: 681b ldr r3, [r3, #0]
800b5e0: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000
800b5e4: 6a3b ldr r3, [r7, #32]
800b5e6: 601a str r2, [r3, #0]
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
800b5e8: 6a3b ldr r3, [r7, #32]
800b5ea: 68db ldr r3, [r3, #12]
800b5ec: 623b str r3, [r7, #32]
for (i=0; i< heth.RxFrameInfos.SegCount; i++)
800b5ee: 693b ldr r3, [r7, #16]
800b5f0: 3301 adds r3, #1
800b5f2: 613b str r3, [r7, #16]
800b5f4: 4b12 ldr r3, [pc, #72] ; (800b640 <low_level_input+0x164>)
800b5f6: 6b9b ldr r3, [r3, #56] ; 0x38
800b5f8: 693a ldr r2, [r7, #16]
800b5fa: 429a cmp r2, r3
800b5fc: d3ee bcc.n 800b5dc <low_level_input+0x100>
}
/* Clear Segment_Count */
heth.RxFrameInfos.SegCount =0;
800b5fe: 4b10 ldr r3, [pc, #64] ; (800b640 <low_level_input+0x164>)
800b600: 2200 movs r2, #0
800b602: 639a str r2, [r3, #56] ; 0x38
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
if ((heth.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
800b604: 4b0e ldr r3, [pc, #56] ; (800b640 <low_level_input+0x164>)
800b606: 681a ldr r2, [r3, #0]
800b608: f241 0314 movw r3, #4116 ; 0x1014
800b60c: 4413 add r3, r2
800b60e: 681b ldr r3, [r3, #0]
800b610: f003 0380 and.w r3, r3, #128 ; 0x80
800b614: 2b00 cmp r3, #0
800b616: d00d beq.n 800b634 <low_level_input+0x158>
{
/* Clear RBUS ETHERNET DMA flag */
heth.Instance->DMASR = ETH_DMASR_RBUS;
800b618: 4b09 ldr r3, [pc, #36] ; (800b640 <low_level_input+0x164>)
800b61a: 681a ldr r2, [r3, #0]
800b61c: f241 0314 movw r3, #4116 ; 0x1014
800b620: 4413 add r3, r2
800b622: 2280 movs r2, #128 ; 0x80
800b624: 601a str r2, [r3, #0]
/* Resume DMA reception */
heth.Instance->DMARPDR = 0;
800b626: 4b06 ldr r3, [pc, #24] ; (800b640 <low_level_input+0x164>)
800b628: 681a ldr r2, [r3, #0]
800b62a: f241 0308 movw r3, #4104 ; 0x1008
800b62e: 4413 add r3, r2
800b630: 2200 movs r2, #0
800b632: 601a str r2, [r3, #0]
}
return p;
800b634: 6afb ldr r3, [r7, #44] ; 0x2c
}
800b636: 4618 mov r0, r3
800b638: 3730 adds r7, #48 ; 0x30
800b63a: 46bd mov sp, r7
800b63c: bd80 pop {r7, pc}
800b63e: bf00 nop
800b640: 2000a8ec .word 0x2000a8ec
0800b644 <ethernetif_input>:
* the appropriate input function is called.
*
* @param netif the lwip network interface structure for this ethernetif
*/
void ethernetif_input(void const * argument)
{
800b644: b580 push {r7, lr}
800b646: b084 sub sp, #16
800b648: af00 add r7, sp, #0
800b64a: 6078 str r0, [r7, #4]
struct pbuf *p;
struct netif *netif = (struct netif *) argument;
800b64c: 687b ldr r3, [r7, #4]
800b64e: 60fb str r3, [r7, #12]
for( ;; )
{
if (osSemaphoreWait(s_xSemaphore, TIME_WAITING_FOR_INPUT) == osOK)
800b650: 4b12 ldr r3, [pc, #72] ; (800b69c <ethernetif_input+0x58>)
800b652: 681b ldr r3, [r3, #0]
800b654: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
800b658: 4618 mov r0, r3
800b65a: f000 fa99 bl 800bb90 <osSemaphoreWait>
800b65e: 4603 mov r3, r0
800b660: 2b00 cmp r3, #0
800b662: d1f5 bne.n 800b650 <ethernetif_input+0xc>
{
do
{
LOCK_TCPIP_CORE();
800b664: 480e ldr r0, [pc, #56] ; (800b6a0 <ethernetif_input+0x5c>)
800b666: f00f fc05 bl 801ae74 <sys_mutex_lock>
p = low_level_input( netif );
800b66a: 68f8 ldr r0, [r7, #12]
800b66c: f7ff ff36 bl 800b4dc <low_level_input>
800b670: 60b8 str r0, [r7, #8]
if (p != NULL)
800b672: 68bb ldr r3, [r7, #8]
800b674: 2b00 cmp r3, #0
800b676: d00a beq.n 800b68e <ethernetif_input+0x4a>
{
if (netif->input( p, netif) != ERR_OK )
800b678: 68fb ldr r3, [r7, #12]
800b67a: 691b ldr r3, [r3, #16]
800b67c: 68f9 ldr r1, [r7, #12]
800b67e: 68b8 ldr r0, [r7, #8]
800b680: 4798 blx r3
800b682: 4603 mov r3, r0
800b684: 2b00 cmp r3, #0
800b686: d002 beq.n 800b68e <ethernetif_input+0x4a>
{
pbuf_free(p);
800b688: 68b8 ldr r0, [r7, #8]
800b68a: f004 ff8f bl 80105ac <pbuf_free>
}
}
UNLOCK_TCPIP_CORE();
800b68e: 4804 ldr r0, [pc, #16] ; (800b6a0 <ethernetif_input+0x5c>)
800b690: f00f fbff bl 801ae92 <sys_mutex_unlock>
} while(p!=NULL);
800b694: 68bb ldr r3, [r7, #8]
800b696: 2b00 cmp r3, #0
800b698: d1e4 bne.n 800b664 <ethernetif_input+0x20>
if (osSemaphoreWait(s_xSemaphore, TIME_WAITING_FOR_INPUT) == osOK)
800b69a: e7d9 b.n 800b650 <ethernetif_input+0xc>
800b69c: 2000057c .word 0x2000057c
800b6a0: 2000c104 .word 0x2000c104
0800b6a4 <ethernetif_init>:
* @return ERR_OK if the loopif is initialized
* ERR_MEM if private data couldn't be allocated
* any other err_t on error
*/
err_t ethernetif_init(struct netif *netif)
{
800b6a4: b580 push {r7, lr}
800b6a6: b082 sub sp, #8
800b6a8: af00 add r7, sp, #0
800b6aa: 6078 str r0, [r7, #4]
LWIP_ASSERT("netif != NULL", (netif != NULL));
800b6ac: 687b ldr r3, [r7, #4]
800b6ae: 2b00 cmp r3, #0
800b6b0: d106 bne.n 800b6c0 <ethernetif_init+0x1c>
800b6b2: 4b0e ldr r3, [pc, #56] ; (800b6ec <ethernetif_init+0x48>)
800b6b4: f240 222b movw r2, #555 ; 0x22b
800b6b8: 490d ldr r1, [pc, #52] ; (800b6f0 <ethernetif_init+0x4c>)
800b6ba: 480e ldr r0, [pc, #56] ; (800b6f4 <ethernetif_init+0x50>)
800b6bc: f00f fc82 bl 801afc4 <iprintf>
#if LWIP_NETIF_HOSTNAME
/* Initialize interface hostname */
netif->hostname = "lwip";
#endif /* LWIP_NETIF_HOSTNAME */
netif->name[0] = IFNAME0;
800b6c0: 687b ldr r3, [r7, #4]
800b6c2: 2273 movs r2, #115 ; 0x73
800b6c4: f883 2032 strb.w r2, [r3, #50] ; 0x32
netif->name[1] = IFNAME1;
800b6c8: 687b ldr r3, [r7, #4]
800b6ca: 2274 movs r2, #116 ; 0x74
800b6cc: f883 2033 strb.w r2, [r3, #51] ; 0x33
* is available...) */
#if LWIP_IPV4
#if LWIP_ARP || LWIP_ETHERNET
#if LWIP_ARP
netif->output = etharp_output;
800b6d0: 687b ldr r3, [r7, #4]
800b6d2: 4a09 ldr r2, [pc, #36] ; (800b6f8 <ethernetif_init+0x54>)
800b6d4: 615a str r2, [r3, #20]
#if LWIP_IPV6
netif->output_ip6 = ethip6_output;
#endif /* LWIP_IPV6 */
netif->linkoutput = low_level_output;
800b6d6: 687b ldr r3, [r7, #4]
800b6d8: 4a08 ldr r2, [pc, #32] ; (800b6fc <ethernetif_init+0x58>)
800b6da: 619a str r2, [r3, #24]
/* initialize the hardware */
low_level_init(netif);
800b6dc: 6878 ldr r0, [r7, #4]
800b6de: f7ff fd87 bl 800b1f0 <low_level_init>
return ERR_OK;
800b6e2: 2300 movs r3, #0
}
800b6e4: 4618 mov r0, r3
800b6e6: 3708 adds r7, #8
800b6e8: 46bd mov sp, r7
800b6ea: bd80 pop {r7, pc}
800b6ec: 0801c14c .word 0x0801c14c
800b6f0: 0801c168 .word 0x0801c168
800b6f4: 0801c178 .word 0x0801c178
800b6f8: 08018fe5 .word 0x08018fe5
800b6fc: 0800b3a1 .word 0x0800b3a1
0800b700 <sys_now>:
* when LWIP_TIMERS == 1 and NO_SYS == 1
* @param None
* @retval Time
*/
u32_t sys_now(void)
{
800b700: b580 push {r7, lr}
800b702: af00 add r7, sp, #0
return HAL_GetTick();
800b704: f7f9 f864 bl 80047d0 <HAL_GetTick>
800b708: 4603 mov r3, r0
}
800b70a: 4618 mov r0, r3
800b70c: bd80 pop {r7, pc}
...
0800b710 <ethernetif_set_link>:
* @param netif: the network interface
* @retval None
*/
void ethernetif_set_link(void const *argument)
{
800b710: b580 push {r7, lr}
800b712: b084 sub sp, #16
800b714: af00 add r7, sp, #0
800b716: 6078 str r0, [r7, #4]
uint32_t regvalue = 0;
800b718: 2300 movs r3, #0
800b71a: 60bb str r3, [r7, #8]
struct link_str *link_arg = (struct link_str *)argument;
800b71c: 687b ldr r3, [r7, #4]
800b71e: 60fb str r3, [r7, #12]
for(;;)
{
/* Read PHY_BSR*/
HAL_ETH_ReadPHYRegister(&heth, PHY_BSR, &regvalue);
800b720: f107 0308 add.w r3, r7, #8
800b724: 461a mov r2, r3
800b726: 2101 movs r1, #1
800b728: 4816 ldr r0, [pc, #88] ; (800b784 <ethernetif_set_link+0x74>)
800b72a: f7fa ffc2 bl 80066b2 <HAL_ETH_ReadPHYRegister>
regvalue &= PHY_LINKED_STATUS;
800b72e: 68bb ldr r3, [r7, #8]
800b730: f003 0304 and.w r3, r3, #4
800b734: 60bb str r3, [r7, #8]
/* Check whether the netif link down and the PHY link is up */
if(!netif_is_link_up(link_arg->netif) && (regvalue))
800b736: 68fb ldr r3, [r7, #12]
800b738: 681b ldr r3, [r3, #0]
800b73a: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b73e: f003 0304 and.w r3, r3, #4
800b742: 2b00 cmp r3, #0
800b744: d108 bne.n 800b758 <ethernetif_set_link+0x48>
800b746: 68bb ldr r3, [r7, #8]
800b748: 2b00 cmp r3, #0
800b74a: d005 beq.n 800b758 <ethernetif_set_link+0x48>
{
/* network cable is connected */
netif_set_link_up(link_arg->netif);
800b74c: 68fb ldr r3, [r7, #12]
800b74e: 681b ldr r3, [r3, #0]
800b750: 4618 mov r0, r3
800b752: f004 fb15 bl 800fd80 <netif_set_link_up>
800b756: e011 b.n 800b77c <ethernetif_set_link+0x6c>
}
else if(netif_is_link_up(link_arg->netif) && (!regvalue))
800b758: 68fb ldr r3, [r7, #12]
800b75a: 681b ldr r3, [r3, #0]
800b75c: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b760: 089b lsrs r3, r3, #2
800b762: f003 0301 and.w r3, r3, #1
800b766: b2db uxtb r3, r3
800b768: 2b00 cmp r3, #0
800b76a: d007 beq.n 800b77c <ethernetif_set_link+0x6c>
800b76c: 68bb ldr r3, [r7, #8]
800b76e: 2b00 cmp r3, #0
800b770: d104 bne.n 800b77c <ethernetif_set_link+0x6c>
{
/* network cable is dis-connected */
netif_set_link_down(link_arg->netif);
800b772: 68fb ldr r3, [r7, #12]
800b774: 681b ldr r3, [r3, #0]
800b776: 4618 mov r0, r3
800b778: f004 fb3a bl 800fdf0 <netif_set_link_down>
}
/* Suspend thread for 200 ms */
osDelay(200);
800b77c: 20c8 movs r0, #200 ; 0xc8
800b77e: f000 f916 bl 800b9ae <osDelay>
HAL_ETH_ReadPHYRegister(&heth, PHY_BSR, &regvalue);
800b782: e7cd b.n 800b720 <ethernetif_set_link+0x10>
800b784: 2000a8ec .word 0x2000a8ec
0800b788 <ethernetif_update_config>:
* to update low level driver configuration.
* @param netif: The network interface
* @retval None
*/
void ethernetif_update_config(struct netif *netif)
{
800b788: b580 push {r7, lr}
800b78a: b084 sub sp, #16
800b78c: af00 add r7, sp, #0
800b78e: 6078 str r0, [r7, #4]
__IO uint32_t tickstart = 0;
800b790: 2300 movs r3, #0
800b792: 60fb str r3, [r7, #12]
uint32_t regvalue = 0;
800b794: 2300 movs r3, #0
800b796: 60bb str r3, [r7, #8]
if(netif_is_link_up(netif))
800b798: 687b ldr r3, [r7, #4]
800b79a: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b79e: 089b lsrs r3, r3, #2
800b7a0: f003 0301 and.w r3, r3, #1
800b7a4: b2db uxtb r3, r3
800b7a6: 2b00 cmp r3, #0
800b7a8: d05d beq.n 800b866 <ethernetif_update_config+0xde>
{
/* Restart the auto-negotiation */
if(heth.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
800b7aa: 4b34 ldr r3, [pc, #208] ; (800b87c <ethernetif_update_config+0xf4>)
800b7ac: 685b ldr r3, [r3, #4]
800b7ae: 2b00 cmp r3, #0
800b7b0: d03f beq.n 800b832 <ethernetif_update_config+0xaa>
{
/* Enable Auto-Negotiation */
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, PHY_AUTONEGOTIATION);
800b7b2: f44f 5280 mov.w r2, #4096 ; 0x1000
800b7b6: 2100 movs r1, #0
800b7b8: 4830 ldr r0, [pc, #192] ; (800b87c <ethernetif_update_config+0xf4>)
800b7ba: f7fa ffe2 bl 8006782 <HAL_ETH_WritePHYRegister>
/* Get tick */
tickstart = HAL_GetTick();
800b7be: f7f9 f807 bl 80047d0 <HAL_GetTick>
800b7c2: 4603 mov r3, r0
800b7c4: 60fb str r3, [r7, #12]
/* Wait until the auto-negotiation will be completed */
do
{
HAL_ETH_ReadPHYRegister(&heth, PHY_BSR, &regvalue);
800b7c6: f107 0308 add.w r3, r7, #8
800b7ca: 461a mov r2, r3
800b7cc: 2101 movs r1, #1
800b7ce: 482b ldr r0, [pc, #172] ; (800b87c <ethernetif_update_config+0xf4>)
800b7d0: f7fa ff6f bl 80066b2 <HAL_ETH_ReadPHYRegister>
/* Check for the Timeout ( 1s ) */
if((HAL_GetTick() - tickstart ) > 1000)
800b7d4: f7f8 fffc bl 80047d0 <HAL_GetTick>
800b7d8: 4602 mov r2, r0
800b7da: 68fb ldr r3, [r7, #12]
800b7dc: 1ad3 subs r3, r2, r3
800b7de: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
800b7e2: d828 bhi.n 800b836 <ethernetif_update_config+0xae>
{
/* In case of timeout */
goto error;
}
} while (((regvalue & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
800b7e4: 68bb ldr r3, [r7, #8]
800b7e6: f003 0320 and.w r3, r3, #32
800b7ea: 2b00 cmp r3, #0
800b7ec: d0eb beq.n 800b7c6 <ethernetif_update_config+0x3e>
/* Read the result of the auto-negotiation */
HAL_ETH_ReadPHYRegister(&heth, PHY_SR, &regvalue);
800b7ee: f107 0308 add.w r3, r7, #8
800b7f2: 461a mov r2, r3
800b7f4: 2110 movs r1, #16
800b7f6: 4821 ldr r0, [pc, #132] ; (800b87c <ethernetif_update_config+0xf4>)
800b7f8: f7fa ff5b bl 80066b2 <HAL_ETH_ReadPHYRegister>
/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
if((regvalue & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
800b7fc: 68bb ldr r3, [r7, #8]
800b7fe: f003 0304 and.w r3, r3, #4
800b802: 2b00 cmp r3, #0
800b804: d004 beq.n 800b810 <ethernetif_update_config+0x88>
{
/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
heth.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
800b806: 4b1d ldr r3, [pc, #116] ; (800b87c <ethernetif_update_config+0xf4>)
800b808: f44f 6200 mov.w r2, #2048 ; 0x800
800b80c: 60da str r2, [r3, #12]
800b80e: e002 b.n 800b816 <ethernetif_update_config+0x8e>
}
else
{
/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
heth.Init.DuplexMode = ETH_MODE_HALFDUPLEX;
800b810: 4b1a ldr r3, [pc, #104] ; (800b87c <ethernetif_update_config+0xf4>)
800b812: 2200 movs r2, #0
800b814: 60da str r2, [r3, #12]
}
/* Configure the MAC with the speed fixed by the auto-negotiation process */
if(regvalue & PHY_SPEED_STATUS)
800b816: 68bb ldr r3, [r7, #8]
800b818: f003 0302 and.w r3, r3, #2
800b81c: 2b00 cmp r3, #0
800b81e: d003 beq.n 800b828 <ethernetif_update_config+0xa0>
{
/* Set Ethernet speed to 10M following the auto-negotiation */
heth.Init.Speed = ETH_SPEED_10M;
800b820: 4b16 ldr r3, [pc, #88] ; (800b87c <ethernetif_update_config+0xf4>)
800b822: 2200 movs r2, #0
800b824: 609a str r2, [r3, #8]
800b826: e016 b.n 800b856 <ethernetif_update_config+0xce>
}
else
{
/* Set Ethernet speed to 100M following the auto-negotiation */
heth.Init.Speed = ETH_SPEED_100M;
800b828: 4b14 ldr r3, [pc, #80] ; (800b87c <ethernetif_update_config+0xf4>)
800b82a: f44f 4280 mov.w r2, #16384 ; 0x4000
800b82e: 609a str r2, [r3, #8]
800b830: e011 b.n 800b856 <ethernetif_update_config+0xce>
}
}
else /* AutoNegotiation Disable */
{
error :
800b832: bf00 nop
800b834: e000 b.n 800b838 <ethernetif_update_config+0xb0>
goto error;
800b836: bf00 nop
/* Check parameters */
assert_param(IS_ETH_SPEED(heth.Init.Speed));
assert_param(IS_ETH_DUPLEX_MODE(heth.Init.DuplexMode));
/* Set MAC Speed and Duplex Mode to PHY */
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, ((uint16_t)(heth.Init.DuplexMode >> 3) |
800b838: 4b10 ldr r3, [pc, #64] ; (800b87c <ethernetif_update_config+0xf4>)
800b83a: 68db ldr r3, [r3, #12]
800b83c: 08db lsrs r3, r3, #3
800b83e: b29a uxth r2, r3
(uint16_t)(heth.Init.Speed >> 1)));
800b840: 4b0e ldr r3, [pc, #56] ; (800b87c <ethernetif_update_config+0xf4>)
800b842: 689b ldr r3, [r3, #8]
800b844: 085b lsrs r3, r3, #1
800b846: b29b uxth r3, r3
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, ((uint16_t)(heth.Init.DuplexMode >> 3) |
800b848: 4313 orrs r3, r2
800b84a: b29b uxth r3, r3
800b84c: 461a mov r2, r3
800b84e: 2100 movs r1, #0
800b850: 480a ldr r0, [pc, #40] ; (800b87c <ethernetif_update_config+0xf4>)
800b852: f7fa ff96 bl 8006782 <HAL_ETH_WritePHYRegister>
}
/* ETHERNET MAC Re-Configuration */
HAL_ETH_ConfigMAC(&heth, (ETH_MACInitTypeDef *) NULL);
800b856: 2100 movs r1, #0
800b858: 4808 ldr r0, [pc, #32] ; (800b87c <ethernetif_update_config+0xf4>)
800b85a: f7fb f857 bl 800690c <HAL_ETH_ConfigMAC>
/* Restart MAC interface */
HAL_ETH_Start(&heth);
800b85e: 4807 ldr r0, [pc, #28] ; (800b87c <ethernetif_update_config+0xf4>)
800b860: f7fa fff5 bl 800684e <HAL_ETH_Start>
800b864: e002 b.n 800b86c <ethernetif_update_config+0xe4>
}
else
{
/* Stop MAC interface */
HAL_ETH_Stop(&heth);
800b866: 4805 ldr r0, [pc, #20] ; (800b87c <ethernetif_update_config+0xf4>)
800b868: f7fb f820 bl 80068ac <HAL_ETH_Stop>
}
ethernetif_notify_conn_changed(netif);
800b86c: 6878 ldr r0, [r7, #4]
800b86e: f000 f807 bl 800b880 <ethernetif_notify_conn_changed>
}
800b872: bf00 nop
800b874: 3710 adds r7, #16
800b876: 46bd mov sp, r7
800b878: bd80 pop {r7, pc}
800b87a: bf00 nop
800b87c: 2000a8ec .word 0x2000a8ec
0800b880 <ethernetif_notify_conn_changed>:
* @brief This function notify user about link status changement.
* @param netif: the network interface
* @retval None
*/
__weak void ethernetif_notify_conn_changed(struct netif *netif)
{
800b880: b480 push {r7}
800b882: b083 sub sp, #12
800b884: af00 add r7, sp, #0
800b886: 6078 str r0, [r7, #4]
/* NOTE : This is function could be implemented in user file
when the callback is needed,
*/
}
800b888: bf00 nop
800b88a: 370c adds r7, #12
800b88c: 46bd mov sp, r7
800b88e: f85d 7b04 ldr.w r7, [sp], #4
800b892: 4770 bx lr
0800b894 <makeFreeRtosPriority>:
extern void xPortSysTickHandler(void);
/* Convert from CMSIS type osPriority to FreeRTOS priority number */
static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority)
{
800b894: b480 push {r7}
800b896: b085 sub sp, #20
800b898: af00 add r7, sp, #0
800b89a: 4603 mov r3, r0
800b89c: 80fb strh r3, [r7, #6]
unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY;
800b89e: 2300 movs r3, #0
800b8a0: 60fb str r3, [r7, #12]
if (priority != osPriorityError) {
800b8a2: f9b7 3006 ldrsh.w r3, [r7, #6]
800b8a6: 2b84 cmp r3, #132 ; 0x84
800b8a8: d005 beq.n 800b8b6 <makeFreeRtosPriority+0x22>
fpriority += (priority - osPriorityIdle);
800b8aa: f9b7 2006 ldrsh.w r2, [r7, #6]
800b8ae: 68fb ldr r3, [r7, #12]
800b8b0: 4413 add r3, r2
800b8b2: 3303 adds r3, #3
800b8b4: 60fb str r3, [r7, #12]
}
return fpriority;
800b8b6: 68fb ldr r3, [r7, #12]
}
800b8b8: 4618 mov r0, r3
800b8ba: 3714 adds r7, #20
800b8bc: 46bd mov sp, r7
800b8be: f85d 7b04 ldr.w r7, [sp], #4
800b8c2: 4770 bx lr
0800b8c4 <inHandlerMode>:
#endif
/* Determine whether we are in thread mode or handler mode. */
static int inHandlerMode (void)
{
800b8c4: b480 push {r7}
800b8c6: b083 sub sp, #12
800b8c8: af00 add r7, sp, #0
*/
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
800b8ca: f3ef 8305 mrs r3, IPSR
800b8ce: 607b str r3, [r7, #4]
return(result);
800b8d0: 687b ldr r3, [r7, #4]
return __get_IPSR() != 0;
800b8d2: 2b00 cmp r3, #0
800b8d4: bf14 ite ne
800b8d6: 2301 movne r3, #1
800b8d8: 2300 moveq r3, #0
800b8da: b2db uxtb r3, r3
}
800b8dc: 4618 mov r0, r3
800b8de: 370c adds r7, #12
800b8e0: 46bd mov sp, r7
800b8e2: f85d 7b04 ldr.w r7, [sp], #4
800b8e6: 4770 bx lr
0800b8e8 <osKernelStart>:
* @param argument pointer that is passed to the thread function as start argument.
* @retval status code that indicates the execution status of the function
* @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
*/
osStatus osKernelStart (void)
{
800b8e8: b580 push {r7, lr}
800b8ea: af00 add r7, sp, #0
vTaskStartScheduler();
800b8ec: f001 fe46 bl 800d57c <vTaskStartScheduler>
return osOK;
800b8f0: 2300 movs r3, #0
}
800b8f2: 4618 mov r0, r3
800b8f4: bd80 pop {r7, pc}
0800b8f6 <osKernelSysTick>:
* @param None
* @retval None
* @note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
*/
uint32_t osKernelSysTick(void)
{
800b8f6: b580 push {r7, lr}
800b8f8: af00 add r7, sp, #0
if (inHandlerMode()) {
800b8fa: f7ff ffe3 bl 800b8c4 <inHandlerMode>
800b8fe: 4603 mov r3, r0
800b900: 2b00 cmp r3, #0
800b902: d003 beq.n 800b90c <osKernelSysTick+0x16>
return xTaskGetTickCountFromISR();
800b904: f001 ff5a bl 800d7bc <xTaskGetTickCountFromISR>
800b908: 4603 mov r3, r0
800b90a: e002 b.n 800b912 <osKernelSysTick+0x1c>
}
else {
return xTaskGetTickCount();
800b90c: f001 ff46 bl 800d79c <xTaskGetTickCount>
800b910: 4603 mov r3, r0
}
}
800b912: 4618 mov r0, r3
800b914: bd80 pop {r7, pc}
0800b916 <osThreadCreate>:
* @param argument pointer that is passed to the thread function as start argument.
* @retval thread ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
*/
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
{
800b916: b5f0 push {r4, r5, r6, r7, lr}
800b918: b089 sub sp, #36 ; 0x24
800b91a: af04 add r7, sp, #16
800b91c: 6078 str r0, [r7, #4]
800b91e: 6039 str r1, [r7, #0]
TaskHandle_t handle;
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) {
800b920: 687b ldr r3, [r7, #4]
800b922: 695b ldr r3, [r3, #20]
800b924: 2b00 cmp r3, #0
800b926: d020 beq.n 800b96a <osThreadCreate+0x54>
800b928: 687b ldr r3, [r7, #4]
800b92a: 699b ldr r3, [r3, #24]
800b92c: 2b00 cmp r3, #0
800b92e: d01c beq.n 800b96a <osThreadCreate+0x54>
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800b930: 687b ldr r3, [r7, #4]
800b932: 685c ldr r4, [r3, #4]
800b934: 687b ldr r3, [r7, #4]
800b936: 681d ldr r5, [r3, #0]
800b938: 687b ldr r3, [r7, #4]
800b93a: 691e ldr r6, [r3, #16]
800b93c: 687b ldr r3, [r7, #4]
800b93e: f9b3 3008 ldrsh.w r3, [r3, #8]
800b942: 4618 mov r0, r3
800b944: f7ff ffa6 bl 800b894 <makeFreeRtosPriority>
800b948: 4601 mov r1, r0
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
thread_def->buffer, thread_def->controlblock);
800b94a: 687b ldr r3, [r7, #4]
800b94c: 695b ldr r3, [r3, #20]
800b94e: 687a ldr r2, [r7, #4]
800b950: 6992 ldr r2, [r2, #24]
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800b952: 9202 str r2, [sp, #8]
800b954: 9301 str r3, [sp, #4]
800b956: 9100 str r1, [sp, #0]
800b958: 683b ldr r3, [r7, #0]
800b95a: 4632 mov r2, r6
800b95c: 4629 mov r1, r5
800b95e: 4620 mov r0, r4
800b960: f001 fb1a bl 800cf98 <xTaskCreateStatic>
800b964: 4603 mov r3, r0
800b966: 60fb str r3, [r7, #12]
800b968: e01c b.n 800b9a4 <osThreadCreate+0x8e>
}
else {
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800b96a: 687b ldr r3, [r7, #4]
800b96c: 685c ldr r4, [r3, #4]
800b96e: 687b ldr r3, [r7, #4]
800b970: 681d ldr r5, [r3, #0]
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
800b972: 687b ldr r3, [r7, #4]
800b974: 691b ldr r3, [r3, #16]
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800b976: b29e uxth r6, r3
800b978: 687b ldr r3, [r7, #4]
800b97a: f9b3 3008 ldrsh.w r3, [r3, #8]
800b97e: 4618 mov r0, r3
800b980: f7ff ff88 bl 800b894 <makeFreeRtosPriority>
800b984: 4602 mov r2, r0
800b986: f107 030c add.w r3, r7, #12
800b98a: 9301 str r3, [sp, #4]
800b98c: 9200 str r2, [sp, #0]
800b98e: 683b ldr r3, [r7, #0]
800b990: 4632 mov r2, r6
800b992: 4629 mov r1, r5
800b994: 4620 mov r0, r4
800b996: f001 fb62 bl 800d05e <xTaskCreate>
800b99a: 4603 mov r3, r0
800b99c: 2b01 cmp r3, #1
800b99e: d001 beq.n 800b9a4 <osThreadCreate+0x8e>
&handle) != pdPASS) {
return NULL;
800b9a0: 2300 movs r3, #0
800b9a2: e000 b.n 800b9a6 <osThreadCreate+0x90>
&handle) != pdPASS) {
return NULL;
}
#endif
return handle;
800b9a4: 68fb ldr r3, [r7, #12]
}
800b9a6: 4618 mov r0, r3
800b9a8: 3714 adds r7, #20
800b9aa: 46bd mov sp, r7
800b9ac: bdf0 pop {r4, r5, r6, r7, pc}
0800b9ae <osDelay>:
* @brief Wait for Timeout (Time Delay)
* @param millisec time delay value
* @retval status code that indicates the execution status of the function.
*/
osStatus osDelay (uint32_t millisec)
{
800b9ae: b580 push {r7, lr}
800b9b0: b084 sub sp, #16
800b9b2: af00 add r7, sp, #0
800b9b4: 6078 str r0, [r7, #4]
#if INCLUDE_vTaskDelay
TickType_t ticks = millisec / portTICK_PERIOD_MS;
800b9b6: 687b ldr r3, [r7, #4]
800b9b8: 60fb str r3, [r7, #12]
vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */
800b9ba: 68fb ldr r3, [r7, #12]
800b9bc: 2b00 cmp r3, #0
800b9be: d001 beq.n 800b9c4 <osDelay+0x16>
800b9c0: 68fb ldr r3, [r7, #12]
800b9c2: e000 b.n 800b9c6 <osDelay+0x18>
800b9c4: 2301 movs r3, #1
800b9c6: 4618 mov r0, r3
800b9c8: f001 fda2 bl 800d510 <vTaskDelay>
return osOK;
800b9cc: 2300 movs r3, #0
#else
(void) millisec;
return osErrorResource;
#endif
}
800b9ce: 4618 mov r0, r3
800b9d0: 3710 adds r7, #16
800b9d2: 46bd mov sp, r7
800b9d4: bd80 pop {r7, pc}
0800b9d6 <osMutexCreate>:
* @param mutex_def mutex definition referenced with \ref osMutex.
* @retval mutex ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
*/
osMutexId osMutexCreate (const osMutexDef_t *mutex_def)
{
800b9d6: b580 push {r7, lr}
800b9d8: b082 sub sp, #8
800b9da: af00 add r7, sp, #0
800b9dc: 6078 str r0, [r7, #4]
#if ( configUSE_MUTEXES == 1)
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
if (mutex_def->controlblock != NULL) {
800b9de: 687b ldr r3, [r7, #4]
800b9e0: 685b ldr r3, [r3, #4]
800b9e2: 2b00 cmp r3, #0
800b9e4: d007 beq.n 800b9f6 <osMutexCreate+0x20>
return xSemaphoreCreateMutexStatic( mutex_def->controlblock );
800b9e6: 687b ldr r3, [r7, #4]
800b9e8: 685b ldr r3, [r3, #4]
800b9ea: 4619 mov r1, r3
800b9ec: 2001 movs r0, #1
800b9ee: f000 fc62 bl 800c2b6 <xQueueCreateMutexStatic>
800b9f2: 4603 mov r3, r0
800b9f4: e003 b.n 800b9fe <osMutexCreate+0x28>
}
else {
return xSemaphoreCreateMutex();
800b9f6: 2001 movs r0, #1
800b9f8: f000 fc45 bl 800c286 <xQueueCreateMutex>
800b9fc: 4603 mov r3, r0
return xSemaphoreCreateMutex();
#endif
#else
return NULL;
#endif
}
800b9fe: 4618 mov r0, r3
800ba00: 3708 adds r7, #8
800ba02: 46bd mov sp, r7
800ba04: bd80 pop {r7, pc}
...
0800ba08 <osMutexWait>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
*/
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
{
800ba08: b580 push {r7, lr}
800ba0a: b084 sub sp, #16
800ba0c: af00 add r7, sp, #0
800ba0e: 6078 str r0, [r7, #4]
800ba10: 6039 str r1, [r7, #0]
TickType_t ticks;
portBASE_TYPE taskWoken = pdFALSE;
800ba12: 2300 movs r3, #0
800ba14: 60bb str r3, [r7, #8]
if (mutex_id == NULL) {
800ba16: 687b ldr r3, [r7, #4]
800ba18: 2b00 cmp r3, #0
800ba1a: d101 bne.n 800ba20 <osMutexWait+0x18>
return osErrorParameter;
800ba1c: 2380 movs r3, #128 ; 0x80
800ba1e: e03a b.n 800ba96 <osMutexWait+0x8e>
}
ticks = 0;
800ba20: 2300 movs r3, #0
800ba22: 60fb str r3, [r7, #12]
if (millisec == osWaitForever) {
800ba24: 683b ldr r3, [r7, #0]
800ba26: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800ba2a: d103 bne.n 800ba34 <osMutexWait+0x2c>
ticks = portMAX_DELAY;
800ba2c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
800ba30: 60fb str r3, [r7, #12]
800ba32: e009 b.n 800ba48 <osMutexWait+0x40>
}
else if (millisec != 0) {
800ba34: 683b ldr r3, [r7, #0]
800ba36: 2b00 cmp r3, #0
800ba38: d006 beq.n 800ba48 <osMutexWait+0x40>
ticks = millisec / portTICK_PERIOD_MS;
800ba3a: 683b ldr r3, [r7, #0]
800ba3c: 60fb str r3, [r7, #12]
if (ticks == 0) {
800ba3e: 68fb ldr r3, [r7, #12]
800ba40: 2b00 cmp r3, #0
800ba42: d101 bne.n 800ba48 <osMutexWait+0x40>
ticks = 1;
800ba44: 2301 movs r3, #1
800ba46: 60fb str r3, [r7, #12]
}
}
if (inHandlerMode()) {
800ba48: f7ff ff3c bl 800b8c4 <inHandlerMode>
800ba4c: 4603 mov r3, r0
800ba4e: 2b00 cmp r3, #0
800ba50: d017 beq.n 800ba82 <osMutexWait+0x7a>
if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) {
800ba52: f107 0308 add.w r3, r7, #8
800ba56: 461a mov r2, r3
800ba58: 2100 movs r1, #0
800ba5a: 6878 ldr r0, [r7, #4]
800ba5c: f001 f8ee bl 800cc3c <xQueueReceiveFromISR>
800ba60: 4603 mov r3, r0
800ba62: 2b01 cmp r3, #1
800ba64: d001 beq.n 800ba6a <osMutexWait+0x62>
return osErrorOS;
800ba66: 23ff movs r3, #255 ; 0xff
800ba68: e015 b.n 800ba96 <osMutexWait+0x8e>
}
portEND_SWITCHING_ISR(taskWoken);
800ba6a: 68bb ldr r3, [r7, #8]
800ba6c: 2b00 cmp r3, #0
800ba6e: d011 beq.n 800ba94 <osMutexWait+0x8c>
800ba70: 4b0b ldr r3, [pc, #44] ; (800baa0 <osMutexWait+0x98>)
800ba72: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800ba76: 601a str r2, [r3, #0]
800ba78: f3bf 8f4f dsb sy
800ba7c: f3bf 8f6f isb sy
800ba80: e008 b.n 800ba94 <osMutexWait+0x8c>
}
else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) {
800ba82: 68f9 ldr r1, [r7, #12]
800ba84: 6878 ldr r0, [r7, #4]
800ba86: f000 ffc5 bl 800ca14 <xQueueSemaphoreTake>
800ba8a: 4603 mov r3, r0
800ba8c: 2b01 cmp r3, #1
800ba8e: d001 beq.n 800ba94 <osMutexWait+0x8c>
return osErrorOS;
800ba90: 23ff movs r3, #255 ; 0xff
800ba92: e000 b.n 800ba96 <osMutexWait+0x8e>
}
return osOK;
800ba94: 2300 movs r3, #0
}
800ba96: 4618 mov r0, r3
800ba98: 3710 adds r7, #16
800ba9a: 46bd mov sp, r7
800ba9c: bd80 pop {r7, pc}
800ba9e: bf00 nop
800baa0: e000ed04 .word 0xe000ed04
0800baa4 <osMutexRelease>:
* @param mutex_id mutex ID obtained by \ref osMutexCreate.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
*/
osStatus osMutexRelease (osMutexId mutex_id)
{
800baa4: b580 push {r7, lr}
800baa6: b084 sub sp, #16
800baa8: af00 add r7, sp, #0
800baaa: 6078 str r0, [r7, #4]
osStatus result = osOK;
800baac: 2300 movs r3, #0
800baae: 60fb str r3, [r7, #12]
portBASE_TYPE taskWoken = pdFALSE;
800bab0: 2300 movs r3, #0
800bab2: 60bb str r3, [r7, #8]
if (inHandlerMode()) {
800bab4: f7ff ff06 bl 800b8c4 <inHandlerMode>
800bab8: 4603 mov r3, r0
800baba: 2b00 cmp r3, #0
800babc: d016 beq.n 800baec <osMutexRelease+0x48>
if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) {
800babe: f107 0308 add.w r3, r7, #8
800bac2: 4619 mov r1, r3
800bac4: 6878 ldr r0, [r7, #4]
800bac6: f000 fe29 bl 800c71c <xQueueGiveFromISR>
800baca: 4603 mov r3, r0
800bacc: 2b01 cmp r3, #1
800bace: d001 beq.n 800bad4 <osMutexRelease+0x30>
return osErrorOS;
800bad0: 23ff movs r3, #255 ; 0xff
800bad2: e017 b.n 800bb04 <osMutexRelease+0x60>
}
portEND_SWITCHING_ISR(taskWoken);
800bad4: 68bb ldr r3, [r7, #8]
800bad6: 2b00 cmp r3, #0
800bad8: d013 beq.n 800bb02 <osMutexRelease+0x5e>
800bada: 4b0c ldr r3, [pc, #48] ; (800bb0c <osMutexRelease+0x68>)
800badc: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bae0: 601a str r2, [r3, #0]
800bae2: f3bf 8f4f dsb sy
800bae6: f3bf 8f6f isb sy
800baea: e00a b.n 800bb02 <osMutexRelease+0x5e>
}
else if (xSemaphoreGive(mutex_id) != pdTRUE)
800baec: 2300 movs r3, #0
800baee: 2200 movs r2, #0
800baf0: 2100 movs r1, #0
800baf2: 6878 ldr r0, [r7, #4]
800baf4: f000 fc6c bl 800c3d0 <xQueueGenericSend>
800baf8: 4603 mov r3, r0
800bafa: 2b01 cmp r3, #1
800bafc: d001 beq.n 800bb02 <osMutexRelease+0x5e>
{
result = osErrorOS;
800bafe: 23ff movs r3, #255 ; 0xff
800bb00: 60fb str r3, [r7, #12]
}
return result;
800bb02: 68fb ldr r3, [r7, #12]
}
800bb04: 4618 mov r0, r3
800bb06: 3710 adds r7, #16
800bb08: 46bd mov sp, r7
800bb0a: bd80 pop {r7, pc}
800bb0c: e000ed04 .word 0xe000ed04
0800bb10 <osSemaphoreCreate>:
* @param count number of available resources.
* @retval semaphore ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
*/
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)
{
800bb10: b580 push {r7, lr}
800bb12: b086 sub sp, #24
800bb14: af02 add r7, sp, #8
800bb16: 6078 str r0, [r7, #4]
800bb18: 6039 str r1, [r7, #0]
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
osSemaphoreId sema;
if (semaphore_def->controlblock != NULL){
800bb1a: 687b ldr r3, [r7, #4]
800bb1c: 685b ldr r3, [r3, #4]
800bb1e: 2b00 cmp r3, #0
800bb20: d016 beq.n 800bb50 <osSemaphoreCreate+0x40>
if (count == 1) {
800bb22: 683b ldr r3, [r7, #0]
800bb24: 2b01 cmp r3, #1
800bb26: d10a bne.n 800bb3e <osSemaphoreCreate+0x2e>
return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock );
800bb28: 687b ldr r3, [r7, #4]
800bb2a: 685b ldr r3, [r3, #4]
800bb2c: 2203 movs r2, #3
800bb2e: 9200 str r2, [sp, #0]
800bb30: 2200 movs r2, #0
800bb32: 2100 movs r1, #0
800bb34: 2001 movs r0, #1
800bb36: f000 faa9 bl 800c08c <xQueueGenericCreateStatic>
800bb3a: 4603 mov r3, r0
800bb3c: e023 b.n 800bb86 <osSemaphoreCreate+0x76>
}
else {
#if (configUSE_COUNTING_SEMAPHORES == 1 )
return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock );
800bb3e: 6838 ldr r0, [r7, #0]
800bb40: 6839 ldr r1, [r7, #0]
800bb42: 687b ldr r3, [r7, #4]
800bb44: 685b ldr r3, [r3, #4]
800bb46: 461a mov r2, r3
800bb48: f000 fbd0 bl 800c2ec <xQueueCreateCountingSemaphoreStatic>
800bb4c: 4603 mov r3, r0
800bb4e: e01a b.n 800bb86 <osSemaphoreCreate+0x76>
return NULL;
#endif
}
}
else {
if (count == 1) {
800bb50: 683b ldr r3, [r7, #0]
800bb52: 2b01 cmp r3, #1
800bb54: d110 bne.n 800bb78 <osSemaphoreCreate+0x68>
vSemaphoreCreateBinary(sema);
800bb56: 2203 movs r2, #3
800bb58: 2100 movs r1, #0
800bb5a: 2001 movs r0, #1
800bb5c: f000 fb18 bl 800c190 <xQueueGenericCreate>
800bb60: 60f8 str r0, [r7, #12]
800bb62: 68fb ldr r3, [r7, #12]
800bb64: 2b00 cmp r3, #0
800bb66: d005 beq.n 800bb74 <osSemaphoreCreate+0x64>
800bb68: 2300 movs r3, #0
800bb6a: 2200 movs r2, #0
800bb6c: 2100 movs r1, #0
800bb6e: 68f8 ldr r0, [r7, #12]
800bb70: f000 fc2e bl 800c3d0 <xQueueGenericSend>
return sema;
800bb74: 68fb ldr r3, [r7, #12]
800bb76: e006 b.n 800bb86 <osSemaphoreCreate+0x76>
}
else {
#if (configUSE_COUNTING_SEMAPHORES == 1 )
return xSemaphoreCreateCounting(count, count);
800bb78: 683b ldr r3, [r7, #0]
800bb7a: 683a ldr r2, [r7, #0]
800bb7c: 4611 mov r1, r2
800bb7e: 4618 mov r0, r3
800bb80: f000 fbef bl 800c362 <xQueueCreateCountingSemaphore>
800bb84: 4603 mov r3, r0
#else
return NULL;
#endif
}
#endif
}
800bb86: 4618 mov r0, r3
800bb88: 3710 adds r7, #16
800bb8a: 46bd mov sp, r7
800bb8c: bd80 pop {r7, pc}
...
0800bb90 <osSemaphoreWait>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval number of available tokens, or -1 in case of incorrect parameters.
* @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
*/
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
{
800bb90: b580 push {r7, lr}
800bb92: b084 sub sp, #16
800bb94: af00 add r7, sp, #0
800bb96: 6078 str r0, [r7, #4]
800bb98: 6039 str r1, [r7, #0]
TickType_t ticks;
portBASE_TYPE taskWoken = pdFALSE;
800bb9a: 2300 movs r3, #0
800bb9c: 60bb str r3, [r7, #8]
if (semaphore_id == NULL) {
800bb9e: 687b ldr r3, [r7, #4]
800bba0: 2b00 cmp r3, #0
800bba2: d101 bne.n 800bba8 <osSemaphoreWait+0x18>
return osErrorParameter;
800bba4: 2380 movs r3, #128 ; 0x80
800bba6: e03a b.n 800bc1e <osSemaphoreWait+0x8e>
}
ticks = 0;
800bba8: 2300 movs r3, #0
800bbaa: 60fb str r3, [r7, #12]
if (millisec == osWaitForever) {
800bbac: 683b ldr r3, [r7, #0]
800bbae: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800bbb2: d103 bne.n 800bbbc <osSemaphoreWait+0x2c>
ticks = portMAX_DELAY;
800bbb4: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
800bbb8: 60fb str r3, [r7, #12]
800bbba: e009 b.n 800bbd0 <osSemaphoreWait+0x40>
}
else if (millisec != 0) {
800bbbc: 683b ldr r3, [r7, #0]
800bbbe: 2b00 cmp r3, #0
800bbc0: d006 beq.n 800bbd0 <osSemaphoreWait+0x40>
ticks = millisec / portTICK_PERIOD_MS;
800bbc2: 683b ldr r3, [r7, #0]
800bbc4: 60fb str r3, [r7, #12]
if (ticks == 0) {
800bbc6: 68fb ldr r3, [r7, #12]
800bbc8: 2b00 cmp r3, #0
800bbca: d101 bne.n 800bbd0 <osSemaphoreWait+0x40>
ticks = 1;
800bbcc: 2301 movs r3, #1
800bbce: 60fb str r3, [r7, #12]
}
}
if (inHandlerMode()) {
800bbd0: f7ff fe78 bl 800b8c4 <inHandlerMode>
800bbd4: 4603 mov r3, r0
800bbd6: 2b00 cmp r3, #0
800bbd8: d017 beq.n 800bc0a <osSemaphoreWait+0x7a>
if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) {
800bbda: f107 0308 add.w r3, r7, #8
800bbde: 461a mov r2, r3
800bbe0: 2100 movs r1, #0
800bbe2: 6878 ldr r0, [r7, #4]
800bbe4: f001 f82a bl 800cc3c <xQueueReceiveFromISR>
800bbe8: 4603 mov r3, r0
800bbea: 2b01 cmp r3, #1
800bbec: d001 beq.n 800bbf2 <osSemaphoreWait+0x62>
return osErrorOS;
800bbee: 23ff movs r3, #255 ; 0xff
800bbf0: e015 b.n 800bc1e <osSemaphoreWait+0x8e>
}
portEND_SWITCHING_ISR(taskWoken);
800bbf2: 68bb ldr r3, [r7, #8]
800bbf4: 2b00 cmp r3, #0
800bbf6: d011 beq.n 800bc1c <osSemaphoreWait+0x8c>
800bbf8: 4b0b ldr r3, [pc, #44] ; (800bc28 <osSemaphoreWait+0x98>)
800bbfa: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bbfe: 601a str r2, [r3, #0]
800bc00: f3bf 8f4f dsb sy
800bc04: f3bf 8f6f isb sy
800bc08: e008 b.n 800bc1c <osSemaphoreWait+0x8c>
}
else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) {
800bc0a: 68f9 ldr r1, [r7, #12]
800bc0c: 6878 ldr r0, [r7, #4]
800bc0e: f000 ff01 bl 800ca14 <xQueueSemaphoreTake>
800bc12: 4603 mov r3, r0
800bc14: 2b01 cmp r3, #1
800bc16: d001 beq.n 800bc1c <osSemaphoreWait+0x8c>
return osErrorOS;
800bc18: 23ff movs r3, #255 ; 0xff
800bc1a: e000 b.n 800bc1e <osSemaphoreWait+0x8e>
}
return osOK;
800bc1c: 2300 movs r3, #0
}
800bc1e: 4618 mov r0, r3
800bc20: 3710 adds r7, #16
800bc22: 46bd mov sp, r7
800bc24: bd80 pop {r7, pc}
800bc26: bf00 nop
800bc28: e000ed04 .word 0xe000ed04
0800bc2c <osSemaphoreRelease>:
* @param semaphore_id semaphore object referenced with \ref osSemaphore.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
*/
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
{
800bc2c: b580 push {r7, lr}
800bc2e: b084 sub sp, #16
800bc30: af00 add r7, sp, #0
800bc32: 6078 str r0, [r7, #4]
osStatus result = osOK;
800bc34: 2300 movs r3, #0
800bc36: 60fb str r3, [r7, #12]
portBASE_TYPE taskWoken = pdFALSE;
800bc38: 2300 movs r3, #0
800bc3a: 60bb str r3, [r7, #8]
if (inHandlerMode()) {
800bc3c: f7ff fe42 bl 800b8c4 <inHandlerMode>
800bc40: 4603 mov r3, r0
800bc42: 2b00 cmp r3, #0
800bc44: d016 beq.n 800bc74 <osSemaphoreRelease+0x48>
if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) {
800bc46: f107 0308 add.w r3, r7, #8
800bc4a: 4619 mov r1, r3
800bc4c: 6878 ldr r0, [r7, #4]
800bc4e: f000 fd65 bl 800c71c <xQueueGiveFromISR>
800bc52: 4603 mov r3, r0
800bc54: 2b01 cmp r3, #1
800bc56: d001 beq.n 800bc5c <osSemaphoreRelease+0x30>
return osErrorOS;
800bc58: 23ff movs r3, #255 ; 0xff
800bc5a: e017 b.n 800bc8c <osSemaphoreRelease+0x60>
}
portEND_SWITCHING_ISR(taskWoken);
800bc5c: 68bb ldr r3, [r7, #8]
800bc5e: 2b00 cmp r3, #0
800bc60: d013 beq.n 800bc8a <osSemaphoreRelease+0x5e>
800bc62: 4b0c ldr r3, [pc, #48] ; (800bc94 <osSemaphoreRelease+0x68>)
800bc64: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bc68: 601a str r2, [r3, #0]
800bc6a: f3bf 8f4f dsb sy
800bc6e: f3bf 8f6f isb sy
800bc72: e00a b.n 800bc8a <osSemaphoreRelease+0x5e>
}
else {
if (xSemaphoreGive(semaphore_id) != pdTRUE) {
800bc74: 2300 movs r3, #0
800bc76: 2200 movs r2, #0
800bc78: 2100 movs r1, #0
800bc7a: 6878 ldr r0, [r7, #4]
800bc7c: f000 fba8 bl 800c3d0 <xQueueGenericSend>
800bc80: 4603 mov r3, r0
800bc82: 2b01 cmp r3, #1
800bc84: d001 beq.n 800bc8a <osSemaphoreRelease+0x5e>
result = osErrorOS;
800bc86: 23ff movs r3, #255 ; 0xff
800bc88: 60fb str r3, [r7, #12]
}
}
return result;
800bc8a: 68fb ldr r3, [r7, #12]
}
800bc8c: 4618 mov r0, r3
800bc8e: 3710 adds r7, #16
800bc90: 46bd mov sp, r7
800bc92: bd80 pop {r7, pc}
800bc94: e000ed04 .word 0xe000ed04
0800bc98 <osMessageCreate>:
* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
* @retval message queue ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
*/
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)
{
800bc98: b590 push {r4, r7, lr}
800bc9a: b085 sub sp, #20
800bc9c: af02 add r7, sp, #8
800bc9e: 6078 str r0, [r7, #4]
800bca0: 6039 str r1, [r7, #0]
(void) thread_id;
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) {
800bca2: 687b ldr r3, [r7, #4]
800bca4: 689b ldr r3, [r3, #8]
800bca6: 2b00 cmp r3, #0
800bca8: d011 beq.n 800bcce <osMessageCreate+0x36>
800bcaa: 687b ldr r3, [r7, #4]
800bcac: 68db ldr r3, [r3, #12]
800bcae: 2b00 cmp r3, #0
800bcb0: d00d beq.n 800bcce <osMessageCreate+0x36>
return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
800bcb2: 687b ldr r3, [r7, #4]
800bcb4: 6818 ldr r0, [r3, #0]
800bcb6: 687b ldr r3, [r7, #4]
800bcb8: 6859 ldr r1, [r3, #4]
800bcba: 687b ldr r3, [r7, #4]
800bcbc: 689a ldr r2, [r3, #8]
800bcbe: 687b ldr r3, [r7, #4]
800bcc0: 68db ldr r3, [r3, #12]
800bcc2: 2400 movs r4, #0
800bcc4: 9400 str r4, [sp, #0]
800bcc6: f000 f9e1 bl 800c08c <xQueueGenericCreateStatic>
800bcca: 4603 mov r3, r0
800bccc: e008 b.n 800bce0 <osMessageCreate+0x48>
}
else {
return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
800bcce: 687b ldr r3, [r7, #4]
800bcd0: 6818 ldr r0, [r3, #0]
800bcd2: 687b ldr r3, [r7, #4]
800bcd4: 685b ldr r3, [r3, #4]
800bcd6: 2200 movs r2, #0
800bcd8: 4619 mov r1, r3
800bcda: f000 fa59 bl 800c190 <xQueueGenericCreate>
800bcde: 4603 mov r3, r0
#elif ( configSUPPORT_STATIC_ALLOCATION == 1 )
return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
#else
return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
#endif
}
800bce0: 4618 mov r0, r3
800bce2: 370c adds r7, #12
800bce4: 46bd mov sp, r7
800bce6: bd90 pop {r4, r7, pc}
0800bce8 <osMessagePut>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
*/
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
{
800bce8: b580 push {r7, lr}
800bcea: b086 sub sp, #24
800bcec: af00 add r7, sp, #0
800bcee: 60f8 str r0, [r7, #12]
800bcf0: 60b9 str r1, [r7, #8]
800bcf2: 607a str r2, [r7, #4]
portBASE_TYPE taskWoken = pdFALSE;
800bcf4: 2300 movs r3, #0
800bcf6: 613b str r3, [r7, #16]
TickType_t ticks;
ticks = millisec / portTICK_PERIOD_MS;
800bcf8: 687b ldr r3, [r7, #4]
800bcfa: 617b str r3, [r7, #20]
if (ticks == 0) {
800bcfc: 697b ldr r3, [r7, #20]
800bcfe: 2b00 cmp r3, #0
800bd00: d101 bne.n 800bd06 <osMessagePut+0x1e>
ticks = 1;
800bd02: 2301 movs r3, #1
800bd04: 617b str r3, [r7, #20]
}
if (inHandlerMode()) {
800bd06: f7ff fddd bl 800b8c4 <inHandlerMode>
800bd0a: 4603 mov r3, r0
800bd0c: 2b00 cmp r3, #0
800bd0e: d018 beq.n 800bd42 <osMessagePut+0x5a>
if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) {
800bd10: f107 0210 add.w r2, r7, #16
800bd14: f107 0108 add.w r1, r7, #8
800bd18: 2300 movs r3, #0
800bd1a: 68f8 ldr r0, [r7, #12]
800bd1c: f000 fc5e bl 800c5dc <xQueueGenericSendFromISR>
800bd20: 4603 mov r3, r0
800bd22: 2b01 cmp r3, #1
800bd24: d001 beq.n 800bd2a <osMessagePut+0x42>
return osErrorOS;
800bd26: 23ff movs r3, #255 ; 0xff
800bd28: e018 b.n 800bd5c <osMessagePut+0x74>
}
portEND_SWITCHING_ISR(taskWoken);
800bd2a: 693b ldr r3, [r7, #16]
800bd2c: 2b00 cmp r3, #0
800bd2e: d014 beq.n 800bd5a <osMessagePut+0x72>
800bd30: 4b0c ldr r3, [pc, #48] ; (800bd64 <osMessagePut+0x7c>)
800bd32: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bd36: 601a str r2, [r3, #0]
800bd38: f3bf 8f4f dsb sy
800bd3c: f3bf 8f6f isb sy
800bd40: e00b b.n 800bd5a <osMessagePut+0x72>
}
else {
if (xQueueSend(queue_id, &info, ticks) != pdTRUE) {
800bd42: f107 0108 add.w r1, r7, #8
800bd46: 2300 movs r3, #0
800bd48: 697a ldr r2, [r7, #20]
800bd4a: 68f8 ldr r0, [r7, #12]
800bd4c: f000 fb40 bl 800c3d0 <xQueueGenericSend>
800bd50: 4603 mov r3, r0
800bd52: 2b01 cmp r3, #1
800bd54: d001 beq.n 800bd5a <osMessagePut+0x72>
return osErrorOS;
800bd56: 23ff movs r3, #255 ; 0xff
800bd58: e000 b.n 800bd5c <osMessagePut+0x74>
}
}
return osOK;
800bd5a: 2300 movs r3, #0
}
800bd5c: 4618 mov r0, r3
800bd5e: 3718 adds r7, #24
800bd60: 46bd mov sp, r7
800bd62: bd80 pop {r7, pc}
800bd64: e000ed04 .word 0xe000ed04
0800bd68 <osMessageGet>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval event information that includes status code.
* @note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
*/
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
{
800bd68: b590 push {r4, r7, lr}
800bd6a: b08b sub sp, #44 ; 0x2c
800bd6c: af00 add r7, sp, #0
800bd6e: 60f8 str r0, [r7, #12]
800bd70: 60b9 str r1, [r7, #8]
800bd72: 607a str r2, [r7, #4]
portBASE_TYPE taskWoken;
TickType_t ticks;
osEvent event;
event.def.message_id = queue_id;
800bd74: 68bb ldr r3, [r7, #8]
800bd76: 61fb str r3, [r7, #28]
event.value.v = 0;
800bd78: 2300 movs r3, #0
800bd7a: 61bb str r3, [r7, #24]
if (queue_id == NULL) {
800bd7c: 68bb ldr r3, [r7, #8]
800bd7e: 2b00 cmp r3, #0
800bd80: d10a bne.n 800bd98 <osMessageGet+0x30>
event.status = osErrorParameter;
800bd82: 2380 movs r3, #128 ; 0x80
800bd84: 617b str r3, [r7, #20]
return event;
800bd86: 68fb ldr r3, [r7, #12]
800bd88: 461c mov r4, r3
800bd8a: f107 0314 add.w r3, r7, #20
800bd8e: e893 0007 ldmia.w r3, {r0, r1, r2}
800bd92: e884 0007 stmia.w r4, {r0, r1, r2}
800bd96: e054 b.n 800be42 <osMessageGet+0xda>
}
taskWoken = pdFALSE;
800bd98: 2300 movs r3, #0
800bd9a: 623b str r3, [r7, #32]
ticks = 0;
800bd9c: 2300 movs r3, #0
800bd9e: 627b str r3, [r7, #36] ; 0x24
if (millisec == osWaitForever) {
800bda0: 687b ldr r3, [r7, #4]
800bda2: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800bda6: d103 bne.n 800bdb0 <osMessageGet+0x48>
ticks = portMAX_DELAY;
800bda8: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
800bdac: 627b str r3, [r7, #36] ; 0x24
800bdae: e009 b.n 800bdc4 <osMessageGet+0x5c>
}
else if (millisec != 0) {
800bdb0: 687b ldr r3, [r7, #4]
800bdb2: 2b00 cmp r3, #0
800bdb4: d006 beq.n 800bdc4 <osMessageGet+0x5c>
ticks = millisec / portTICK_PERIOD_MS;
800bdb6: 687b ldr r3, [r7, #4]
800bdb8: 627b str r3, [r7, #36] ; 0x24
if (ticks == 0) {
800bdba: 6a7b ldr r3, [r7, #36] ; 0x24
800bdbc: 2b00 cmp r3, #0
800bdbe: d101 bne.n 800bdc4 <osMessageGet+0x5c>
ticks = 1;
800bdc0: 2301 movs r3, #1
800bdc2: 627b str r3, [r7, #36] ; 0x24
}
}
if (inHandlerMode()) {
800bdc4: f7ff fd7e bl 800b8c4 <inHandlerMode>
800bdc8: 4603 mov r3, r0
800bdca: 2b00 cmp r3, #0
800bdcc: d01c beq.n 800be08 <osMessageGet+0xa0>
if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) {
800bdce: f107 0220 add.w r2, r7, #32
800bdd2: f107 0314 add.w r3, r7, #20
800bdd6: 3304 adds r3, #4
800bdd8: 4619 mov r1, r3
800bdda: 68b8 ldr r0, [r7, #8]
800bddc: f000 ff2e bl 800cc3c <xQueueReceiveFromISR>
800bde0: 4603 mov r3, r0
800bde2: 2b01 cmp r3, #1
800bde4: d102 bne.n 800bdec <osMessageGet+0x84>
/* We have mail */
event.status = osEventMessage;
800bde6: 2310 movs r3, #16
800bde8: 617b str r3, [r7, #20]
800bdea: e001 b.n 800bdf0 <osMessageGet+0x88>
}
else {
event.status = osOK;
800bdec: 2300 movs r3, #0
800bdee: 617b str r3, [r7, #20]
}
portEND_SWITCHING_ISR(taskWoken);
800bdf0: 6a3b ldr r3, [r7, #32]
800bdf2: 2b00 cmp r3, #0
800bdf4: d01d beq.n 800be32 <osMessageGet+0xca>
800bdf6: 4b15 ldr r3, [pc, #84] ; (800be4c <osMessageGet+0xe4>)
800bdf8: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bdfc: 601a str r2, [r3, #0]
800bdfe: f3bf 8f4f dsb sy
800be02: f3bf 8f6f isb sy
800be06: e014 b.n 800be32 <osMessageGet+0xca>
}
else {
if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) {
800be08: f107 0314 add.w r3, r7, #20
800be0c: 3304 adds r3, #4
800be0e: 6a7a ldr r2, [r7, #36] ; 0x24
800be10: 4619 mov r1, r3
800be12: 68b8 ldr r0, [r7, #8]
800be14: f000 fd18 bl 800c848 <xQueueReceive>
800be18: 4603 mov r3, r0
800be1a: 2b01 cmp r3, #1
800be1c: d102 bne.n 800be24 <osMessageGet+0xbc>
/* We have mail */
event.status = osEventMessage;
800be1e: 2310 movs r3, #16
800be20: 617b str r3, [r7, #20]
800be22: e006 b.n 800be32 <osMessageGet+0xca>
}
else {
event.status = (ticks == 0) ? osOK : osEventTimeout;
800be24: 6a7b ldr r3, [r7, #36] ; 0x24
800be26: 2b00 cmp r3, #0
800be28: d101 bne.n 800be2e <osMessageGet+0xc6>
800be2a: 2300 movs r3, #0
800be2c: e000 b.n 800be30 <osMessageGet+0xc8>
800be2e: 2340 movs r3, #64 ; 0x40
800be30: 617b str r3, [r7, #20]
}
}
return event;
800be32: 68fb ldr r3, [r7, #12]
800be34: 461c mov r4, r3
800be36: f107 0314 add.w r3, r7, #20
800be3a: e893 0007 ldmia.w r3, {r0, r1, r2}
800be3e: e884 0007 stmia.w r4, {r0, r1, r2}
}
800be42: 68f8 ldr r0, [r7, #12]
800be44: 372c adds r7, #44 ; 0x2c
800be46: 46bd mov sp, r7
800be48: bd90 pop {r4, r7, pc}
800be4a: bf00 nop
800be4c: e000ed04 .word 0xe000ed04
0800be50 <vListInitialise>:
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/
void vListInitialise( List_t * const pxList )
{
800be50: b480 push {r7}
800be52: b083 sub sp, #12
800be54: af00 add r7, sp, #0
800be56: 6078 str r0, [r7, #4]
/* The list structure contains a list item which is used to mark the
end of the list. To initialise the list the list end is inserted
as the only list entry. */
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
800be58: 687b ldr r3, [r7, #4]
800be5a: f103 0208 add.w r2, r3, #8
800be5e: 687b ldr r3, [r7, #4]
800be60: 605a str r2, [r3, #4]
/* The list end value is the highest possible value in the list to
ensure it remains at the end of the list. */
pxList->xListEnd.xItemValue = portMAX_DELAY;
800be62: 687b ldr r3, [r7, #4]
800be64: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800be68: 609a str r2, [r3, #8]
/* The list end next and previous pointers point to itself so we know
when the list is empty. */
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
800be6a: 687b ldr r3, [r7, #4]
800be6c: f103 0208 add.w r2, r3, #8
800be70: 687b ldr r3, [r7, #4]
800be72: 60da str r2, [r3, #12]
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
800be74: 687b ldr r3, [r7, #4]
800be76: f103 0208 add.w r2, r3, #8
800be7a: 687b ldr r3, [r7, #4]
800be7c: 611a str r2, [r3, #16]
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
800be7e: 687b ldr r3, [r7, #4]
800be80: 2200 movs r2, #0
800be82: 601a str r2, [r3, #0]
/* Write known values into the list if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
800be84: bf00 nop
800be86: 370c adds r7, #12
800be88: 46bd mov sp, r7
800be8a: f85d 7b04 ldr.w r7, [sp], #4
800be8e: 4770 bx lr
0800be90 <vListInitialiseItem>:
/*-----------------------------------------------------------*/
void vListInitialiseItem( ListItem_t * const pxItem )
{
800be90: b480 push {r7}
800be92: b083 sub sp, #12
800be94: af00 add r7, sp, #0
800be96: 6078 str r0, [r7, #4]
/* Make sure the list item is not recorded as being on a list. */
pxItem->pxContainer = NULL;
800be98: 687b ldr r3, [r7, #4]
800be9a: 2200 movs r2, #0
800be9c: 611a str r2, [r3, #16]
/* Write known values into the list item if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
800be9e: bf00 nop
800bea0: 370c adds r7, #12
800bea2: 46bd mov sp, r7
800bea4: f85d 7b04 ldr.w r7, [sp], #4
800bea8: 4770 bx lr
0800beaa <vListInsertEnd>:
/*-----------------------------------------------------------*/
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
800beaa: b480 push {r7}
800beac: b085 sub sp, #20
800beae: af00 add r7, sp, #0
800beb0: 6078 str r0, [r7, #4]
800beb2: 6039 str r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
800beb4: 687b ldr r3, [r7, #4]
800beb6: 685b ldr r3, [r3, #4]
800beb8: 60fb str r3, [r7, #12]
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
/* Insert a new list item into pxList, but rather than sort the list,
makes the new list item the last item to be removed by a call to
listGET_OWNER_OF_NEXT_ENTRY(). */
pxNewListItem->pxNext = pxIndex;
800beba: 683b ldr r3, [r7, #0]
800bebc: 68fa ldr r2, [r7, #12]
800bebe: 605a str r2, [r3, #4]
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
800bec0: 68fb ldr r3, [r7, #12]
800bec2: 689a ldr r2, [r3, #8]
800bec4: 683b ldr r3, [r7, #0]
800bec6: 609a str r2, [r3, #8]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
pxIndex->pxPrevious->pxNext = pxNewListItem;
800bec8: 68fb ldr r3, [r7, #12]
800beca: 689b ldr r3, [r3, #8]
800becc: 683a ldr r2, [r7, #0]
800bece: 605a str r2, [r3, #4]
pxIndex->pxPrevious = pxNewListItem;
800bed0: 68fb ldr r3, [r7, #12]
800bed2: 683a ldr r2, [r7, #0]
800bed4: 609a str r2, [r3, #8]
/* Remember which list the item is in. */
pxNewListItem->pxContainer = pxList;
800bed6: 683b ldr r3, [r7, #0]
800bed8: 687a ldr r2, [r7, #4]
800beda: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
800bedc: 687b ldr r3, [r7, #4]
800bede: 681b ldr r3, [r3, #0]
800bee0: 1c5a adds r2, r3, #1
800bee2: 687b ldr r3, [r7, #4]
800bee4: 601a str r2, [r3, #0]
}
800bee6: bf00 nop
800bee8: 3714 adds r7, #20
800beea: 46bd mov sp, r7
800beec: f85d 7b04 ldr.w r7, [sp], #4
800bef0: 4770 bx lr
0800bef2 <vListInsert>:
/*-----------------------------------------------------------*/
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
800bef2: b480 push {r7}
800bef4: b085 sub sp, #20
800bef6: af00 add r7, sp, #0
800bef8: 6078 str r0, [r7, #4]
800befa: 6039 str r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
800befc: 683b ldr r3, [r7, #0]
800befe: 681b ldr r3, [r3, #0]
800bf00: 60bb str r3, [r7, #8]
new list item should be placed after it. This ensures that TCBs which are
stored in ready lists (all of which have the same xItemValue value) get a
share of the CPU. However, if the xItemValue is the same as the back marker
the iteration loop below will not end. Therefore the value is checked
first, and the algorithm slightly modified if necessary. */
if( xValueOfInsertion == portMAX_DELAY )
800bf02: 68bb ldr r3, [r7, #8]
800bf04: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800bf08: d103 bne.n 800bf12 <vListInsert+0x20>
{
pxIterator = pxList->xListEnd.pxPrevious;
800bf0a: 687b ldr r3, [r7, #4]
800bf0c: 691b ldr r3, [r3, #16]
800bf0e: 60fb str r3, [r7, #12]
800bf10: e00c b.n 800bf2c <vListInsert+0x3a>
4) Using a queue or semaphore before it has been initialised or
before the scheduler has been started (are interrupts firing
before vTaskStartScheduler() has been called?).
**********************************************************************/
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
800bf12: 687b ldr r3, [r7, #4]
800bf14: 3308 adds r3, #8
800bf16: 60fb str r3, [r7, #12]
800bf18: e002 b.n 800bf20 <vListInsert+0x2e>
800bf1a: 68fb ldr r3, [r7, #12]
800bf1c: 685b ldr r3, [r3, #4]
800bf1e: 60fb str r3, [r7, #12]
800bf20: 68fb ldr r3, [r7, #12]
800bf22: 685b ldr r3, [r3, #4]
800bf24: 681b ldr r3, [r3, #0]
800bf26: 68ba ldr r2, [r7, #8]
800bf28: 429a cmp r2, r3
800bf2a: d2f6 bcs.n 800bf1a <vListInsert+0x28>
/* There is nothing to do here, just iterating to the wanted
insertion position. */
}
}
pxNewListItem->pxNext = pxIterator->pxNext;
800bf2c: 68fb ldr r3, [r7, #12]
800bf2e: 685a ldr r2, [r3, #4]
800bf30: 683b ldr r3, [r7, #0]
800bf32: 605a str r2, [r3, #4]
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
800bf34: 683b ldr r3, [r7, #0]
800bf36: 685b ldr r3, [r3, #4]
800bf38: 683a ldr r2, [r7, #0]
800bf3a: 609a str r2, [r3, #8]
pxNewListItem->pxPrevious = pxIterator;
800bf3c: 683b ldr r3, [r7, #0]
800bf3e: 68fa ldr r2, [r7, #12]
800bf40: 609a str r2, [r3, #8]
pxIterator->pxNext = pxNewListItem;
800bf42: 68fb ldr r3, [r7, #12]
800bf44: 683a ldr r2, [r7, #0]
800bf46: 605a str r2, [r3, #4]
/* Remember which list the item is in. This allows fast removal of the
item later. */
pxNewListItem->pxContainer = pxList;
800bf48: 683b ldr r3, [r7, #0]
800bf4a: 687a ldr r2, [r7, #4]
800bf4c: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
800bf4e: 687b ldr r3, [r7, #4]
800bf50: 681b ldr r3, [r3, #0]
800bf52: 1c5a adds r2, r3, #1
800bf54: 687b ldr r3, [r7, #4]
800bf56: 601a str r2, [r3, #0]
}
800bf58: bf00 nop
800bf5a: 3714 adds r7, #20
800bf5c: 46bd mov sp, r7
800bf5e: f85d 7b04 ldr.w r7, [sp], #4
800bf62: 4770 bx lr
0800bf64 <uxListRemove>:
/*-----------------------------------------------------------*/
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
800bf64: b480 push {r7}
800bf66: b085 sub sp, #20
800bf68: af00 add r7, sp, #0
800bf6a: 6078 str r0, [r7, #4]
/* The list item knows which list it is in. Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
800bf6c: 687b ldr r3, [r7, #4]
800bf6e: 691b ldr r3, [r3, #16]
800bf70: 60fb str r3, [r7, #12]
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
800bf72: 687b ldr r3, [r7, #4]
800bf74: 685b ldr r3, [r3, #4]
800bf76: 687a ldr r2, [r7, #4]
800bf78: 6892 ldr r2, [r2, #8]
800bf7a: 609a str r2, [r3, #8]
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
800bf7c: 687b ldr r3, [r7, #4]
800bf7e: 689b ldr r3, [r3, #8]
800bf80: 687a ldr r2, [r7, #4]
800bf82: 6852 ldr r2, [r2, #4]
800bf84: 605a str r2, [r3, #4]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
/* Make sure the index is left pointing to a valid item. */
if( pxList->pxIndex == pxItemToRemove )
800bf86: 68fb ldr r3, [r7, #12]
800bf88: 685b ldr r3, [r3, #4]
800bf8a: 687a ldr r2, [r7, #4]
800bf8c: 429a cmp r2, r3
800bf8e: d103 bne.n 800bf98 <uxListRemove+0x34>
{
pxList->pxIndex = pxItemToRemove->pxPrevious;
800bf90: 687b ldr r3, [r7, #4]
800bf92: 689a ldr r2, [r3, #8]
800bf94: 68fb ldr r3, [r7, #12]
800bf96: 605a str r2, [r3, #4]
else
{
mtCOVERAGE_TEST_MARKER();
}
pxItemToRemove->pxContainer = NULL;
800bf98: 687b ldr r3, [r7, #4]
800bf9a: 2200 movs r2, #0
800bf9c: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )--;
800bf9e: 68fb ldr r3, [r7, #12]
800bfa0: 681b ldr r3, [r3, #0]
800bfa2: 1e5a subs r2, r3, #1
800bfa4: 68fb ldr r3, [r7, #12]
800bfa6: 601a str r2, [r3, #0]
return pxList->uxNumberOfItems;
800bfa8: 68fb ldr r3, [r7, #12]
800bfaa: 681b ldr r3, [r3, #0]
}
800bfac: 4618 mov r0, r3
800bfae: 3714 adds r7, #20
800bfb0: 46bd mov sp, r7
800bfb2: f85d 7b04 ldr.w r7, [sp], #4
800bfb6: 4770 bx lr
0800bfb8 <xQueueGenericReset>:
} \
taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
800bfb8: b580 push {r7, lr}
800bfba: b084 sub sp, #16
800bfbc: af00 add r7, sp, #0
800bfbe: 6078 str r0, [r7, #4]
800bfc0: 6039 str r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
800bfc2: 687b ldr r3, [r7, #4]
800bfc4: 60fb str r3, [r7, #12]
configASSERT( pxQueue );
800bfc6: 68fb ldr r3, [r7, #12]
800bfc8: 2b00 cmp r3, #0
800bfca: d10c bne.n 800bfe6 <xQueueGenericReset+0x2e>
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;
__asm volatile
800bfcc: f04f 0350 mov.w r3, #80 ; 0x50
800bfd0: b672 cpsid i
800bfd2: f383 8811 msr BASEPRI, r3
800bfd6: f3bf 8f6f isb sy
800bfda: f3bf 8f4f dsb sy
800bfde: b662 cpsie i
800bfe0: 60bb str r3, [r7, #8]
" isb \n" \
" dsb \n" \
" cpsie i \n" \
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
800bfe2: bf00 nop
800bfe4: e7fe b.n 800bfe4 <xQueueGenericReset+0x2c>
taskENTER_CRITICAL();
800bfe6: f002 fa71 bl 800e4cc <vPortEnterCritical>
{
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
800bfea: 68fb ldr r3, [r7, #12]
800bfec: 681a ldr r2, [r3, #0]
800bfee: 68fb ldr r3, [r7, #12]
800bff0: 6bdb ldr r3, [r3, #60] ; 0x3c
800bff2: 68f9 ldr r1, [r7, #12]
800bff4: 6c09 ldr r1, [r1, #64] ; 0x40
800bff6: fb01 f303 mul.w r3, r1, r3
800bffa: 441a add r2, r3
800bffc: 68fb ldr r3, [r7, #12]
800bffe: 609a str r2, [r3, #8]
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
800c000: 68fb ldr r3, [r7, #12]
800c002: 2200 movs r2, #0
800c004: 639a str r2, [r3, #56] ; 0x38
pxQueue->pcWriteTo = pxQueue->pcHead;
800c006: 68fb ldr r3, [r7, #12]
800c008: 681a ldr r2, [r3, #0]
800c00a: 68fb ldr r3, [r7, #12]
800c00c: 605a str r2, [r3, #4]
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
800c00e: 68fb ldr r3, [r7, #12]
800c010: 681a ldr r2, [r3, #0]
800c012: 68fb ldr r3, [r7, #12]
800c014: 6bdb ldr r3, [r3, #60] ; 0x3c
800c016: 3b01 subs r3, #1
800c018: 68f9 ldr r1, [r7, #12]
800c01a: 6c09 ldr r1, [r1, #64] ; 0x40
800c01c: fb01 f303 mul.w r3, r1, r3
800c020: 441a add r2, r3
800c022: 68fb ldr r3, [r7, #12]
800c024: 60da str r2, [r3, #12]
pxQueue->cRxLock = queueUNLOCKED;
800c026: 68fb ldr r3, [r7, #12]
800c028: 22ff movs r2, #255 ; 0xff
800c02a: f883 2044 strb.w r2, [r3, #68] ; 0x44
pxQueue->cTxLock = queueUNLOCKED;
800c02e: 68fb ldr r3, [r7, #12]
800c030: 22ff movs r2, #255 ; 0xff
800c032: f883 2045 strb.w r2, [r3, #69] ; 0x45
if( xNewQueue == pdFALSE )
800c036: 683b ldr r3, [r7, #0]
800c038: 2b00 cmp r3, #0
800c03a: d114 bne.n 800c066 <xQueueGenericReset+0xae>
/* If there are tasks blocked waiting to read from the queue, then
the tasks will remain blocked as after this function exits the queue
will still be empty. If there are tasks blocked waiting to write to
the queue, then one should be unblocked as after this function exits
it will be possible to write to it. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800c03c: 68fb ldr r3, [r7, #12]
800c03e: 691b ldr r3, [r3, #16]
800c040: 2b00 cmp r3, #0
800c042: d01a beq.n 800c07a <xQueueGenericReset+0xc2>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800c044: 68fb ldr r3, [r7, #12]
800c046: 3310 adds r3, #16
800c048: 4618 mov r0, r3
800c04a: f001 fd2b bl 800daa4 <xTaskRemoveFromEventList>
800c04e: 4603 mov r3, r0
800c050: 2b00 cmp r3, #0
800c052: d012 beq.n 800c07a <xQueueGenericReset+0xc2>
{
queueYIELD_IF_USING_PREEMPTION();
800c054: 4b0c ldr r3, [pc, #48] ; (800c088 <xQueueGenericReset+0xd0>)
800c056: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c05a: 601a str r2, [r3, #0]
800c05c: f3bf 8f4f dsb sy
800c060: f3bf 8f6f isb sy
800c064: e009 b.n 800c07a <xQueueGenericReset+0xc2>
}
}
else
{
/* Ensure the event queues start in the correct state. */
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
800c066: 68fb ldr r3, [r7, #12]
800c068: 3310 adds r3, #16
800c06a: 4618 mov r0, r3
800c06c: f7ff fef0 bl 800be50 <vListInitialise>
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
800c070: 68fb ldr r3, [r7, #12]
800c072: 3324 adds r3, #36 ; 0x24
800c074: 4618 mov r0, r3
800c076: f7ff feeb bl 800be50 <vListInitialise>
}
}
taskEXIT_CRITICAL();
800c07a: f002 fa5b bl 800e534 <vPortExitCritical>
/* A value is returned for calling semantic consistency with previous
versions. */
return pdPASS;
800c07e: 2301 movs r3, #1
}
800c080: 4618 mov r0, r3
800c082: 3710 adds r7, #16
800c084: 46bd mov sp, r7
800c086: bd80 pop {r7, pc}
800c088: e000ed04 .word 0xe000ed04
0800c08c <xQueueGenericCreateStatic>:
/*-----------------------------------------------------------*/
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
{
800c08c: b580 push {r7, lr}
800c08e: b08e sub sp, #56 ; 0x38
800c090: af02 add r7, sp, #8
800c092: 60f8 str r0, [r7, #12]
800c094: 60b9 str r1, [r7, #8]
800c096: 607a str r2, [r7, #4]
800c098: 603b str r3, [r7, #0]
Queue_t *pxNewQueue;
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
800c09a: 68fb ldr r3, [r7, #12]
800c09c: 2b00 cmp r3, #0
800c09e: d10c bne.n 800c0ba <xQueueGenericCreateStatic+0x2e>
__asm volatile
800c0a0: f04f 0350 mov.w r3, #80 ; 0x50
800c0a4: b672 cpsid i
800c0a6: f383 8811 msr BASEPRI, r3
800c0aa: f3bf 8f6f isb sy
800c0ae: f3bf 8f4f dsb sy
800c0b2: b662 cpsie i
800c0b4: 62bb str r3, [r7, #40] ; 0x28
}
800c0b6: bf00 nop
800c0b8: e7fe b.n 800c0b8 <xQueueGenericCreateStatic+0x2c>
/* The StaticQueue_t structure and the queue storage area must be
supplied. */
configASSERT( pxStaticQueue != NULL );
800c0ba: 683b ldr r3, [r7, #0]
800c0bc: 2b00 cmp r3, #0
800c0be: d10c bne.n 800c0da <xQueueGenericCreateStatic+0x4e>
__asm volatile
800c0c0: f04f 0350 mov.w r3, #80 ; 0x50
800c0c4: b672 cpsid i
800c0c6: f383 8811 msr BASEPRI, r3
800c0ca: f3bf 8f6f isb sy
800c0ce: f3bf 8f4f dsb sy
800c0d2: b662 cpsie i
800c0d4: 627b str r3, [r7, #36] ; 0x24
}
800c0d6: bf00 nop
800c0d8: e7fe b.n 800c0d8 <xQueueGenericCreateStatic+0x4c>
/* A queue storage area should be provided if the item size is not 0, and
should not be provided if the item size is 0. */
configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
800c0da: 687b ldr r3, [r7, #4]
800c0dc: 2b00 cmp r3, #0
800c0de: d002 beq.n 800c0e6 <xQueueGenericCreateStatic+0x5a>
800c0e0: 68bb ldr r3, [r7, #8]
800c0e2: 2b00 cmp r3, #0
800c0e4: d001 beq.n 800c0ea <xQueueGenericCreateStatic+0x5e>
800c0e6: 2301 movs r3, #1
800c0e8: e000 b.n 800c0ec <xQueueGenericCreateStatic+0x60>
800c0ea: 2300 movs r3, #0
800c0ec: 2b00 cmp r3, #0
800c0ee: d10c bne.n 800c10a <xQueueGenericCreateStatic+0x7e>
__asm volatile
800c0f0: f04f 0350 mov.w r3, #80 ; 0x50
800c0f4: b672 cpsid i
800c0f6: f383 8811 msr BASEPRI, r3
800c0fa: f3bf 8f6f isb sy
800c0fe: f3bf 8f4f dsb sy
800c102: b662 cpsie i
800c104: 623b str r3, [r7, #32]
}
800c106: bf00 nop
800c108: e7fe b.n 800c108 <xQueueGenericCreateStatic+0x7c>
configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
800c10a: 687b ldr r3, [r7, #4]
800c10c: 2b00 cmp r3, #0
800c10e: d102 bne.n 800c116 <xQueueGenericCreateStatic+0x8a>
800c110: 68bb ldr r3, [r7, #8]
800c112: 2b00 cmp r3, #0
800c114: d101 bne.n 800c11a <xQueueGenericCreateStatic+0x8e>
800c116: 2301 movs r3, #1
800c118: e000 b.n 800c11c <xQueueGenericCreateStatic+0x90>
800c11a: 2300 movs r3, #0
800c11c: 2b00 cmp r3, #0
800c11e: d10c bne.n 800c13a <xQueueGenericCreateStatic+0xae>
__asm volatile
800c120: f04f 0350 mov.w r3, #80 ; 0x50
800c124: b672 cpsid i
800c126: f383 8811 msr BASEPRI, r3
800c12a: f3bf 8f6f isb sy
800c12e: f3bf 8f4f dsb sy
800c132: b662 cpsie i
800c134: 61fb str r3, [r7, #28]
}
800c136: bf00 nop
800c138: e7fe b.n 800c138 <xQueueGenericCreateStatic+0xac>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticQueue_t or StaticSemaphore_t equals the size of
the real queue and semaphore structures. */
volatile size_t xSize = sizeof( StaticQueue_t );
800c13a: 2348 movs r3, #72 ; 0x48
800c13c: 617b str r3, [r7, #20]
configASSERT( xSize == sizeof( Queue_t ) );
800c13e: 697b ldr r3, [r7, #20]
800c140: 2b48 cmp r3, #72 ; 0x48
800c142: d00c beq.n 800c15e <xQueueGenericCreateStatic+0xd2>
__asm volatile
800c144: f04f 0350 mov.w r3, #80 ; 0x50
800c148: b672 cpsid i
800c14a: f383 8811 msr BASEPRI, r3
800c14e: f3bf 8f6f isb sy
800c152: f3bf 8f4f dsb sy
800c156: b662 cpsie i
800c158: 61bb str r3, [r7, #24]
}
800c15a: bf00 nop
800c15c: e7fe b.n 800c15c <xQueueGenericCreateStatic+0xd0>
( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
800c15e: 697b ldr r3, [r7, #20]
#endif /* configASSERT_DEFINED */
/* The address of a statically allocated queue was passed in, use it.
The address of a statically allocated storage area was also passed in
but is already set. */
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
800c160: 683b ldr r3, [r7, #0]
800c162: 62fb str r3, [r7, #44] ; 0x2c
if( pxNewQueue != NULL )
800c164: 6afb ldr r3, [r7, #44] ; 0x2c
800c166: 2b00 cmp r3, #0
800c168: d00d beq.n 800c186 <xQueueGenericCreateStatic+0xfa>
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
/* Queues can be allocated wither statically or dynamically, so
note this queue was allocated statically in case the queue is
later deleted. */
pxNewQueue->ucStaticallyAllocated = pdTRUE;
800c16a: 6afb ldr r3, [r7, #44] ; 0x2c
800c16c: 2201 movs r2, #1
800c16e: f883 2046 strb.w r2, [r3, #70] ; 0x46
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
800c172: f897 2038 ldrb.w r2, [r7, #56] ; 0x38
800c176: 6afb ldr r3, [r7, #44] ; 0x2c
800c178: 9300 str r3, [sp, #0]
800c17a: 4613 mov r3, r2
800c17c: 687a ldr r2, [r7, #4]
800c17e: 68b9 ldr r1, [r7, #8]
800c180: 68f8 ldr r0, [r7, #12]
800c182: f000 f847 bl 800c214 <prvInitialiseNewQueue>
{
traceQUEUE_CREATE_FAILED( ucQueueType );
mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
800c186: 6afb ldr r3, [r7, #44] ; 0x2c
}
800c188: 4618 mov r0, r3
800c18a: 3730 adds r7, #48 ; 0x30
800c18c: 46bd mov sp, r7
800c18e: bd80 pop {r7, pc}
0800c190 <xQueueGenericCreate>:
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
{
800c190: b580 push {r7, lr}
800c192: b08a sub sp, #40 ; 0x28
800c194: af02 add r7, sp, #8
800c196: 60f8 str r0, [r7, #12]
800c198: 60b9 str r1, [r7, #8]
800c19a: 4613 mov r3, r2
800c19c: 71fb strb r3, [r7, #7]
Queue_t *pxNewQueue;
size_t xQueueSizeInBytes;
uint8_t *pucQueueStorage;
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
800c19e: 68fb ldr r3, [r7, #12]
800c1a0: 2b00 cmp r3, #0
800c1a2: d10c bne.n 800c1be <xQueueGenericCreate+0x2e>
__asm volatile
800c1a4: f04f 0350 mov.w r3, #80 ; 0x50
800c1a8: b672 cpsid i
800c1aa: f383 8811 msr BASEPRI, r3
800c1ae: f3bf 8f6f isb sy
800c1b2: f3bf 8f4f dsb sy
800c1b6: b662 cpsie i
800c1b8: 613b str r3, [r7, #16]
}
800c1ba: bf00 nop
800c1bc: e7fe b.n 800c1bc <xQueueGenericCreate+0x2c>
if( uxItemSize == ( UBaseType_t ) 0 )
800c1be: 68bb ldr r3, [r7, #8]
800c1c0: 2b00 cmp r3, #0
800c1c2: d102 bne.n 800c1ca <xQueueGenericCreate+0x3a>
{
/* There is not going to be a queue storage area. */
xQueueSizeInBytes = ( size_t ) 0;
800c1c4: 2300 movs r3, #0
800c1c6: 61fb str r3, [r7, #28]
800c1c8: e004 b.n 800c1d4 <xQueueGenericCreate+0x44>
}
else
{
/* Allocate enough space to hold the maximum number of items that
can be in the queue at any time. */
xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800c1ca: 68fb ldr r3, [r7, #12]
800c1cc: 68ba ldr r2, [r7, #8]
800c1ce: fb02 f303 mul.w r3, r2, r3
800c1d2: 61fb str r3, [r7, #28]
alignment requirements of the Queue_t structure - which in this case
is an int8_t *. Therefore, whenever the stack alignment requirements
are greater than or equal to the pointer to char requirements the cast
is safe. In other cases alignment requirements are not strict (one or
two bytes). */
pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
800c1d4: 69fb ldr r3, [r7, #28]
800c1d6: 3348 adds r3, #72 ; 0x48
800c1d8: 4618 mov r0, r3
800c1da: f002 faa3 bl 800e724 <pvPortMalloc>
800c1de: 61b8 str r0, [r7, #24]
if( pxNewQueue != NULL )
800c1e0: 69bb ldr r3, [r7, #24]
800c1e2: 2b00 cmp r3, #0
800c1e4: d011 beq.n 800c20a <xQueueGenericCreate+0x7a>
{
/* Jump past the queue structure to find the location of the queue
storage area. */
pucQueueStorage = ( uint8_t * ) pxNewQueue;
800c1e6: 69bb ldr r3, [r7, #24]
800c1e8: 617b str r3, [r7, #20]
pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
800c1ea: 697b ldr r3, [r7, #20]
800c1ec: 3348 adds r3, #72 ; 0x48
800c1ee: 617b str r3, [r7, #20]
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
/* Queues can be created either statically or dynamically, so
note this task was created dynamically in case it is later
deleted. */
pxNewQueue->ucStaticallyAllocated = pdFALSE;
800c1f0: 69bb ldr r3, [r7, #24]
800c1f2: 2200 movs r2, #0
800c1f4: f883 2046 strb.w r2, [r3, #70] ; 0x46
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
800c1f8: 79fa ldrb r2, [r7, #7]
800c1fa: 69bb ldr r3, [r7, #24]
800c1fc: 9300 str r3, [sp, #0]
800c1fe: 4613 mov r3, r2
800c200: 697a ldr r2, [r7, #20]
800c202: 68b9 ldr r1, [r7, #8]
800c204: 68f8 ldr r0, [r7, #12]
800c206: f000 f805 bl 800c214 <prvInitialiseNewQueue>
{
traceQUEUE_CREATE_FAILED( ucQueueType );
mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
800c20a: 69bb ldr r3, [r7, #24]
}
800c20c: 4618 mov r0, r3
800c20e: 3720 adds r7, #32
800c210: 46bd mov sp, r7
800c212: bd80 pop {r7, pc}
0800c214 <prvInitialiseNewQueue>:
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
800c214: b580 push {r7, lr}
800c216: b084 sub sp, #16
800c218: af00 add r7, sp, #0
800c21a: 60f8 str r0, [r7, #12]
800c21c: 60b9 str r1, [r7, #8]
800c21e: 607a str r2, [r7, #4]
800c220: 70fb strb r3, [r7, #3]
/* Remove compiler warnings about unused parameters should
configUSE_TRACE_FACILITY not be set to 1. */
( void ) ucQueueType;
if( uxItemSize == ( UBaseType_t ) 0 )
800c222: 68bb ldr r3, [r7, #8]
800c224: 2b00 cmp r3, #0
800c226: d103 bne.n 800c230 <prvInitialiseNewQueue+0x1c>
{
/* No RAM was allocated for the queue storage area, but PC head cannot
be set to NULL because NULL is used as a key to say the queue is used as
a mutex. Therefore just set pcHead to point to the queue as a benign
value that is known to be within the memory map. */
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
800c228: 69bb ldr r3, [r7, #24]
800c22a: 69ba ldr r2, [r7, #24]
800c22c: 601a str r2, [r3, #0]
800c22e: e002 b.n 800c236 <prvInitialiseNewQueue+0x22>
}
else
{
/* Set the head to the start of the queue storage area. */
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
800c230: 69bb ldr r3, [r7, #24]
800c232: 687a ldr r2, [r7, #4]
800c234: 601a str r2, [r3, #0]
}
/* Initialise the queue members as described where the queue type is
defined. */
pxNewQueue->uxLength = uxQueueLength;
800c236: 69bb ldr r3, [r7, #24]
800c238: 68fa ldr r2, [r7, #12]
800c23a: 63da str r2, [r3, #60] ; 0x3c
pxNewQueue->uxItemSize = uxItemSize;
800c23c: 69bb ldr r3, [r7, #24]
800c23e: 68ba ldr r2, [r7, #8]
800c240: 641a str r2, [r3, #64] ; 0x40
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
800c242: 2101 movs r1, #1
800c244: 69b8 ldr r0, [r7, #24]
800c246: f7ff feb7 bl 800bfb8 <xQueueGenericReset>
pxNewQueue->pxQueueSetContainer = NULL;
}
#endif /* configUSE_QUEUE_SETS */
traceQUEUE_CREATE( pxNewQueue );
}
800c24a: bf00 nop
800c24c: 3710 adds r7, #16
800c24e: 46bd mov sp, r7
800c250: bd80 pop {r7, pc}
0800c252 <prvInitialiseMutex>:
/*-----------------------------------------------------------*/
#if( configUSE_MUTEXES == 1 )
static void prvInitialiseMutex( Queue_t *pxNewQueue )
{
800c252: b580 push {r7, lr}
800c254: b082 sub sp, #8
800c256: af00 add r7, sp, #0
800c258: 6078 str r0, [r7, #4]
if( pxNewQueue != NULL )
800c25a: 687b ldr r3, [r7, #4]
800c25c: 2b00 cmp r3, #0
800c25e: d00e beq.n 800c27e <prvInitialiseMutex+0x2c>
{
/* The queue create function will set all the queue structure members
correctly for a generic queue, but this function is creating a
mutex. Overwrite those members that need to be set differently -
in particular the information required for priority inheritance. */
pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
800c260: 687b ldr r3, [r7, #4]
800c262: 2200 movs r2, #0
800c264: 609a str r2, [r3, #8]
pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
800c266: 687b ldr r3, [r7, #4]
800c268: 2200 movs r2, #0
800c26a: 601a str r2, [r3, #0]
/* In case this is a recursive mutex. */
pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
800c26c: 687b ldr r3, [r7, #4]
800c26e: 2200 movs r2, #0
800c270: 60da str r2, [r3, #12]
traceCREATE_MUTEX( pxNewQueue );
/* Start with the semaphore in the expected state. */
( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
800c272: 2300 movs r3, #0
800c274: 2200 movs r2, #0
800c276: 2100 movs r1, #0
800c278: 6878 ldr r0, [r7, #4]
800c27a: f000 f8a9 bl 800c3d0 <xQueueGenericSend>
}
else
{
traceCREATE_MUTEX_FAILED();
}
}
800c27e: bf00 nop
800c280: 3708 adds r7, #8
800c282: 46bd mov sp, r7
800c284: bd80 pop {r7, pc}
0800c286 <xQueueCreateMutex>:
/*-----------------------------------------------------------*/
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
{
800c286: b580 push {r7, lr}
800c288: b086 sub sp, #24
800c28a: af00 add r7, sp, #0
800c28c: 4603 mov r3, r0
800c28e: 71fb strb r3, [r7, #7]
QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
800c290: 2301 movs r3, #1
800c292: 617b str r3, [r7, #20]
800c294: 2300 movs r3, #0
800c296: 613b str r3, [r7, #16]
xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
800c298: 79fb ldrb r3, [r7, #7]
800c29a: 461a mov r2, r3
800c29c: 6939 ldr r1, [r7, #16]
800c29e: 6978 ldr r0, [r7, #20]
800c2a0: f7ff ff76 bl 800c190 <xQueueGenericCreate>
800c2a4: 60f8 str r0, [r7, #12]
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
800c2a6: 68f8 ldr r0, [r7, #12]
800c2a8: f7ff ffd3 bl 800c252 <prvInitialiseMutex>
return xNewQueue;
800c2ac: 68fb ldr r3, [r7, #12]
}
800c2ae: 4618 mov r0, r3
800c2b0: 3718 adds r7, #24
800c2b2: 46bd mov sp, r7
800c2b4: bd80 pop {r7, pc}
0800c2b6 <xQueueCreateMutexStatic>:
/*-----------------------------------------------------------*/
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
{
800c2b6: b580 push {r7, lr}
800c2b8: b088 sub sp, #32
800c2ba: af02 add r7, sp, #8
800c2bc: 4603 mov r3, r0
800c2be: 6039 str r1, [r7, #0]
800c2c0: 71fb strb r3, [r7, #7]
QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
800c2c2: 2301 movs r3, #1
800c2c4: 617b str r3, [r7, #20]
800c2c6: 2300 movs r3, #0
800c2c8: 613b str r3, [r7, #16]
/* Prevent compiler warnings about unused parameters if
configUSE_TRACE_FACILITY does not equal 1. */
( void ) ucQueueType;
xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
800c2ca: 79fb ldrb r3, [r7, #7]
800c2cc: 9300 str r3, [sp, #0]
800c2ce: 683b ldr r3, [r7, #0]
800c2d0: 2200 movs r2, #0
800c2d2: 6939 ldr r1, [r7, #16]
800c2d4: 6978 ldr r0, [r7, #20]
800c2d6: f7ff fed9 bl 800c08c <xQueueGenericCreateStatic>
800c2da: 60f8 str r0, [r7, #12]
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
800c2dc: 68f8 ldr r0, [r7, #12]
800c2de: f7ff ffb8 bl 800c252 <prvInitialiseMutex>
return xNewQueue;
800c2e2: 68fb ldr r3, [r7, #12]
}
800c2e4: 4618 mov r0, r3
800c2e6: 3718 adds r7, #24
800c2e8: 46bd mov sp, r7
800c2ea: bd80 pop {r7, pc}
0800c2ec <xQueueCreateCountingSemaphoreStatic>:
/*-----------------------------------------------------------*/
#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
{
800c2ec: b580 push {r7, lr}
800c2ee: b08a sub sp, #40 ; 0x28
800c2f0: af02 add r7, sp, #8
800c2f2: 60f8 str r0, [r7, #12]
800c2f4: 60b9 str r1, [r7, #8]
800c2f6: 607a str r2, [r7, #4]
QueueHandle_t xHandle;
configASSERT( uxMaxCount != 0 );
800c2f8: 68fb ldr r3, [r7, #12]
800c2fa: 2b00 cmp r3, #0
800c2fc: d10c bne.n 800c318 <xQueueCreateCountingSemaphoreStatic+0x2c>
__asm volatile
800c2fe: f04f 0350 mov.w r3, #80 ; 0x50
800c302: b672 cpsid i
800c304: f383 8811 msr BASEPRI, r3
800c308: f3bf 8f6f isb sy
800c30c: f3bf 8f4f dsb sy
800c310: b662 cpsie i
800c312: 61bb str r3, [r7, #24]
}
800c314: bf00 nop
800c316: e7fe b.n 800c316 <xQueueCreateCountingSemaphoreStatic+0x2a>
configASSERT( uxInitialCount <= uxMaxCount );
800c318: 68ba ldr r2, [r7, #8]
800c31a: 68fb ldr r3, [r7, #12]
800c31c: 429a cmp r2, r3
800c31e: d90c bls.n 800c33a <xQueueCreateCountingSemaphoreStatic+0x4e>
__asm volatile
800c320: f04f 0350 mov.w r3, #80 ; 0x50
800c324: b672 cpsid i
800c326: f383 8811 msr BASEPRI, r3
800c32a: f3bf 8f6f isb sy
800c32e: f3bf 8f4f dsb sy
800c332: b662 cpsie i
800c334: 617b str r3, [r7, #20]
}
800c336: bf00 nop
800c338: e7fe b.n 800c338 <xQueueCreateCountingSemaphoreStatic+0x4c>
xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
800c33a: 2302 movs r3, #2
800c33c: 9300 str r3, [sp, #0]
800c33e: 687b ldr r3, [r7, #4]
800c340: 2200 movs r2, #0
800c342: 2100 movs r1, #0
800c344: 68f8 ldr r0, [r7, #12]
800c346: f7ff fea1 bl 800c08c <xQueueGenericCreateStatic>
800c34a: 61f8 str r0, [r7, #28]
if( xHandle != NULL )
800c34c: 69fb ldr r3, [r7, #28]
800c34e: 2b00 cmp r3, #0
800c350: d002 beq.n 800c358 <xQueueCreateCountingSemaphoreStatic+0x6c>
{
( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
800c352: 69fb ldr r3, [r7, #28]
800c354: 68ba ldr r2, [r7, #8]
800c356: 639a str r2, [r3, #56] ; 0x38
else
{
traceCREATE_COUNTING_SEMAPHORE_FAILED();
}
return xHandle;
800c358: 69fb ldr r3, [r7, #28]
}
800c35a: 4618 mov r0, r3
800c35c: 3720 adds r7, #32
800c35e: 46bd mov sp, r7
800c360: bd80 pop {r7, pc}
0800c362 <xQueueCreateCountingSemaphore>:
/*-----------------------------------------------------------*/
#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
{
800c362: b580 push {r7, lr}
800c364: b086 sub sp, #24
800c366: af00 add r7, sp, #0
800c368: 6078 str r0, [r7, #4]
800c36a: 6039 str r1, [r7, #0]
QueueHandle_t xHandle;
configASSERT( uxMaxCount != 0 );
800c36c: 687b ldr r3, [r7, #4]
800c36e: 2b00 cmp r3, #0
800c370: d10c bne.n 800c38c <xQueueCreateCountingSemaphore+0x2a>
__asm volatile
800c372: f04f 0350 mov.w r3, #80 ; 0x50
800c376: b672 cpsid i
800c378: f383 8811 msr BASEPRI, r3
800c37c: f3bf 8f6f isb sy
800c380: f3bf 8f4f dsb sy
800c384: b662 cpsie i
800c386: 613b str r3, [r7, #16]
}
800c388: bf00 nop
800c38a: e7fe b.n 800c38a <xQueueCreateCountingSemaphore+0x28>
configASSERT( uxInitialCount <= uxMaxCount );
800c38c: 683a ldr r2, [r7, #0]
800c38e: 687b ldr r3, [r7, #4]
800c390: 429a cmp r2, r3
800c392: d90c bls.n 800c3ae <xQueueCreateCountingSemaphore+0x4c>
__asm volatile
800c394: f04f 0350 mov.w r3, #80 ; 0x50
800c398: b672 cpsid i
800c39a: f383 8811 msr BASEPRI, r3
800c39e: f3bf 8f6f isb sy
800c3a2: f3bf 8f4f dsb sy
800c3a6: b662 cpsie i
800c3a8: 60fb str r3, [r7, #12]
}
800c3aa: bf00 nop
800c3ac: e7fe b.n 800c3ac <xQueueCreateCountingSemaphore+0x4a>
xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
800c3ae: 2202 movs r2, #2
800c3b0: 2100 movs r1, #0
800c3b2: 6878 ldr r0, [r7, #4]
800c3b4: f7ff feec bl 800c190 <xQueueGenericCreate>
800c3b8: 6178 str r0, [r7, #20]
if( xHandle != NULL )
800c3ba: 697b ldr r3, [r7, #20]
800c3bc: 2b00 cmp r3, #0
800c3be: d002 beq.n 800c3c6 <xQueueCreateCountingSemaphore+0x64>
{
( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
800c3c0: 697b ldr r3, [r7, #20]
800c3c2: 683a ldr r2, [r7, #0]
800c3c4: 639a str r2, [r3, #56] ; 0x38
else
{
traceCREATE_COUNTING_SEMAPHORE_FAILED();
}
return xHandle;
800c3c6: 697b ldr r3, [r7, #20]
}
800c3c8: 4618 mov r0, r3
800c3ca: 3718 adds r7, #24
800c3cc: 46bd mov sp, r7
800c3ce: bd80 pop {r7, pc}
0800c3d0 <xQueueGenericSend>:
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
800c3d0: b580 push {r7, lr}
800c3d2: b08e sub sp, #56 ; 0x38
800c3d4: af00 add r7, sp, #0
800c3d6: 60f8 str r0, [r7, #12]
800c3d8: 60b9 str r1, [r7, #8]
800c3da: 607a str r2, [r7, #4]
800c3dc: 603b str r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
800c3de: 2300 movs r3, #0
800c3e0: 637b str r3, [r7, #52] ; 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
800c3e2: 68fb ldr r3, [r7, #12]
800c3e4: 633b str r3, [r7, #48] ; 0x30
configASSERT( pxQueue );
800c3e6: 6b3b ldr r3, [r7, #48] ; 0x30
800c3e8: 2b00 cmp r3, #0
800c3ea: d10c bne.n 800c406 <xQueueGenericSend+0x36>
__asm volatile
800c3ec: f04f 0350 mov.w r3, #80 ; 0x50
800c3f0: b672 cpsid i
800c3f2: f383 8811 msr BASEPRI, r3
800c3f6: f3bf 8f6f isb sy
800c3fa: f3bf 8f4f dsb sy
800c3fe: b662 cpsie i
800c400: 62bb str r3, [r7, #40] ; 0x28
}
800c402: bf00 nop
800c404: e7fe b.n 800c404 <xQueueGenericSend+0x34>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
800c406: 68bb ldr r3, [r7, #8]
800c408: 2b00 cmp r3, #0
800c40a: d103 bne.n 800c414 <xQueueGenericSend+0x44>
800c40c: 6b3b ldr r3, [r7, #48] ; 0x30
800c40e: 6c1b ldr r3, [r3, #64] ; 0x40
800c410: 2b00 cmp r3, #0
800c412: d101 bne.n 800c418 <xQueueGenericSend+0x48>
800c414: 2301 movs r3, #1
800c416: e000 b.n 800c41a <xQueueGenericSend+0x4a>
800c418: 2300 movs r3, #0
800c41a: 2b00 cmp r3, #0
800c41c: d10c bne.n 800c438 <xQueueGenericSend+0x68>
__asm volatile
800c41e: f04f 0350 mov.w r3, #80 ; 0x50
800c422: b672 cpsid i
800c424: f383 8811 msr BASEPRI, r3
800c428: f3bf 8f6f isb sy
800c42c: f3bf 8f4f dsb sy
800c430: b662 cpsie i
800c432: 627b str r3, [r7, #36] ; 0x24
}
800c434: bf00 nop
800c436: e7fe b.n 800c436 <xQueueGenericSend+0x66>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
800c438: 683b ldr r3, [r7, #0]
800c43a: 2b02 cmp r3, #2
800c43c: d103 bne.n 800c446 <xQueueGenericSend+0x76>
800c43e: 6b3b ldr r3, [r7, #48] ; 0x30
800c440: 6bdb ldr r3, [r3, #60] ; 0x3c
800c442: 2b01 cmp r3, #1
800c444: d101 bne.n 800c44a <xQueueGenericSend+0x7a>
800c446: 2301 movs r3, #1
800c448: e000 b.n 800c44c <xQueueGenericSend+0x7c>
800c44a: 2300 movs r3, #0
800c44c: 2b00 cmp r3, #0
800c44e: d10c bne.n 800c46a <xQueueGenericSend+0x9a>
__asm volatile
800c450: f04f 0350 mov.w r3, #80 ; 0x50
800c454: b672 cpsid i
800c456: f383 8811 msr BASEPRI, r3
800c45a: f3bf 8f6f isb sy
800c45e: f3bf 8f4f dsb sy
800c462: b662 cpsie i
800c464: 623b str r3, [r7, #32]
}
800c466: bf00 nop
800c468: e7fe b.n 800c468 <xQueueGenericSend+0x98>
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
800c46a: f001 fce1 bl 800de30 <xTaskGetSchedulerState>
800c46e: 4603 mov r3, r0
800c470: 2b00 cmp r3, #0
800c472: d102 bne.n 800c47a <xQueueGenericSend+0xaa>
800c474: 687b ldr r3, [r7, #4]
800c476: 2b00 cmp r3, #0
800c478: d101 bne.n 800c47e <xQueueGenericSend+0xae>
800c47a: 2301 movs r3, #1
800c47c: e000 b.n 800c480 <xQueueGenericSend+0xb0>
800c47e: 2300 movs r3, #0
800c480: 2b00 cmp r3, #0
800c482: d10c bne.n 800c49e <xQueueGenericSend+0xce>
__asm volatile
800c484: f04f 0350 mov.w r3, #80 ; 0x50
800c488: b672 cpsid i
800c48a: f383 8811 msr BASEPRI, r3
800c48e: f3bf 8f6f isb sy
800c492: f3bf 8f4f dsb sy
800c496: b662 cpsie i
800c498: 61fb str r3, [r7, #28]
}
800c49a: bf00 nop
800c49c: e7fe b.n 800c49c <xQueueGenericSend+0xcc>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
800c49e: f002 f815 bl 800e4cc <vPortEnterCritical>
{
/* Is there room on the queue now? The running task must be the
highest priority task wanting to access the queue. If the head item
in the queue is to be overwritten then it does not matter if the
queue is full. */
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
800c4a2: 6b3b ldr r3, [r7, #48] ; 0x30
800c4a4: 6b9a ldr r2, [r3, #56] ; 0x38
800c4a6: 6b3b ldr r3, [r7, #48] ; 0x30
800c4a8: 6bdb ldr r3, [r3, #60] ; 0x3c
800c4aa: 429a cmp r2, r3
800c4ac: d302 bcc.n 800c4b4 <xQueueGenericSend+0xe4>
800c4ae: 683b ldr r3, [r7, #0]
800c4b0: 2b02 cmp r3, #2
800c4b2: d129 bne.n 800c508 <xQueueGenericSend+0x138>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
800c4b4: 683a ldr r2, [r7, #0]
800c4b6: 68b9 ldr r1, [r7, #8]
800c4b8: 6b38 ldr r0, [r7, #48] ; 0x30
800c4ba: f000 fc5d bl 800cd78 <prvCopyDataToQueue>
800c4be: 62f8 str r0, [r7, #44] ; 0x2c
/* If there was a task waiting for data to arrive on the
queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800c4c0: 6b3b ldr r3, [r7, #48] ; 0x30
800c4c2: 6a5b ldr r3, [r3, #36] ; 0x24
800c4c4: 2b00 cmp r3, #0
800c4c6: d010 beq.n 800c4ea <xQueueGenericSend+0x11a>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800c4c8: 6b3b ldr r3, [r7, #48] ; 0x30
800c4ca: 3324 adds r3, #36 ; 0x24
800c4cc: 4618 mov r0, r3
800c4ce: f001 fae9 bl 800daa4 <xTaskRemoveFromEventList>
800c4d2: 4603 mov r3, r0
800c4d4: 2b00 cmp r3, #0
800c4d6: d013 beq.n 800c500 <xQueueGenericSend+0x130>
{
/* The unblocked task has a priority higher than
our own so yield immediately. Yes it is ok to do
this from within the critical section - the kernel
takes care of that. */
queueYIELD_IF_USING_PREEMPTION();
800c4d8: 4b3f ldr r3, [pc, #252] ; (800c5d8 <xQueueGenericSend+0x208>)
800c4da: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c4de: 601a str r2, [r3, #0]
800c4e0: f3bf 8f4f dsb sy
800c4e4: f3bf 8f6f isb sy
800c4e8: e00a b.n 800c500 <xQueueGenericSend+0x130>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else if( xYieldRequired != pdFALSE )
800c4ea: 6afb ldr r3, [r7, #44] ; 0x2c
800c4ec: 2b00 cmp r3, #0
800c4ee: d007 beq.n 800c500 <xQueueGenericSend+0x130>
{
/* This path is a special case that will only get
executed if the task was holding multiple mutexes and
the mutexes were given back in an order that is
different to that in which they were taken. */
queueYIELD_IF_USING_PREEMPTION();
800c4f0: 4b39 ldr r3, [pc, #228] ; (800c5d8 <xQueueGenericSend+0x208>)
800c4f2: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c4f6: 601a str r2, [r3, #0]
800c4f8: f3bf 8f4f dsb sy
800c4fc: f3bf 8f6f isb sy
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
taskEXIT_CRITICAL();
800c500: f002 f818 bl 800e534 <vPortExitCritical>
return pdPASS;
800c504: 2301 movs r3, #1
800c506: e063 b.n 800c5d0 <xQueueGenericSend+0x200>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
800c508: 687b ldr r3, [r7, #4]
800c50a: 2b00 cmp r3, #0
800c50c: d103 bne.n 800c516 <xQueueGenericSend+0x146>
{
/* The queue was full and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
800c50e: f002 f811 bl 800e534 <vPortExitCritical>
/* Return to the original privilege level before exiting
the function. */
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
800c512: 2300 movs r3, #0
800c514: e05c b.n 800c5d0 <xQueueGenericSend+0x200>
}
else if( xEntryTimeSet == pdFALSE )
800c516: 6b7b ldr r3, [r7, #52] ; 0x34
800c518: 2b00 cmp r3, #0
800c51a: d106 bne.n 800c52a <xQueueGenericSend+0x15a>
{
/* The queue was full and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
800c51c: f107 0314 add.w r3, r7, #20
800c520: 4618 mov r0, r3
800c522: f001 fb23 bl 800db6c <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
800c526: 2301 movs r3, #1
800c528: 637b str r3, [r7, #52] ; 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
800c52a: f002 f803 bl 800e534 <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
800c52e: f001 f889 bl 800d644 <vTaskSuspendAll>
prvLockQueue( pxQueue );
800c532: f001 ffcb bl 800e4cc <vPortEnterCritical>
800c536: 6b3b ldr r3, [r7, #48] ; 0x30
800c538: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800c53c: b25b sxtb r3, r3
800c53e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800c542: d103 bne.n 800c54c <xQueueGenericSend+0x17c>
800c544: 6b3b ldr r3, [r7, #48] ; 0x30
800c546: 2200 movs r2, #0
800c548: f883 2044 strb.w r2, [r3, #68] ; 0x44
800c54c: 6b3b ldr r3, [r7, #48] ; 0x30
800c54e: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800c552: b25b sxtb r3, r3
800c554: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800c558: d103 bne.n 800c562 <xQueueGenericSend+0x192>
800c55a: 6b3b ldr r3, [r7, #48] ; 0x30
800c55c: 2200 movs r2, #0
800c55e: f883 2045 strb.w r2, [r3, #69] ; 0x45
800c562: f001 ffe7 bl 800e534 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
800c566: 1d3a adds r2, r7, #4
800c568: f107 0314 add.w r3, r7, #20
800c56c: 4611 mov r1, r2
800c56e: 4618 mov r0, r3
800c570: f001 fb12 bl 800db98 <xTaskCheckForTimeOut>
800c574: 4603 mov r3, r0
800c576: 2b00 cmp r3, #0
800c578: d124 bne.n 800c5c4 <xQueueGenericSend+0x1f4>
{
if( prvIsQueueFull( pxQueue ) != pdFALSE )
800c57a: 6b38 ldr r0, [r7, #48] ; 0x30
800c57c: f000 fcf4 bl 800cf68 <prvIsQueueFull>
800c580: 4603 mov r3, r0
800c582: 2b00 cmp r3, #0
800c584: d018 beq.n 800c5b8 <xQueueGenericSend+0x1e8>
{
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
800c586: 6b3b ldr r3, [r7, #48] ; 0x30
800c588: 3310 adds r3, #16
800c58a: 687a ldr r2, [r7, #4]
800c58c: 4611 mov r1, r2
800c58e: 4618 mov r0, r3
800c590: f001 fa62 bl 800da58 <vTaskPlaceOnEventList>
/* Unlocking the queue means queue events can effect the
event list. It is possible that interrupts occurring now
remove this task from the event list again - but as the
scheduler is suspended the task will go onto the pending
ready last instead of the actual ready list. */
prvUnlockQueue( pxQueue );
800c594: 6b38 ldr r0, [r7, #48] ; 0x30
800c596: f000 fc7f bl 800ce98 <prvUnlockQueue>
/* Resuming the scheduler will move tasks from the pending
ready list into the ready list - so it is feasible that this
task is already in a ready list before it yields - in which
case the yield will not cause a context switch unless there
is also a higher priority task in the pending ready list. */
if( xTaskResumeAll() == pdFALSE )
800c59a: f001 f861 bl 800d660 <xTaskResumeAll>
800c59e: 4603 mov r3, r0
800c5a0: 2b00 cmp r3, #0
800c5a2: f47f af7c bne.w 800c49e <xQueueGenericSend+0xce>
{
portYIELD_WITHIN_API();
800c5a6: 4b0c ldr r3, [pc, #48] ; (800c5d8 <xQueueGenericSend+0x208>)
800c5a8: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c5ac: 601a str r2, [r3, #0]
800c5ae: f3bf 8f4f dsb sy
800c5b2: f3bf 8f6f isb sy
800c5b6: e772 b.n 800c49e <xQueueGenericSend+0xce>
}
}
else
{
/* Try again. */
prvUnlockQueue( pxQueue );
800c5b8: 6b38 ldr r0, [r7, #48] ; 0x30
800c5ba: f000 fc6d bl 800ce98 <prvUnlockQueue>
( void ) xTaskResumeAll();
800c5be: f001 f84f bl 800d660 <xTaskResumeAll>
800c5c2: e76c b.n 800c49e <xQueueGenericSend+0xce>
}
}
else
{
/* The timeout has expired. */
prvUnlockQueue( pxQueue );
800c5c4: 6b38 ldr r0, [r7, #48] ; 0x30
800c5c6: f000 fc67 bl 800ce98 <prvUnlockQueue>
( void ) xTaskResumeAll();
800c5ca: f001 f849 bl 800d660 <xTaskResumeAll>
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
800c5ce: 2300 movs r3, #0
}
} /*lint -restore */
}
800c5d0: 4618 mov r0, r3
800c5d2: 3738 adds r7, #56 ; 0x38
800c5d4: 46bd mov sp, r7
800c5d6: bd80 pop {r7, pc}
800c5d8: e000ed04 .word 0xe000ed04
0800c5dc <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
800c5dc: b580 push {r7, lr}
800c5de: b08e sub sp, #56 ; 0x38
800c5e0: af00 add r7, sp, #0
800c5e2: 60f8 str r0, [r7, #12]
800c5e4: 60b9 str r1, [r7, #8]
800c5e6: 607a str r2, [r7, #4]
800c5e8: 603b str r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
800c5ea: 68fb ldr r3, [r7, #12]
800c5ec: 633b str r3, [r7, #48] ; 0x30
configASSERT( pxQueue );
800c5ee: 6b3b ldr r3, [r7, #48] ; 0x30
800c5f0: 2b00 cmp r3, #0
800c5f2: d10c bne.n 800c60e <xQueueGenericSendFromISR+0x32>
__asm volatile
800c5f4: f04f 0350 mov.w r3, #80 ; 0x50
800c5f8: b672 cpsid i
800c5fa: f383 8811 msr BASEPRI, r3
800c5fe: f3bf 8f6f isb sy
800c602: f3bf 8f4f dsb sy
800c606: b662 cpsie i
800c608: 627b str r3, [r7, #36] ; 0x24
}
800c60a: bf00 nop
800c60c: e7fe b.n 800c60c <xQueueGenericSendFromISR+0x30>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
800c60e: 68bb ldr r3, [r7, #8]
800c610: 2b00 cmp r3, #0
800c612: d103 bne.n 800c61c <xQueueGenericSendFromISR+0x40>
800c614: 6b3b ldr r3, [r7, #48] ; 0x30
800c616: 6c1b ldr r3, [r3, #64] ; 0x40
800c618: 2b00 cmp r3, #0
800c61a: d101 bne.n 800c620 <xQueueGenericSendFromISR+0x44>
800c61c: 2301 movs r3, #1
800c61e: e000 b.n 800c622 <xQueueGenericSendFromISR+0x46>
800c620: 2300 movs r3, #0
800c622: 2b00 cmp r3, #0
800c624: d10c bne.n 800c640 <xQueueGenericSendFromISR+0x64>
__asm volatile
800c626: f04f 0350 mov.w r3, #80 ; 0x50
800c62a: b672 cpsid i
800c62c: f383 8811 msr BASEPRI, r3
800c630: f3bf 8f6f isb sy
800c634: f3bf 8f4f dsb sy
800c638: b662 cpsie i
800c63a: 623b str r3, [r7, #32]
}
800c63c: bf00 nop
800c63e: e7fe b.n 800c63e <xQueueGenericSendFromISR+0x62>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
800c640: 683b ldr r3, [r7, #0]
800c642: 2b02 cmp r3, #2
800c644: d103 bne.n 800c64e <xQueueGenericSendFromISR+0x72>
800c646: 6b3b ldr r3, [r7, #48] ; 0x30
800c648: 6bdb ldr r3, [r3, #60] ; 0x3c
800c64a: 2b01 cmp r3, #1
800c64c: d101 bne.n 800c652 <xQueueGenericSendFromISR+0x76>
800c64e: 2301 movs r3, #1
800c650: e000 b.n 800c654 <xQueueGenericSendFromISR+0x78>
800c652: 2300 movs r3, #0
800c654: 2b00 cmp r3, #0
800c656: d10c bne.n 800c672 <xQueueGenericSendFromISR+0x96>
__asm volatile
800c658: f04f 0350 mov.w r3, #80 ; 0x50
800c65c: b672 cpsid i
800c65e: f383 8811 msr BASEPRI, r3
800c662: f3bf 8f6f isb sy
800c666: f3bf 8f4f dsb sy
800c66a: b662 cpsie i
800c66c: 61fb str r3, [r7, #28]
}
800c66e: bf00 nop
800c670: e7fe b.n 800c670 <xQueueGenericSendFromISR+0x94>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800c672: f002 f813 bl 800e69c <vPortValidateInterruptPriority>
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile
800c676: f3ef 8211 mrs r2, BASEPRI
800c67a: f04f 0350 mov.w r3, #80 ; 0x50
800c67e: b672 cpsid i
800c680: f383 8811 msr BASEPRI, r3
800c684: f3bf 8f6f isb sy
800c688: f3bf 8f4f dsb sy
800c68c: b662 cpsie i
800c68e: 61ba str r2, [r7, #24]
800c690: 617b str r3, [r7, #20]
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
/* This return will not be reached but is necessary to prevent compiler
warnings. */
return ulOriginalBASEPRI;
800c692: 69bb ldr r3, [r7, #24]
/* Similar to xQueueGenericSend, except without blocking if there is no room
in the queue. Also don't directly wake a task that was blocked on a queue
read, instead return a flag to say whether a context switch is required or
not (i.e. has a task with a higher priority than us been woken by this
post). */
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
800c694: 62fb str r3, [r7, #44] ; 0x2c
{
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
800c696: 6b3b ldr r3, [r7, #48] ; 0x30
800c698: 6b9a ldr r2, [r3, #56] ; 0x38
800c69a: 6b3b ldr r3, [r7, #48] ; 0x30
800c69c: 6bdb ldr r3, [r3, #60] ; 0x3c
800c69e: 429a cmp r2, r3
800c6a0: d302 bcc.n 800c6a8 <xQueueGenericSendFromISR+0xcc>
800c6a2: 683b ldr r3, [r7, #0]
800c6a4: 2b02 cmp r3, #2
800c6a6: d12c bne.n 800c702 <xQueueGenericSendFromISR+0x126>
{
const int8_t cTxLock = pxQueue->cTxLock;
800c6a8: 6b3b ldr r3, [r7, #48] ; 0x30
800c6aa: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800c6ae: f887 302b strb.w r3, [r7, #43] ; 0x2b
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
semaphore or mutex. That means prvCopyDataToQueue() cannot result
in a task disinheriting a priority and prvCopyDataToQueue() can be
called here even though the disinherit function does not check if
the scheduler is suspended before accessing the ready lists. */
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
800c6b2: 683a ldr r2, [r7, #0]
800c6b4: 68b9 ldr r1, [r7, #8]
800c6b6: 6b38 ldr r0, [r7, #48] ; 0x30
800c6b8: f000 fb5e bl 800cd78 <prvCopyDataToQueue>
/* The event list is not altered if the queue is locked. This will
be done when the queue is unlocked later. */
if( cTxLock == queueUNLOCKED )
800c6bc: f997 302b ldrsb.w r3, [r7, #43] ; 0x2b
800c6c0: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800c6c4: d112 bne.n 800c6ec <xQueueGenericSendFromISR+0x110>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800c6c6: 6b3b ldr r3, [r7, #48] ; 0x30
800c6c8: 6a5b ldr r3, [r3, #36] ; 0x24
800c6ca: 2b00 cmp r3, #0
800c6cc: d016 beq.n 800c6fc <xQueueGenericSendFromISR+0x120>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800c6ce: 6b3b ldr r3, [r7, #48] ; 0x30
800c6d0: 3324 adds r3, #36 ; 0x24
800c6d2: 4618 mov r0, r3
800c6d4: f001 f9e6 bl 800daa4 <xTaskRemoveFromEventList>
800c6d8: 4603 mov r3, r0
800c6da: 2b00 cmp r3, #0
800c6dc: d00e beq.n 800c6fc <xQueueGenericSendFromISR+0x120>
{
/* The task waiting has a higher priority so record that a
context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
800c6de: 687b ldr r3, [r7, #4]
800c6e0: 2b00 cmp r3, #0
800c6e2: d00b beq.n 800c6fc <xQueueGenericSendFromISR+0x120>
{
*pxHigherPriorityTaskWoken = pdTRUE;
800c6e4: 687b ldr r3, [r7, #4]
800c6e6: 2201 movs r2, #1
800c6e8: 601a str r2, [r3, #0]
800c6ea: e007 b.n 800c6fc <xQueueGenericSendFromISR+0x120>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
800c6ec: f897 302b ldrb.w r3, [r7, #43] ; 0x2b
800c6f0: 3301 adds r3, #1
800c6f2: b2db uxtb r3, r3
800c6f4: b25a sxtb r2, r3
800c6f6: 6b3b ldr r3, [r7, #48] ; 0x30
800c6f8: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
xReturn = pdPASS;
800c6fc: 2301 movs r3, #1
800c6fe: 637b str r3, [r7, #52] ; 0x34
{
800c700: e001 b.n 800c706 <xQueueGenericSendFromISR+0x12a>
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
800c702: 2300 movs r3, #0
800c704: 637b str r3, [r7, #52] ; 0x34
800c706: 6afb ldr r3, [r7, #44] ; 0x2c
800c708: 613b str r3, [r7, #16]
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
__asm volatile
800c70a: 693b ldr r3, [r7, #16]
800c70c: f383 8811 msr BASEPRI, r3
(
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
);
}
800c710: bf00 nop
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800c712: 6b7b ldr r3, [r7, #52] ; 0x34
}
800c714: 4618 mov r0, r3
800c716: 3738 adds r7, #56 ; 0x38
800c718: 46bd mov sp, r7
800c71a: bd80 pop {r7, pc}
0800c71c <xQueueGiveFromISR>:
/*-----------------------------------------------------------*/
BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
{
800c71c: b580 push {r7, lr}
800c71e: b08e sub sp, #56 ; 0x38
800c720: af00 add r7, sp, #0
800c722: 6078 str r0, [r7, #4]
800c724: 6039 str r1, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
800c726: 687b ldr r3, [r7, #4]
800c728: 633b str r3, [r7, #48] ; 0x30
item size is 0. Don't directly wake a task that was blocked on a queue
read, instead return a flag to say whether a context switch is required or
not (i.e. has a task with a higher priority than us been woken by this
post). */
configASSERT( pxQueue );
800c72a: 6b3b ldr r3, [r7, #48] ; 0x30
800c72c: 2b00 cmp r3, #0
800c72e: d10c bne.n 800c74a <xQueueGiveFromISR+0x2e>
__asm volatile
800c730: f04f 0350 mov.w r3, #80 ; 0x50
800c734: b672 cpsid i
800c736: f383 8811 msr BASEPRI, r3
800c73a: f3bf 8f6f isb sy
800c73e: f3bf 8f4f dsb sy
800c742: b662 cpsie i
800c744: 623b str r3, [r7, #32]
}
800c746: bf00 nop
800c748: e7fe b.n 800c748 <xQueueGiveFromISR+0x2c>
/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
if the item size is not 0. */
configASSERT( pxQueue->uxItemSize == 0 );
800c74a: 6b3b ldr r3, [r7, #48] ; 0x30
800c74c: 6c1b ldr r3, [r3, #64] ; 0x40
800c74e: 2b00 cmp r3, #0
800c750: d00c beq.n 800c76c <xQueueGiveFromISR+0x50>
__asm volatile
800c752: f04f 0350 mov.w r3, #80 ; 0x50
800c756: b672 cpsid i
800c758: f383 8811 msr BASEPRI, r3
800c75c: f3bf 8f6f isb sy
800c760: f3bf 8f4f dsb sy
800c764: b662 cpsie i
800c766: 61fb str r3, [r7, #28]
}
800c768: bf00 nop
800c76a: e7fe b.n 800c76a <xQueueGiveFromISR+0x4e>
/* Normally a mutex would not be given from an interrupt, especially if
there is a mutex holder, as priority inheritance makes no sense for an
interrupts, only tasks. */
configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
800c76c: 6b3b ldr r3, [r7, #48] ; 0x30
800c76e: 681b ldr r3, [r3, #0]
800c770: 2b00 cmp r3, #0
800c772: d103 bne.n 800c77c <xQueueGiveFromISR+0x60>
800c774: 6b3b ldr r3, [r7, #48] ; 0x30
800c776: 689b ldr r3, [r3, #8]
800c778: 2b00 cmp r3, #0
800c77a: d101 bne.n 800c780 <xQueueGiveFromISR+0x64>
800c77c: 2301 movs r3, #1
800c77e: e000 b.n 800c782 <xQueueGiveFromISR+0x66>
800c780: 2300 movs r3, #0
800c782: 2b00 cmp r3, #0
800c784: d10c bne.n 800c7a0 <xQueueGiveFromISR+0x84>
__asm volatile
800c786: f04f 0350 mov.w r3, #80 ; 0x50
800c78a: b672 cpsid i
800c78c: f383 8811 msr BASEPRI, r3
800c790: f3bf 8f6f isb sy
800c794: f3bf 8f4f dsb sy
800c798: b662 cpsie i
800c79a: 61bb str r3, [r7, #24]
}
800c79c: bf00 nop
800c79e: e7fe b.n 800c79e <xQueueGiveFromISR+0x82>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800c7a0: f001 ff7c bl 800e69c <vPortValidateInterruptPriority>
__asm volatile
800c7a4: f3ef 8211 mrs r2, BASEPRI
800c7a8: f04f 0350 mov.w r3, #80 ; 0x50
800c7ac: b672 cpsid i
800c7ae: f383 8811 msr BASEPRI, r3
800c7b2: f3bf 8f6f isb sy
800c7b6: f3bf 8f4f dsb sy
800c7ba: b662 cpsie i
800c7bc: 617a str r2, [r7, #20]
800c7be: 613b str r3, [r7, #16]
return ulOriginalBASEPRI;
800c7c0: 697b ldr r3, [r7, #20]
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
800c7c2: 62fb str r3, [r7, #44] ; 0x2c
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
800c7c4: 6b3b ldr r3, [r7, #48] ; 0x30
800c7c6: 6b9b ldr r3, [r3, #56] ; 0x38
800c7c8: 62bb str r3, [r7, #40] ; 0x28
/* When the queue is used to implement a semaphore no data is ever
moved through the queue but it is still valid to see if the queue 'has
space'. */
if( uxMessagesWaiting < pxQueue->uxLength )
800c7ca: 6b3b ldr r3, [r7, #48] ; 0x30
800c7cc: 6bdb ldr r3, [r3, #60] ; 0x3c
800c7ce: 6aba ldr r2, [r7, #40] ; 0x28
800c7d0: 429a cmp r2, r3
800c7d2: d22b bcs.n 800c82c <xQueueGiveFromISR+0x110>
{
const int8_t cTxLock = pxQueue->cTxLock;
800c7d4: 6b3b ldr r3, [r7, #48] ; 0x30
800c7d6: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800c7da: f887 3027 strb.w r3, [r7, #39] ; 0x27
holder - and if there is a mutex holder then the mutex cannot be
given from an ISR. As this is the ISR version of the function it
can be assumed there is no mutex holder and no need to determine if
priority disinheritance is needed. Simply increase the count of
messages (semaphores) available. */
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
800c7de: 6abb ldr r3, [r7, #40] ; 0x28
800c7e0: 1c5a adds r2, r3, #1
800c7e2: 6b3b ldr r3, [r7, #48] ; 0x30
800c7e4: 639a str r2, [r3, #56] ; 0x38
/* The event list is not altered if the queue is locked. This will
be done when the queue is unlocked later. */
if( cTxLock == queueUNLOCKED )
800c7e6: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
800c7ea: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800c7ee: d112 bne.n 800c816 <xQueueGiveFromISR+0xfa>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800c7f0: 6b3b ldr r3, [r7, #48] ; 0x30
800c7f2: 6a5b ldr r3, [r3, #36] ; 0x24
800c7f4: 2b00 cmp r3, #0
800c7f6: d016 beq.n 800c826 <xQueueGiveFromISR+0x10a>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800c7f8: 6b3b ldr r3, [r7, #48] ; 0x30
800c7fa: 3324 adds r3, #36 ; 0x24
800c7fc: 4618 mov r0, r3
800c7fe: f001 f951 bl 800daa4 <xTaskRemoveFromEventList>
800c802: 4603 mov r3, r0
800c804: 2b00 cmp r3, #0
800c806: d00e beq.n 800c826 <xQueueGiveFromISR+0x10a>
{
/* The task waiting has a higher priority so record that a
context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
800c808: 683b ldr r3, [r7, #0]
800c80a: 2b00 cmp r3, #0
800c80c: d00b beq.n 800c826 <xQueueGiveFromISR+0x10a>
{
*pxHigherPriorityTaskWoken = pdTRUE;
800c80e: 683b ldr r3, [r7, #0]
800c810: 2201 movs r2, #1
800c812: 601a str r2, [r3, #0]
800c814: e007 b.n 800c826 <xQueueGiveFromISR+0x10a>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
800c816: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
800c81a: 3301 adds r3, #1
800c81c: b2db uxtb r3, r3
800c81e: b25a sxtb r2, r3
800c820: 6b3b ldr r3, [r7, #48] ; 0x30
800c822: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
xReturn = pdPASS;
800c826: 2301 movs r3, #1
800c828: 637b str r3, [r7, #52] ; 0x34
800c82a: e001 b.n 800c830 <xQueueGiveFromISR+0x114>
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
800c82c: 2300 movs r3, #0
800c82e: 637b str r3, [r7, #52] ; 0x34
800c830: 6afb ldr r3, [r7, #44] ; 0x2c
800c832: 60fb str r3, [r7, #12]
__asm volatile
800c834: 68fb ldr r3, [r7, #12]
800c836: f383 8811 msr BASEPRI, r3
}
800c83a: bf00 nop
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800c83c: 6b7b ldr r3, [r7, #52] ; 0x34
}
800c83e: 4618 mov r0, r3
800c840: 3738 adds r7, #56 ; 0x38
800c842: 46bd mov sp, r7
800c844: bd80 pop {r7, pc}
...
0800c848 <xQueueReceive>:
/*-----------------------------------------------------------*/
BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
800c848: b580 push {r7, lr}
800c84a: b08c sub sp, #48 ; 0x30
800c84c: af00 add r7, sp, #0
800c84e: 60f8 str r0, [r7, #12]
800c850: 60b9 str r1, [r7, #8]
800c852: 607a str r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
800c854: 2300 movs r3, #0
800c856: 62fb str r3, [r7, #44] ; 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
800c858: 68fb ldr r3, [r7, #12]
800c85a: 62bb str r3, [r7, #40] ; 0x28
/* Check the pointer is not NULL. */
configASSERT( ( pxQueue ) );
800c85c: 6abb ldr r3, [r7, #40] ; 0x28
800c85e: 2b00 cmp r3, #0
800c860: d10c bne.n 800c87c <xQueueReceive+0x34>
__asm volatile
800c862: f04f 0350 mov.w r3, #80 ; 0x50
800c866: b672 cpsid i
800c868: f383 8811 msr BASEPRI, r3
800c86c: f3bf 8f6f isb sy
800c870: f3bf 8f4f dsb sy
800c874: b662 cpsie i
800c876: 623b str r3, [r7, #32]
}
800c878: bf00 nop
800c87a: e7fe b.n 800c87a <xQueueReceive+0x32>
/* The buffer into which data is received can only be NULL if the data size
is zero (so no data is copied into the buffer. */
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
800c87c: 68bb ldr r3, [r7, #8]
800c87e: 2b00 cmp r3, #0
800c880: d103 bne.n 800c88a <xQueueReceive+0x42>
800c882: 6abb ldr r3, [r7, #40] ; 0x28
800c884: 6c1b ldr r3, [r3, #64] ; 0x40
800c886: 2b00 cmp r3, #0
800c888: d101 bne.n 800c88e <xQueueReceive+0x46>
800c88a: 2301 movs r3, #1
800c88c: e000 b.n 800c890 <xQueueReceive+0x48>
800c88e: 2300 movs r3, #0
800c890: 2b00 cmp r3, #0
800c892: d10c bne.n 800c8ae <xQueueReceive+0x66>
__asm volatile
800c894: f04f 0350 mov.w r3, #80 ; 0x50
800c898: b672 cpsid i
800c89a: f383 8811 msr BASEPRI, r3
800c89e: f3bf 8f6f isb sy
800c8a2: f3bf 8f4f dsb sy
800c8a6: b662 cpsie i
800c8a8: 61fb str r3, [r7, #28]
}
800c8aa: bf00 nop
800c8ac: e7fe b.n 800c8ac <xQueueReceive+0x64>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
800c8ae: f001 fabf bl 800de30 <xTaskGetSchedulerState>
800c8b2: 4603 mov r3, r0
800c8b4: 2b00 cmp r3, #0
800c8b6: d102 bne.n 800c8be <xQueueReceive+0x76>
800c8b8: 687b ldr r3, [r7, #4]
800c8ba: 2b00 cmp r3, #0
800c8bc: d101 bne.n 800c8c2 <xQueueReceive+0x7a>
800c8be: 2301 movs r3, #1
800c8c0: e000 b.n 800c8c4 <xQueueReceive+0x7c>
800c8c2: 2300 movs r3, #0
800c8c4: 2b00 cmp r3, #0
800c8c6: d10c bne.n 800c8e2 <xQueueReceive+0x9a>
__asm volatile
800c8c8: f04f 0350 mov.w r3, #80 ; 0x50
800c8cc: b672 cpsid i
800c8ce: f383 8811 msr BASEPRI, r3
800c8d2: f3bf 8f6f isb sy
800c8d6: f3bf 8f4f dsb sy
800c8da: b662 cpsie i
800c8dc: 61bb str r3, [r7, #24]
}
800c8de: bf00 nop
800c8e0: e7fe b.n 800c8e0 <xQueueReceive+0x98>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
800c8e2: f001 fdf3 bl 800e4cc <vPortEnterCritical>
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
800c8e6: 6abb ldr r3, [r7, #40] ; 0x28
800c8e8: 6b9b ldr r3, [r3, #56] ; 0x38
800c8ea: 627b str r3, [r7, #36] ; 0x24
/* Is there data in the queue now? To be running the calling task
must be the highest priority task wanting to access the queue. */
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800c8ec: 6a7b ldr r3, [r7, #36] ; 0x24
800c8ee: 2b00 cmp r3, #0
800c8f0: d01f beq.n 800c932 <xQueueReceive+0xea>
{
/* Data available, remove one item. */
prvCopyDataFromQueue( pxQueue, pvBuffer );
800c8f2: 68b9 ldr r1, [r7, #8]
800c8f4: 6ab8 ldr r0, [r7, #40] ; 0x28
800c8f6: f000 faa9 bl 800ce4c <prvCopyDataFromQueue>
traceQUEUE_RECEIVE( pxQueue );
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
800c8fa: 6a7b ldr r3, [r7, #36] ; 0x24
800c8fc: 1e5a subs r2, r3, #1
800c8fe: 6abb ldr r3, [r7, #40] ; 0x28
800c900: 639a str r2, [r3, #56] ; 0x38
/* There is now space in the queue, were any tasks waiting to
post to the queue? If so, unblock the highest priority waiting
task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800c902: 6abb ldr r3, [r7, #40] ; 0x28
800c904: 691b ldr r3, [r3, #16]
800c906: 2b00 cmp r3, #0
800c908: d00f beq.n 800c92a <xQueueReceive+0xe2>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800c90a: 6abb ldr r3, [r7, #40] ; 0x28
800c90c: 3310 adds r3, #16
800c90e: 4618 mov r0, r3
800c910: f001 f8c8 bl 800daa4 <xTaskRemoveFromEventList>
800c914: 4603 mov r3, r0
800c916: 2b00 cmp r3, #0
800c918: d007 beq.n 800c92a <xQueueReceive+0xe2>
{
queueYIELD_IF_USING_PREEMPTION();
800c91a: 4b3d ldr r3, [pc, #244] ; (800ca10 <xQueueReceive+0x1c8>)
800c91c: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c920: 601a str r2, [r3, #0]
800c922: f3bf 8f4f dsb sy
800c926: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
800c92a: f001 fe03 bl 800e534 <vPortExitCritical>
return pdPASS;
800c92e: 2301 movs r3, #1
800c930: e069 b.n 800ca06 <xQueueReceive+0x1be>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
800c932: 687b ldr r3, [r7, #4]
800c934: 2b00 cmp r3, #0
800c936: d103 bne.n 800c940 <xQueueReceive+0xf8>
{
/* The queue was empty and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
800c938: f001 fdfc bl 800e534 <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800c93c: 2300 movs r3, #0
800c93e: e062 b.n 800ca06 <xQueueReceive+0x1be>
}
else if( xEntryTimeSet == pdFALSE )
800c940: 6afb ldr r3, [r7, #44] ; 0x2c
800c942: 2b00 cmp r3, #0
800c944: d106 bne.n 800c954 <xQueueReceive+0x10c>
{
/* The queue was empty and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
800c946: f107 0310 add.w r3, r7, #16
800c94a: 4618 mov r0, r3
800c94c: f001 f90e bl 800db6c <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
800c950: 2301 movs r3, #1
800c952: 62fb str r3, [r7, #44] ; 0x2c
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
800c954: f001 fdee bl 800e534 <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
800c958: f000 fe74 bl 800d644 <vTaskSuspendAll>
prvLockQueue( pxQueue );
800c95c: f001 fdb6 bl 800e4cc <vPortEnterCritical>
800c960: 6abb ldr r3, [r7, #40] ; 0x28
800c962: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800c966: b25b sxtb r3, r3
800c968: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800c96c: d103 bne.n 800c976 <xQueueReceive+0x12e>
800c96e: 6abb ldr r3, [r7, #40] ; 0x28
800c970: 2200 movs r2, #0
800c972: f883 2044 strb.w r2, [r3, #68] ; 0x44
800c976: 6abb ldr r3, [r7, #40] ; 0x28
800c978: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800c97c: b25b sxtb r3, r3
800c97e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800c982: d103 bne.n 800c98c <xQueueReceive+0x144>
800c984: 6abb ldr r3, [r7, #40] ; 0x28
800c986: 2200 movs r2, #0
800c988: f883 2045 strb.w r2, [r3, #69] ; 0x45
800c98c: f001 fdd2 bl 800e534 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
800c990: 1d3a adds r2, r7, #4
800c992: f107 0310 add.w r3, r7, #16
800c996: 4611 mov r1, r2
800c998: 4618 mov r0, r3
800c99a: f001 f8fd bl 800db98 <xTaskCheckForTimeOut>
800c99e: 4603 mov r3, r0
800c9a0: 2b00 cmp r3, #0
800c9a2: d123 bne.n 800c9ec <xQueueReceive+0x1a4>
{
/* The timeout has not expired. If the queue is still empty place
the task on the list of tasks waiting to receive from the queue. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
800c9a4: 6ab8 ldr r0, [r7, #40] ; 0x28
800c9a6: f000 fac9 bl 800cf3c <prvIsQueueEmpty>
800c9aa: 4603 mov r3, r0
800c9ac: 2b00 cmp r3, #0
800c9ae: d017 beq.n 800c9e0 <xQueueReceive+0x198>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
800c9b0: 6abb ldr r3, [r7, #40] ; 0x28
800c9b2: 3324 adds r3, #36 ; 0x24
800c9b4: 687a ldr r2, [r7, #4]
800c9b6: 4611 mov r1, r2
800c9b8: 4618 mov r0, r3
800c9ba: f001 f84d bl 800da58 <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
800c9be: 6ab8 ldr r0, [r7, #40] ; 0x28
800c9c0: f000 fa6a bl 800ce98 <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
800c9c4: f000 fe4c bl 800d660 <xTaskResumeAll>
800c9c8: 4603 mov r3, r0
800c9ca: 2b00 cmp r3, #0
800c9cc: d189 bne.n 800c8e2 <xQueueReceive+0x9a>
{
portYIELD_WITHIN_API();
800c9ce: 4b10 ldr r3, [pc, #64] ; (800ca10 <xQueueReceive+0x1c8>)
800c9d0: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c9d4: 601a str r2, [r3, #0]
800c9d6: f3bf 8f4f dsb sy
800c9da: f3bf 8f6f isb sy
800c9de: e780 b.n 800c8e2 <xQueueReceive+0x9a>
}
else
{
/* The queue contains data again. Loop back to try and read the
data. */
prvUnlockQueue( pxQueue );
800c9e0: 6ab8 ldr r0, [r7, #40] ; 0x28
800c9e2: f000 fa59 bl 800ce98 <prvUnlockQueue>
( void ) xTaskResumeAll();
800c9e6: f000 fe3b bl 800d660 <xTaskResumeAll>
800c9ea: e77a b.n 800c8e2 <xQueueReceive+0x9a>
}
else
{
/* Timed out. If there is no data in the queue exit, otherwise loop
back and attempt to read the data. */
prvUnlockQueue( pxQueue );
800c9ec: 6ab8 ldr r0, [r7, #40] ; 0x28
800c9ee: f000 fa53 bl 800ce98 <prvUnlockQueue>
( void ) xTaskResumeAll();
800c9f2: f000 fe35 bl 800d660 <xTaskResumeAll>
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
800c9f6: 6ab8 ldr r0, [r7, #40] ; 0x28
800c9f8: f000 faa0 bl 800cf3c <prvIsQueueEmpty>
800c9fc: 4603 mov r3, r0
800c9fe: 2b00 cmp r3, #0
800ca00: f43f af6f beq.w 800c8e2 <xQueueReceive+0x9a>
{
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800ca04: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
800ca06: 4618 mov r0, r3
800ca08: 3730 adds r7, #48 ; 0x30
800ca0a: 46bd mov sp, r7
800ca0c: bd80 pop {r7, pc}
800ca0e: bf00 nop
800ca10: e000ed04 .word 0xe000ed04
0800ca14 <xQueueSemaphoreTake>:
/*-----------------------------------------------------------*/
BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
{
800ca14: b580 push {r7, lr}
800ca16: b08e sub sp, #56 ; 0x38
800ca18: af00 add r7, sp, #0
800ca1a: 6078 str r0, [r7, #4]
800ca1c: 6039 str r1, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE;
800ca1e: 2300 movs r3, #0
800ca20: 637b str r3, [r7, #52] ; 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
800ca22: 687b ldr r3, [r7, #4]
800ca24: 62fb str r3, [r7, #44] ; 0x2c
#if( configUSE_MUTEXES == 1 )
BaseType_t xInheritanceOccurred = pdFALSE;
800ca26: 2300 movs r3, #0
800ca28: 633b str r3, [r7, #48] ; 0x30
#endif
/* Check the queue pointer is not NULL. */
configASSERT( ( pxQueue ) );
800ca2a: 6afb ldr r3, [r7, #44] ; 0x2c
800ca2c: 2b00 cmp r3, #0
800ca2e: d10c bne.n 800ca4a <xQueueSemaphoreTake+0x36>
__asm volatile
800ca30: f04f 0350 mov.w r3, #80 ; 0x50
800ca34: b672 cpsid i
800ca36: f383 8811 msr BASEPRI, r3
800ca3a: f3bf 8f6f isb sy
800ca3e: f3bf 8f4f dsb sy
800ca42: b662 cpsie i
800ca44: 623b str r3, [r7, #32]
}
800ca46: bf00 nop
800ca48: e7fe b.n 800ca48 <xQueueSemaphoreTake+0x34>
/* Check this really is a semaphore, in which case the item size will be
0. */
configASSERT( pxQueue->uxItemSize == 0 );
800ca4a: 6afb ldr r3, [r7, #44] ; 0x2c
800ca4c: 6c1b ldr r3, [r3, #64] ; 0x40
800ca4e: 2b00 cmp r3, #0
800ca50: d00c beq.n 800ca6c <xQueueSemaphoreTake+0x58>
__asm volatile
800ca52: f04f 0350 mov.w r3, #80 ; 0x50
800ca56: b672 cpsid i
800ca58: f383 8811 msr BASEPRI, r3
800ca5c: f3bf 8f6f isb sy
800ca60: f3bf 8f4f dsb sy
800ca64: b662 cpsie i
800ca66: 61fb str r3, [r7, #28]
}
800ca68: bf00 nop
800ca6a: e7fe b.n 800ca6a <xQueueSemaphoreTake+0x56>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
800ca6c: f001 f9e0 bl 800de30 <xTaskGetSchedulerState>
800ca70: 4603 mov r3, r0
800ca72: 2b00 cmp r3, #0
800ca74: d102 bne.n 800ca7c <xQueueSemaphoreTake+0x68>
800ca76: 683b ldr r3, [r7, #0]
800ca78: 2b00 cmp r3, #0
800ca7a: d101 bne.n 800ca80 <xQueueSemaphoreTake+0x6c>
800ca7c: 2301 movs r3, #1
800ca7e: e000 b.n 800ca82 <xQueueSemaphoreTake+0x6e>
800ca80: 2300 movs r3, #0
800ca82: 2b00 cmp r3, #0
800ca84: d10c bne.n 800caa0 <xQueueSemaphoreTake+0x8c>
__asm volatile
800ca86: f04f 0350 mov.w r3, #80 ; 0x50
800ca8a: b672 cpsid i
800ca8c: f383 8811 msr BASEPRI, r3
800ca90: f3bf 8f6f isb sy
800ca94: f3bf 8f4f dsb sy
800ca98: b662 cpsie i
800ca9a: 61bb str r3, [r7, #24]
}
800ca9c: bf00 nop
800ca9e: e7fe b.n 800ca9e <xQueueSemaphoreTake+0x8a>
/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
statements within the function itself. This is done in the interest
of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
800caa0: f001 fd14 bl 800e4cc <vPortEnterCritical>
{
/* Semaphores are queues with an item size of 0, and where the
number of messages in the queue is the semaphore's count value. */
const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
800caa4: 6afb ldr r3, [r7, #44] ; 0x2c
800caa6: 6b9b ldr r3, [r3, #56] ; 0x38
800caa8: 62bb str r3, [r7, #40] ; 0x28
/* Is there data in the queue now? To be running the calling task
must be the highest priority task wanting to access the queue. */
if( uxSemaphoreCount > ( UBaseType_t ) 0 )
800caaa: 6abb ldr r3, [r7, #40] ; 0x28
800caac: 2b00 cmp r3, #0
800caae: d024 beq.n 800cafa <xQueueSemaphoreTake+0xe6>
{
traceQUEUE_RECEIVE( pxQueue );
/* Semaphores are queues with a data size of zero and where the
messages waiting is the semaphore's count. Reduce the count. */
pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
800cab0: 6abb ldr r3, [r7, #40] ; 0x28
800cab2: 1e5a subs r2, r3, #1
800cab4: 6afb ldr r3, [r7, #44] ; 0x2c
800cab6: 639a str r2, [r3, #56] ; 0x38
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
800cab8: 6afb ldr r3, [r7, #44] ; 0x2c
800caba: 681b ldr r3, [r3, #0]
800cabc: 2b00 cmp r3, #0
800cabe: d104 bne.n 800caca <xQueueSemaphoreTake+0xb6>
{
/* Record the information required to implement
priority inheritance should it become necessary. */
pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
800cac0: f001 fb7c bl 800e1bc <pvTaskIncrementMutexHeldCount>
800cac4: 4602 mov r2, r0
800cac6: 6afb ldr r3, [r7, #44] ; 0x2c
800cac8: 609a str r2, [r3, #8]
}
#endif /* configUSE_MUTEXES */
/* Check to see if other tasks are blocked waiting to give the
semaphore, and if so, unblock the highest priority such task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800caca: 6afb ldr r3, [r7, #44] ; 0x2c
800cacc: 691b ldr r3, [r3, #16]
800cace: 2b00 cmp r3, #0
800cad0: d00f beq.n 800caf2 <xQueueSemaphoreTake+0xde>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800cad2: 6afb ldr r3, [r7, #44] ; 0x2c
800cad4: 3310 adds r3, #16
800cad6: 4618 mov r0, r3
800cad8: f000 ffe4 bl 800daa4 <xTaskRemoveFromEventList>
800cadc: 4603 mov r3, r0
800cade: 2b00 cmp r3, #0
800cae0: d007 beq.n 800caf2 <xQueueSemaphoreTake+0xde>
{
queueYIELD_IF_USING_PREEMPTION();
800cae2: 4b55 ldr r3, [pc, #340] ; (800cc38 <xQueueSemaphoreTake+0x224>)
800cae4: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800cae8: 601a str r2, [r3, #0]
800caea: f3bf 8f4f dsb sy
800caee: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
800caf2: f001 fd1f bl 800e534 <vPortExitCritical>
return pdPASS;
800caf6: 2301 movs r3, #1
800caf8: e099 b.n 800cc2e <xQueueSemaphoreTake+0x21a>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
800cafa: 683b ldr r3, [r7, #0]
800cafc: 2b00 cmp r3, #0
800cafe: d113 bne.n 800cb28 <xQueueSemaphoreTake+0x114>
/* For inheritance to have occurred there must have been an
initial timeout, and an adjusted timeout cannot become 0, as
if it were 0 the function would have exited. */
#if( configUSE_MUTEXES == 1 )
{
configASSERT( xInheritanceOccurred == pdFALSE );
800cb00: 6b3b ldr r3, [r7, #48] ; 0x30
800cb02: 2b00 cmp r3, #0
800cb04: d00c beq.n 800cb20 <xQueueSemaphoreTake+0x10c>
__asm volatile
800cb06: f04f 0350 mov.w r3, #80 ; 0x50
800cb0a: b672 cpsid i
800cb0c: f383 8811 msr BASEPRI, r3
800cb10: f3bf 8f6f isb sy
800cb14: f3bf 8f4f dsb sy
800cb18: b662 cpsie i
800cb1a: 617b str r3, [r7, #20]
}
800cb1c: bf00 nop
800cb1e: e7fe b.n 800cb1e <xQueueSemaphoreTake+0x10a>
}
#endif /* configUSE_MUTEXES */
/* The semaphore count was 0 and no block time is specified
(or the block time has expired) so exit now. */
taskEXIT_CRITICAL();
800cb20: f001 fd08 bl 800e534 <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800cb24: 2300 movs r3, #0
800cb26: e082 b.n 800cc2e <xQueueSemaphoreTake+0x21a>
}
else if( xEntryTimeSet == pdFALSE )
800cb28: 6b7b ldr r3, [r7, #52] ; 0x34
800cb2a: 2b00 cmp r3, #0
800cb2c: d106 bne.n 800cb3c <xQueueSemaphoreTake+0x128>
{
/* The semaphore count was 0 and a block time was specified
so configure the timeout structure ready to block. */
vTaskInternalSetTimeOutState( &xTimeOut );
800cb2e: f107 030c add.w r3, r7, #12
800cb32: 4618 mov r0, r3
800cb34: f001 f81a bl 800db6c <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
800cb38: 2301 movs r3, #1
800cb3a: 637b str r3, [r7, #52] ; 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
800cb3c: f001 fcfa bl 800e534 <vPortExitCritical>
/* Interrupts and other tasks can give to and take from the semaphore
now the critical section has been exited. */
vTaskSuspendAll();
800cb40: f000 fd80 bl 800d644 <vTaskSuspendAll>
prvLockQueue( pxQueue );
800cb44: f001 fcc2 bl 800e4cc <vPortEnterCritical>
800cb48: 6afb ldr r3, [r7, #44] ; 0x2c
800cb4a: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800cb4e: b25b sxtb r3, r3
800cb50: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800cb54: d103 bne.n 800cb5e <xQueueSemaphoreTake+0x14a>
800cb56: 6afb ldr r3, [r7, #44] ; 0x2c
800cb58: 2200 movs r2, #0
800cb5a: f883 2044 strb.w r2, [r3, #68] ; 0x44
800cb5e: 6afb ldr r3, [r7, #44] ; 0x2c
800cb60: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800cb64: b25b sxtb r3, r3
800cb66: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800cb6a: d103 bne.n 800cb74 <xQueueSemaphoreTake+0x160>
800cb6c: 6afb ldr r3, [r7, #44] ; 0x2c
800cb6e: 2200 movs r2, #0
800cb70: f883 2045 strb.w r2, [r3, #69] ; 0x45
800cb74: f001 fcde bl 800e534 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
800cb78: 463a mov r2, r7
800cb7a: f107 030c add.w r3, r7, #12
800cb7e: 4611 mov r1, r2
800cb80: 4618 mov r0, r3
800cb82: f001 f809 bl 800db98 <xTaskCheckForTimeOut>
800cb86: 4603 mov r3, r0
800cb88: 2b00 cmp r3, #0
800cb8a: d132 bne.n 800cbf2 <xQueueSemaphoreTake+0x1de>
{
/* A block time is specified and not expired. If the semaphore
count is 0 then enter the Blocked state to wait for a semaphore to
become available. As semaphores are implemented with queues the
queue being empty is equivalent to the semaphore count being 0. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
800cb8c: 6af8 ldr r0, [r7, #44] ; 0x2c
800cb8e: f000 f9d5 bl 800cf3c <prvIsQueueEmpty>
800cb92: 4603 mov r3, r0
800cb94: 2b00 cmp r3, #0
800cb96: d026 beq.n 800cbe6 <xQueueSemaphoreTake+0x1d2>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
800cb98: 6afb ldr r3, [r7, #44] ; 0x2c
800cb9a: 681b ldr r3, [r3, #0]
800cb9c: 2b00 cmp r3, #0
800cb9e: d109 bne.n 800cbb4 <xQueueSemaphoreTake+0x1a0>
{
taskENTER_CRITICAL();
800cba0: f001 fc94 bl 800e4cc <vPortEnterCritical>
{
xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
800cba4: 6afb ldr r3, [r7, #44] ; 0x2c
800cba6: 689b ldr r3, [r3, #8]
800cba8: 4618 mov r0, r3
800cbaa: f001 f95f bl 800de6c <xTaskPriorityInherit>
800cbae: 6338 str r0, [r7, #48] ; 0x30
}
taskEXIT_CRITICAL();
800cbb0: f001 fcc0 bl 800e534 <vPortExitCritical>
mtCOVERAGE_TEST_MARKER();
}
}
#endif
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
800cbb4: 6afb ldr r3, [r7, #44] ; 0x2c
800cbb6: 3324 adds r3, #36 ; 0x24
800cbb8: 683a ldr r2, [r7, #0]
800cbba: 4611 mov r1, r2
800cbbc: 4618 mov r0, r3
800cbbe: f000 ff4b bl 800da58 <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
800cbc2: 6af8 ldr r0, [r7, #44] ; 0x2c
800cbc4: f000 f968 bl 800ce98 <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
800cbc8: f000 fd4a bl 800d660 <xTaskResumeAll>
800cbcc: 4603 mov r3, r0
800cbce: 2b00 cmp r3, #0
800cbd0: f47f af66 bne.w 800caa0 <xQueueSemaphoreTake+0x8c>
{
portYIELD_WITHIN_API();
800cbd4: 4b18 ldr r3, [pc, #96] ; (800cc38 <xQueueSemaphoreTake+0x224>)
800cbd6: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800cbda: 601a str r2, [r3, #0]
800cbdc: f3bf 8f4f dsb sy
800cbe0: f3bf 8f6f isb sy
800cbe4: e75c b.n 800caa0 <xQueueSemaphoreTake+0x8c>
}
else
{
/* There was no timeout and the semaphore count was not 0, so
attempt to take the semaphore again. */
prvUnlockQueue( pxQueue );
800cbe6: 6af8 ldr r0, [r7, #44] ; 0x2c
800cbe8: f000 f956 bl 800ce98 <prvUnlockQueue>
( void ) xTaskResumeAll();
800cbec: f000 fd38 bl 800d660 <xTaskResumeAll>
800cbf0: e756 b.n 800caa0 <xQueueSemaphoreTake+0x8c>
}
}
else
{
/* Timed out. */
prvUnlockQueue( pxQueue );
800cbf2: 6af8 ldr r0, [r7, #44] ; 0x2c
800cbf4: f000 f950 bl 800ce98 <prvUnlockQueue>
( void ) xTaskResumeAll();
800cbf8: f000 fd32 bl 800d660 <xTaskResumeAll>
/* If the semaphore count is 0 exit now as the timeout has
expired. Otherwise return to attempt to take the semaphore that is
known to be available. As semaphores are implemented by queues the
queue being empty is equivalent to the semaphore count being 0. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
800cbfc: 6af8 ldr r0, [r7, #44] ; 0x2c
800cbfe: f000 f99d bl 800cf3c <prvIsQueueEmpty>
800cc02: 4603 mov r3, r0
800cc04: 2b00 cmp r3, #0
800cc06: f43f af4b beq.w 800caa0 <xQueueSemaphoreTake+0x8c>
#if ( configUSE_MUTEXES == 1 )
{
/* xInheritanceOccurred could only have be set if
pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
test the mutex type again to check it is actually a mutex. */
if( xInheritanceOccurred != pdFALSE )
800cc0a: 6b3b ldr r3, [r7, #48] ; 0x30
800cc0c: 2b00 cmp r3, #0
800cc0e: d00d beq.n 800cc2c <xQueueSemaphoreTake+0x218>
{
taskENTER_CRITICAL();
800cc10: f001 fc5c bl 800e4cc <vPortEnterCritical>
/* This task blocking on the mutex caused another
task to inherit this task's priority. Now this task
has timed out the priority should be disinherited
again, but only as low as the next highest priority
task that is waiting for the same mutex. */
uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
800cc14: 6af8 ldr r0, [r7, #44] ; 0x2c
800cc16: f000 f897 bl 800cd48 <prvGetDisinheritPriorityAfterTimeout>
800cc1a: 6278 str r0, [r7, #36] ; 0x24
vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
800cc1c: 6afb ldr r3, [r7, #44] ; 0x2c
800cc1e: 689b ldr r3, [r3, #8]
800cc20: 6a79 ldr r1, [r7, #36] ; 0x24
800cc22: 4618 mov r0, r3
800cc24: f001 fa2c bl 800e080 <vTaskPriorityDisinheritAfterTimeout>
}
taskEXIT_CRITICAL();
800cc28: f001 fc84 bl 800e534 <vPortExitCritical>
}
}
#endif /* configUSE_MUTEXES */
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800cc2c: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
800cc2e: 4618 mov r0, r3
800cc30: 3738 adds r7, #56 ; 0x38
800cc32: 46bd mov sp, r7
800cc34: bd80 pop {r7, pc}
800cc36: bf00 nop
800cc38: e000ed04 .word 0xe000ed04
0800cc3c <xQueueReceiveFromISR>:
} /*lint -restore */
}
/*-----------------------------------------------------------*/
BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
{
800cc3c: b580 push {r7, lr}
800cc3e: b08e sub sp, #56 ; 0x38
800cc40: af00 add r7, sp, #0
800cc42: 60f8 str r0, [r7, #12]
800cc44: 60b9 str r1, [r7, #8]
800cc46: 607a str r2, [r7, #4]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
800cc48: 68fb ldr r3, [r7, #12]
800cc4a: 633b str r3, [r7, #48] ; 0x30
configASSERT( pxQueue );
800cc4c: 6b3b ldr r3, [r7, #48] ; 0x30
800cc4e: 2b00 cmp r3, #0
800cc50: d10c bne.n 800cc6c <xQueueReceiveFromISR+0x30>
__asm volatile
800cc52: f04f 0350 mov.w r3, #80 ; 0x50
800cc56: b672 cpsid i
800cc58: f383 8811 msr BASEPRI, r3
800cc5c: f3bf 8f6f isb sy
800cc60: f3bf 8f4f dsb sy
800cc64: b662 cpsie i
800cc66: 623b str r3, [r7, #32]
}
800cc68: bf00 nop
800cc6a: e7fe b.n 800cc6a <xQueueReceiveFromISR+0x2e>
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
800cc6c: 68bb ldr r3, [r7, #8]
800cc6e: 2b00 cmp r3, #0
800cc70: d103 bne.n 800cc7a <xQueueReceiveFromISR+0x3e>
800cc72: 6b3b ldr r3, [r7, #48] ; 0x30
800cc74: 6c1b ldr r3, [r3, #64] ; 0x40
800cc76: 2b00 cmp r3, #0
800cc78: d101 bne.n 800cc7e <xQueueReceiveFromISR+0x42>
800cc7a: 2301 movs r3, #1
800cc7c: e000 b.n 800cc80 <xQueueReceiveFromISR+0x44>
800cc7e: 2300 movs r3, #0
800cc80: 2b00 cmp r3, #0
800cc82: d10c bne.n 800cc9e <xQueueReceiveFromISR+0x62>
__asm volatile
800cc84: f04f 0350 mov.w r3, #80 ; 0x50
800cc88: b672 cpsid i
800cc8a: f383 8811 msr BASEPRI, r3
800cc8e: f3bf 8f6f isb sy
800cc92: f3bf 8f4f dsb sy
800cc96: b662 cpsie i
800cc98: 61fb str r3, [r7, #28]
}
800cc9a: bf00 nop
800cc9c: e7fe b.n 800cc9c <xQueueReceiveFromISR+0x60>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800cc9e: f001 fcfd bl 800e69c <vPortValidateInterruptPriority>
__asm volatile
800cca2: f3ef 8211 mrs r2, BASEPRI
800cca6: f04f 0350 mov.w r3, #80 ; 0x50
800ccaa: b672 cpsid i
800ccac: f383 8811 msr BASEPRI, r3
800ccb0: f3bf 8f6f isb sy
800ccb4: f3bf 8f4f dsb sy
800ccb8: b662 cpsie i
800ccba: 61ba str r2, [r7, #24]
800ccbc: 617b str r3, [r7, #20]
return ulOriginalBASEPRI;
800ccbe: 69bb ldr r3, [r7, #24]
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
800ccc0: 62fb str r3, [r7, #44] ; 0x2c
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
800ccc2: 6b3b ldr r3, [r7, #48] ; 0x30
800ccc4: 6b9b ldr r3, [r3, #56] ; 0x38
800ccc6: 62bb str r3, [r7, #40] ; 0x28
/* Cannot block in an ISR, so check there is data available. */
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800ccc8: 6abb ldr r3, [r7, #40] ; 0x28
800ccca: 2b00 cmp r3, #0
800cccc: d02f beq.n 800cd2e <xQueueReceiveFromISR+0xf2>
{
const int8_t cRxLock = pxQueue->cRxLock;
800ccce: 6b3b ldr r3, [r7, #48] ; 0x30
800ccd0: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800ccd4: f887 3027 strb.w r3, [r7, #39] ; 0x27
traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
prvCopyDataFromQueue( pxQueue, pvBuffer );
800ccd8: 68b9 ldr r1, [r7, #8]
800ccda: 6b38 ldr r0, [r7, #48] ; 0x30
800ccdc: f000 f8b6 bl 800ce4c <prvCopyDataFromQueue>
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
800cce0: 6abb ldr r3, [r7, #40] ; 0x28
800cce2: 1e5a subs r2, r3, #1
800cce4: 6b3b ldr r3, [r7, #48] ; 0x30
800cce6: 639a str r2, [r3, #56] ; 0x38
/* If the queue is locked the event list will not be modified.
Instead update the lock count so the task that unlocks the queue
will know that an ISR has removed data while the queue was
locked. */
if( cRxLock == queueUNLOCKED )
800cce8: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
800ccec: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800ccf0: d112 bne.n 800cd18 <xQueueReceiveFromISR+0xdc>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800ccf2: 6b3b ldr r3, [r7, #48] ; 0x30
800ccf4: 691b ldr r3, [r3, #16]
800ccf6: 2b00 cmp r3, #0
800ccf8: d016 beq.n 800cd28 <xQueueReceiveFromISR+0xec>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800ccfa: 6b3b ldr r3, [r7, #48] ; 0x30
800ccfc: 3310 adds r3, #16
800ccfe: 4618 mov r0, r3
800cd00: f000 fed0 bl 800daa4 <xTaskRemoveFromEventList>
800cd04: 4603 mov r3, r0
800cd06: 2b00 cmp r3, #0
800cd08: d00e beq.n 800cd28 <xQueueReceiveFromISR+0xec>
{
/* The task waiting has a higher priority than us so
force a context switch. */
if( pxHigherPriorityTaskWoken != NULL )
800cd0a: 687b ldr r3, [r7, #4]
800cd0c: 2b00 cmp r3, #0
800cd0e: d00b beq.n 800cd28 <xQueueReceiveFromISR+0xec>
{
*pxHigherPriorityTaskWoken = pdTRUE;
800cd10: 687b ldr r3, [r7, #4]
800cd12: 2201 movs r2, #1
800cd14: 601a str r2, [r3, #0]
800cd16: e007 b.n 800cd28 <xQueueReceiveFromISR+0xec>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was removed while it was locked. */
pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
800cd18: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
800cd1c: 3301 adds r3, #1
800cd1e: b2db uxtb r3, r3
800cd20: b25a sxtb r2, r3
800cd22: 6b3b ldr r3, [r7, #48] ; 0x30
800cd24: f883 2044 strb.w r2, [r3, #68] ; 0x44
}
xReturn = pdPASS;
800cd28: 2301 movs r3, #1
800cd2a: 637b str r3, [r7, #52] ; 0x34
800cd2c: e001 b.n 800cd32 <xQueueReceiveFromISR+0xf6>
}
else
{
xReturn = pdFAIL;
800cd2e: 2300 movs r3, #0
800cd30: 637b str r3, [r7, #52] ; 0x34
800cd32: 6afb ldr r3, [r7, #44] ; 0x2c
800cd34: 613b str r3, [r7, #16]
__asm volatile
800cd36: 693b ldr r3, [r7, #16]
800cd38: f383 8811 msr BASEPRI, r3
}
800cd3c: bf00 nop
traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800cd3e: 6b7b ldr r3, [r7, #52] ; 0x34
}
800cd40: 4618 mov r0, r3
800cd42: 3738 adds r7, #56 ; 0x38
800cd44: 46bd mov sp, r7
800cd46: bd80 pop {r7, pc}
0800cd48 <prvGetDisinheritPriorityAfterTimeout>:
/*-----------------------------------------------------------*/
#if( configUSE_MUTEXES == 1 )
static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
{
800cd48: b480 push {r7}
800cd4a: b085 sub sp, #20
800cd4c: af00 add r7, sp, #0
800cd4e: 6078 str r0, [r7, #4]
priority, but the waiting task times out, then the holder should
disinherit the priority - but only down to the highest priority of any
other tasks that are waiting for the same mutex. For this purpose,
return the priority of the highest priority task that is waiting for the
mutex. */
if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
800cd50: 687b ldr r3, [r7, #4]
800cd52: 6a5b ldr r3, [r3, #36] ; 0x24
800cd54: 2b00 cmp r3, #0
800cd56: d006 beq.n 800cd66 <prvGetDisinheritPriorityAfterTimeout+0x1e>
{
uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
800cd58: 687b ldr r3, [r7, #4]
800cd5a: 6b1b ldr r3, [r3, #48] ; 0x30
800cd5c: 681b ldr r3, [r3, #0]
800cd5e: f1c3 0307 rsb r3, r3, #7
800cd62: 60fb str r3, [r7, #12]
800cd64: e001 b.n 800cd6a <prvGetDisinheritPriorityAfterTimeout+0x22>
}
else
{
uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
800cd66: 2300 movs r3, #0
800cd68: 60fb str r3, [r7, #12]
}
return uxHighestPriorityOfWaitingTasks;
800cd6a: 68fb ldr r3, [r7, #12]
}
800cd6c: 4618 mov r0, r3
800cd6e: 3714 adds r7, #20
800cd70: 46bd mov sp, r7
800cd72: f85d 7b04 ldr.w r7, [sp], #4
800cd76: 4770 bx lr
0800cd78 <prvCopyDataToQueue>:
#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
800cd78: b580 push {r7, lr}
800cd7a: b086 sub sp, #24
800cd7c: af00 add r7, sp, #0
800cd7e: 60f8 str r0, [r7, #12]
800cd80: 60b9 str r1, [r7, #8]
800cd82: 607a str r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
800cd84: 2300 movs r3, #0
800cd86: 617b str r3, [r7, #20]
UBaseType_t uxMessagesWaiting;
/* This function is called from a critical section. */
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
800cd88: 68fb ldr r3, [r7, #12]
800cd8a: 6b9b ldr r3, [r3, #56] ; 0x38
800cd8c: 613b str r3, [r7, #16]
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
800cd8e: 68fb ldr r3, [r7, #12]
800cd90: 6c1b ldr r3, [r3, #64] ; 0x40
800cd92: 2b00 cmp r3, #0
800cd94: d10d bne.n 800cdb2 <prvCopyDataToQueue+0x3a>
{
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
800cd96: 68fb ldr r3, [r7, #12]
800cd98: 681b ldr r3, [r3, #0]
800cd9a: 2b00 cmp r3, #0
800cd9c: d14d bne.n 800ce3a <prvCopyDataToQueue+0xc2>
{
/* The mutex is no longer being held. */
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
800cd9e: 68fb ldr r3, [r7, #12]
800cda0: 689b ldr r3, [r3, #8]
800cda2: 4618 mov r0, r3
800cda4: f001 f8e2 bl 800df6c <xTaskPriorityDisinherit>
800cda8: 6178 str r0, [r7, #20]
pxQueue->u.xSemaphore.xMutexHolder = NULL;
800cdaa: 68fb ldr r3, [r7, #12]
800cdac: 2200 movs r2, #0
800cdae: 609a str r2, [r3, #8]
800cdb0: e043 b.n 800ce3a <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_MUTEXES */
}
else if( xPosition == queueSEND_TO_BACK )
800cdb2: 687b ldr r3, [r7, #4]
800cdb4: 2b00 cmp r3, #0
800cdb6: d119 bne.n 800cdec <prvCopyDataToQueue+0x74>
{
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
800cdb8: 68fb ldr r3, [r7, #12]
800cdba: 6858 ldr r0, [r3, #4]
800cdbc: 68fb ldr r3, [r7, #12]
800cdbe: 6c1b ldr r3, [r3, #64] ; 0x40
800cdc0: 461a mov r2, r3
800cdc2: 68b9 ldr r1, [r7, #8]
800cdc4: f00e f8e8 bl 801af98 <memcpy>
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
800cdc8: 68fb ldr r3, [r7, #12]
800cdca: 685a ldr r2, [r3, #4]
800cdcc: 68fb ldr r3, [r7, #12]
800cdce: 6c1b ldr r3, [r3, #64] ; 0x40
800cdd0: 441a add r2, r3
800cdd2: 68fb ldr r3, [r7, #12]
800cdd4: 605a str r2, [r3, #4]
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
800cdd6: 68fb ldr r3, [r7, #12]
800cdd8: 685a ldr r2, [r3, #4]
800cdda: 68fb ldr r3, [r7, #12]
800cddc: 689b ldr r3, [r3, #8]
800cdde: 429a cmp r2, r3
800cde0: d32b bcc.n 800ce3a <prvCopyDataToQueue+0xc2>
{
pxQueue->pcWriteTo = pxQueue->pcHead;
800cde2: 68fb ldr r3, [r7, #12]
800cde4: 681a ldr r2, [r3, #0]
800cde6: 68fb ldr r3, [r7, #12]
800cde8: 605a str r2, [r3, #4]
800cdea: e026 b.n 800ce3a <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
800cdec: 68fb ldr r3, [r7, #12]
800cdee: 68d8 ldr r0, [r3, #12]
800cdf0: 68fb ldr r3, [r7, #12]
800cdf2: 6c1b ldr r3, [r3, #64] ; 0x40
800cdf4: 461a mov r2, r3
800cdf6: 68b9 ldr r1, [r7, #8]
800cdf8: f00e f8ce bl 801af98 <memcpy>
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
800cdfc: 68fb ldr r3, [r7, #12]
800cdfe: 68da ldr r2, [r3, #12]
800ce00: 68fb ldr r3, [r7, #12]
800ce02: 6c1b ldr r3, [r3, #64] ; 0x40
800ce04: 425b negs r3, r3
800ce06: 441a add r2, r3
800ce08: 68fb ldr r3, [r7, #12]
800ce0a: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
800ce0c: 68fb ldr r3, [r7, #12]
800ce0e: 68da ldr r2, [r3, #12]
800ce10: 68fb ldr r3, [r7, #12]
800ce12: 681b ldr r3, [r3, #0]
800ce14: 429a cmp r2, r3
800ce16: d207 bcs.n 800ce28 <prvCopyDataToQueue+0xb0>
{
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
800ce18: 68fb ldr r3, [r7, #12]
800ce1a: 689a ldr r2, [r3, #8]
800ce1c: 68fb ldr r3, [r7, #12]
800ce1e: 6c1b ldr r3, [r3, #64] ; 0x40
800ce20: 425b negs r3, r3
800ce22: 441a add r2, r3
800ce24: 68fb ldr r3, [r7, #12]
800ce26: 60da str r2, [r3, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
if( xPosition == queueOVERWRITE )
800ce28: 687b ldr r3, [r7, #4]
800ce2a: 2b02 cmp r3, #2
800ce2c: d105 bne.n 800ce3a <prvCopyDataToQueue+0xc2>
{
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800ce2e: 693b ldr r3, [r7, #16]
800ce30: 2b00 cmp r3, #0
800ce32: d002 beq.n 800ce3a <prvCopyDataToQueue+0xc2>
{
/* An item is not being added but overwritten, so subtract
one from the recorded number of items in the queue so when
one is added again below the number of recorded items remains
correct. */
--uxMessagesWaiting;
800ce34: 693b ldr r3, [r7, #16]
800ce36: 3b01 subs r3, #1
800ce38: 613b str r3, [r7, #16]
{
mtCOVERAGE_TEST_MARKER();
}
}
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
800ce3a: 693b ldr r3, [r7, #16]
800ce3c: 1c5a adds r2, r3, #1
800ce3e: 68fb ldr r3, [r7, #12]
800ce40: 639a str r2, [r3, #56] ; 0x38
return xReturn;
800ce42: 697b ldr r3, [r7, #20]
}
800ce44: 4618 mov r0, r3
800ce46: 3718 adds r7, #24
800ce48: 46bd mov sp, r7
800ce4a: bd80 pop {r7, pc}
0800ce4c <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/
static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
800ce4c: b580 push {r7, lr}
800ce4e: b082 sub sp, #8
800ce50: af00 add r7, sp, #0
800ce52: 6078 str r0, [r7, #4]
800ce54: 6039 str r1, [r7, #0]
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
800ce56: 687b ldr r3, [r7, #4]
800ce58: 6c1b ldr r3, [r3, #64] ; 0x40
800ce5a: 2b00 cmp r3, #0
800ce5c: d018 beq.n 800ce90 <prvCopyDataFromQueue+0x44>
{
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
800ce5e: 687b ldr r3, [r7, #4]
800ce60: 68da ldr r2, [r3, #12]
800ce62: 687b ldr r3, [r7, #4]
800ce64: 6c1b ldr r3, [r3, #64] ; 0x40
800ce66: 441a add r2, r3
800ce68: 687b ldr r3, [r7, #4]
800ce6a: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
800ce6c: 687b ldr r3, [r7, #4]
800ce6e: 68da ldr r2, [r3, #12]
800ce70: 687b ldr r3, [r7, #4]
800ce72: 689b ldr r3, [r3, #8]
800ce74: 429a cmp r2, r3
800ce76: d303 bcc.n 800ce80 <prvCopyDataFromQueue+0x34>
{
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
800ce78: 687b ldr r3, [r7, #4]
800ce7a: 681a ldr r2, [r3, #0]
800ce7c: 687b ldr r3, [r7, #4]
800ce7e: 60da str r2, [r3, #12]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
800ce80: 687b ldr r3, [r7, #4]
800ce82: 68d9 ldr r1, [r3, #12]
800ce84: 687b ldr r3, [r7, #4]
800ce86: 6c1b ldr r3, [r3, #64] ; 0x40
800ce88: 461a mov r2, r3
800ce8a: 6838 ldr r0, [r7, #0]
800ce8c: f00e f884 bl 801af98 <memcpy>
}
}
800ce90: bf00 nop
800ce92: 3708 adds r7, #8
800ce94: 46bd mov sp, r7
800ce96: bd80 pop {r7, pc}
0800ce98 <prvUnlockQueue>:
/*-----------------------------------------------------------*/
static void prvUnlockQueue( Queue_t * const pxQueue )
{
800ce98: b580 push {r7, lr}
800ce9a: b084 sub sp, #16
800ce9c: af00 add r7, sp, #0
800ce9e: 6078 str r0, [r7, #4]
/* The lock counts contains the number of extra data items placed or
removed from the queue while the queue was locked. When a queue is
locked items can be added or removed, but the event lists cannot be
updated. */
taskENTER_CRITICAL();
800cea0: f001 fb14 bl 800e4cc <vPortEnterCritical>
{
int8_t cTxLock = pxQueue->cTxLock;
800cea4: 687b ldr r3, [r7, #4]
800cea6: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800ceaa: 73fb strb r3, [r7, #15]
/* See if data was added to the queue while it was locked. */
while( cTxLock > queueLOCKED_UNMODIFIED )
800ceac: e011 b.n 800ced2 <prvUnlockQueue+0x3a>
}
#else /* configUSE_QUEUE_SETS */
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800ceae: 687b ldr r3, [r7, #4]
800ceb0: 6a5b ldr r3, [r3, #36] ; 0x24
800ceb2: 2b00 cmp r3, #0
800ceb4: d012 beq.n 800cedc <prvUnlockQueue+0x44>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800ceb6: 687b ldr r3, [r7, #4]
800ceb8: 3324 adds r3, #36 ; 0x24
800ceba: 4618 mov r0, r3
800cebc: f000 fdf2 bl 800daa4 <xTaskRemoveFromEventList>
800cec0: 4603 mov r3, r0
800cec2: 2b00 cmp r3, #0
800cec4: d001 beq.n 800ceca <prvUnlockQueue+0x32>
{
/* The task waiting has a higher priority so record that
a context switch is required. */
vTaskMissedYield();
800cec6: f000 fecd bl 800dc64 <vTaskMissedYield>
break;
}
}
#endif /* configUSE_QUEUE_SETS */
--cTxLock;
800ceca: 7bfb ldrb r3, [r7, #15]
800cecc: 3b01 subs r3, #1
800cece: b2db uxtb r3, r3
800ced0: 73fb strb r3, [r7, #15]
while( cTxLock > queueLOCKED_UNMODIFIED )
800ced2: f997 300f ldrsb.w r3, [r7, #15]
800ced6: 2b00 cmp r3, #0
800ced8: dce9 bgt.n 800ceae <prvUnlockQueue+0x16>
800ceda: e000 b.n 800cede <prvUnlockQueue+0x46>
break;
800cedc: bf00 nop
}
pxQueue->cTxLock = queueUNLOCKED;
800cede: 687b ldr r3, [r7, #4]
800cee0: 22ff movs r2, #255 ; 0xff
800cee2: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
taskEXIT_CRITICAL();
800cee6: f001 fb25 bl 800e534 <vPortExitCritical>
/* Do the same for the Rx lock. */
taskENTER_CRITICAL();
800ceea: f001 faef bl 800e4cc <vPortEnterCritical>
{
int8_t cRxLock = pxQueue->cRxLock;
800ceee: 687b ldr r3, [r7, #4]
800cef0: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800cef4: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
800cef6: e011 b.n 800cf1c <prvUnlockQueue+0x84>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800cef8: 687b ldr r3, [r7, #4]
800cefa: 691b ldr r3, [r3, #16]
800cefc: 2b00 cmp r3, #0
800cefe: d012 beq.n 800cf26 <prvUnlockQueue+0x8e>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800cf00: 687b ldr r3, [r7, #4]
800cf02: 3310 adds r3, #16
800cf04: 4618 mov r0, r3
800cf06: f000 fdcd bl 800daa4 <xTaskRemoveFromEventList>
800cf0a: 4603 mov r3, r0
800cf0c: 2b00 cmp r3, #0
800cf0e: d001 beq.n 800cf14 <prvUnlockQueue+0x7c>
{
vTaskMissedYield();
800cf10: f000 fea8 bl 800dc64 <vTaskMissedYield>
else
{
mtCOVERAGE_TEST_MARKER();
}
--cRxLock;
800cf14: 7bbb ldrb r3, [r7, #14]
800cf16: 3b01 subs r3, #1
800cf18: b2db uxtb r3, r3
800cf1a: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
800cf1c: f997 300e ldrsb.w r3, [r7, #14]
800cf20: 2b00 cmp r3, #0
800cf22: dce9 bgt.n 800cef8 <prvUnlockQueue+0x60>
800cf24: e000 b.n 800cf28 <prvUnlockQueue+0x90>
}
else
{
break;
800cf26: bf00 nop
}
}
pxQueue->cRxLock = queueUNLOCKED;
800cf28: 687b ldr r3, [r7, #4]
800cf2a: 22ff movs r2, #255 ; 0xff
800cf2c: f883 2044 strb.w r2, [r3, #68] ; 0x44
}
taskEXIT_CRITICAL();
800cf30: f001 fb00 bl 800e534 <vPortExitCritical>
}
800cf34: bf00 nop
800cf36: 3710 adds r7, #16
800cf38: 46bd mov sp, r7
800cf3a: bd80 pop {r7, pc}
0800cf3c <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
800cf3c: b580 push {r7, lr}
800cf3e: b084 sub sp, #16
800cf40: af00 add r7, sp, #0
800cf42: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
800cf44: f001 fac2 bl 800e4cc <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
800cf48: 687b ldr r3, [r7, #4]
800cf4a: 6b9b ldr r3, [r3, #56] ; 0x38
800cf4c: 2b00 cmp r3, #0
800cf4e: d102 bne.n 800cf56 <prvIsQueueEmpty+0x1a>
{
xReturn = pdTRUE;
800cf50: 2301 movs r3, #1
800cf52: 60fb str r3, [r7, #12]
800cf54: e001 b.n 800cf5a <prvIsQueueEmpty+0x1e>
}
else
{
xReturn = pdFALSE;
800cf56: 2300 movs r3, #0
800cf58: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
800cf5a: f001 faeb bl 800e534 <vPortExitCritical>
return xReturn;
800cf5e: 68fb ldr r3, [r7, #12]
}
800cf60: 4618 mov r0, r3
800cf62: 3710 adds r7, #16
800cf64: 46bd mov sp, r7
800cf66: bd80 pop {r7, pc}
0800cf68 <prvIsQueueFull>:
return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
800cf68: b580 push {r7, lr}
800cf6a: b084 sub sp, #16
800cf6c: af00 add r7, sp, #0
800cf6e: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
800cf70: f001 faac bl 800e4cc <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
800cf74: 687b ldr r3, [r7, #4]
800cf76: 6b9a ldr r2, [r3, #56] ; 0x38
800cf78: 687b ldr r3, [r7, #4]
800cf7a: 6bdb ldr r3, [r3, #60] ; 0x3c
800cf7c: 429a cmp r2, r3
800cf7e: d102 bne.n 800cf86 <prvIsQueueFull+0x1e>
{
xReturn = pdTRUE;
800cf80: 2301 movs r3, #1
800cf82: 60fb str r3, [r7, #12]
800cf84: e001 b.n 800cf8a <prvIsQueueFull+0x22>
}
else
{
xReturn = pdFALSE;
800cf86: 2300 movs r3, #0
800cf88: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
800cf8a: f001 fad3 bl 800e534 <vPortExitCritical>
return xReturn;
800cf8e: 68fb ldr r3, [r7, #12]
}
800cf90: 4618 mov r0, r3
800cf92: 3710 adds r7, #16
800cf94: 46bd mov sp, r7
800cf96: bd80 pop {r7, pc}
0800cf98 <xTaskCreateStatic>:
const uint32_t ulStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
StaticTask_t * const pxTaskBuffer )
{
800cf98: b580 push {r7, lr}
800cf9a: b08e sub sp, #56 ; 0x38
800cf9c: af04 add r7, sp, #16
800cf9e: 60f8 str r0, [r7, #12]
800cfa0: 60b9 str r1, [r7, #8]
800cfa2: 607a str r2, [r7, #4]
800cfa4: 603b str r3, [r7, #0]
TCB_t *pxNewTCB;
TaskHandle_t xReturn;
configASSERT( puxStackBuffer != NULL );
800cfa6: 6b7b ldr r3, [r7, #52] ; 0x34
800cfa8: 2b00 cmp r3, #0
800cfaa: d10c bne.n 800cfc6 <xTaskCreateStatic+0x2e>
__asm volatile
800cfac: f04f 0350 mov.w r3, #80 ; 0x50
800cfb0: b672 cpsid i
800cfb2: f383 8811 msr BASEPRI, r3
800cfb6: f3bf 8f6f isb sy
800cfba: f3bf 8f4f dsb sy
800cfbe: b662 cpsie i
800cfc0: 623b str r3, [r7, #32]
}
800cfc2: bf00 nop
800cfc4: e7fe b.n 800cfc4 <xTaskCreateStatic+0x2c>
configASSERT( pxTaskBuffer != NULL );
800cfc6: 6bbb ldr r3, [r7, #56] ; 0x38
800cfc8: 2b00 cmp r3, #0
800cfca: d10c bne.n 800cfe6 <xTaskCreateStatic+0x4e>
__asm volatile
800cfcc: f04f 0350 mov.w r3, #80 ; 0x50
800cfd0: b672 cpsid i
800cfd2: f383 8811 msr BASEPRI, r3
800cfd6: f3bf 8f6f isb sy
800cfda: f3bf 8f4f dsb sy
800cfde: b662 cpsie i
800cfe0: 61fb str r3, [r7, #28]
}
800cfe2: bf00 nop
800cfe4: e7fe b.n 800cfe4 <xTaskCreateStatic+0x4c>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticTask_t equals the size of the real task
structure. */
volatile size_t xSize = sizeof( StaticTask_t );
800cfe6: 2358 movs r3, #88 ; 0x58
800cfe8: 613b str r3, [r7, #16]
configASSERT( xSize == sizeof( TCB_t ) );
800cfea: 693b ldr r3, [r7, #16]
800cfec: 2b58 cmp r3, #88 ; 0x58
800cfee: d00c beq.n 800d00a <xTaskCreateStatic+0x72>
__asm volatile
800cff0: f04f 0350 mov.w r3, #80 ; 0x50
800cff4: b672 cpsid i
800cff6: f383 8811 msr BASEPRI, r3
800cffa: f3bf 8f6f isb sy
800cffe: f3bf 8f4f dsb sy
800d002: b662 cpsie i
800d004: 61bb str r3, [r7, #24]
}
800d006: bf00 nop
800d008: e7fe b.n 800d008 <xTaskCreateStatic+0x70>
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
800d00a: 693b ldr r3, [r7, #16]
}
#endif /* configASSERT_DEFINED */
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
800d00c: 6bbb ldr r3, [r7, #56] ; 0x38
800d00e: 2b00 cmp r3, #0
800d010: d01e beq.n 800d050 <xTaskCreateStatic+0xb8>
800d012: 6b7b ldr r3, [r7, #52] ; 0x34
800d014: 2b00 cmp r3, #0
800d016: d01b beq.n 800d050 <xTaskCreateStatic+0xb8>
{
/* The memory used for the task's TCB and stack are passed into this
function - use them. */
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
800d018: 6bbb ldr r3, [r7, #56] ; 0x38
800d01a: 627b str r3, [r7, #36] ; 0x24
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
800d01c: 6a7b ldr r3, [r7, #36] ; 0x24
800d01e: 6b7a ldr r2, [r7, #52] ; 0x34
800d020: 631a str r2, [r3, #48] ; 0x30
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created statically in case the task is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
800d022: 6a7b ldr r3, [r7, #36] ; 0x24
800d024: 2202 movs r2, #2
800d026: f883 2055 strb.w r2, [r3, #85] ; 0x55
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
800d02a: 2300 movs r3, #0
800d02c: 9303 str r3, [sp, #12]
800d02e: 6a7b ldr r3, [r7, #36] ; 0x24
800d030: 9302 str r3, [sp, #8]
800d032: f107 0314 add.w r3, r7, #20
800d036: 9301 str r3, [sp, #4]
800d038: 6b3b ldr r3, [r7, #48] ; 0x30
800d03a: 9300 str r3, [sp, #0]
800d03c: 683b ldr r3, [r7, #0]
800d03e: 687a ldr r2, [r7, #4]
800d040: 68b9 ldr r1, [r7, #8]
800d042: 68f8 ldr r0, [r7, #12]
800d044: f000 f850 bl 800d0e8 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
800d048: 6a78 ldr r0, [r7, #36] ; 0x24
800d04a: f000 f8e1 bl 800d210 <prvAddNewTaskToReadyList>
800d04e: e001 b.n 800d054 <xTaskCreateStatic+0xbc>
}
else
{
xReturn = NULL;
800d050: 2300 movs r3, #0
800d052: 617b str r3, [r7, #20]
}
return xReturn;
800d054: 697b ldr r3, [r7, #20]
}
800d056: 4618 mov r0, r3
800d058: 3728 adds r7, #40 ; 0x28
800d05a: 46bd mov sp, r7
800d05c: bd80 pop {r7, pc}
0800d05e <xTaskCreate>:
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const configSTACK_DEPTH_TYPE usStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask )
{
800d05e: b580 push {r7, lr}
800d060: b08c sub sp, #48 ; 0x30
800d062: af04 add r7, sp, #16
800d064: 60f8 str r0, [r7, #12]
800d066: 60b9 str r1, [r7, #8]
800d068: 603b str r3, [r7, #0]
800d06a: 4613 mov r3, r2
800d06c: 80fb strh r3, [r7, #6]
#else /* portSTACK_GROWTH */
{
StackType_t *pxStack;
/* Allocate space for the stack used by the task being created. */
pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
800d06e: 88fb ldrh r3, [r7, #6]
800d070: 009b lsls r3, r3, #2
800d072: 4618 mov r0, r3
800d074: f001 fb56 bl 800e724 <pvPortMalloc>
800d078: 6178 str r0, [r7, #20]
if( pxStack != NULL )
800d07a: 697b ldr r3, [r7, #20]
800d07c: 2b00 cmp r3, #0
800d07e: d00e beq.n 800d09e <xTaskCreate+0x40>
{
/* Allocate space for the TCB. */
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
800d080: 2058 movs r0, #88 ; 0x58
800d082: f001 fb4f bl 800e724 <pvPortMalloc>
800d086: 61f8 str r0, [r7, #28]
if( pxNewTCB != NULL )
800d088: 69fb ldr r3, [r7, #28]
800d08a: 2b00 cmp r3, #0
800d08c: d003 beq.n 800d096 <xTaskCreate+0x38>
{
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxStack;
800d08e: 69fb ldr r3, [r7, #28]
800d090: 697a ldr r2, [r7, #20]
800d092: 631a str r2, [r3, #48] ; 0x30
800d094: e005 b.n 800d0a2 <xTaskCreate+0x44>
}
else
{
/* The stack cannot be used as the TCB was not created. Free
it again. */
vPortFree( pxStack );
800d096: 6978 ldr r0, [r7, #20]
800d098: f001 fc14 bl 800e8c4 <vPortFree>
800d09c: e001 b.n 800d0a2 <xTaskCreate+0x44>
}
}
else
{
pxNewTCB = NULL;
800d09e: 2300 movs r3, #0
800d0a0: 61fb str r3, [r7, #28]
}
}
#endif /* portSTACK_GROWTH */
if( pxNewTCB != NULL )
800d0a2: 69fb ldr r3, [r7, #28]
800d0a4: 2b00 cmp r3, #0
800d0a6: d017 beq.n 800d0d8 <xTaskCreate+0x7a>
{
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created dynamically in case it is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
800d0a8: 69fb ldr r3, [r7, #28]
800d0aa: 2200 movs r2, #0
800d0ac: f883 2055 strb.w r2, [r3, #85] ; 0x55
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
800d0b0: 88fa ldrh r2, [r7, #6]
800d0b2: 2300 movs r3, #0
800d0b4: 9303 str r3, [sp, #12]
800d0b6: 69fb ldr r3, [r7, #28]
800d0b8: 9302 str r3, [sp, #8]
800d0ba: 6afb ldr r3, [r7, #44] ; 0x2c
800d0bc: 9301 str r3, [sp, #4]
800d0be: 6abb ldr r3, [r7, #40] ; 0x28
800d0c0: 9300 str r3, [sp, #0]
800d0c2: 683b ldr r3, [r7, #0]
800d0c4: 68b9 ldr r1, [r7, #8]
800d0c6: 68f8 ldr r0, [r7, #12]
800d0c8: f000 f80e bl 800d0e8 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
800d0cc: 69f8 ldr r0, [r7, #28]
800d0ce: f000 f89f bl 800d210 <prvAddNewTaskToReadyList>
xReturn = pdPASS;
800d0d2: 2301 movs r3, #1
800d0d4: 61bb str r3, [r7, #24]
800d0d6: e002 b.n 800d0de <xTaskCreate+0x80>
}
else
{
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
800d0d8: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
800d0dc: 61bb str r3, [r7, #24]
}
return xReturn;
800d0de: 69bb ldr r3, [r7, #24]
}
800d0e0: 4618 mov r0, r3
800d0e2: 3720 adds r7, #32
800d0e4: 46bd mov sp, r7
800d0e6: bd80 pop {r7, pc}
0800d0e8 <prvInitialiseNewTask>:
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask,
TCB_t *pxNewTCB,
const MemoryRegion_t * const xRegions )
{
800d0e8: b580 push {r7, lr}
800d0ea: b088 sub sp, #32
800d0ec: af00 add r7, sp, #0
800d0ee: 60f8 str r0, [r7, #12]
800d0f0: 60b9 str r1, [r7, #8]
800d0f2: 607a str r2, [r7, #4]
800d0f4: 603b str r3, [r7, #0]
/* Avoid dependency on memset() if it is not required. */
#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
{
/* Fill the stack with a known value to assist debugging. */
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
800d0f6: 6b3b ldr r3, [r7, #48] ; 0x30
800d0f8: 6b18 ldr r0, [r3, #48] ; 0x30
800d0fa: 687b ldr r3, [r7, #4]
800d0fc: 009b lsls r3, r3, #2
800d0fe: 461a mov r2, r3
800d100: 21a5 movs r1, #165 ; 0xa5
800d102: f00d ff57 bl 801afb4 <memset>
grows from high memory to low (as per the 80x86) or vice versa.
portSTACK_GROWTH is used to make the result positive or negative as required
by the port. */
#if( portSTACK_GROWTH < 0 )
{
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
800d106: 6b3b ldr r3, [r7, #48] ; 0x30
800d108: 6b1a ldr r2, [r3, #48] ; 0x30
800d10a: 6879 ldr r1, [r7, #4]
800d10c: f06f 4340 mvn.w r3, #3221225472 ; 0xc0000000
800d110: 440b add r3, r1
800d112: 009b lsls r3, r3, #2
800d114: 4413 add r3, r2
800d116: 61bb str r3, [r7, #24]
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
800d118: 69bb ldr r3, [r7, #24]
800d11a: f023 0307 bic.w r3, r3, #7
800d11e: 61bb str r3, [r7, #24]
/* Check the alignment of the calculated top of stack is correct. */
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
800d120: 69bb ldr r3, [r7, #24]
800d122: f003 0307 and.w r3, r3, #7
800d126: 2b00 cmp r3, #0
800d128: d00c beq.n 800d144 <prvInitialiseNewTask+0x5c>
__asm volatile
800d12a: f04f 0350 mov.w r3, #80 ; 0x50
800d12e: b672 cpsid i
800d130: f383 8811 msr BASEPRI, r3
800d134: f3bf 8f6f isb sy
800d138: f3bf 8f4f dsb sy
800d13c: b662 cpsie i
800d13e: 617b str r3, [r7, #20]
}
800d140: bf00 nop
800d142: e7fe b.n 800d142 <prvInitialiseNewTask+0x5a>
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
}
#endif /* portSTACK_GROWTH */
/* Store the task name in the TCB. */
if( pcName != NULL )
800d144: 68bb ldr r3, [r7, #8]
800d146: 2b00 cmp r3, #0
800d148: d01f beq.n 800d18a <prvInitialiseNewTask+0xa2>
{
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
800d14a: 2300 movs r3, #0
800d14c: 61fb str r3, [r7, #28]
800d14e: e012 b.n 800d176 <prvInitialiseNewTask+0x8e>
{
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
800d150: 68ba ldr r2, [r7, #8]
800d152: 69fb ldr r3, [r7, #28]
800d154: 4413 add r3, r2
800d156: 7819 ldrb r1, [r3, #0]
800d158: 6b3a ldr r2, [r7, #48] ; 0x30
800d15a: 69fb ldr r3, [r7, #28]
800d15c: 4413 add r3, r2
800d15e: 3334 adds r3, #52 ; 0x34
800d160: 460a mov r2, r1
800d162: 701a strb r2, [r3, #0]
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
configMAX_TASK_NAME_LEN characters just in case the memory after the
string is not accessible (extremely unlikely). */
if( pcName[ x ] == ( char ) 0x00 )
800d164: 68ba ldr r2, [r7, #8]
800d166: 69fb ldr r3, [r7, #28]
800d168: 4413 add r3, r2
800d16a: 781b ldrb r3, [r3, #0]
800d16c: 2b00 cmp r3, #0
800d16e: d006 beq.n 800d17e <prvInitialiseNewTask+0x96>
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
800d170: 69fb ldr r3, [r7, #28]
800d172: 3301 adds r3, #1
800d174: 61fb str r3, [r7, #28]
800d176: 69fb ldr r3, [r7, #28]
800d178: 2b0f cmp r3, #15
800d17a: d9e9 bls.n 800d150 <prvInitialiseNewTask+0x68>
800d17c: e000 b.n 800d180 <prvInitialiseNewTask+0x98>
{
break;
800d17e: bf00 nop
}
}
/* Ensure the name string is terminated in the case that the string length
was greater or equal to configMAX_TASK_NAME_LEN. */
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
800d180: 6b3b ldr r3, [r7, #48] ; 0x30
800d182: 2200 movs r2, #0
800d184: f883 2043 strb.w r2, [r3, #67] ; 0x43
800d188: e003 b.n 800d192 <prvInitialiseNewTask+0xaa>
}
else
{
/* The task has not been given a name, so just ensure there is a NULL
terminator when it is read out. */
pxNewTCB->pcTaskName[ 0 ] = 0x00;
800d18a: 6b3b ldr r3, [r7, #48] ; 0x30
800d18c: 2200 movs r2, #0
800d18e: f883 2034 strb.w r2, [r3, #52] ; 0x34
}
/* This is used as an array index so must ensure it's not too large. First
remove the privilege bit if one is present. */
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
800d192: 6abb ldr r3, [r7, #40] ; 0x28
800d194: 2b06 cmp r3, #6
800d196: d901 bls.n 800d19c <prvInitialiseNewTask+0xb4>
{
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
800d198: 2306 movs r3, #6
800d19a: 62bb str r3, [r7, #40] ; 0x28
else
{
mtCOVERAGE_TEST_MARKER();
}
pxNewTCB->uxPriority = uxPriority;
800d19c: 6b3b ldr r3, [r7, #48] ; 0x30
800d19e: 6aba ldr r2, [r7, #40] ; 0x28
800d1a0: 62da str r2, [r3, #44] ; 0x2c
#if ( configUSE_MUTEXES == 1 )
{
pxNewTCB->uxBasePriority = uxPriority;
800d1a2: 6b3b ldr r3, [r7, #48] ; 0x30
800d1a4: 6aba ldr r2, [r7, #40] ; 0x28
800d1a6: 645a str r2, [r3, #68] ; 0x44
pxNewTCB->uxMutexesHeld = 0;
800d1a8: 6b3b ldr r3, [r7, #48] ; 0x30
800d1aa: 2200 movs r2, #0
800d1ac: 649a str r2, [r3, #72] ; 0x48
}
#endif /* configUSE_MUTEXES */
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
800d1ae: 6b3b ldr r3, [r7, #48] ; 0x30
800d1b0: 3304 adds r3, #4
800d1b2: 4618 mov r0, r3
800d1b4: f7fe fe6c bl 800be90 <vListInitialiseItem>
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
800d1b8: 6b3b ldr r3, [r7, #48] ; 0x30
800d1ba: 3318 adds r3, #24
800d1bc: 4618 mov r0, r3
800d1be: f7fe fe67 bl 800be90 <vListInitialiseItem>
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
back to the containing TCB from a generic item in a list. */
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
800d1c2: 6b3b ldr r3, [r7, #48] ; 0x30
800d1c4: 6b3a ldr r2, [r7, #48] ; 0x30
800d1c6: 611a str r2, [r3, #16]
/* Event lists are always in priority order. */
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800d1c8: 6abb ldr r3, [r7, #40] ; 0x28
800d1ca: f1c3 0207 rsb r2, r3, #7
800d1ce: 6b3b ldr r3, [r7, #48] ; 0x30
800d1d0: 619a str r2, [r3, #24]
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
800d1d2: 6b3b ldr r3, [r7, #48] ; 0x30
800d1d4: 6b3a ldr r2, [r7, #48] ; 0x30
800d1d6: 625a str r2, [r3, #36] ; 0x24
}
#endif /* portCRITICAL_NESTING_IN_TCB */
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
{
pxNewTCB->pxTaskTag = NULL;
800d1d8: 6b3b ldr r3, [r7, #48] ; 0x30
800d1da: 2200 movs r2, #0
800d1dc: 64da str r2, [r3, #76] ; 0x4c
}
#endif
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
{
pxNewTCB->ulNotifiedValue = 0;
800d1de: 6b3b ldr r3, [r7, #48] ; 0x30
800d1e0: 2200 movs r2, #0
800d1e2: 651a str r2, [r3, #80] ; 0x50
pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
800d1e4: 6b3b ldr r3, [r7, #48] ; 0x30
800d1e6: 2200 movs r2, #0
800d1e8: f883 2054 strb.w r2, [r3, #84] ; 0x54
}
#endif /* portSTACK_GROWTH */
}
#else /* portHAS_STACK_OVERFLOW_CHECKING */
{
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
800d1ec: 683a ldr r2, [r7, #0]
800d1ee: 68f9 ldr r1, [r7, #12]
800d1f0: 69b8 ldr r0, [r7, #24]
800d1f2: f001 f85d bl 800e2b0 <pxPortInitialiseStack>
800d1f6: 4602 mov r2, r0
800d1f8: 6b3b ldr r3, [r7, #48] ; 0x30
800d1fa: 601a str r2, [r3, #0]
}
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
}
#endif /* portUSING_MPU_WRAPPERS */
if( pxCreatedTask != NULL )
800d1fc: 6afb ldr r3, [r7, #44] ; 0x2c
800d1fe: 2b00 cmp r3, #0
800d200: d002 beq.n 800d208 <prvInitialiseNewTask+0x120>
{
/* Pass the handle out in an anonymous way. The handle can be used to
change the created task's priority, delete the created task, etc.*/
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
800d202: 6afb ldr r3, [r7, #44] ; 0x2c
800d204: 6b3a ldr r2, [r7, #48] ; 0x30
800d206: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800d208: bf00 nop
800d20a: 3720 adds r7, #32
800d20c: 46bd mov sp, r7
800d20e: bd80 pop {r7, pc}
0800d210 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/
static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
800d210: b580 push {r7, lr}
800d212: b082 sub sp, #8
800d214: af00 add r7, sp, #0
800d216: 6078 str r0, [r7, #4]
/* Ensure interrupts don't access the task lists while the lists are being
updated. */
taskENTER_CRITICAL();
800d218: f001 f958 bl 800e4cc <vPortEnterCritical>
{
uxCurrentNumberOfTasks++;
800d21c: 4b2a ldr r3, [pc, #168] ; (800d2c8 <prvAddNewTaskToReadyList+0xb8>)
800d21e: 681b ldr r3, [r3, #0]
800d220: 3301 adds r3, #1
800d222: 4a29 ldr r2, [pc, #164] ; (800d2c8 <prvAddNewTaskToReadyList+0xb8>)
800d224: 6013 str r3, [r2, #0]
if( pxCurrentTCB == NULL )
800d226: 4b29 ldr r3, [pc, #164] ; (800d2cc <prvAddNewTaskToReadyList+0xbc>)
800d228: 681b ldr r3, [r3, #0]
800d22a: 2b00 cmp r3, #0
800d22c: d109 bne.n 800d242 <prvAddNewTaskToReadyList+0x32>
{
/* There are no other tasks, or all the other tasks are in
the suspended state - make this the current task. */
pxCurrentTCB = pxNewTCB;
800d22e: 4a27 ldr r2, [pc, #156] ; (800d2cc <prvAddNewTaskToReadyList+0xbc>)
800d230: 687b ldr r3, [r7, #4]
800d232: 6013 str r3, [r2, #0]
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
800d234: 4b24 ldr r3, [pc, #144] ; (800d2c8 <prvAddNewTaskToReadyList+0xb8>)
800d236: 681b ldr r3, [r3, #0]
800d238: 2b01 cmp r3, #1
800d23a: d110 bne.n 800d25e <prvAddNewTaskToReadyList+0x4e>
{
/* This is the first task to be created so do the preliminary
initialisation required. We will not recover if this call
fails, but we will report the failure. */
prvInitialiseTaskLists();
800d23c: f000 fd38 bl 800dcb0 <prvInitialiseTaskLists>
800d240: e00d b.n 800d25e <prvAddNewTaskToReadyList+0x4e>
else
{
/* If the scheduler is not already running, make this task the
current task if it is the highest priority task to be created
so far. */
if( xSchedulerRunning == pdFALSE )
800d242: 4b23 ldr r3, [pc, #140] ; (800d2d0 <prvAddNewTaskToReadyList+0xc0>)
800d244: 681b ldr r3, [r3, #0]
800d246: 2b00 cmp r3, #0
800d248: d109 bne.n 800d25e <prvAddNewTaskToReadyList+0x4e>
{
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
800d24a: 4b20 ldr r3, [pc, #128] ; (800d2cc <prvAddNewTaskToReadyList+0xbc>)
800d24c: 681b ldr r3, [r3, #0]
800d24e: 6ada ldr r2, [r3, #44] ; 0x2c
800d250: 687b ldr r3, [r7, #4]
800d252: 6adb ldr r3, [r3, #44] ; 0x2c
800d254: 429a cmp r2, r3
800d256: d802 bhi.n 800d25e <prvAddNewTaskToReadyList+0x4e>
{
pxCurrentTCB = pxNewTCB;
800d258: 4a1c ldr r2, [pc, #112] ; (800d2cc <prvAddNewTaskToReadyList+0xbc>)
800d25a: 687b ldr r3, [r7, #4]
800d25c: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
uxTaskNumber++;
800d25e: 4b1d ldr r3, [pc, #116] ; (800d2d4 <prvAddNewTaskToReadyList+0xc4>)
800d260: 681b ldr r3, [r3, #0]
800d262: 3301 adds r3, #1
800d264: 4a1b ldr r2, [pc, #108] ; (800d2d4 <prvAddNewTaskToReadyList+0xc4>)
800d266: 6013 str r3, [r2, #0]
pxNewTCB->uxTCBNumber = uxTaskNumber;
}
#endif /* configUSE_TRACE_FACILITY */
traceTASK_CREATE( pxNewTCB );
prvAddTaskToReadyList( pxNewTCB );
800d268: 687b ldr r3, [r7, #4]
800d26a: 6adb ldr r3, [r3, #44] ; 0x2c
800d26c: 2201 movs r2, #1
800d26e: 409a lsls r2, r3
800d270: 4b19 ldr r3, [pc, #100] ; (800d2d8 <prvAddNewTaskToReadyList+0xc8>)
800d272: 681b ldr r3, [r3, #0]
800d274: 4313 orrs r3, r2
800d276: 4a18 ldr r2, [pc, #96] ; (800d2d8 <prvAddNewTaskToReadyList+0xc8>)
800d278: 6013 str r3, [r2, #0]
800d27a: 687b ldr r3, [r7, #4]
800d27c: 6ada ldr r2, [r3, #44] ; 0x2c
800d27e: 4613 mov r3, r2
800d280: 009b lsls r3, r3, #2
800d282: 4413 add r3, r2
800d284: 009b lsls r3, r3, #2
800d286: 4a15 ldr r2, [pc, #84] ; (800d2dc <prvAddNewTaskToReadyList+0xcc>)
800d288: 441a add r2, r3
800d28a: 687b ldr r3, [r7, #4]
800d28c: 3304 adds r3, #4
800d28e: 4619 mov r1, r3
800d290: 4610 mov r0, r2
800d292: f7fe fe0a bl 800beaa <vListInsertEnd>
portSETUP_TCB( pxNewTCB );
}
taskEXIT_CRITICAL();
800d296: f001 f94d bl 800e534 <vPortExitCritical>
if( xSchedulerRunning != pdFALSE )
800d29a: 4b0d ldr r3, [pc, #52] ; (800d2d0 <prvAddNewTaskToReadyList+0xc0>)
800d29c: 681b ldr r3, [r3, #0]
800d29e: 2b00 cmp r3, #0
800d2a0: d00e beq.n 800d2c0 <prvAddNewTaskToReadyList+0xb0>
{
/* If the created task is of a higher priority than the current task
then it should run now. */
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
800d2a2: 4b0a ldr r3, [pc, #40] ; (800d2cc <prvAddNewTaskToReadyList+0xbc>)
800d2a4: 681b ldr r3, [r3, #0]
800d2a6: 6ada ldr r2, [r3, #44] ; 0x2c
800d2a8: 687b ldr r3, [r7, #4]
800d2aa: 6adb ldr r3, [r3, #44] ; 0x2c
800d2ac: 429a cmp r2, r3
800d2ae: d207 bcs.n 800d2c0 <prvAddNewTaskToReadyList+0xb0>
{
taskYIELD_IF_USING_PREEMPTION();
800d2b0: 4b0b ldr r3, [pc, #44] ; (800d2e0 <prvAddNewTaskToReadyList+0xd0>)
800d2b2: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d2b6: 601a str r2, [r3, #0]
800d2b8: f3bf 8f4f dsb sy
800d2bc: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800d2c0: bf00 nop
800d2c2: 3708 adds r7, #8
800d2c4: 46bd mov sp, r7
800d2c6: bd80 pop {r7, pc}
800d2c8: 20000680 .word 0x20000680
800d2cc: 20000580 .word 0x20000580
800d2d0: 2000068c .word 0x2000068c
800d2d4: 2000069c .word 0x2000069c
800d2d8: 20000688 .word 0x20000688
800d2dc: 20000584 .word 0x20000584
800d2e0: e000ed04 .word 0xe000ed04
0800d2e4 <vTaskDelete>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
void vTaskDelete( TaskHandle_t xTaskToDelete )
{
800d2e4: b580 push {r7, lr}
800d2e6: b084 sub sp, #16
800d2e8: af00 add r7, sp, #0
800d2ea: 6078 str r0, [r7, #4]
TCB_t *pxTCB;
taskENTER_CRITICAL();
800d2ec: f001 f8ee bl 800e4cc <vPortEnterCritical>
{
/* If null is passed in here then it is the calling task that is
being deleted. */
pxTCB = prvGetTCBFromHandle( xTaskToDelete );
800d2f0: 687b ldr r3, [r7, #4]
800d2f2: 2b00 cmp r3, #0
800d2f4: d102 bne.n 800d2fc <vTaskDelete+0x18>
800d2f6: 4b3a ldr r3, [pc, #232] ; (800d3e0 <vTaskDelete+0xfc>)
800d2f8: 681b ldr r3, [r3, #0]
800d2fa: e000 b.n 800d2fe <vTaskDelete+0x1a>
800d2fc: 687b ldr r3, [r7, #4]
800d2fe: 60fb str r3, [r7, #12]
/* Remove task from the ready list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800d300: 68fb ldr r3, [r7, #12]
800d302: 3304 adds r3, #4
800d304: 4618 mov r0, r3
800d306: f7fe fe2d bl 800bf64 <uxListRemove>
800d30a: 4603 mov r3, r0
800d30c: 2b00 cmp r3, #0
800d30e: d115 bne.n 800d33c <vTaskDelete+0x58>
{
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
800d310: 68fb ldr r3, [r7, #12]
800d312: 6ada ldr r2, [r3, #44] ; 0x2c
800d314: 4933 ldr r1, [pc, #204] ; (800d3e4 <vTaskDelete+0x100>)
800d316: 4613 mov r3, r2
800d318: 009b lsls r3, r3, #2
800d31a: 4413 add r3, r2
800d31c: 009b lsls r3, r3, #2
800d31e: 440b add r3, r1
800d320: 681b ldr r3, [r3, #0]
800d322: 2b00 cmp r3, #0
800d324: d10a bne.n 800d33c <vTaskDelete+0x58>
800d326: 68fb ldr r3, [r7, #12]
800d328: 6adb ldr r3, [r3, #44] ; 0x2c
800d32a: 2201 movs r2, #1
800d32c: fa02 f303 lsl.w r3, r2, r3
800d330: 43da mvns r2, r3
800d332: 4b2d ldr r3, [pc, #180] ; (800d3e8 <vTaskDelete+0x104>)
800d334: 681b ldr r3, [r3, #0]
800d336: 4013 ands r3, r2
800d338: 4a2b ldr r2, [pc, #172] ; (800d3e8 <vTaskDelete+0x104>)
800d33a: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
/* Is the task waiting on an event also? */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
800d33c: 68fb ldr r3, [r7, #12]
800d33e: 6a9b ldr r3, [r3, #40] ; 0x28
800d340: 2b00 cmp r3, #0
800d342: d004 beq.n 800d34e <vTaskDelete+0x6a>
{
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800d344: 68fb ldr r3, [r7, #12]
800d346: 3318 adds r3, #24
800d348: 4618 mov r0, r3
800d34a: f7fe fe0b bl 800bf64 <uxListRemove>
/* Increment the uxTaskNumber also so kernel aware debuggers can
detect that the task lists need re-generating. This is done before
portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
not return. */
uxTaskNumber++;
800d34e: 4b27 ldr r3, [pc, #156] ; (800d3ec <vTaskDelete+0x108>)
800d350: 681b ldr r3, [r3, #0]
800d352: 3301 adds r3, #1
800d354: 4a25 ldr r2, [pc, #148] ; (800d3ec <vTaskDelete+0x108>)
800d356: 6013 str r3, [r2, #0]
if( pxTCB == pxCurrentTCB )
800d358: 4b21 ldr r3, [pc, #132] ; (800d3e0 <vTaskDelete+0xfc>)
800d35a: 681b ldr r3, [r3, #0]
800d35c: 68fa ldr r2, [r7, #12]
800d35e: 429a cmp r2, r3
800d360: d10b bne.n 800d37a <vTaskDelete+0x96>
/* A task is deleting itself. This cannot complete within the
task itself, as a context switch to another task is required.
Place the task in the termination list. The idle task will
check the termination list and free up any memory allocated by
the scheduler for the TCB and stack of the deleted task. */
vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
800d362: 68fb ldr r3, [r7, #12]
800d364: 3304 adds r3, #4
800d366: 4619 mov r1, r3
800d368: 4821 ldr r0, [pc, #132] ; (800d3f0 <vTaskDelete+0x10c>)
800d36a: f7fe fd9e bl 800beaa <vListInsertEnd>
/* Increment the ucTasksDeleted variable so the idle task knows
there is a task that has been deleted and that it should therefore
check the xTasksWaitingTermination list. */
++uxDeletedTasksWaitingCleanUp;
800d36e: 4b21 ldr r3, [pc, #132] ; (800d3f4 <vTaskDelete+0x110>)
800d370: 681b ldr r3, [r3, #0]
800d372: 3301 adds r3, #1
800d374: 4a1f ldr r2, [pc, #124] ; (800d3f4 <vTaskDelete+0x110>)
800d376: 6013 str r3, [r2, #0]
800d378: e009 b.n 800d38e <vTaskDelete+0xaa>
required. */
portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
}
else
{
--uxCurrentNumberOfTasks;
800d37a: 4b1f ldr r3, [pc, #124] ; (800d3f8 <vTaskDelete+0x114>)
800d37c: 681b ldr r3, [r3, #0]
800d37e: 3b01 subs r3, #1
800d380: 4a1d ldr r2, [pc, #116] ; (800d3f8 <vTaskDelete+0x114>)
800d382: 6013 str r3, [r2, #0]
prvDeleteTCB( pxTCB );
800d384: 68f8 ldr r0, [r7, #12]
800d386: f000 fd01 bl 800dd8c <prvDeleteTCB>
/* Reset the next expected unblock time in case it referred to
the task that has just been deleted. */
prvResetNextTaskUnblockTime();
800d38a: f000 fd31 bl 800ddf0 <prvResetNextTaskUnblockTime>
}
traceTASK_DELETE( pxTCB );
}
taskEXIT_CRITICAL();
800d38e: f001 f8d1 bl 800e534 <vPortExitCritical>
/* Force a reschedule if it is the currently running task that has just
been deleted. */
if( xSchedulerRunning != pdFALSE )
800d392: 4b1a ldr r3, [pc, #104] ; (800d3fc <vTaskDelete+0x118>)
800d394: 681b ldr r3, [r3, #0]
800d396: 2b00 cmp r3, #0
800d398: d01d beq.n 800d3d6 <vTaskDelete+0xf2>
{
if( pxTCB == pxCurrentTCB )
800d39a: 4b11 ldr r3, [pc, #68] ; (800d3e0 <vTaskDelete+0xfc>)
800d39c: 681b ldr r3, [r3, #0]
800d39e: 68fa ldr r2, [r7, #12]
800d3a0: 429a cmp r2, r3
800d3a2: d118 bne.n 800d3d6 <vTaskDelete+0xf2>
{
configASSERT( uxSchedulerSuspended == 0 );
800d3a4: 4b16 ldr r3, [pc, #88] ; (800d400 <vTaskDelete+0x11c>)
800d3a6: 681b ldr r3, [r3, #0]
800d3a8: 2b00 cmp r3, #0
800d3aa: d00c beq.n 800d3c6 <vTaskDelete+0xe2>
__asm volatile
800d3ac: f04f 0350 mov.w r3, #80 ; 0x50
800d3b0: b672 cpsid i
800d3b2: f383 8811 msr BASEPRI, r3
800d3b6: f3bf 8f6f isb sy
800d3ba: f3bf 8f4f dsb sy
800d3be: b662 cpsie i
800d3c0: 60bb str r3, [r7, #8]
}
800d3c2: bf00 nop
800d3c4: e7fe b.n 800d3c4 <vTaskDelete+0xe0>
portYIELD_WITHIN_API();
800d3c6: 4b0f ldr r3, [pc, #60] ; (800d404 <vTaskDelete+0x120>)
800d3c8: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d3cc: 601a str r2, [r3, #0]
800d3ce: f3bf 8f4f dsb sy
800d3d2: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
800d3d6: bf00 nop
800d3d8: 3710 adds r7, #16
800d3da: 46bd mov sp, r7
800d3dc: bd80 pop {r7, pc}
800d3de: bf00 nop
800d3e0: 20000580 .word 0x20000580
800d3e4: 20000584 .word 0x20000584
800d3e8: 20000688 .word 0x20000688
800d3ec: 2000069c .word 0x2000069c
800d3f0: 20000654 .word 0x20000654
800d3f4: 20000668 .word 0x20000668
800d3f8: 20000680 .word 0x20000680
800d3fc: 2000068c .word 0x2000068c
800d400: 200006a8 .word 0x200006a8
800d404: e000ed04 .word 0xe000ed04
0800d408 <vTaskDelayUntil>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelayUntil == 1 )
void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
{
800d408: b580 push {r7, lr}
800d40a: b08a sub sp, #40 ; 0x28
800d40c: af00 add r7, sp, #0
800d40e: 6078 str r0, [r7, #4]
800d410: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
800d412: 2300 movs r3, #0
800d414: 627b str r3, [r7, #36] ; 0x24
configASSERT( pxPreviousWakeTime );
800d416: 687b ldr r3, [r7, #4]
800d418: 2b00 cmp r3, #0
800d41a: d10c bne.n 800d436 <vTaskDelayUntil+0x2e>
__asm volatile
800d41c: f04f 0350 mov.w r3, #80 ; 0x50
800d420: b672 cpsid i
800d422: f383 8811 msr BASEPRI, r3
800d426: f3bf 8f6f isb sy
800d42a: f3bf 8f4f dsb sy
800d42e: b662 cpsie i
800d430: 617b str r3, [r7, #20]
}
800d432: bf00 nop
800d434: e7fe b.n 800d434 <vTaskDelayUntil+0x2c>
configASSERT( ( xTimeIncrement > 0U ) );
800d436: 683b ldr r3, [r7, #0]
800d438: 2b00 cmp r3, #0
800d43a: d10c bne.n 800d456 <vTaskDelayUntil+0x4e>
__asm volatile
800d43c: f04f 0350 mov.w r3, #80 ; 0x50
800d440: b672 cpsid i
800d442: f383 8811 msr BASEPRI, r3
800d446: f3bf 8f6f isb sy
800d44a: f3bf 8f4f dsb sy
800d44e: b662 cpsie i
800d450: 613b str r3, [r7, #16]
}
800d452: bf00 nop
800d454: e7fe b.n 800d454 <vTaskDelayUntil+0x4c>
configASSERT( uxSchedulerSuspended == 0 );
800d456: 4b2b ldr r3, [pc, #172] ; (800d504 <vTaskDelayUntil+0xfc>)
800d458: 681b ldr r3, [r3, #0]
800d45a: 2b00 cmp r3, #0
800d45c: d00c beq.n 800d478 <vTaskDelayUntil+0x70>
__asm volatile
800d45e: f04f 0350 mov.w r3, #80 ; 0x50
800d462: b672 cpsid i
800d464: f383 8811 msr BASEPRI, r3
800d468: f3bf 8f6f isb sy
800d46c: f3bf 8f4f dsb sy
800d470: b662 cpsie i
800d472: 60fb str r3, [r7, #12]
}
800d474: bf00 nop
800d476: e7fe b.n 800d476 <vTaskDelayUntil+0x6e>
vTaskSuspendAll();
800d478: f000 f8e4 bl 800d644 <vTaskSuspendAll>
{
/* Minor optimisation. The tick count cannot change in this
block. */
const TickType_t xConstTickCount = xTickCount;
800d47c: 4b22 ldr r3, [pc, #136] ; (800d508 <vTaskDelayUntil+0x100>)
800d47e: 681b ldr r3, [r3, #0]
800d480: 623b str r3, [r7, #32]
/* Generate the tick time at which the task wants to wake. */
xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
800d482: 687b ldr r3, [r7, #4]
800d484: 681b ldr r3, [r3, #0]
800d486: 683a ldr r2, [r7, #0]
800d488: 4413 add r3, r2
800d48a: 61fb str r3, [r7, #28]
if( xConstTickCount < *pxPreviousWakeTime )
800d48c: 687b ldr r3, [r7, #4]
800d48e: 681b ldr r3, [r3, #0]
800d490: 6a3a ldr r2, [r7, #32]
800d492: 429a cmp r2, r3
800d494: d20b bcs.n 800d4ae <vTaskDelayUntil+0xa6>
/* The tick count has overflowed since this function was
lasted called. In this case the only time we should ever
actually delay is if the wake time has also overflowed,
and the wake time is greater than the tick time. When this
is the case it is as if neither time had overflowed. */
if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
800d496: 687b ldr r3, [r7, #4]
800d498: 681b ldr r3, [r3, #0]
800d49a: 69fa ldr r2, [r7, #28]
800d49c: 429a cmp r2, r3
800d49e: d211 bcs.n 800d4c4 <vTaskDelayUntil+0xbc>
800d4a0: 69fa ldr r2, [r7, #28]
800d4a2: 6a3b ldr r3, [r7, #32]
800d4a4: 429a cmp r2, r3
800d4a6: d90d bls.n 800d4c4 <vTaskDelayUntil+0xbc>
{
xShouldDelay = pdTRUE;
800d4a8: 2301 movs r3, #1
800d4aa: 627b str r3, [r7, #36] ; 0x24
800d4ac: e00a b.n 800d4c4 <vTaskDelayUntil+0xbc>
else
{
/* The tick time has not overflowed. In this case we will
delay if either the wake time has overflowed, and/or the
tick time is less than the wake time. */
if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
800d4ae: 687b ldr r3, [r7, #4]
800d4b0: 681b ldr r3, [r3, #0]
800d4b2: 69fa ldr r2, [r7, #28]
800d4b4: 429a cmp r2, r3
800d4b6: d303 bcc.n 800d4c0 <vTaskDelayUntil+0xb8>
800d4b8: 69fa ldr r2, [r7, #28]
800d4ba: 6a3b ldr r3, [r7, #32]
800d4bc: 429a cmp r2, r3
800d4be: d901 bls.n 800d4c4 <vTaskDelayUntil+0xbc>
{
xShouldDelay = pdTRUE;
800d4c0: 2301 movs r3, #1
800d4c2: 627b str r3, [r7, #36] ; 0x24
mtCOVERAGE_TEST_MARKER();
}
}
/* Update the wake time ready for the next call. */
*pxPreviousWakeTime = xTimeToWake;
800d4c4: 687b ldr r3, [r7, #4]
800d4c6: 69fa ldr r2, [r7, #28]
800d4c8: 601a str r2, [r3, #0]
if( xShouldDelay != pdFALSE )
800d4ca: 6a7b ldr r3, [r7, #36] ; 0x24
800d4cc: 2b00 cmp r3, #0
800d4ce: d006 beq.n 800d4de <vTaskDelayUntil+0xd6>
{
traceTASK_DELAY_UNTIL( xTimeToWake );
/* prvAddCurrentTaskToDelayedList() needs the block time, not
the time to wake, so subtract the current tick count. */
prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
800d4d0: 69fa ldr r2, [r7, #28]
800d4d2: 6a3b ldr r3, [r7, #32]
800d4d4: 1ad3 subs r3, r2, r3
800d4d6: 2100 movs r1, #0
800d4d8: 4618 mov r0, r3
800d4da: f000 fe83 bl 800e1e4 <prvAddCurrentTaskToDelayedList>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
xAlreadyYielded = xTaskResumeAll();
800d4de: f000 f8bf bl 800d660 <xTaskResumeAll>
800d4e2: 61b8 str r0, [r7, #24]
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
800d4e4: 69bb ldr r3, [r7, #24]
800d4e6: 2b00 cmp r3, #0
800d4e8: d107 bne.n 800d4fa <vTaskDelayUntil+0xf2>
{
portYIELD_WITHIN_API();
800d4ea: 4b08 ldr r3, [pc, #32] ; (800d50c <vTaskDelayUntil+0x104>)
800d4ec: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d4f0: 601a str r2, [r3, #0]
800d4f2: f3bf 8f4f dsb sy
800d4f6: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800d4fa: bf00 nop
800d4fc: 3728 adds r7, #40 ; 0x28
800d4fe: 46bd mov sp, r7
800d500: bd80 pop {r7, pc}
800d502: bf00 nop
800d504: 200006a8 .word 0x200006a8
800d508: 20000684 .word 0x20000684
800d50c: e000ed04 .word 0xe000ed04
0800d510 <vTaskDelay>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelay == 1 )
void vTaskDelay( const TickType_t xTicksToDelay )
{
800d510: b580 push {r7, lr}
800d512: b084 sub sp, #16
800d514: af00 add r7, sp, #0
800d516: 6078 str r0, [r7, #4]
BaseType_t xAlreadyYielded = pdFALSE;
800d518: 2300 movs r3, #0
800d51a: 60fb str r3, [r7, #12]
/* A delay time of zero just forces a reschedule. */
if( xTicksToDelay > ( TickType_t ) 0U )
800d51c: 687b ldr r3, [r7, #4]
800d51e: 2b00 cmp r3, #0
800d520: d019 beq.n 800d556 <vTaskDelay+0x46>
{
configASSERT( uxSchedulerSuspended == 0 );
800d522: 4b14 ldr r3, [pc, #80] ; (800d574 <vTaskDelay+0x64>)
800d524: 681b ldr r3, [r3, #0]
800d526: 2b00 cmp r3, #0
800d528: d00c beq.n 800d544 <vTaskDelay+0x34>
__asm volatile
800d52a: f04f 0350 mov.w r3, #80 ; 0x50
800d52e: b672 cpsid i
800d530: f383 8811 msr BASEPRI, r3
800d534: f3bf 8f6f isb sy
800d538: f3bf 8f4f dsb sy
800d53c: b662 cpsie i
800d53e: 60bb str r3, [r7, #8]
}
800d540: bf00 nop
800d542: e7fe b.n 800d542 <vTaskDelay+0x32>
vTaskSuspendAll();
800d544: f000 f87e bl 800d644 <vTaskSuspendAll>
list or removed from the blocked list until the scheduler
is resumed.
This task cannot be in an event list as it is the currently
executing task. */
prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
800d548: 2100 movs r1, #0
800d54a: 6878 ldr r0, [r7, #4]
800d54c: f000 fe4a bl 800e1e4 <prvAddCurrentTaskToDelayedList>
}
xAlreadyYielded = xTaskResumeAll();
800d550: f000 f886 bl 800d660 <xTaskResumeAll>
800d554: 60f8 str r0, [r7, #12]
mtCOVERAGE_TEST_MARKER();
}
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
800d556: 68fb ldr r3, [r7, #12]
800d558: 2b00 cmp r3, #0
800d55a: d107 bne.n 800d56c <vTaskDelay+0x5c>
{
portYIELD_WITHIN_API();
800d55c: 4b06 ldr r3, [pc, #24] ; (800d578 <vTaskDelay+0x68>)
800d55e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d562: 601a str r2, [r3, #0]
800d564: f3bf 8f4f dsb sy
800d568: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800d56c: bf00 nop
800d56e: 3710 adds r7, #16
800d570: 46bd mov sp, r7
800d572: bd80 pop {r7, pc}
800d574: 200006a8 .word 0x200006a8
800d578: e000ed04 .word 0xe000ed04
0800d57c <vTaskStartScheduler>:
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/
void vTaskStartScheduler( void )
{
800d57c: b580 push {r7, lr}
800d57e: b08a sub sp, #40 ; 0x28
800d580: af04 add r7, sp, #16
BaseType_t xReturn;
/* Add the idle task at the lowest priority. */
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
StaticTask_t *pxIdleTaskTCBBuffer = NULL;
800d582: 2300 movs r3, #0
800d584: 60bb str r3, [r7, #8]
StackType_t *pxIdleTaskStackBuffer = NULL;
800d586: 2300 movs r3, #0
800d588: 607b str r3, [r7, #4]
uint32_t ulIdleTaskStackSize;
/* The Idle task is created using user provided RAM - obtain the
address of the RAM then create the idle task. */
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
800d58a: 463a mov r2, r7
800d58c: 1d39 adds r1, r7, #4
800d58e: f107 0308 add.w r3, r7, #8
800d592: 4618 mov r0, r3
800d594: f7f3 f822 bl 80005dc <vApplicationGetIdleTaskMemory>
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
800d598: 6839 ldr r1, [r7, #0]
800d59a: 687b ldr r3, [r7, #4]
800d59c: 68ba ldr r2, [r7, #8]
800d59e: 9202 str r2, [sp, #8]
800d5a0: 9301 str r3, [sp, #4]
800d5a2: 2300 movs r3, #0
800d5a4: 9300 str r3, [sp, #0]
800d5a6: 2300 movs r3, #0
800d5a8: 460a mov r2, r1
800d5aa: 4920 ldr r1, [pc, #128] ; (800d62c <vTaskStartScheduler+0xb0>)
800d5ac: 4820 ldr r0, [pc, #128] ; (800d630 <vTaskStartScheduler+0xb4>)
800d5ae: f7ff fcf3 bl 800cf98 <xTaskCreateStatic>
800d5b2: 4603 mov r3, r0
800d5b4: 4a1f ldr r2, [pc, #124] ; (800d634 <vTaskStartScheduler+0xb8>)
800d5b6: 6013 str r3, [r2, #0]
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
pxIdleTaskStackBuffer,
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
if( xIdleTaskHandle != NULL )
800d5b8: 4b1e ldr r3, [pc, #120] ; (800d634 <vTaskStartScheduler+0xb8>)
800d5ba: 681b ldr r3, [r3, #0]
800d5bc: 2b00 cmp r3, #0
800d5be: d002 beq.n 800d5c6 <vTaskStartScheduler+0x4a>
{
xReturn = pdPASS;
800d5c0: 2301 movs r3, #1
800d5c2: 617b str r3, [r7, #20]
800d5c4: e001 b.n 800d5ca <vTaskStartScheduler+0x4e>
}
else
{
xReturn = pdFAIL;
800d5c6: 2300 movs r3, #0
800d5c8: 617b str r3, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_TIMERS */
if( xReturn == pdPASS )
800d5ca: 697b ldr r3, [r7, #20]
800d5cc: 2b01 cmp r3, #1
800d5ce: d118 bne.n 800d602 <vTaskStartScheduler+0x86>
__asm volatile
800d5d0: f04f 0350 mov.w r3, #80 ; 0x50
800d5d4: b672 cpsid i
800d5d6: f383 8811 msr BASEPRI, r3
800d5da: f3bf 8f6f isb sy
800d5de: f3bf 8f4f dsb sy
800d5e2: b662 cpsie i
800d5e4: 613b str r3, [r7, #16]
}
800d5e6: bf00 nop
structure specific to the task that will run first. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
xNextTaskUnblockTime = portMAX_DELAY;
800d5e8: 4b13 ldr r3, [pc, #76] ; (800d638 <vTaskStartScheduler+0xbc>)
800d5ea: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800d5ee: 601a str r2, [r3, #0]
xSchedulerRunning = pdTRUE;
800d5f0: 4b12 ldr r3, [pc, #72] ; (800d63c <vTaskStartScheduler+0xc0>)
800d5f2: 2201 movs r2, #1
800d5f4: 601a str r2, [r3, #0]
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
800d5f6: 4b12 ldr r3, [pc, #72] ; (800d640 <vTaskStartScheduler+0xc4>)
800d5f8: 2200 movs r2, #0
800d5fa: 601a str r2, [r3, #0]
traceTASK_SWITCHED_IN();
/* Setting up the timer tick is hardware specific and thus in the
portable interface. */
if( xPortStartScheduler() != pdFALSE )
800d5fc: f000 fee8 bl 800e3d0 <xPortStartScheduler>
}
/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
meaning xIdleTaskHandle is not used anywhere else. */
( void ) xIdleTaskHandle;
}
800d600: e010 b.n 800d624 <vTaskStartScheduler+0xa8>
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
800d602: 697b ldr r3, [r7, #20]
800d604: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800d608: d10c bne.n 800d624 <vTaskStartScheduler+0xa8>
__asm volatile
800d60a: f04f 0350 mov.w r3, #80 ; 0x50
800d60e: b672 cpsid i
800d610: f383 8811 msr BASEPRI, r3
800d614: f3bf 8f6f isb sy
800d618: f3bf 8f4f dsb sy
800d61c: b662 cpsie i
800d61e: 60fb str r3, [r7, #12]
}
800d620: bf00 nop
800d622: e7fe b.n 800d622 <vTaskStartScheduler+0xa6>
}
800d624: bf00 nop
800d626: 3718 adds r7, #24
800d628: 46bd mov sp, r7
800d62a: bd80 pop {r7, pc}
800d62c: 0801c1a0 .word 0x0801c1a0
800d630: 0800dc7d .word 0x0800dc7d
800d634: 200006a4 .word 0x200006a4
800d638: 200006a0 .word 0x200006a0
800d63c: 2000068c .word 0x2000068c
800d640: 20000684 .word 0x20000684
0800d644 <vTaskSuspendAll>:
vPortEndScheduler();
}
/*----------------------------------------------------------*/
void vTaskSuspendAll( void )
{
800d644: b480 push {r7}
800d646: af00 add r7, sp, #0
/* A critical section is not required as the variable is of type
BaseType_t. Please read Richard Barry's reply in the following link to a
post in the FreeRTOS support forum before reporting this as a bug! -
http://goo.gl/wu4acr */
++uxSchedulerSuspended;
800d648: 4b04 ldr r3, [pc, #16] ; (800d65c <vTaskSuspendAll+0x18>)
800d64a: 681b ldr r3, [r3, #0]
800d64c: 3301 adds r3, #1
800d64e: 4a03 ldr r2, [pc, #12] ; (800d65c <vTaskSuspendAll+0x18>)
800d650: 6013 str r3, [r2, #0]
portMEMORY_BARRIER();
}
800d652: bf00 nop
800d654: 46bd mov sp, r7
800d656: f85d 7b04 ldr.w r7, [sp], #4
800d65a: 4770 bx lr
800d65c: 200006a8 .word 0x200006a8
0800d660 <xTaskResumeAll>:
#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/
BaseType_t xTaskResumeAll( void )
{
800d660: b580 push {r7, lr}
800d662: b084 sub sp, #16
800d664: af00 add r7, sp, #0
TCB_t *pxTCB = NULL;
800d666: 2300 movs r3, #0
800d668: 60fb str r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
800d66a: 2300 movs r3, #0
800d66c: 60bb str r3, [r7, #8]
/* If uxSchedulerSuspended is zero then this function does not match a
previous call to vTaskSuspendAll(). */
configASSERT( uxSchedulerSuspended );
800d66e: 4b42 ldr r3, [pc, #264] ; (800d778 <xTaskResumeAll+0x118>)
800d670: 681b ldr r3, [r3, #0]
800d672: 2b00 cmp r3, #0
800d674: d10c bne.n 800d690 <xTaskResumeAll+0x30>
__asm volatile
800d676: f04f 0350 mov.w r3, #80 ; 0x50
800d67a: b672 cpsid i
800d67c: f383 8811 msr BASEPRI, r3
800d680: f3bf 8f6f isb sy
800d684: f3bf 8f4f dsb sy
800d688: b662 cpsie i
800d68a: 603b str r3, [r7, #0]
}
800d68c: bf00 nop
800d68e: e7fe b.n 800d68e <xTaskResumeAll+0x2e>
/* It is possible that an ISR caused a task to be removed from an event
list while the scheduler was suspended. If this was the case then the
removed task will have been added to the xPendingReadyList. Once the
scheduler has been resumed it is safe to move all the pending ready
tasks from this list into their appropriate ready list. */
taskENTER_CRITICAL();
800d690: f000 ff1c bl 800e4cc <vPortEnterCritical>
{
--uxSchedulerSuspended;
800d694: 4b38 ldr r3, [pc, #224] ; (800d778 <xTaskResumeAll+0x118>)
800d696: 681b ldr r3, [r3, #0]
800d698: 3b01 subs r3, #1
800d69a: 4a37 ldr r2, [pc, #220] ; (800d778 <xTaskResumeAll+0x118>)
800d69c: 6013 str r3, [r2, #0]
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800d69e: 4b36 ldr r3, [pc, #216] ; (800d778 <xTaskResumeAll+0x118>)
800d6a0: 681b ldr r3, [r3, #0]
800d6a2: 2b00 cmp r3, #0
800d6a4: d161 bne.n 800d76a <xTaskResumeAll+0x10a>
{
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
800d6a6: 4b35 ldr r3, [pc, #212] ; (800d77c <xTaskResumeAll+0x11c>)
800d6a8: 681b ldr r3, [r3, #0]
800d6aa: 2b00 cmp r3, #0
800d6ac: d05d beq.n 800d76a <xTaskResumeAll+0x10a>
{
/* Move any readied tasks from the pending list into the
appropriate ready list. */
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
800d6ae: e02e b.n 800d70e <xTaskResumeAll+0xae>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800d6b0: 4b33 ldr r3, [pc, #204] ; (800d780 <xTaskResumeAll+0x120>)
800d6b2: 68db ldr r3, [r3, #12]
800d6b4: 68db ldr r3, [r3, #12]
800d6b6: 60fb str r3, [r7, #12]
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800d6b8: 68fb ldr r3, [r7, #12]
800d6ba: 3318 adds r3, #24
800d6bc: 4618 mov r0, r3
800d6be: f7fe fc51 bl 800bf64 <uxListRemove>
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800d6c2: 68fb ldr r3, [r7, #12]
800d6c4: 3304 adds r3, #4
800d6c6: 4618 mov r0, r3
800d6c8: f7fe fc4c bl 800bf64 <uxListRemove>
prvAddTaskToReadyList( pxTCB );
800d6cc: 68fb ldr r3, [r7, #12]
800d6ce: 6adb ldr r3, [r3, #44] ; 0x2c
800d6d0: 2201 movs r2, #1
800d6d2: 409a lsls r2, r3
800d6d4: 4b2b ldr r3, [pc, #172] ; (800d784 <xTaskResumeAll+0x124>)
800d6d6: 681b ldr r3, [r3, #0]
800d6d8: 4313 orrs r3, r2
800d6da: 4a2a ldr r2, [pc, #168] ; (800d784 <xTaskResumeAll+0x124>)
800d6dc: 6013 str r3, [r2, #0]
800d6de: 68fb ldr r3, [r7, #12]
800d6e0: 6ada ldr r2, [r3, #44] ; 0x2c
800d6e2: 4613 mov r3, r2
800d6e4: 009b lsls r3, r3, #2
800d6e6: 4413 add r3, r2
800d6e8: 009b lsls r3, r3, #2
800d6ea: 4a27 ldr r2, [pc, #156] ; (800d788 <xTaskResumeAll+0x128>)
800d6ec: 441a add r2, r3
800d6ee: 68fb ldr r3, [r7, #12]
800d6f0: 3304 adds r3, #4
800d6f2: 4619 mov r1, r3
800d6f4: 4610 mov r0, r2
800d6f6: f7fe fbd8 bl 800beaa <vListInsertEnd>
/* If the moved task has a priority higher than the current
task then a yield must be performed. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
800d6fa: 68fb ldr r3, [r7, #12]
800d6fc: 6ada ldr r2, [r3, #44] ; 0x2c
800d6fe: 4b23 ldr r3, [pc, #140] ; (800d78c <xTaskResumeAll+0x12c>)
800d700: 681b ldr r3, [r3, #0]
800d702: 6adb ldr r3, [r3, #44] ; 0x2c
800d704: 429a cmp r2, r3
800d706: d302 bcc.n 800d70e <xTaskResumeAll+0xae>
{
xYieldPending = pdTRUE;
800d708: 4b21 ldr r3, [pc, #132] ; (800d790 <xTaskResumeAll+0x130>)
800d70a: 2201 movs r2, #1
800d70c: 601a str r2, [r3, #0]
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
800d70e: 4b1c ldr r3, [pc, #112] ; (800d780 <xTaskResumeAll+0x120>)
800d710: 681b ldr r3, [r3, #0]
800d712: 2b00 cmp r3, #0
800d714: d1cc bne.n 800d6b0 <xTaskResumeAll+0x50>
{
mtCOVERAGE_TEST_MARKER();
}
}
if( pxTCB != NULL )
800d716: 68fb ldr r3, [r7, #12]
800d718: 2b00 cmp r3, #0
800d71a: d001 beq.n 800d720 <xTaskResumeAll+0xc0>
which may have prevented the next unblock time from being
re-calculated, in which case re-calculate it now. Mainly
important for low power tickless implementations, where
this can prevent an unnecessary exit from low power
state. */
prvResetNextTaskUnblockTime();
800d71c: f000 fb68 bl 800ddf0 <prvResetNextTaskUnblockTime>
/* If any ticks occurred while the scheduler was suspended then
they should be processed now. This ensures the tick count does
not slip, and that any delayed tasks are resumed at the correct
time. */
{
UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
800d720: 4b1c ldr r3, [pc, #112] ; (800d794 <xTaskResumeAll+0x134>)
800d722: 681b ldr r3, [r3, #0]
800d724: 607b str r3, [r7, #4]
if( uxPendedCounts > ( UBaseType_t ) 0U )
800d726: 687b ldr r3, [r7, #4]
800d728: 2b00 cmp r3, #0
800d72a: d010 beq.n 800d74e <xTaskResumeAll+0xee>
{
do
{
if( xTaskIncrementTick() != pdFALSE )
800d72c: f000 f858 bl 800d7e0 <xTaskIncrementTick>
800d730: 4603 mov r3, r0
800d732: 2b00 cmp r3, #0
800d734: d002 beq.n 800d73c <xTaskResumeAll+0xdc>
{
xYieldPending = pdTRUE;
800d736: 4b16 ldr r3, [pc, #88] ; (800d790 <xTaskResumeAll+0x130>)
800d738: 2201 movs r2, #1
800d73a: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
--uxPendedCounts;
800d73c: 687b ldr r3, [r7, #4]
800d73e: 3b01 subs r3, #1
800d740: 607b str r3, [r7, #4]
} while( uxPendedCounts > ( UBaseType_t ) 0U );
800d742: 687b ldr r3, [r7, #4]
800d744: 2b00 cmp r3, #0
800d746: d1f1 bne.n 800d72c <xTaskResumeAll+0xcc>
uxPendedTicks = 0;
800d748: 4b12 ldr r3, [pc, #72] ; (800d794 <xTaskResumeAll+0x134>)
800d74a: 2200 movs r2, #0
800d74c: 601a str r2, [r3, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
if( xYieldPending != pdFALSE )
800d74e: 4b10 ldr r3, [pc, #64] ; (800d790 <xTaskResumeAll+0x130>)
800d750: 681b ldr r3, [r3, #0]
800d752: 2b00 cmp r3, #0
800d754: d009 beq.n 800d76a <xTaskResumeAll+0x10a>
{
#if( configUSE_PREEMPTION != 0 )
{
xAlreadyYielded = pdTRUE;
800d756: 2301 movs r3, #1
800d758: 60bb str r3, [r7, #8]
}
#endif
taskYIELD_IF_USING_PREEMPTION();
800d75a: 4b0f ldr r3, [pc, #60] ; (800d798 <xTaskResumeAll+0x138>)
800d75c: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d760: 601a str r2, [r3, #0]
800d762: f3bf 8f4f dsb sy
800d766: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
800d76a: f000 fee3 bl 800e534 <vPortExitCritical>
return xAlreadyYielded;
800d76e: 68bb ldr r3, [r7, #8]
}
800d770: 4618 mov r0, r3
800d772: 3710 adds r7, #16
800d774: 46bd mov sp, r7
800d776: bd80 pop {r7, pc}
800d778: 200006a8 .word 0x200006a8
800d77c: 20000680 .word 0x20000680
800d780: 20000640 .word 0x20000640
800d784: 20000688 .word 0x20000688
800d788: 20000584 .word 0x20000584
800d78c: 20000580 .word 0x20000580
800d790: 20000694 .word 0x20000694
800d794: 20000690 .word 0x20000690
800d798: e000ed04 .word 0xe000ed04
0800d79c <xTaskGetTickCount>:
/*-----------------------------------------------------------*/
TickType_t xTaskGetTickCount( void )
{
800d79c: b480 push {r7}
800d79e: b083 sub sp, #12
800d7a0: af00 add r7, sp, #0
TickType_t xTicks;
/* Critical section required if running on a 16 bit processor. */
portTICK_TYPE_ENTER_CRITICAL();
{
xTicks = xTickCount;
800d7a2: 4b05 ldr r3, [pc, #20] ; (800d7b8 <xTaskGetTickCount+0x1c>)
800d7a4: 681b ldr r3, [r3, #0]
800d7a6: 607b str r3, [r7, #4]
}
portTICK_TYPE_EXIT_CRITICAL();
return xTicks;
800d7a8: 687b ldr r3, [r7, #4]
}
800d7aa: 4618 mov r0, r3
800d7ac: 370c adds r7, #12
800d7ae: 46bd mov sp, r7
800d7b0: f85d 7b04 ldr.w r7, [sp], #4
800d7b4: 4770 bx lr
800d7b6: bf00 nop
800d7b8: 20000684 .word 0x20000684
0800d7bc <xTaskGetTickCountFromISR>:
/*-----------------------------------------------------------*/
TickType_t xTaskGetTickCountFromISR( void )
{
800d7bc: b580 push {r7, lr}
800d7be: b082 sub sp, #8
800d7c0: af00 add r7, sp, #0
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800d7c2: f000 ff6b bl 800e69c <vPortValidateInterruptPriority>
uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
800d7c6: 2300 movs r3, #0
800d7c8: 607b str r3, [r7, #4]
{
xReturn = xTickCount;
800d7ca: 4b04 ldr r3, [pc, #16] ; (800d7dc <xTaskGetTickCountFromISR+0x20>)
800d7cc: 681b ldr r3, [r3, #0]
800d7ce: 603b str r3, [r7, #0]
}
portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800d7d0: 683b ldr r3, [r7, #0]
}
800d7d2: 4618 mov r0, r3
800d7d4: 3708 adds r7, #8
800d7d6: 46bd mov sp, r7
800d7d8: bd80 pop {r7, pc}
800d7da: bf00 nop
800d7dc: 20000684 .word 0x20000684
0800d7e0 <xTaskIncrementTick>:
#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/
BaseType_t xTaskIncrementTick( void )
{
800d7e0: b580 push {r7, lr}
800d7e2: b086 sub sp, #24
800d7e4: af00 add r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
800d7e6: 2300 movs r3, #0
800d7e8: 617b str r3, [r7, #20]
/* Called by the portable layer each time a tick interrupt occurs.
Increments the tick then checks to see if the new tick value will cause any
tasks to be unblocked. */
traceTASK_INCREMENT_TICK( xTickCount );
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800d7ea: 4b4f ldr r3, [pc, #316] ; (800d928 <xTaskIncrementTick+0x148>)
800d7ec: 681b ldr r3, [r3, #0]
800d7ee: 2b00 cmp r3, #0
800d7f0: f040 808a bne.w 800d908 <xTaskIncrementTick+0x128>
{
/* Minor optimisation. The tick count cannot change in this
block. */
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
800d7f4: 4b4d ldr r3, [pc, #308] ; (800d92c <xTaskIncrementTick+0x14c>)
800d7f6: 681b ldr r3, [r3, #0]
800d7f8: 3301 adds r3, #1
800d7fa: 613b str r3, [r7, #16]
/* Increment the RTOS tick, switching the delayed and overflowed
delayed lists if it wraps to 0. */
xTickCount = xConstTickCount;
800d7fc: 4a4b ldr r2, [pc, #300] ; (800d92c <xTaskIncrementTick+0x14c>)
800d7fe: 693b ldr r3, [r7, #16]
800d800: 6013 str r3, [r2, #0]
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
800d802: 693b ldr r3, [r7, #16]
800d804: 2b00 cmp r3, #0
800d806: d122 bne.n 800d84e <xTaskIncrementTick+0x6e>
{
taskSWITCH_DELAYED_LISTS();
800d808: 4b49 ldr r3, [pc, #292] ; (800d930 <xTaskIncrementTick+0x150>)
800d80a: 681b ldr r3, [r3, #0]
800d80c: 681b ldr r3, [r3, #0]
800d80e: 2b00 cmp r3, #0
800d810: d00c beq.n 800d82c <xTaskIncrementTick+0x4c>
__asm volatile
800d812: f04f 0350 mov.w r3, #80 ; 0x50
800d816: b672 cpsid i
800d818: f383 8811 msr BASEPRI, r3
800d81c: f3bf 8f6f isb sy
800d820: f3bf 8f4f dsb sy
800d824: b662 cpsie i
800d826: 603b str r3, [r7, #0]
}
800d828: bf00 nop
800d82a: e7fe b.n 800d82a <xTaskIncrementTick+0x4a>
800d82c: 4b40 ldr r3, [pc, #256] ; (800d930 <xTaskIncrementTick+0x150>)
800d82e: 681b ldr r3, [r3, #0]
800d830: 60fb str r3, [r7, #12]
800d832: 4b40 ldr r3, [pc, #256] ; (800d934 <xTaskIncrementTick+0x154>)
800d834: 681b ldr r3, [r3, #0]
800d836: 4a3e ldr r2, [pc, #248] ; (800d930 <xTaskIncrementTick+0x150>)
800d838: 6013 str r3, [r2, #0]
800d83a: 4a3e ldr r2, [pc, #248] ; (800d934 <xTaskIncrementTick+0x154>)
800d83c: 68fb ldr r3, [r7, #12]
800d83e: 6013 str r3, [r2, #0]
800d840: 4b3d ldr r3, [pc, #244] ; (800d938 <xTaskIncrementTick+0x158>)
800d842: 681b ldr r3, [r3, #0]
800d844: 3301 adds r3, #1
800d846: 4a3c ldr r2, [pc, #240] ; (800d938 <xTaskIncrementTick+0x158>)
800d848: 6013 str r3, [r2, #0]
800d84a: f000 fad1 bl 800ddf0 <prvResetNextTaskUnblockTime>
/* See if this tick has made a timeout expire. Tasks are stored in
the queue in the order of their wake time - meaning once one task
has been found whose block time has not expired there is no need to
look any further down the list. */
if( xConstTickCount >= xNextTaskUnblockTime )
800d84e: 4b3b ldr r3, [pc, #236] ; (800d93c <xTaskIncrementTick+0x15c>)
800d850: 681b ldr r3, [r3, #0]
800d852: 693a ldr r2, [r7, #16]
800d854: 429a cmp r2, r3
800d856: d348 bcc.n 800d8ea <xTaskIncrementTick+0x10a>
{
for( ;; )
{
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800d858: 4b35 ldr r3, [pc, #212] ; (800d930 <xTaskIncrementTick+0x150>)
800d85a: 681b ldr r3, [r3, #0]
800d85c: 681b ldr r3, [r3, #0]
800d85e: 2b00 cmp r3, #0
800d860: d104 bne.n 800d86c <xTaskIncrementTick+0x8c>
/* The delayed list is empty. Set xNextTaskUnblockTime
to the maximum possible value so it is extremely
unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass
next time through. */
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800d862: 4b36 ldr r3, [pc, #216] ; (800d93c <xTaskIncrementTick+0x15c>)
800d864: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800d868: 601a str r2, [r3, #0]
break;
800d86a: e03e b.n 800d8ea <xTaskIncrementTick+0x10a>
{
/* The delayed list is not empty, get the value of the
item at the head of the delayed list. This is the time
at which the task at the head of the delayed list must
be removed from the Blocked state. */
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800d86c: 4b30 ldr r3, [pc, #192] ; (800d930 <xTaskIncrementTick+0x150>)
800d86e: 681b ldr r3, [r3, #0]
800d870: 68db ldr r3, [r3, #12]
800d872: 68db ldr r3, [r3, #12]
800d874: 60bb str r3, [r7, #8]
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
800d876: 68bb ldr r3, [r7, #8]
800d878: 685b ldr r3, [r3, #4]
800d87a: 607b str r3, [r7, #4]
if( xConstTickCount < xItemValue )
800d87c: 693a ldr r2, [r7, #16]
800d87e: 687b ldr r3, [r7, #4]
800d880: 429a cmp r2, r3
800d882: d203 bcs.n 800d88c <xTaskIncrementTick+0xac>
/* It is not time to unblock this item yet, but the
item value is the time at which the task at the head
of the blocked list must be removed from the Blocked
state - so record the item value in
xNextTaskUnblockTime. */
xNextTaskUnblockTime = xItemValue;
800d884: 4a2d ldr r2, [pc, #180] ; (800d93c <xTaskIncrementTick+0x15c>)
800d886: 687b ldr r3, [r7, #4]
800d888: 6013 str r3, [r2, #0]
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
800d88a: e02e b.n 800d8ea <xTaskIncrementTick+0x10a>
{
mtCOVERAGE_TEST_MARKER();
}
/* It is time to remove the item from the Blocked state. */
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800d88c: 68bb ldr r3, [r7, #8]
800d88e: 3304 adds r3, #4
800d890: 4618 mov r0, r3
800d892: f7fe fb67 bl 800bf64 <uxListRemove>
/* Is the task waiting on an event also? If so remove
it from the event list. */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
800d896: 68bb ldr r3, [r7, #8]
800d898: 6a9b ldr r3, [r3, #40] ; 0x28
800d89a: 2b00 cmp r3, #0
800d89c: d004 beq.n 800d8a8 <xTaskIncrementTick+0xc8>
{
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800d89e: 68bb ldr r3, [r7, #8]
800d8a0: 3318 adds r3, #24
800d8a2: 4618 mov r0, r3
800d8a4: f7fe fb5e bl 800bf64 <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
/* Place the unblocked task into the appropriate ready
list. */
prvAddTaskToReadyList( pxTCB );
800d8a8: 68bb ldr r3, [r7, #8]
800d8aa: 6adb ldr r3, [r3, #44] ; 0x2c
800d8ac: 2201 movs r2, #1
800d8ae: 409a lsls r2, r3
800d8b0: 4b23 ldr r3, [pc, #140] ; (800d940 <xTaskIncrementTick+0x160>)
800d8b2: 681b ldr r3, [r3, #0]
800d8b4: 4313 orrs r3, r2
800d8b6: 4a22 ldr r2, [pc, #136] ; (800d940 <xTaskIncrementTick+0x160>)
800d8b8: 6013 str r3, [r2, #0]
800d8ba: 68bb ldr r3, [r7, #8]
800d8bc: 6ada ldr r2, [r3, #44] ; 0x2c
800d8be: 4613 mov r3, r2
800d8c0: 009b lsls r3, r3, #2
800d8c2: 4413 add r3, r2
800d8c4: 009b lsls r3, r3, #2
800d8c6: 4a1f ldr r2, [pc, #124] ; (800d944 <xTaskIncrementTick+0x164>)
800d8c8: 441a add r2, r3
800d8ca: 68bb ldr r3, [r7, #8]
800d8cc: 3304 adds r3, #4
800d8ce: 4619 mov r1, r3
800d8d0: 4610 mov r0, r2
800d8d2: f7fe faea bl 800beaa <vListInsertEnd>
{
/* Preemption is on, but a context switch should
only be performed if the unblocked task has a
priority that is equal to or higher than the
currently executing task. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
800d8d6: 68bb ldr r3, [r7, #8]
800d8d8: 6ada ldr r2, [r3, #44] ; 0x2c
800d8da: 4b1b ldr r3, [pc, #108] ; (800d948 <xTaskIncrementTick+0x168>)
800d8dc: 681b ldr r3, [r3, #0]
800d8de: 6adb ldr r3, [r3, #44] ; 0x2c
800d8e0: 429a cmp r2, r3
800d8e2: d3b9 bcc.n 800d858 <xTaskIncrementTick+0x78>
{
xSwitchRequired = pdTRUE;
800d8e4: 2301 movs r3, #1
800d8e6: 617b str r3, [r7, #20]
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800d8e8: e7b6 b.n 800d858 <xTaskIncrementTick+0x78>
/* Tasks of equal priority to the currently running task will share
processing time (time slice) if preemption is on, and the application
writer has not explicitly turned time slicing off. */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
{
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
800d8ea: 4b17 ldr r3, [pc, #92] ; (800d948 <xTaskIncrementTick+0x168>)
800d8ec: 681b ldr r3, [r3, #0]
800d8ee: 6ada ldr r2, [r3, #44] ; 0x2c
800d8f0: 4914 ldr r1, [pc, #80] ; (800d944 <xTaskIncrementTick+0x164>)
800d8f2: 4613 mov r3, r2
800d8f4: 009b lsls r3, r3, #2
800d8f6: 4413 add r3, r2
800d8f8: 009b lsls r3, r3, #2
800d8fa: 440b add r3, r1
800d8fc: 681b ldr r3, [r3, #0]
800d8fe: 2b01 cmp r3, #1
800d900: d907 bls.n 800d912 <xTaskIncrementTick+0x132>
{
xSwitchRequired = pdTRUE;
800d902: 2301 movs r3, #1
800d904: 617b str r3, [r7, #20]
800d906: e004 b.n 800d912 <xTaskIncrementTick+0x132>
}
#endif /* configUSE_TICK_HOOK */
}
else
{
++uxPendedTicks;
800d908: 4b10 ldr r3, [pc, #64] ; (800d94c <xTaskIncrementTick+0x16c>)
800d90a: 681b ldr r3, [r3, #0]
800d90c: 3301 adds r3, #1
800d90e: 4a0f ldr r2, [pc, #60] ; (800d94c <xTaskIncrementTick+0x16c>)
800d910: 6013 str r3, [r2, #0]
#endif
}
#if ( configUSE_PREEMPTION == 1 )
{
if( xYieldPending != pdFALSE )
800d912: 4b0f ldr r3, [pc, #60] ; (800d950 <xTaskIncrementTick+0x170>)
800d914: 681b ldr r3, [r3, #0]
800d916: 2b00 cmp r3, #0
800d918: d001 beq.n 800d91e <xTaskIncrementTick+0x13e>
{
xSwitchRequired = pdTRUE;
800d91a: 2301 movs r3, #1
800d91c: 617b str r3, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_PREEMPTION */
return xSwitchRequired;
800d91e: 697b ldr r3, [r7, #20]
}
800d920: 4618 mov r0, r3
800d922: 3718 adds r7, #24
800d924: 46bd mov sp, r7
800d926: bd80 pop {r7, pc}
800d928: 200006a8 .word 0x200006a8
800d92c: 20000684 .word 0x20000684
800d930: 20000638 .word 0x20000638
800d934: 2000063c .word 0x2000063c
800d938: 20000698 .word 0x20000698
800d93c: 200006a0 .word 0x200006a0
800d940: 20000688 .word 0x20000688
800d944: 20000584 .word 0x20000584
800d948: 20000580 .word 0x20000580
800d94c: 20000690 .word 0x20000690
800d950: 20000694 .word 0x20000694
0800d954 <vTaskSwitchContext>:
#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/
void vTaskSwitchContext( void )
{
800d954: b580 push {r7, lr}
800d956: b088 sub sp, #32
800d958: af00 add r7, sp, #0
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
800d95a: 4b3a ldr r3, [pc, #232] ; (800da44 <vTaskSwitchContext+0xf0>)
800d95c: 681b ldr r3, [r3, #0]
800d95e: 2b00 cmp r3, #0
800d960: d003 beq.n 800d96a <vTaskSwitchContext+0x16>
{
/* The scheduler is currently suspended - do not allow a context
switch. */
xYieldPending = pdTRUE;
800d962: 4b39 ldr r3, [pc, #228] ; (800da48 <vTaskSwitchContext+0xf4>)
800d964: 2201 movs r2, #1
800d966: 601a str r2, [r3, #0]
structure specific to this task. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
}
}
800d968: e068 b.n 800da3c <vTaskSwitchContext+0xe8>
xYieldPending = pdFALSE;
800d96a: 4b37 ldr r3, [pc, #220] ; (800da48 <vTaskSwitchContext+0xf4>)
800d96c: 2200 movs r2, #0
800d96e: 601a str r2, [r3, #0]
taskCHECK_FOR_STACK_OVERFLOW();
800d970: 4b36 ldr r3, [pc, #216] ; (800da4c <vTaskSwitchContext+0xf8>)
800d972: 681b ldr r3, [r3, #0]
800d974: 6b1b ldr r3, [r3, #48] ; 0x30
800d976: 61fb str r3, [r7, #28]
800d978: f04f 33a5 mov.w r3, #2779096485 ; 0xa5a5a5a5
800d97c: 61bb str r3, [r7, #24]
800d97e: 69fb ldr r3, [r7, #28]
800d980: 681b ldr r3, [r3, #0]
800d982: 69ba ldr r2, [r7, #24]
800d984: 429a cmp r2, r3
800d986: d111 bne.n 800d9ac <vTaskSwitchContext+0x58>
800d988: 69fb ldr r3, [r7, #28]
800d98a: 3304 adds r3, #4
800d98c: 681b ldr r3, [r3, #0]
800d98e: 69ba ldr r2, [r7, #24]
800d990: 429a cmp r2, r3
800d992: d10b bne.n 800d9ac <vTaskSwitchContext+0x58>
800d994: 69fb ldr r3, [r7, #28]
800d996: 3308 adds r3, #8
800d998: 681b ldr r3, [r3, #0]
800d99a: 69ba ldr r2, [r7, #24]
800d99c: 429a cmp r2, r3
800d99e: d105 bne.n 800d9ac <vTaskSwitchContext+0x58>
800d9a0: 69fb ldr r3, [r7, #28]
800d9a2: 330c adds r3, #12
800d9a4: 681b ldr r3, [r3, #0]
800d9a6: 69ba ldr r2, [r7, #24]
800d9a8: 429a cmp r2, r3
800d9aa: d008 beq.n 800d9be <vTaskSwitchContext+0x6a>
800d9ac: 4b27 ldr r3, [pc, #156] ; (800da4c <vTaskSwitchContext+0xf8>)
800d9ae: 681a ldr r2, [r3, #0]
800d9b0: 4b26 ldr r3, [pc, #152] ; (800da4c <vTaskSwitchContext+0xf8>)
800d9b2: 681b ldr r3, [r3, #0]
800d9b4: 3334 adds r3, #52 ; 0x34
800d9b6: 4619 mov r1, r3
800d9b8: 4610 mov r0, r2
800d9ba: f7f2 fdfc bl 80005b6 <vApplicationStackOverflowHook>
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800d9be: 4b24 ldr r3, [pc, #144] ; (800da50 <vTaskSwitchContext+0xfc>)
800d9c0: 681b ldr r3, [r3, #0]
800d9c2: 60fb str r3, [r7, #12]
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
800d9c4: 68fb ldr r3, [r7, #12]
800d9c6: fab3 f383 clz r3, r3
800d9ca: 72fb strb r3, [r7, #11]
return ucReturn;
800d9cc: 7afb ldrb r3, [r7, #11]
800d9ce: f1c3 031f rsb r3, r3, #31
800d9d2: 617b str r3, [r7, #20]
800d9d4: 491f ldr r1, [pc, #124] ; (800da54 <vTaskSwitchContext+0x100>)
800d9d6: 697a ldr r2, [r7, #20]
800d9d8: 4613 mov r3, r2
800d9da: 009b lsls r3, r3, #2
800d9dc: 4413 add r3, r2
800d9de: 009b lsls r3, r3, #2
800d9e0: 440b add r3, r1
800d9e2: 681b ldr r3, [r3, #0]
800d9e4: 2b00 cmp r3, #0
800d9e6: d10c bne.n 800da02 <vTaskSwitchContext+0xae>
__asm volatile
800d9e8: f04f 0350 mov.w r3, #80 ; 0x50
800d9ec: b672 cpsid i
800d9ee: f383 8811 msr BASEPRI, r3
800d9f2: f3bf 8f6f isb sy
800d9f6: f3bf 8f4f dsb sy
800d9fa: b662 cpsie i
800d9fc: 607b str r3, [r7, #4]
}
800d9fe: bf00 nop
800da00: e7fe b.n 800da00 <vTaskSwitchContext+0xac>
800da02: 697a ldr r2, [r7, #20]
800da04: 4613 mov r3, r2
800da06: 009b lsls r3, r3, #2
800da08: 4413 add r3, r2
800da0a: 009b lsls r3, r3, #2
800da0c: 4a11 ldr r2, [pc, #68] ; (800da54 <vTaskSwitchContext+0x100>)
800da0e: 4413 add r3, r2
800da10: 613b str r3, [r7, #16]
800da12: 693b ldr r3, [r7, #16]
800da14: 685b ldr r3, [r3, #4]
800da16: 685a ldr r2, [r3, #4]
800da18: 693b ldr r3, [r7, #16]
800da1a: 605a str r2, [r3, #4]
800da1c: 693b ldr r3, [r7, #16]
800da1e: 685a ldr r2, [r3, #4]
800da20: 693b ldr r3, [r7, #16]
800da22: 3308 adds r3, #8
800da24: 429a cmp r2, r3
800da26: d104 bne.n 800da32 <vTaskSwitchContext+0xde>
800da28: 693b ldr r3, [r7, #16]
800da2a: 685b ldr r3, [r3, #4]
800da2c: 685a ldr r2, [r3, #4]
800da2e: 693b ldr r3, [r7, #16]
800da30: 605a str r2, [r3, #4]
800da32: 693b ldr r3, [r7, #16]
800da34: 685b ldr r3, [r3, #4]
800da36: 68db ldr r3, [r3, #12]
800da38: 4a04 ldr r2, [pc, #16] ; (800da4c <vTaskSwitchContext+0xf8>)
800da3a: 6013 str r3, [r2, #0]
}
800da3c: bf00 nop
800da3e: 3720 adds r7, #32
800da40: 46bd mov sp, r7
800da42: bd80 pop {r7, pc}
800da44: 200006a8 .word 0x200006a8
800da48: 20000694 .word 0x20000694
800da4c: 20000580 .word 0x20000580
800da50: 20000688 .word 0x20000688
800da54: 20000584 .word 0x20000584
0800da58 <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
800da58: b580 push {r7, lr}
800da5a: b084 sub sp, #16
800da5c: af00 add r7, sp, #0
800da5e: 6078 str r0, [r7, #4]
800da60: 6039 str r1, [r7, #0]
configASSERT( pxEventList );
800da62: 687b ldr r3, [r7, #4]
800da64: 2b00 cmp r3, #0
800da66: d10c bne.n 800da82 <vTaskPlaceOnEventList+0x2a>
__asm volatile
800da68: f04f 0350 mov.w r3, #80 ; 0x50
800da6c: b672 cpsid i
800da6e: f383 8811 msr BASEPRI, r3
800da72: f3bf 8f6f isb sy
800da76: f3bf 8f4f dsb sy
800da7a: b662 cpsie i
800da7c: 60fb str r3, [r7, #12]
}
800da7e: bf00 nop
800da80: e7fe b.n 800da80 <vTaskPlaceOnEventList+0x28>
/* Place the event list item of the TCB in the appropriate event list.
This is placed in the list in priority order so the highest priority task
is the first to be woken by the event. The queue that contains the event
list is locked, preventing simultaneous access from interrupts. */
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
800da82: 4b07 ldr r3, [pc, #28] ; (800daa0 <vTaskPlaceOnEventList+0x48>)
800da84: 681b ldr r3, [r3, #0]
800da86: 3318 adds r3, #24
800da88: 4619 mov r1, r3
800da8a: 6878 ldr r0, [r7, #4]
800da8c: f7fe fa31 bl 800bef2 <vListInsert>
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
800da90: 2101 movs r1, #1
800da92: 6838 ldr r0, [r7, #0]
800da94: f000 fba6 bl 800e1e4 <prvAddCurrentTaskToDelayedList>
}
800da98: bf00 nop
800da9a: 3710 adds r7, #16
800da9c: 46bd mov sp, r7
800da9e: bd80 pop {r7, pc}
800daa0: 20000580 .word 0x20000580
0800daa4 <xTaskRemoveFromEventList>:
#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
800daa4: b580 push {r7, lr}
800daa6: b086 sub sp, #24
800daa8: af00 add r7, sp, #0
800daaa: 6078 str r0, [r7, #4]
get called - the lock count on the queue will get modified instead. This
means exclusive access to the event list is guaranteed here.
This function assumes that a check has already been made to ensure that
pxEventList is not empty. */
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800daac: 687b ldr r3, [r7, #4]
800daae: 68db ldr r3, [r3, #12]
800dab0: 68db ldr r3, [r3, #12]
800dab2: 613b str r3, [r7, #16]
configASSERT( pxUnblockedTCB );
800dab4: 693b ldr r3, [r7, #16]
800dab6: 2b00 cmp r3, #0
800dab8: d10c bne.n 800dad4 <xTaskRemoveFromEventList+0x30>
__asm volatile
800daba: f04f 0350 mov.w r3, #80 ; 0x50
800dabe: b672 cpsid i
800dac0: f383 8811 msr BASEPRI, r3
800dac4: f3bf 8f6f isb sy
800dac8: f3bf 8f4f dsb sy
800dacc: b662 cpsie i
800dace: 60fb str r3, [r7, #12]
}
800dad0: bf00 nop
800dad2: e7fe b.n 800dad2 <xTaskRemoveFromEventList+0x2e>
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
800dad4: 693b ldr r3, [r7, #16]
800dad6: 3318 adds r3, #24
800dad8: 4618 mov r0, r3
800dada: f7fe fa43 bl 800bf64 <uxListRemove>
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800dade: 4b1d ldr r3, [pc, #116] ; (800db54 <xTaskRemoveFromEventList+0xb0>)
800dae0: 681b ldr r3, [r3, #0]
800dae2: 2b00 cmp r3, #0
800dae4: d11c bne.n 800db20 <xTaskRemoveFromEventList+0x7c>
{
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
800dae6: 693b ldr r3, [r7, #16]
800dae8: 3304 adds r3, #4
800daea: 4618 mov r0, r3
800daec: f7fe fa3a bl 800bf64 <uxListRemove>
prvAddTaskToReadyList( pxUnblockedTCB );
800daf0: 693b ldr r3, [r7, #16]
800daf2: 6adb ldr r3, [r3, #44] ; 0x2c
800daf4: 2201 movs r2, #1
800daf6: 409a lsls r2, r3
800daf8: 4b17 ldr r3, [pc, #92] ; (800db58 <xTaskRemoveFromEventList+0xb4>)
800dafa: 681b ldr r3, [r3, #0]
800dafc: 4313 orrs r3, r2
800dafe: 4a16 ldr r2, [pc, #88] ; (800db58 <xTaskRemoveFromEventList+0xb4>)
800db00: 6013 str r3, [r2, #0]
800db02: 693b ldr r3, [r7, #16]
800db04: 6ada ldr r2, [r3, #44] ; 0x2c
800db06: 4613 mov r3, r2
800db08: 009b lsls r3, r3, #2
800db0a: 4413 add r3, r2
800db0c: 009b lsls r3, r3, #2
800db0e: 4a13 ldr r2, [pc, #76] ; (800db5c <xTaskRemoveFromEventList+0xb8>)
800db10: 441a add r2, r3
800db12: 693b ldr r3, [r7, #16]
800db14: 3304 adds r3, #4
800db16: 4619 mov r1, r3
800db18: 4610 mov r0, r2
800db1a: f7fe f9c6 bl 800beaa <vListInsertEnd>
800db1e: e005 b.n 800db2c <xTaskRemoveFromEventList+0x88>
}
else
{
/* The delayed and ready lists cannot be accessed, so hold this task
pending until the scheduler is resumed. */
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
800db20: 693b ldr r3, [r7, #16]
800db22: 3318 adds r3, #24
800db24: 4619 mov r1, r3
800db26: 480e ldr r0, [pc, #56] ; (800db60 <xTaskRemoveFromEventList+0xbc>)
800db28: f7fe f9bf bl 800beaa <vListInsertEnd>
}
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
800db2c: 693b ldr r3, [r7, #16]
800db2e: 6ada ldr r2, [r3, #44] ; 0x2c
800db30: 4b0c ldr r3, [pc, #48] ; (800db64 <xTaskRemoveFromEventList+0xc0>)
800db32: 681b ldr r3, [r3, #0]
800db34: 6adb ldr r3, [r3, #44] ; 0x2c
800db36: 429a cmp r2, r3
800db38: d905 bls.n 800db46 <xTaskRemoveFromEventList+0xa2>
{
/* Return true if the task removed from the event list has a higher
priority than the calling task. This allows the calling task to know if
it should force a context switch now. */
xReturn = pdTRUE;
800db3a: 2301 movs r3, #1
800db3c: 617b str r3, [r7, #20]
/* Mark that a yield is pending in case the user is not using the
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
xYieldPending = pdTRUE;
800db3e: 4b0a ldr r3, [pc, #40] ; (800db68 <xTaskRemoveFromEventList+0xc4>)
800db40: 2201 movs r2, #1
800db42: 601a str r2, [r3, #0]
800db44: e001 b.n 800db4a <xTaskRemoveFromEventList+0xa6>
}
else
{
xReturn = pdFALSE;
800db46: 2300 movs r3, #0
800db48: 617b str r3, [r7, #20]
}
return xReturn;
800db4a: 697b ldr r3, [r7, #20]
}
800db4c: 4618 mov r0, r3
800db4e: 3718 adds r7, #24
800db50: 46bd mov sp, r7
800db52: bd80 pop {r7, pc}
800db54: 200006a8 .word 0x200006a8
800db58: 20000688 .word 0x20000688
800db5c: 20000584 .word 0x20000584
800db60: 20000640 .word 0x20000640
800db64: 20000580 .word 0x20000580
800db68: 20000694 .word 0x20000694
0800db6c <vTaskInternalSetTimeOutState>:
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
800db6c: b480 push {r7}
800db6e: b083 sub sp, #12
800db70: af00 add r7, sp, #0
800db72: 6078 str r0, [r7, #4]
/* For internal use only as it does not use a critical section. */
pxTimeOut->xOverflowCount = xNumOfOverflows;
800db74: 4b06 ldr r3, [pc, #24] ; (800db90 <vTaskInternalSetTimeOutState+0x24>)
800db76: 681a ldr r2, [r3, #0]
800db78: 687b ldr r3, [r7, #4]
800db7a: 601a str r2, [r3, #0]
pxTimeOut->xTimeOnEntering = xTickCount;
800db7c: 4b05 ldr r3, [pc, #20] ; (800db94 <vTaskInternalSetTimeOutState+0x28>)
800db7e: 681a ldr r2, [r3, #0]
800db80: 687b ldr r3, [r7, #4]
800db82: 605a str r2, [r3, #4]
}
800db84: bf00 nop
800db86: 370c adds r7, #12
800db88: 46bd mov sp, r7
800db8a: f85d 7b04 ldr.w r7, [sp], #4
800db8e: 4770 bx lr
800db90: 20000698 .word 0x20000698
800db94: 20000684 .word 0x20000684
0800db98 <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
800db98: b580 push {r7, lr}
800db9a: b088 sub sp, #32
800db9c: af00 add r7, sp, #0
800db9e: 6078 str r0, [r7, #4]
800dba0: 6039 str r1, [r7, #0]
BaseType_t xReturn;
configASSERT( pxTimeOut );
800dba2: 687b ldr r3, [r7, #4]
800dba4: 2b00 cmp r3, #0
800dba6: d10c bne.n 800dbc2 <xTaskCheckForTimeOut+0x2a>
__asm volatile
800dba8: f04f 0350 mov.w r3, #80 ; 0x50
800dbac: b672 cpsid i
800dbae: f383 8811 msr BASEPRI, r3
800dbb2: f3bf 8f6f isb sy
800dbb6: f3bf 8f4f dsb sy
800dbba: b662 cpsie i
800dbbc: 613b str r3, [r7, #16]
}
800dbbe: bf00 nop
800dbc0: e7fe b.n 800dbc0 <xTaskCheckForTimeOut+0x28>
configASSERT( pxTicksToWait );
800dbc2: 683b ldr r3, [r7, #0]
800dbc4: 2b00 cmp r3, #0
800dbc6: d10c bne.n 800dbe2 <xTaskCheckForTimeOut+0x4a>
__asm volatile
800dbc8: f04f 0350 mov.w r3, #80 ; 0x50
800dbcc: b672 cpsid i
800dbce: f383 8811 msr BASEPRI, r3
800dbd2: f3bf 8f6f isb sy
800dbd6: f3bf 8f4f dsb sy
800dbda: b662 cpsie i
800dbdc: 60fb str r3, [r7, #12]
}
800dbde: bf00 nop
800dbe0: e7fe b.n 800dbe0 <xTaskCheckForTimeOut+0x48>
taskENTER_CRITICAL();
800dbe2: f000 fc73 bl 800e4cc <vPortEnterCritical>
{
/* Minor optimisation. The tick count cannot change in this block. */
const TickType_t xConstTickCount = xTickCount;
800dbe6: 4b1d ldr r3, [pc, #116] ; (800dc5c <xTaskCheckForTimeOut+0xc4>)
800dbe8: 681b ldr r3, [r3, #0]
800dbea: 61bb str r3, [r7, #24]
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
800dbec: 687b ldr r3, [r7, #4]
800dbee: 685b ldr r3, [r3, #4]
800dbf0: 69ba ldr r2, [r7, #24]
800dbf2: 1ad3 subs r3, r2, r3
800dbf4: 617b str r3, [r7, #20]
}
else
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
if( *pxTicksToWait == portMAX_DELAY )
800dbf6: 683b ldr r3, [r7, #0]
800dbf8: 681b ldr r3, [r3, #0]
800dbfa: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800dbfe: d102 bne.n 800dc06 <xTaskCheckForTimeOut+0x6e>
{
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
specified is the maximum block time then the task should block
indefinitely, and therefore never time out. */
xReturn = pdFALSE;
800dc00: 2300 movs r3, #0
800dc02: 61fb str r3, [r7, #28]
800dc04: e023 b.n 800dc4e <xTaskCheckForTimeOut+0xb6>
}
else
#endif
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
800dc06: 687b ldr r3, [r7, #4]
800dc08: 681a ldr r2, [r3, #0]
800dc0a: 4b15 ldr r3, [pc, #84] ; (800dc60 <xTaskCheckForTimeOut+0xc8>)
800dc0c: 681b ldr r3, [r3, #0]
800dc0e: 429a cmp r2, r3
800dc10: d007 beq.n 800dc22 <xTaskCheckForTimeOut+0x8a>
800dc12: 687b ldr r3, [r7, #4]
800dc14: 685b ldr r3, [r3, #4]
800dc16: 69ba ldr r2, [r7, #24]
800dc18: 429a cmp r2, r3
800dc1a: d302 bcc.n 800dc22 <xTaskCheckForTimeOut+0x8a>
/* The tick count is greater than the time at which
vTaskSetTimeout() was called, but has also overflowed since
vTaskSetTimeOut() was called. It must have wrapped all the way
around and gone past again. This passed since vTaskSetTimeout()
was called. */
xReturn = pdTRUE;
800dc1c: 2301 movs r3, #1
800dc1e: 61fb str r3, [r7, #28]
800dc20: e015 b.n 800dc4e <xTaskCheckForTimeOut+0xb6>
}
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
800dc22: 683b ldr r3, [r7, #0]
800dc24: 681b ldr r3, [r3, #0]
800dc26: 697a ldr r2, [r7, #20]
800dc28: 429a cmp r2, r3
800dc2a: d20b bcs.n 800dc44 <xTaskCheckForTimeOut+0xac>
{
/* Not a genuine timeout. Adjust parameters for time remaining. */
*pxTicksToWait -= xElapsedTime;
800dc2c: 683b ldr r3, [r7, #0]
800dc2e: 681a ldr r2, [r3, #0]
800dc30: 697b ldr r3, [r7, #20]
800dc32: 1ad2 subs r2, r2, r3
800dc34: 683b ldr r3, [r7, #0]
800dc36: 601a str r2, [r3, #0]
vTaskInternalSetTimeOutState( pxTimeOut );
800dc38: 6878 ldr r0, [r7, #4]
800dc3a: f7ff ff97 bl 800db6c <vTaskInternalSetTimeOutState>
xReturn = pdFALSE;
800dc3e: 2300 movs r3, #0
800dc40: 61fb str r3, [r7, #28]
800dc42: e004 b.n 800dc4e <xTaskCheckForTimeOut+0xb6>
}
else
{
*pxTicksToWait = 0;
800dc44: 683b ldr r3, [r7, #0]
800dc46: 2200 movs r2, #0
800dc48: 601a str r2, [r3, #0]
xReturn = pdTRUE;
800dc4a: 2301 movs r3, #1
800dc4c: 61fb str r3, [r7, #28]
}
}
taskEXIT_CRITICAL();
800dc4e: f000 fc71 bl 800e534 <vPortExitCritical>
return xReturn;
800dc52: 69fb ldr r3, [r7, #28]
}
800dc54: 4618 mov r0, r3
800dc56: 3720 adds r7, #32
800dc58: 46bd mov sp, r7
800dc5a: bd80 pop {r7, pc}
800dc5c: 20000684 .word 0x20000684
800dc60: 20000698 .word 0x20000698
0800dc64 <vTaskMissedYield>:
/*-----------------------------------------------------------*/
void vTaskMissedYield( void )
{
800dc64: b480 push {r7}
800dc66: af00 add r7, sp, #0
xYieldPending = pdTRUE;
800dc68: 4b03 ldr r3, [pc, #12] ; (800dc78 <vTaskMissedYield+0x14>)
800dc6a: 2201 movs r2, #1
800dc6c: 601a str r2, [r3, #0]
}
800dc6e: bf00 nop
800dc70: 46bd mov sp, r7
800dc72: f85d 7b04 ldr.w r7, [sp], #4
800dc76: 4770 bx lr
800dc78: 20000694 .word 0x20000694
0800dc7c <prvIdleTask>:
*
* void prvIdleTask( void *pvParameters );
*
*/
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
800dc7c: b580 push {r7, lr}
800dc7e: b082 sub sp, #8
800dc80: af00 add r7, sp, #0
800dc82: 6078 str r0, [r7, #4]
for( ;; )
{
/* See if any tasks have deleted themselves - if so then the idle task
is responsible for freeing the deleted task's TCB and stack. */
prvCheckTasksWaitingTermination();
800dc84: f000 f854 bl 800dd30 <prvCheckTasksWaitingTermination>
A critical region is not required here as we are just reading from
the list, and an occasional incorrect value will not matter. If
the ready list at the idle priority contains more than one task
then a task other than the idle task is ready to execute. */
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
800dc88: 4b07 ldr r3, [pc, #28] ; (800dca8 <prvIdleTask+0x2c>)
800dc8a: 681b ldr r3, [r3, #0]
800dc8c: 2b01 cmp r3, #1
800dc8e: d907 bls.n 800dca0 <prvIdleTask+0x24>
{
taskYIELD();
800dc90: 4b06 ldr r3, [pc, #24] ; (800dcac <prvIdleTask+0x30>)
800dc92: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800dc96: 601a str r2, [r3, #0]
800dc98: f3bf 8f4f dsb sy
800dc9c: f3bf 8f6f isb sy
/* Call the user defined function from within the idle task. This
allows the application designer to add background functionality
without the overhead of a separate task.
NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
CALL A FUNCTION THAT MIGHT BLOCK. */
vApplicationIdleHook();
800dca0: f7f2 fc82 bl 80005a8 <vApplicationIdleHook>
prvCheckTasksWaitingTermination();
800dca4: e7ee b.n 800dc84 <prvIdleTask+0x8>
800dca6: bf00 nop
800dca8: 20000584 .word 0x20000584
800dcac: e000ed04 .word 0xe000ed04
0800dcb0 <prvInitialiseTaskLists>:
#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/
static void prvInitialiseTaskLists( void )
{
800dcb0: b580 push {r7, lr}
800dcb2: b082 sub sp, #8
800dcb4: af00 add r7, sp, #0
UBaseType_t uxPriority;
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
800dcb6: 2300 movs r3, #0
800dcb8: 607b str r3, [r7, #4]
800dcba: e00c b.n 800dcd6 <prvInitialiseTaskLists+0x26>
{
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
800dcbc: 687a ldr r2, [r7, #4]
800dcbe: 4613 mov r3, r2
800dcc0: 009b lsls r3, r3, #2
800dcc2: 4413 add r3, r2
800dcc4: 009b lsls r3, r3, #2
800dcc6: 4a12 ldr r2, [pc, #72] ; (800dd10 <prvInitialiseTaskLists+0x60>)
800dcc8: 4413 add r3, r2
800dcca: 4618 mov r0, r3
800dccc: f7fe f8c0 bl 800be50 <vListInitialise>
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
800dcd0: 687b ldr r3, [r7, #4]
800dcd2: 3301 adds r3, #1
800dcd4: 607b str r3, [r7, #4]
800dcd6: 687b ldr r3, [r7, #4]
800dcd8: 2b06 cmp r3, #6
800dcda: d9ef bls.n 800dcbc <prvInitialiseTaskLists+0xc>
}
vListInitialise( &xDelayedTaskList1 );
800dcdc: 480d ldr r0, [pc, #52] ; (800dd14 <prvInitialiseTaskLists+0x64>)
800dcde: f7fe f8b7 bl 800be50 <vListInitialise>
vListInitialise( &xDelayedTaskList2 );
800dce2: 480d ldr r0, [pc, #52] ; (800dd18 <prvInitialiseTaskLists+0x68>)
800dce4: f7fe f8b4 bl 800be50 <vListInitialise>
vListInitialise( &xPendingReadyList );
800dce8: 480c ldr r0, [pc, #48] ; (800dd1c <prvInitialiseTaskLists+0x6c>)
800dcea: f7fe f8b1 bl 800be50 <vListInitialise>
#if ( INCLUDE_vTaskDelete == 1 )
{
vListInitialise( &xTasksWaitingTermination );
800dcee: 480c ldr r0, [pc, #48] ; (800dd20 <prvInitialiseTaskLists+0x70>)
800dcf0: f7fe f8ae bl 800be50 <vListInitialise>
}
#endif /* INCLUDE_vTaskDelete */
#if ( INCLUDE_vTaskSuspend == 1 )
{
vListInitialise( &xSuspendedTaskList );
800dcf4: 480b ldr r0, [pc, #44] ; (800dd24 <prvInitialiseTaskLists+0x74>)
800dcf6: f7fe f8ab bl 800be50 <vListInitialise>
}
#endif /* INCLUDE_vTaskSuspend */
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
using list2. */
pxDelayedTaskList = &xDelayedTaskList1;
800dcfa: 4b0b ldr r3, [pc, #44] ; (800dd28 <prvInitialiseTaskLists+0x78>)
800dcfc: 4a05 ldr r2, [pc, #20] ; (800dd14 <prvInitialiseTaskLists+0x64>)
800dcfe: 601a str r2, [r3, #0]
pxOverflowDelayedTaskList = &xDelayedTaskList2;
800dd00: 4b0a ldr r3, [pc, #40] ; (800dd2c <prvInitialiseTaskLists+0x7c>)
800dd02: 4a05 ldr r2, [pc, #20] ; (800dd18 <prvInitialiseTaskLists+0x68>)
800dd04: 601a str r2, [r3, #0]
}
800dd06: bf00 nop
800dd08: 3708 adds r7, #8
800dd0a: 46bd mov sp, r7
800dd0c: bd80 pop {r7, pc}
800dd0e: bf00 nop
800dd10: 20000584 .word 0x20000584
800dd14: 20000610 .word 0x20000610
800dd18: 20000624 .word 0x20000624
800dd1c: 20000640 .word 0x20000640
800dd20: 20000654 .word 0x20000654
800dd24: 2000066c .word 0x2000066c
800dd28: 20000638 .word 0x20000638
800dd2c: 2000063c .word 0x2000063c
0800dd30 <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/
static void prvCheckTasksWaitingTermination( void )
{
800dd30: b580 push {r7, lr}
800dd32: b082 sub sp, #8
800dd34: af00 add r7, sp, #0
{
TCB_t *pxTCB;
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
being called too often in the idle task. */
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
800dd36: e019 b.n 800dd6c <prvCheckTasksWaitingTermination+0x3c>
{
taskENTER_CRITICAL();
800dd38: f000 fbc8 bl 800e4cc <vPortEnterCritical>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800dd3c: 4b10 ldr r3, [pc, #64] ; (800dd80 <prvCheckTasksWaitingTermination+0x50>)
800dd3e: 68db ldr r3, [r3, #12]
800dd40: 68db ldr r3, [r3, #12]
800dd42: 607b str r3, [r7, #4]
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800dd44: 687b ldr r3, [r7, #4]
800dd46: 3304 adds r3, #4
800dd48: 4618 mov r0, r3
800dd4a: f7fe f90b bl 800bf64 <uxListRemove>
--uxCurrentNumberOfTasks;
800dd4e: 4b0d ldr r3, [pc, #52] ; (800dd84 <prvCheckTasksWaitingTermination+0x54>)
800dd50: 681b ldr r3, [r3, #0]
800dd52: 3b01 subs r3, #1
800dd54: 4a0b ldr r2, [pc, #44] ; (800dd84 <prvCheckTasksWaitingTermination+0x54>)
800dd56: 6013 str r3, [r2, #0]
--uxDeletedTasksWaitingCleanUp;
800dd58: 4b0b ldr r3, [pc, #44] ; (800dd88 <prvCheckTasksWaitingTermination+0x58>)
800dd5a: 681b ldr r3, [r3, #0]
800dd5c: 3b01 subs r3, #1
800dd5e: 4a0a ldr r2, [pc, #40] ; (800dd88 <prvCheckTasksWaitingTermination+0x58>)
800dd60: 6013 str r3, [r2, #0]
}
taskEXIT_CRITICAL();
800dd62: f000 fbe7 bl 800e534 <vPortExitCritical>
prvDeleteTCB( pxTCB );
800dd66: 6878 ldr r0, [r7, #4]
800dd68: f000 f810 bl 800dd8c <prvDeleteTCB>
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
800dd6c: 4b06 ldr r3, [pc, #24] ; (800dd88 <prvCheckTasksWaitingTermination+0x58>)
800dd6e: 681b ldr r3, [r3, #0]
800dd70: 2b00 cmp r3, #0
800dd72: d1e1 bne.n 800dd38 <prvCheckTasksWaitingTermination+0x8>
}
}
#endif /* INCLUDE_vTaskDelete */
}
800dd74: bf00 nop
800dd76: bf00 nop
800dd78: 3708 adds r7, #8
800dd7a: 46bd mov sp, r7
800dd7c: bd80 pop {r7, pc}
800dd7e: bf00 nop
800dd80: 20000654 .word 0x20000654
800dd84: 20000680 .word 0x20000680
800dd88: 20000668 .word 0x20000668
0800dd8c <prvDeleteTCB>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
static void prvDeleteTCB( TCB_t *pxTCB )
{
800dd8c: b580 push {r7, lr}
800dd8e: b084 sub sp, #16
800dd90: af00 add r7, sp, #0
800dd92: 6078 str r0, [r7, #4]
#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* The task could have been allocated statically or dynamically, so
check what was statically allocated before trying to free the
memory. */
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
800dd94: 687b ldr r3, [r7, #4]
800dd96: f893 3055 ldrb.w r3, [r3, #85] ; 0x55
800dd9a: 2b00 cmp r3, #0
800dd9c: d108 bne.n 800ddb0 <prvDeleteTCB+0x24>
{
/* Both the stack and TCB were allocated dynamically, so both
must be freed. */
vPortFree( pxTCB->pxStack );
800dd9e: 687b ldr r3, [r7, #4]
800dda0: 6b1b ldr r3, [r3, #48] ; 0x30
800dda2: 4618 mov r0, r3
800dda4: f000 fd8e bl 800e8c4 <vPortFree>
vPortFree( pxTCB );
800dda8: 6878 ldr r0, [r7, #4]
800ddaa: f000 fd8b bl 800e8c4 <vPortFree>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
800ddae: e01a b.n 800dde6 <prvDeleteTCB+0x5a>
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
800ddb0: 687b ldr r3, [r7, #4]
800ddb2: f893 3055 ldrb.w r3, [r3, #85] ; 0x55
800ddb6: 2b01 cmp r3, #1
800ddb8: d103 bne.n 800ddc2 <prvDeleteTCB+0x36>
vPortFree( pxTCB );
800ddba: 6878 ldr r0, [r7, #4]
800ddbc: f000 fd82 bl 800e8c4 <vPortFree>
}
800ddc0: e011 b.n 800dde6 <prvDeleteTCB+0x5a>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
800ddc2: 687b ldr r3, [r7, #4]
800ddc4: f893 3055 ldrb.w r3, [r3, #85] ; 0x55
800ddc8: 2b02 cmp r3, #2
800ddca: d00c beq.n 800dde6 <prvDeleteTCB+0x5a>
__asm volatile
800ddcc: f04f 0350 mov.w r3, #80 ; 0x50
800ddd0: b672 cpsid i
800ddd2: f383 8811 msr BASEPRI, r3
800ddd6: f3bf 8f6f isb sy
800ddda: f3bf 8f4f dsb sy
800ddde: b662 cpsie i
800dde0: 60fb str r3, [r7, #12]
}
800dde2: bf00 nop
800dde4: e7fe b.n 800dde4 <prvDeleteTCB+0x58>
}
800dde6: bf00 nop
800dde8: 3710 adds r7, #16
800ddea: 46bd mov sp, r7
800ddec: bd80 pop {r7, pc}
...
0800ddf0 <prvResetNextTaskUnblockTime>:
#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/
static void prvResetNextTaskUnblockTime( void )
{
800ddf0: b480 push {r7}
800ddf2: b083 sub sp, #12
800ddf4: af00 add r7, sp, #0
TCB_t *pxTCB;
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800ddf6: 4b0c ldr r3, [pc, #48] ; (800de28 <prvResetNextTaskUnblockTime+0x38>)
800ddf8: 681b ldr r3, [r3, #0]
800ddfa: 681b ldr r3, [r3, #0]
800ddfc: 2b00 cmp r3, #0
800ddfe: d104 bne.n 800de0a <prvResetNextTaskUnblockTime+0x1a>
{
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
the maximum possible value so it is extremely unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
there is an item in the delayed list. */
xNextTaskUnblockTime = portMAX_DELAY;
800de00: 4b0a ldr r3, [pc, #40] ; (800de2c <prvResetNextTaskUnblockTime+0x3c>)
800de02: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800de06: 601a str r2, [r3, #0]
which the task at the head of the delayed list should be removed
from the Blocked state. */
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
}
}
800de08: e008 b.n 800de1c <prvResetNextTaskUnblockTime+0x2c>
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800de0a: 4b07 ldr r3, [pc, #28] ; (800de28 <prvResetNextTaskUnblockTime+0x38>)
800de0c: 681b ldr r3, [r3, #0]
800de0e: 68db ldr r3, [r3, #12]
800de10: 68db ldr r3, [r3, #12]
800de12: 607b str r3, [r7, #4]
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
800de14: 687b ldr r3, [r7, #4]
800de16: 685b ldr r3, [r3, #4]
800de18: 4a04 ldr r2, [pc, #16] ; (800de2c <prvResetNextTaskUnblockTime+0x3c>)
800de1a: 6013 str r3, [r2, #0]
}
800de1c: bf00 nop
800de1e: 370c adds r7, #12
800de20: 46bd mov sp, r7
800de22: f85d 7b04 ldr.w r7, [sp], #4
800de26: 4770 bx lr
800de28: 20000638 .word 0x20000638
800de2c: 200006a0 .word 0x200006a0
0800de30 <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
BaseType_t xTaskGetSchedulerState( void )
{
800de30: b480 push {r7}
800de32: b083 sub sp, #12
800de34: af00 add r7, sp, #0
BaseType_t xReturn;
if( xSchedulerRunning == pdFALSE )
800de36: 4b0b ldr r3, [pc, #44] ; (800de64 <xTaskGetSchedulerState+0x34>)
800de38: 681b ldr r3, [r3, #0]
800de3a: 2b00 cmp r3, #0
800de3c: d102 bne.n 800de44 <xTaskGetSchedulerState+0x14>
{
xReturn = taskSCHEDULER_NOT_STARTED;
800de3e: 2301 movs r3, #1
800de40: 607b str r3, [r7, #4]
800de42: e008 b.n 800de56 <xTaskGetSchedulerState+0x26>
}
else
{
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800de44: 4b08 ldr r3, [pc, #32] ; (800de68 <xTaskGetSchedulerState+0x38>)
800de46: 681b ldr r3, [r3, #0]
800de48: 2b00 cmp r3, #0
800de4a: d102 bne.n 800de52 <xTaskGetSchedulerState+0x22>
{
xReturn = taskSCHEDULER_RUNNING;
800de4c: 2302 movs r3, #2
800de4e: 607b str r3, [r7, #4]
800de50: e001 b.n 800de56 <xTaskGetSchedulerState+0x26>
}
else
{
xReturn = taskSCHEDULER_SUSPENDED;
800de52: 2300 movs r3, #0
800de54: 607b str r3, [r7, #4]
}
}
return xReturn;
800de56: 687b ldr r3, [r7, #4]
}
800de58: 4618 mov r0, r3
800de5a: 370c adds r7, #12
800de5c: 46bd mov sp, r7
800de5e: f85d 7b04 ldr.w r7, [sp], #4
800de62: 4770 bx lr
800de64: 2000068c .word 0x2000068c
800de68: 200006a8 .word 0x200006a8
0800de6c <xTaskPriorityInherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
{
800de6c: b580 push {r7, lr}
800de6e: b084 sub sp, #16
800de70: af00 add r7, sp, #0
800de72: 6078 str r0, [r7, #4]
TCB_t * const pxMutexHolderTCB = pxMutexHolder;
800de74: 687b ldr r3, [r7, #4]
800de76: 60bb str r3, [r7, #8]
BaseType_t xReturn = pdFALSE;
800de78: 2300 movs r3, #0
800de7a: 60fb str r3, [r7, #12]
/* If the mutex was given back by an interrupt while the queue was
locked then the mutex holder might now be NULL. _RB_ Is this still
needed as interrupts can no longer use mutexes? */
if( pxMutexHolder != NULL )
800de7c: 687b ldr r3, [r7, #4]
800de7e: 2b00 cmp r3, #0
800de80: d069 beq.n 800df56 <xTaskPriorityInherit+0xea>
{
/* If the holder of the mutex has a priority below the priority of
the task attempting to obtain the mutex then it will temporarily
inherit the priority of the task attempting to obtain the mutex. */
if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
800de82: 68bb ldr r3, [r7, #8]
800de84: 6ada ldr r2, [r3, #44] ; 0x2c
800de86: 4b36 ldr r3, [pc, #216] ; (800df60 <xTaskPriorityInherit+0xf4>)
800de88: 681b ldr r3, [r3, #0]
800de8a: 6adb ldr r3, [r3, #44] ; 0x2c
800de8c: 429a cmp r2, r3
800de8e: d259 bcs.n 800df44 <xTaskPriorityInherit+0xd8>
{
/* Adjust the mutex holder state to account for its new
priority. Only reset the event list item value if the value is
not being used for anything else. */
if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
800de90: 68bb ldr r3, [r7, #8]
800de92: 699b ldr r3, [r3, #24]
800de94: 2b00 cmp r3, #0
800de96: db06 blt.n 800dea6 <xTaskPriorityInherit+0x3a>
{
listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800de98: 4b31 ldr r3, [pc, #196] ; (800df60 <xTaskPriorityInherit+0xf4>)
800de9a: 681b ldr r3, [r3, #0]
800de9c: 6adb ldr r3, [r3, #44] ; 0x2c
800de9e: f1c3 0207 rsb r2, r3, #7
800dea2: 68bb ldr r3, [r7, #8]
800dea4: 619a str r2, [r3, #24]
mtCOVERAGE_TEST_MARKER();
}
/* If the task being modified is in the ready state it will need
to be moved into a new list. */
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
800dea6: 68bb ldr r3, [r7, #8]
800dea8: 6959 ldr r1, [r3, #20]
800deaa: 68bb ldr r3, [r7, #8]
800deac: 6ada ldr r2, [r3, #44] ; 0x2c
800deae: 4613 mov r3, r2
800deb0: 009b lsls r3, r3, #2
800deb2: 4413 add r3, r2
800deb4: 009b lsls r3, r3, #2
800deb6: 4a2b ldr r2, [pc, #172] ; (800df64 <xTaskPriorityInherit+0xf8>)
800deb8: 4413 add r3, r2
800deba: 4299 cmp r1, r3
800debc: d13a bne.n 800df34 <xTaskPriorityInherit+0xc8>
{
if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800debe: 68bb ldr r3, [r7, #8]
800dec0: 3304 adds r3, #4
800dec2: 4618 mov r0, r3
800dec4: f7fe f84e bl 800bf64 <uxListRemove>
800dec8: 4603 mov r3, r0
800deca: 2b00 cmp r3, #0
800decc: d115 bne.n 800defa <xTaskPriorityInherit+0x8e>
{
taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
800dece: 68bb ldr r3, [r7, #8]
800ded0: 6ada ldr r2, [r3, #44] ; 0x2c
800ded2: 4924 ldr r1, [pc, #144] ; (800df64 <xTaskPriorityInherit+0xf8>)
800ded4: 4613 mov r3, r2
800ded6: 009b lsls r3, r3, #2
800ded8: 4413 add r3, r2
800deda: 009b lsls r3, r3, #2
800dedc: 440b add r3, r1
800dede: 681b ldr r3, [r3, #0]
800dee0: 2b00 cmp r3, #0
800dee2: d10a bne.n 800defa <xTaskPriorityInherit+0x8e>
800dee4: 68bb ldr r3, [r7, #8]
800dee6: 6adb ldr r3, [r3, #44] ; 0x2c
800dee8: 2201 movs r2, #1
800deea: fa02 f303 lsl.w r3, r2, r3
800deee: 43da mvns r2, r3
800def0: 4b1d ldr r3, [pc, #116] ; (800df68 <xTaskPriorityInherit+0xfc>)
800def2: 681b ldr r3, [r3, #0]
800def4: 4013 ands r3, r2
800def6: 4a1c ldr r2, [pc, #112] ; (800df68 <xTaskPriorityInherit+0xfc>)
800def8: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
/* Inherit the priority before being moved into the new list. */
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
800defa: 4b19 ldr r3, [pc, #100] ; (800df60 <xTaskPriorityInherit+0xf4>)
800defc: 681b ldr r3, [r3, #0]
800defe: 6ada ldr r2, [r3, #44] ; 0x2c
800df00: 68bb ldr r3, [r7, #8]
800df02: 62da str r2, [r3, #44] ; 0x2c
prvAddTaskToReadyList( pxMutexHolderTCB );
800df04: 68bb ldr r3, [r7, #8]
800df06: 6adb ldr r3, [r3, #44] ; 0x2c
800df08: 2201 movs r2, #1
800df0a: 409a lsls r2, r3
800df0c: 4b16 ldr r3, [pc, #88] ; (800df68 <xTaskPriorityInherit+0xfc>)
800df0e: 681b ldr r3, [r3, #0]
800df10: 4313 orrs r3, r2
800df12: 4a15 ldr r2, [pc, #84] ; (800df68 <xTaskPriorityInherit+0xfc>)
800df14: 6013 str r3, [r2, #0]
800df16: 68bb ldr r3, [r7, #8]
800df18: 6ada ldr r2, [r3, #44] ; 0x2c
800df1a: 4613 mov r3, r2
800df1c: 009b lsls r3, r3, #2
800df1e: 4413 add r3, r2
800df20: 009b lsls r3, r3, #2
800df22: 4a10 ldr r2, [pc, #64] ; (800df64 <xTaskPriorityInherit+0xf8>)
800df24: 441a add r2, r3
800df26: 68bb ldr r3, [r7, #8]
800df28: 3304 adds r3, #4
800df2a: 4619 mov r1, r3
800df2c: 4610 mov r0, r2
800df2e: f7fd ffbc bl 800beaa <vListInsertEnd>
800df32: e004 b.n 800df3e <xTaskPriorityInherit+0xd2>
}
else
{
/* Just inherit the priority. */
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
800df34: 4b0a ldr r3, [pc, #40] ; (800df60 <xTaskPriorityInherit+0xf4>)
800df36: 681b ldr r3, [r3, #0]
800df38: 6ada ldr r2, [r3, #44] ; 0x2c
800df3a: 68bb ldr r3, [r7, #8]
800df3c: 62da str r2, [r3, #44] ; 0x2c
}
traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
/* Inheritance occurred. */
xReturn = pdTRUE;
800df3e: 2301 movs r3, #1
800df40: 60fb str r3, [r7, #12]
800df42: e008 b.n 800df56 <xTaskPriorityInherit+0xea>
}
else
{
if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
800df44: 68bb ldr r3, [r7, #8]
800df46: 6c5a ldr r2, [r3, #68] ; 0x44
800df48: 4b05 ldr r3, [pc, #20] ; (800df60 <xTaskPriorityInherit+0xf4>)
800df4a: 681b ldr r3, [r3, #0]
800df4c: 6adb ldr r3, [r3, #44] ; 0x2c
800df4e: 429a cmp r2, r3
800df50: d201 bcs.n 800df56 <xTaskPriorityInherit+0xea>
current priority of the mutex holder is not lower than the
priority of the task attempting to take the mutex.
Therefore the mutex holder must have already inherited a
priority, but inheritance would have occurred if that had
not been the case. */
xReturn = pdTRUE;
800df52: 2301 movs r3, #1
800df54: 60fb str r3, [r7, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
800df56: 68fb ldr r3, [r7, #12]
}
800df58: 4618 mov r0, r3
800df5a: 3710 adds r7, #16
800df5c: 46bd mov sp, r7
800df5e: bd80 pop {r7, pc}
800df60: 20000580 .word 0x20000580
800df64: 20000584 .word 0x20000584
800df68: 20000688 .word 0x20000688
0800df6c <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
{
800df6c: b580 push {r7, lr}
800df6e: b086 sub sp, #24
800df70: af00 add r7, sp, #0
800df72: 6078 str r0, [r7, #4]
TCB_t * const pxTCB = pxMutexHolder;
800df74: 687b ldr r3, [r7, #4]
800df76: 613b str r3, [r7, #16]
BaseType_t xReturn = pdFALSE;
800df78: 2300 movs r3, #0
800df7a: 617b str r3, [r7, #20]
if( pxMutexHolder != NULL )
800df7c: 687b ldr r3, [r7, #4]
800df7e: 2b00 cmp r3, #0
800df80: d072 beq.n 800e068 <xTaskPriorityDisinherit+0xfc>
{
/* A task can only have an inherited priority if it holds the mutex.
If the mutex is held by a task then it cannot be given from an
interrupt, and if a mutex is given by the holding task then it must
be the running state task. */
configASSERT( pxTCB == pxCurrentTCB );
800df82: 4b3c ldr r3, [pc, #240] ; (800e074 <xTaskPriorityDisinherit+0x108>)
800df84: 681b ldr r3, [r3, #0]
800df86: 693a ldr r2, [r7, #16]
800df88: 429a cmp r2, r3
800df8a: d00c beq.n 800dfa6 <xTaskPriorityDisinherit+0x3a>
__asm volatile
800df8c: f04f 0350 mov.w r3, #80 ; 0x50
800df90: b672 cpsid i
800df92: f383 8811 msr BASEPRI, r3
800df96: f3bf 8f6f isb sy
800df9a: f3bf 8f4f dsb sy
800df9e: b662 cpsie i
800dfa0: 60fb str r3, [r7, #12]
}
800dfa2: bf00 nop
800dfa4: e7fe b.n 800dfa4 <xTaskPriorityDisinherit+0x38>
configASSERT( pxTCB->uxMutexesHeld );
800dfa6: 693b ldr r3, [r7, #16]
800dfa8: 6c9b ldr r3, [r3, #72] ; 0x48
800dfaa: 2b00 cmp r3, #0
800dfac: d10c bne.n 800dfc8 <xTaskPriorityDisinherit+0x5c>
__asm volatile
800dfae: f04f 0350 mov.w r3, #80 ; 0x50
800dfb2: b672 cpsid i
800dfb4: f383 8811 msr BASEPRI, r3
800dfb8: f3bf 8f6f isb sy
800dfbc: f3bf 8f4f dsb sy
800dfc0: b662 cpsie i
800dfc2: 60bb str r3, [r7, #8]
}
800dfc4: bf00 nop
800dfc6: e7fe b.n 800dfc6 <xTaskPriorityDisinherit+0x5a>
( pxTCB->uxMutexesHeld )--;
800dfc8: 693b ldr r3, [r7, #16]
800dfca: 6c9b ldr r3, [r3, #72] ; 0x48
800dfcc: 1e5a subs r2, r3, #1
800dfce: 693b ldr r3, [r7, #16]
800dfd0: 649a str r2, [r3, #72] ; 0x48
/* Has the holder of the mutex inherited the priority of another
task? */
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
800dfd2: 693b ldr r3, [r7, #16]
800dfd4: 6ada ldr r2, [r3, #44] ; 0x2c
800dfd6: 693b ldr r3, [r7, #16]
800dfd8: 6c5b ldr r3, [r3, #68] ; 0x44
800dfda: 429a cmp r2, r3
800dfdc: d044 beq.n 800e068 <xTaskPriorityDisinherit+0xfc>
{
/* Only disinherit if no other mutexes are held. */
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
800dfde: 693b ldr r3, [r7, #16]
800dfe0: 6c9b ldr r3, [r3, #72] ; 0x48
800dfe2: 2b00 cmp r3, #0
800dfe4: d140 bne.n 800e068 <xTaskPriorityDisinherit+0xfc>
/* A task can only have an inherited priority if it holds
the mutex. If the mutex is held by a task then it cannot be
given from an interrupt, and if a mutex is given by the
holding task then it must be the running state task. Remove
the holding task from the ready list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800dfe6: 693b ldr r3, [r7, #16]
800dfe8: 3304 adds r3, #4
800dfea: 4618 mov r0, r3
800dfec: f7fd ffba bl 800bf64 <uxListRemove>
800dff0: 4603 mov r3, r0
800dff2: 2b00 cmp r3, #0
800dff4: d115 bne.n 800e022 <xTaskPriorityDisinherit+0xb6>
{
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
800dff6: 693b ldr r3, [r7, #16]
800dff8: 6ada ldr r2, [r3, #44] ; 0x2c
800dffa: 491f ldr r1, [pc, #124] ; (800e078 <xTaskPriorityDisinherit+0x10c>)
800dffc: 4613 mov r3, r2
800dffe: 009b lsls r3, r3, #2
800e000: 4413 add r3, r2
800e002: 009b lsls r3, r3, #2
800e004: 440b add r3, r1
800e006: 681b ldr r3, [r3, #0]
800e008: 2b00 cmp r3, #0
800e00a: d10a bne.n 800e022 <xTaskPriorityDisinherit+0xb6>
800e00c: 693b ldr r3, [r7, #16]
800e00e: 6adb ldr r3, [r3, #44] ; 0x2c
800e010: 2201 movs r2, #1
800e012: fa02 f303 lsl.w r3, r2, r3
800e016: 43da mvns r2, r3
800e018: 4b18 ldr r3, [pc, #96] ; (800e07c <xTaskPriorityDisinherit+0x110>)
800e01a: 681b ldr r3, [r3, #0]
800e01c: 4013 ands r3, r2
800e01e: 4a17 ldr r2, [pc, #92] ; (800e07c <xTaskPriorityDisinherit+0x110>)
800e020: 6013 str r3, [r2, #0]
}
/* Disinherit the priority before adding the task into the
new ready list. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
pxTCB->uxPriority = pxTCB->uxBasePriority;
800e022: 693b ldr r3, [r7, #16]
800e024: 6c5a ldr r2, [r3, #68] ; 0x44
800e026: 693b ldr r3, [r7, #16]
800e028: 62da str r2, [r3, #44] ; 0x2c
/* Reset the event list item value. It cannot be in use for
any other purpose if this task is running, and it must be
running to give back the mutex. */
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800e02a: 693b ldr r3, [r7, #16]
800e02c: 6adb ldr r3, [r3, #44] ; 0x2c
800e02e: f1c3 0207 rsb r2, r3, #7
800e032: 693b ldr r3, [r7, #16]
800e034: 619a str r2, [r3, #24]
prvAddTaskToReadyList( pxTCB );
800e036: 693b ldr r3, [r7, #16]
800e038: 6adb ldr r3, [r3, #44] ; 0x2c
800e03a: 2201 movs r2, #1
800e03c: 409a lsls r2, r3
800e03e: 4b0f ldr r3, [pc, #60] ; (800e07c <xTaskPriorityDisinherit+0x110>)
800e040: 681b ldr r3, [r3, #0]
800e042: 4313 orrs r3, r2
800e044: 4a0d ldr r2, [pc, #52] ; (800e07c <xTaskPriorityDisinherit+0x110>)
800e046: 6013 str r3, [r2, #0]
800e048: 693b ldr r3, [r7, #16]
800e04a: 6ada ldr r2, [r3, #44] ; 0x2c
800e04c: 4613 mov r3, r2
800e04e: 009b lsls r3, r3, #2
800e050: 4413 add r3, r2
800e052: 009b lsls r3, r3, #2
800e054: 4a08 ldr r2, [pc, #32] ; (800e078 <xTaskPriorityDisinherit+0x10c>)
800e056: 441a add r2, r3
800e058: 693b ldr r3, [r7, #16]
800e05a: 3304 adds r3, #4
800e05c: 4619 mov r1, r3
800e05e: 4610 mov r0, r2
800e060: f7fd ff23 bl 800beaa <vListInsertEnd>
in an order different to that in which they were taken.
If a context switch did not occur when the first mutex was
returned, even if a task was waiting on it, then a context
switch should occur when the last mutex is returned whether
a task is waiting on it or not. */
xReturn = pdTRUE;
800e064: 2301 movs r3, #1
800e066: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
800e068: 697b ldr r3, [r7, #20]
}
800e06a: 4618 mov r0, r3
800e06c: 3718 adds r7, #24
800e06e: 46bd mov sp, r7
800e070: bd80 pop {r7, pc}
800e072: bf00 nop
800e074: 20000580 .word 0x20000580
800e078: 20000584 .word 0x20000584
800e07c: 20000688 .word 0x20000688
0800e080 <vTaskPriorityDisinheritAfterTimeout>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
{
800e080: b580 push {r7, lr}
800e082: b088 sub sp, #32
800e084: af00 add r7, sp, #0
800e086: 6078 str r0, [r7, #4]
800e088: 6039 str r1, [r7, #0]
TCB_t * const pxTCB = pxMutexHolder;
800e08a: 687b ldr r3, [r7, #4]
800e08c: 61bb str r3, [r7, #24]
UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
800e08e: 2301 movs r3, #1
800e090: 617b str r3, [r7, #20]
if( pxMutexHolder != NULL )
800e092: 687b ldr r3, [r7, #4]
800e094: 2b00 cmp r3, #0
800e096: f000 8087 beq.w 800e1a8 <vTaskPriorityDisinheritAfterTimeout+0x128>
{
/* If pxMutexHolder is not NULL then the holder must hold at least
one mutex. */
configASSERT( pxTCB->uxMutexesHeld );
800e09a: 69bb ldr r3, [r7, #24]
800e09c: 6c9b ldr r3, [r3, #72] ; 0x48
800e09e: 2b00 cmp r3, #0
800e0a0: d10c bne.n 800e0bc <vTaskPriorityDisinheritAfterTimeout+0x3c>
__asm volatile
800e0a2: f04f 0350 mov.w r3, #80 ; 0x50
800e0a6: b672 cpsid i
800e0a8: f383 8811 msr BASEPRI, r3
800e0ac: f3bf 8f6f isb sy
800e0b0: f3bf 8f4f dsb sy
800e0b4: b662 cpsie i
800e0b6: 60fb str r3, [r7, #12]
}
800e0b8: bf00 nop
800e0ba: e7fe b.n 800e0ba <vTaskPriorityDisinheritAfterTimeout+0x3a>
/* Determine the priority to which the priority of the task that
holds the mutex should be set. This will be the greater of the
holding task's base priority and the priority of the highest
priority task that is waiting to obtain the mutex. */
if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
800e0bc: 69bb ldr r3, [r7, #24]
800e0be: 6c5b ldr r3, [r3, #68] ; 0x44
800e0c0: 683a ldr r2, [r7, #0]
800e0c2: 429a cmp r2, r3
800e0c4: d902 bls.n 800e0cc <vTaskPriorityDisinheritAfterTimeout+0x4c>
{
uxPriorityToUse = uxHighestPriorityWaitingTask;
800e0c6: 683b ldr r3, [r7, #0]
800e0c8: 61fb str r3, [r7, #28]
800e0ca: e002 b.n 800e0d2 <vTaskPriorityDisinheritAfterTimeout+0x52>
}
else
{
uxPriorityToUse = pxTCB->uxBasePriority;
800e0cc: 69bb ldr r3, [r7, #24]
800e0ce: 6c5b ldr r3, [r3, #68] ; 0x44
800e0d0: 61fb str r3, [r7, #28]
}
/* Does the priority need to change? */
if( pxTCB->uxPriority != uxPriorityToUse )
800e0d2: 69bb ldr r3, [r7, #24]
800e0d4: 6adb ldr r3, [r3, #44] ; 0x2c
800e0d6: 69fa ldr r2, [r7, #28]
800e0d8: 429a cmp r2, r3
800e0da: d065 beq.n 800e1a8 <vTaskPriorityDisinheritAfterTimeout+0x128>
{
/* Only disinherit if no other mutexes are held. This is a
simplification in the priority inheritance implementation. If
the task that holds the mutex is also holding other mutexes then
the other mutexes may have caused the priority inheritance. */
if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
800e0dc: 69bb ldr r3, [r7, #24]
800e0de: 6c9b ldr r3, [r3, #72] ; 0x48
800e0e0: 697a ldr r2, [r7, #20]
800e0e2: 429a cmp r2, r3
800e0e4: d160 bne.n 800e1a8 <vTaskPriorityDisinheritAfterTimeout+0x128>
{
/* If a task has timed out because it already holds the
mutex it was trying to obtain then it cannot of inherited
its own priority. */
configASSERT( pxTCB != pxCurrentTCB );
800e0e6: 4b32 ldr r3, [pc, #200] ; (800e1b0 <vTaskPriorityDisinheritAfterTimeout+0x130>)
800e0e8: 681b ldr r3, [r3, #0]
800e0ea: 69ba ldr r2, [r7, #24]
800e0ec: 429a cmp r2, r3
800e0ee: d10c bne.n 800e10a <vTaskPriorityDisinheritAfterTimeout+0x8a>
__asm volatile
800e0f0: f04f 0350 mov.w r3, #80 ; 0x50
800e0f4: b672 cpsid i
800e0f6: f383 8811 msr BASEPRI, r3
800e0fa: f3bf 8f6f isb sy
800e0fe: f3bf 8f4f dsb sy
800e102: b662 cpsie i
800e104: 60bb str r3, [r7, #8]
}
800e106: bf00 nop
800e108: e7fe b.n 800e108 <vTaskPriorityDisinheritAfterTimeout+0x88>
/* Disinherit the priority, remembering the previous
priority to facilitate determining the subject task's
state. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
uxPriorityUsedOnEntry = pxTCB->uxPriority;
800e10a: 69bb ldr r3, [r7, #24]
800e10c: 6adb ldr r3, [r3, #44] ; 0x2c
800e10e: 613b str r3, [r7, #16]
pxTCB->uxPriority = uxPriorityToUse;
800e110: 69bb ldr r3, [r7, #24]
800e112: 69fa ldr r2, [r7, #28]
800e114: 62da str r2, [r3, #44] ; 0x2c
/* Only reset the event list item value if the value is not
being used for anything else. */
if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
800e116: 69bb ldr r3, [r7, #24]
800e118: 699b ldr r3, [r3, #24]
800e11a: 2b00 cmp r3, #0
800e11c: db04 blt.n 800e128 <vTaskPriorityDisinheritAfterTimeout+0xa8>
{
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800e11e: 69fb ldr r3, [r7, #28]
800e120: f1c3 0207 rsb r2, r3, #7
800e124: 69bb ldr r3, [r7, #24]
800e126: 619a str r2, [r3, #24]
then the task that holds the mutex could be in either the
Ready, Blocked or Suspended states. Only remove the task
from its current state list if it is in the Ready state as
the task's priority is going to change and there is one
Ready list per priority. */
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
800e128: 69bb ldr r3, [r7, #24]
800e12a: 6959 ldr r1, [r3, #20]
800e12c: 693a ldr r2, [r7, #16]
800e12e: 4613 mov r3, r2
800e130: 009b lsls r3, r3, #2
800e132: 4413 add r3, r2
800e134: 009b lsls r3, r3, #2
800e136: 4a1f ldr r2, [pc, #124] ; (800e1b4 <vTaskPriorityDisinheritAfterTimeout+0x134>)
800e138: 4413 add r3, r2
800e13a: 4299 cmp r1, r3
800e13c: d134 bne.n 800e1a8 <vTaskPriorityDisinheritAfterTimeout+0x128>
{
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800e13e: 69bb ldr r3, [r7, #24]
800e140: 3304 adds r3, #4
800e142: 4618 mov r0, r3
800e144: f7fd ff0e bl 800bf64 <uxListRemove>
800e148: 4603 mov r3, r0
800e14a: 2b00 cmp r3, #0
800e14c: d115 bne.n 800e17a <vTaskPriorityDisinheritAfterTimeout+0xfa>
{
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
800e14e: 69bb ldr r3, [r7, #24]
800e150: 6ada ldr r2, [r3, #44] ; 0x2c
800e152: 4918 ldr r1, [pc, #96] ; (800e1b4 <vTaskPriorityDisinheritAfterTimeout+0x134>)
800e154: 4613 mov r3, r2
800e156: 009b lsls r3, r3, #2
800e158: 4413 add r3, r2
800e15a: 009b lsls r3, r3, #2
800e15c: 440b add r3, r1
800e15e: 681b ldr r3, [r3, #0]
800e160: 2b00 cmp r3, #0
800e162: d10a bne.n 800e17a <vTaskPriorityDisinheritAfterTimeout+0xfa>
800e164: 69bb ldr r3, [r7, #24]
800e166: 6adb ldr r3, [r3, #44] ; 0x2c
800e168: 2201 movs r2, #1
800e16a: fa02 f303 lsl.w r3, r2, r3
800e16e: 43da mvns r2, r3
800e170: 4b11 ldr r3, [pc, #68] ; (800e1b8 <vTaskPriorityDisinheritAfterTimeout+0x138>)
800e172: 681b ldr r3, [r3, #0]
800e174: 4013 ands r3, r2
800e176: 4a10 ldr r2, [pc, #64] ; (800e1b8 <vTaskPriorityDisinheritAfterTimeout+0x138>)
800e178: 6013 str r3, [r2, #0]
else
{
mtCOVERAGE_TEST_MARKER();
}
prvAddTaskToReadyList( pxTCB );
800e17a: 69bb ldr r3, [r7, #24]
800e17c: 6adb ldr r3, [r3, #44] ; 0x2c
800e17e: 2201 movs r2, #1
800e180: 409a lsls r2, r3
800e182: 4b0d ldr r3, [pc, #52] ; (800e1b8 <vTaskPriorityDisinheritAfterTimeout+0x138>)
800e184: 681b ldr r3, [r3, #0]
800e186: 4313 orrs r3, r2
800e188: 4a0b ldr r2, [pc, #44] ; (800e1b8 <vTaskPriorityDisinheritAfterTimeout+0x138>)
800e18a: 6013 str r3, [r2, #0]
800e18c: 69bb ldr r3, [r7, #24]
800e18e: 6ada ldr r2, [r3, #44] ; 0x2c
800e190: 4613 mov r3, r2
800e192: 009b lsls r3, r3, #2
800e194: 4413 add r3, r2
800e196: 009b lsls r3, r3, #2
800e198: 4a06 ldr r2, [pc, #24] ; (800e1b4 <vTaskPriorityDisinheritAfterTimeout+0x134>)
800e19a: 441a add r2, r3
800e19c: 69bb ldr r3, [r7, #24]
800e19e: 3304 adds r3, #4
800e1a0: 4619 mov r1, r3
800e1a2: 4610 mov r0, r2
800e1a4: f7fd fe81 bl 800beaa <vListInsertEnd>
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800e1a8: bf00 nop
800e1aa: 3720 adds r7, #32
800e1ac: 46bd mov sp, r7
800e1ae: bd80 pop {r7, pc}
800e1b0: 20000580 .word 0x20000580
800e1b4: 20000584 .word 0x20000584
800e1b8: 20000688 .word 0x20000688
0800e1bc <pvTaskIncrementMutexHeldCount>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
TaskHandle_t pvTaskIncrementMutexHeldCount( void )
{
800e1bc: b480 push {r7}
800e1be: af00 add r7, sp, #0
/* If xSemaphoreCreateMutex() is called before any tasks have been created
then pxCurrentTCB will be NULL. */
if( pxCurrentTCB != NULL )
800e1c0: 4b07 ldr r3, [pc, #28] ; (800e1e0 <pvTaskIncrementMutexHeldCount+0x24>)
800e1c2: 681b ldr r3, [r3, #0]
800e1c4: 2b00 cmp r3, #0
800e1c6: d004 beq.n 800e1d2 <pvTaskIncrementMutexHeldCount+0x16>
{
( pxCurrentTCB->uxMutexesHeld )++;
800e1c8: 4b05 ldr r3, [pc, #20] ; (800e1e0 <pvTaskIncrementMutexHeldCount+0x24>)
800e1ca: 681b ldr r3, [r3, #0]
800e1cc: 6c9a ldr r2, [r3, #72] ; 0x48
800e1ce: 3201 adds r2, #1
800e1d0: 649a str r2, [r3, #72] ; 0x48
}
return pxCurrentTCB;
800e1d2: 4b03 ldr r3, [pc, #12] ; (800e1e0 <pvTaskIncrementMutexHeldCount+0x24>)
800e1d4: 681b ldr r3, [r3, #0]
}
800e1d6: 4618 mov r0, r3
800e1d8: 46bd mov sp, r7
800e1da: f85d 7b04 ldr.w r7, [sp], #4
800e1de: 4770 bx lr
800e1e0: 20000580 .word 0x20000580
0800e1e4 <prvAddCurrentTaskToDelayedList>:
}
#endif
/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
800e1e4: b580 push {r7, lr}
800e1e6: b084 sub sp, #16
800e1e8: af00 add r7, sp, #0
800e1ea: 6078 str r0, [r7, #4]
800e1ec: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
800e1ee: 4b29 ldr r3, [pc, #164] ; (800e294 <prvAddCurrentTaskToDelayedList+0xb0>)
800e1f0: 681b ldr r3, [r3, #0]
800e1f2: 60fb str r3, [r7, #12]
}
#endif
/* Remove the task from the ready list before adding it to the blocked list
as the same list item is used for both lists. */
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800e1f4: 4b28 ldr r3, [pc, #160] ; (800e298 <prvAddCurrentTaskToDelayedList+0xb4>)
800e1f6: 681b ldr r3, [r3, #0]
800e1f8: 3304 adds r3, #4
800e1fa: 4618 mov r0, r3
800e1fc: f7fd feb2 bl 800bf64 <uxListRemove>
800e200: 4603 mov r3, r0
800e202: 2b00 cmp r3, #0
800e204: d10b bne.n 800e21e <prvAddCurrentTaskToDelayedList+0x3a>
{
/* The current task must be in a ready list, so there is no need to
check, and the port reset macro can be called directly. */
portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
800e206: 4b24 ldr r3, [pc, #144] ; (800e298 <prvAddCurrentTaskToDelayedList+0xb4>)
800e208: 681b ldr r3, [r3, #0]
800e20a: 6adb ldr r3, [r3, #44] ; 0x2c
800e20c: 2201 movs r2, #1
800e20e: fa02 f303 lsl.w r3, r2, r3
800e212: 43da mvns r2, r3
800e214: 4b21 ldr r3, [pc, #132] ; (800e29c <prvAddCurrentTaskToDelayedList+0xb8>)
800e216: 681b ldr r3, [r3, #0]
800e218: 4013 ands r3, r2
800e21a: 4a20 ldr r2, [pc, #128] ; (800e29c <prvAddCurrentTaskToDelayedList+0xb8>)
800e21c: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
800e21e: 687b ldr r3, [r7, #4]
800e220: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800e224: d10a bne.n 800e23c <prvAddCurrentTaskToDelayedList+0x58>
800e226: 683b ldr r3, [r7, #0]
800e228: 2b00 cmp r3, #0
800e22a: d007 beq.n 800e23c <prvAddCurrentTaskToDelayedList+0x58>
{
/* Add the task to the suspended task list instead of a delayed task
list to ensure it is not woken by a timing event. It will block
indefinitely. */
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
800e22c: 4b1a ldr r3, [pc, #104] ; (800e298 <prvAddCurrentTaskToDelayedList+0xb4>)
800e22e: 681b ldr r3, [r3, #0]
800e230: 3304 adds r3, #4
800e232: 4619 mov r1, r3
800e234: 481a ldr r0, [pc, #104] ; (800e2a0 <prvAddCurrentTaskToDelayedList+0xbc>)
800e236: f7fd fe38 bl 800beaa <vListInsertEnd>
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
( void ) xCanBlockIndefinitely;
}
#endif /* INCLUDE_vTaskSuspend */
}
800e23a: e026 b.n 800e28a <prvAddCurrentTaskToDelayedList+0xa6>
xTimeToWake = xConstTickCount + xTicksToWait;
800e23c: 68fa ldr r2, [r7, #12]
800e23e: 687b ldr r3, [r7, #4]
800e240: 4413 add r3, r2
800e242: 60bb str r3, [r7, #8]
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
800e244: 4b14 ldr r3, [pc, #80] ; (800e298 <prvAddCurrentTaskToDelayedList+0xb4>)
800e246: 681b ldr r3, [r3, #0]
800e248: 68ba ldr r2, [r7, #8]
800e24a: 605a str r2, [r3, #4]
if( xTimeToWake < xConstTickCount )
800e24c: 68ba ldr r2, [r7, #8]
800e24e: 68fb ldr r3, [r7, #12]
800e250: 429a cmp r2, r3
800e252: d209 bcs.n 800e268 <prvAddCurrentTaskToDelayedList+0x84>
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
800e254: 4b13 ldr r3, [pc, #76] ; (800e2a4 <prvAddCurrentTaskToDelayedList+0xc0>)
800e256: 681a ldr r2, [r3, #0]
800e258: 4b0f ldr r3, [pc, #60] ; (800e298 <prvAddCurrentTaskToDelayedList+0xb4>)
800e25a: 681b ldr r3, [r3, #0]
800e25c: 3304 adds r3, #4
800e25e: 4619 mov r1, r3
800e260: 4610 mov r0, r2
800e262: f7fd fe46 bl 800bef2 <vListInsert>
}
800e266: e010 b.n 800e28a <prvAddCurrentTaskToDelayedList+0xa6>
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
800e268: 4b0f ldr r3, [pc, #60] ; (800e2a8 <prvAddCurrentTaskToDelayedList+0xc4>)
800e26a: 681a ldr r2, [r3, #0]
800e26c: 4b0a ldr r3, [pc, #40] ; (800e298 <prvAddCurrentTaskToDelayedList+0xb4>)
800e26e: 681b ldr r3, [r3, #0]
800e270: 3304 adds r3, #4
800e272: 4619 mov r1, r3
800e274: 4610 mov r0, r2
800e276: f7fd fe3c bl 800bef2 <vListInsert>
if( xTimeToWake < xNextTaskUnblockTime )
800e27a: 4b0c ldr r3, [pc, #48] ; (800e2ac <prvAddCurrentTaskToDelayedList+0xc8>)
800e27c: 681b ldr r3, [r3, #0]
800e27e: 68ba ldr r2, [r7, #8]
800e280: 429a cmp r2, r3
800e282: d202 bcs.n 800e28a <prvAddCurrentTaskToDelayedList+0xa6>
xNextTaskUnblockTime = xTimeToWake;
800e284: 4a09 ldr r2, [pc, #36] ; (800e2ac <prvAddCurrentTaskToDelayedList+0xc8>)
800e286: 68bb ldr r3, [r7, #8]
800e288: 6013 str r3, [r2, #0]
}
800e28a: bf00 nop
800e28c: 3710 adds r7, #16
800e28e: 46bd mov sp, r7
800e290: bd80 pop {r7, pc}
800e292: bf00 nop
800e294: 20000684 .word 0x20000684
800e298: 20000580 .word 0x20000580
800e29c: 20000688 .word 0x20000688
800e2a0: 2000066c .word 0x2000066c
800e2a4: 2000063c .word 0x2000063c
800e2a8: 20000638 .word 0x20000638
800e2ac: 200006a0 .word 0x200006a0
0800e2b0 <pxPortInitialiseStack>:
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
800e2b0: b480 push {r7}
800e2b2: b085 sub sp, #20
800e2b4: af00 add r7, sp, #0
800e2b6: 60f8 str r0, [r7, #12]
800e2b8: 60b9 str r1, [r7, #8]
800e2ba: 607a str r2, [r7, #4]
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
/* Offset added to account for the way the MCU uses the stack on entry/exit
of interrupts, and to ensure alignment. */
pxTopOfStack--;
800e2bc: 68fb ldr r3, [r7, #12]
800e2be: 3b04 subs r3, #4
800e2c0: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
800e2c2: 68fb ldr r3, [r7, #12]
800e2c4: f04f 7280 mov.w r2, #16777216 ; 0x1000000
800e2c8: 601a str r2, [r3, #0]
pxTopOfStack--;
800e2ca: 68fb ldr r3, [r7, #12]
800e2cc: 3b04 subs r3, #4
800e2ce: 60fb str r3, [r7, #12]
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
800e2d0: 68bb ldr r3, [r7, #8]
800e2d2: f023 0201 bic.w r2, r3, #1
800e2d6: 68fb ldr r3, [r7, #12]
800e2d8: 601a str r2, [r3, #0]
pxTopOfStack--;
800e2da: 68fb ldr r3, [r7, #12]
800e2dc: 3b04 subs r3, #4
800e2de: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
800e2e0: 4a0c ldr r2, [pc, #48] ; (800e314 <pxPortInitialiseStack+0x64>)
800e2e2: 68fb ldr r3, [r7, #12]
800e2e4: 601a str r2, [r3, #0]
/* Save code space by skipping register initialisation. */
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
800e2e6: 68fb ldr r3, [r7, #12]
800e2e8: 3b14 subs r3, #20
800e2ea: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
800e2ec: 687a ldr r2, [r7, #4]
800e2ee: 68fb ldr r3, [r7, #12]
800e2f0: 601a str r2, [r3, #0]
/* A save method is being used that requires each task to maintain its
own exec return value. */
pxTopOfStack--;
800e2f2: 68fb ldr r3, [r7, #12]
800e2f4: 3b04 subs r3, #4
800e2f6: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_EXC_RETURN;
800e2f8: 68fb ldr r3, [r7, #12]
800e2fa: f06f 0202 mvn.w r2, #2
800e2fe: 601a str r2, [r3, #0]
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
800e300: 68fb ldr r3, [r7, #12]
800e302: 3b20 subs r3, #32
800e304: 60fb str r3, [r7, #12]
return pxTopOfStack;
800e306: 68fb ldr r3, [r7, #12]
}
800e308: 4618 mov r0, r3
800e30a: 3714 adds r7, #20
800e30c: 46bd mov sp, r7
800e30e: f85d 7b04 ldr.w r7, [sp], #4
800e312: 4770 bx lr
800e314: 0800e319 .word 0x0800e319
0800e318 <prvTaskExitError>:
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
800e318: b480 push {r7}
800e31a: b085 sub sp, #20
800e31c: af00 add r7, sp, #0
volatile uint32_t ulDummy = 0;
800e31e: 2300 movs r3, #0
800e320: 607b str r3, [r7, #4]
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( uxCriticalNesting == ~0UL );
800e322: 4b14 ldr r3, [pc, #80] ; (800e374 <prvTaskExitError+0x5c>)
800e324: 681b ldr r3, [r3, #0]
800e326: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800e32a: d00c beq.n 800e346 <prvTaskExitError+0x2e>
__asm volatile
800e32c: f04f 0350 mov.w r3, #80 ; 0x50
800e330: b672 cpsid i
800e332: f383 8811 msr BASEPRI, r3
800e336: f3bf 8f6f isb sy
800e33a: f3bf 8f4f dsb sy
800e33e: b662 cpsie i
800e340: 60fb str r3, [r7, #12]
}
800e342: bf00 nop
800e344: e7fe b.n 800e344 <prvTaskExitError+0x2c>
__asm volatile
800e346: f04f 0350 mov.w r3, #80 ; 0x50
800e34a: b672 cpsid i
800e34c: f383 8811 msr BASEPRI, r3
800e350: f3bf 8f6f isb sy
800e354: f3bf 8f4f dsb sy
800e358: b662 cpsie i
800e35a: 60bb str r3, [r7, #8]
}
800e35c: bf00 nop
portDISABLE_INTERRUPTS();
while( ulDummy == 0 )
800e35e: bf00 nop
800e360: 687b ldr r3, [r7, #4]
800e362: 2b00 cmp r3, #0
800e364: d0fc beq.n 800e360 <prvTaskExitError+0x48>
about code appearing after this function is called - making ulDummy
volatile makes the compiler think the function could return and
therefore not output an 'unreachable code' warning for code that appears
after it. */
}
}
800e366: bf00 nop
800e368: bf00 nop
800e36a: 3714 adds r7, #20
800e36c: 46bd mov sp, r7
800e36e: f85d 7b04 ldr.w r7, [sp], #4
800e372: 4770 bx lr
800e374: 20000064 .word 0x20000064
...
0800e380 <SVC_Handler>:
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
__asm volatile (
800e380: 4b07 ldr r3, [pc, #28] ; (800e3a0 <pxCurrentTCBConst2>)
800e382: 6819 ldr r1, [r3, #0]
800e384: 6808 ldr r0, [r1, #0]
800e386: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800e38a: f380 8809 msr PSP, r0
800e38e: f3bf 8f6f isb sy
800e392: f04f 0000 mov.w r0, #0
800e396: f380 8811 msr BASEPRI, r0
800e39a: 4770 bx lr
800e39c: f3af 8000 nop.w
0800e3a0 <pxCurrentTCBConst2>:
800e3a0: 20000580 .word 0x20000580
" bx r14 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
800e3a4: bf00 nop
800e3a6: bf00 nop
0800e3a8 <prvPortStartFirstTask>:
{
/* Start the first task. This also clears the bit that indicates the FPU is
in use in case the FPU was used before the scheduler was started - which
would otherwise result in the unnecessary leaving of space in the SVC stack
for lazy saving of FPU registers. */
__asm volatile(
800e3a8: 4808 ldr r0, [pc, #32] ; (800e3cc <prvPortStartFirstTask+0x24>)
800e3aa: 6800 ldr r0, [r0, #0]
800e3ac: 6800 ldr r0, [r0, #0]
800e3ae: f380 8808 msr MSP, r0
800e3b2: f04f 0000 mov.w r0, #0
800e3b6: f380 8814 msr CONTROL, r0
800e3ba: b662 cpsie i
800e3bc: b661 cpsie f
800e3be: f3bf 8f4f dsb sy
800e3c2: f3bf 8f6f isb sy
800e3c6: df00 svc 0
800e3c8: bf00 nop
" dsb \n"
" isb \n"
" svc 0 \n" /* System call to start first task. */
" nop \n"
);
}
800e3ca: bf00 nop
800e3cc: e000ed08 .word 0xe000ed08
0800e3d0 <xPortStartScheduler>:
/*
* See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
800e3d0: b580 push {r7, lr}
800e3d2: b084 sub sp, #16
800e3d4: af00 add r7, sp, #0
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
#if( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
800e3d6: 4b37 ldr r3, [pc, #220] ; (800e4b4 <xPortStartScheduler+0xe4>)
800e3d8: 60fb str r3, [r7, #12]
functions can be called. ISR safe functions are those that end in
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
ensure interrupt entry is as fast and simple as possible.
Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
800e3da: 68fb ldr r3, [r7, #12]
800e3dc: 781b ldrb r3, [r3, #0]
800e3de: b2db uxtb r3, r3
800e3e0: 607b str r3, [r7, #4]
/* Determine the number of priority bits available. First write to all
possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
800e3e2: 68fb ldr r3, [r7, #12]
800e3e4: 22ff movs r2, #255 ; 0xff
800e3e6: 701a strb r2, [r3, #0]
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
800e3e8: 68fb ldr r3, [r7, #12]
800e3ea: 781b ldrb r3, [r3, #0]
800e3ec: b2db uxtb r3, r3
800e3ee: 70fb strb r3, [r7, #3]
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
800e3f0: 78fb ldrb r3, [r7, #3]
800e3f2: b2db uxtb r3, r3
800e3f4: f003 0350 and.w r3, r3, #80 ; 0x50
800e3f8: b2da uxtb r2, r3
800e3fa: 4b2f ldr r3, [pc, #188] ; (800e4b8 <xPortStartScheduler+0xe8>)
800e3fc: 701a strb r2, [r3, #0]
/* Calculate the maximum acceptable priority group value for the number
of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
800e3fe: 4b2f ldr r3, [pc, #188] ; (800e4bc <xPortStartScheduler+0xec>)
800e400: 2207 movs r2, #7
800e402: 601a str r2, [r3, #0]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
800e404: e009 b.n 800e41a <xPortStartScheduler+0x4a>
{
ulMaxPRIGROUPValue--;
800e406: 4b2d ldr r3, [pc, #180] ; (800e4bc <xPortStartScheduler+0xec>)
800e408: 681b ldr r3, [r3, #0]
800e40a: 3b01 subs r3, #1
800e40c: 4a2b ldr r2, [pc, #172] ; (800e4bc <xPortStartScheduler+0xec>)
800e40e: 6013 str r3, [r2, #0]
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
800e410: 78fb ldrb r3, [r7, #3]
800e412: b2db uxtb r3, r3
800e414: 005b lsls r3, r3, #1
800e416: b2db uxtb r3, r3
800e418: 70fb strb r3, [r7, #3]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
800e41a: 78fb ldrb r3, [r7, #3]
800e41c: b2db uxtb r3, r3
800e41e: f003 0380 and.w r3, r3, #128 ; 0x80
800e422: 2b80 cmp r3, #128 ; 0x80
800e424: d0ef beq.n 800e406 <xPortStartScheduler+0x36>
#ifdef configPRIO_BITS
{
/* Check the FreeRTOS configuration that defines the number of
priority bits matches the number of priority bits actually queried
from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
800e426: 4b25 ldr r3, [pc, #148] ; (800e4bc <xPortStartScheduler+0xec>)
800e428: 681b ldr r3, [r3, #0]
800e42a: f1c3 0307 rsb r3, r3, #7
800e42e: 2b04 cmp r3, #4
800e430: d00c beq.n 800e44c <xPortStartScheduler+0x7c>
__asm volatile
800e432: f04f 0350 mov.w r3, #80 ; 0x50
800e436: b672 cpsid i
800e438: f383 8811 msr BASEPRI, r3
800e43c: f3bf 8f6f isb sy
800e440: f3bf 8f4f dsb sy
800e444: b662 cpsie i
800e446: 60bb str r3, [r7, #8]
}
800e448: bf00 nop
800e44a: e7fe b.n 800e44a <xPortStartScheduler+0x7a>
}
#endif
/* Shift the priority group value back to its position within the AIRCR
register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
800e44c: 4b1b ldr r3, [pc, #108] ; (800e4bc <xPortStartScheduler+0xec>)
800e44e: 681b ldr r3, [r3, #0]
800e450: 021b lsls r3, r3, #8
800e452: 4a1a ldr r2, [pc, #104] ; (800e4bc <xPortStartScheduler+0xec>)
800e454: 6013 str r3, [r2, #0]
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
800e456: 4b19 ldr r3, [pc, #100] ; (800e4bc <xPortStartScheduler+0xec>)
800e458: 681b ldr r3, [r3, #0]
800e45a: f403 63e0 and.w r3, r3, #1792 ; 0x700
800e45e: 4a17 ldr r2, [pc, #92] ; (800e4bc <xPortStartScheduler+0xec>)
800e460: 6013 str r3, [r2, #0]
/* Restore the clobbered interrupt priority register to its original
value. */
*pucFirstUserPriorityRegister = ulOriginalPriority;
800e462: 687b ldr r3, [r7, #4]
800e464: b2da uxtb r2, r3
800e466: 68fb ldr r3, [r7, #12]
800e468: 701a strb r2, [r3, #0]
}
#endif /* conifgASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
800e46a: 4b15 ldr r3, [pc, #84] ; (800e4c0 <xPortStartScheduler+0xf0>)
800e46c: 681b ldr r3, [r3, #0]
800e46e: 4a14 ldr r2, [pc, #80] ; (800e4c0 <xPortStartScheduler+0xf0>)
800e470: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
800e474: 6013 str r3, [r2, #0]
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
800e476: 4b12 ldr r3, [pc, #72] ; (800e4c0 <xPortStartScheduler+0xf0>)
800e478: 681b ldr r3, [r3, #0]
800e47a: 4a11 ldr r2, [pc, #68] ; (800e4c0 <xPortStartScheduler+0xf0>)
800e47c: f043 4370 orr.w r3, r3, #4026531840 ; 0xf0000000
800e480: 6013 str r3, [r2, #0]
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
vPortSetupTimerInterrupt();
800e482: f000 f8dd bl 800e640 <vPortSetupTimerInterrupt>
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
800e486: 4b0f ldr r3, [pc, #60] ; (800e4c4 <xPortStartScheduler+0xf4>)
800e488: 2200 movs r2, #0
800e48a: 601a str r2, [r3, #0]
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
800e48c: f000 f8fc bl 800e688 <vPortEnableVFP>
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
800e490: 4b0d ldr r3, [pc, #52] ; (800e4c8 <xPortStartScheduler+0xf8>)
800e492: 681b ldr r3, [r3, #0]
800e494: 4a0c ldr r2, [pc, #48] ; (800e4c8 <xPortStartScheduler+0xf8>)
800e496: f043 4340 orr.w r3, r3, #3221225472 ; 0xc0000000
800e49a: 6013 str r3, [r2, #0]
/* Start the first task. */
prvPortStartFirstTask();
800e49c: f7ff ff84 bl 800e3a8 <prvPortStartFirstTask>
exit error function to prevent compiler warnings about a static function
not being called in the case that the application writer overrides this
functionality by defining configTASK_RETURN_ADDRESS. Call
vTaskSwitchContext() so link time optimisation does not remove the
symbol. */
vTaskSwitchContext();
800e4a0: f7ff fa58 bl 800d954 <vTaskSwitchContext>
prvTaskExitError();
800e4a4: f7ff ff38 bl 800e318 <prvTaskExitError>
/* Should not get here! */
return 0;
800e4a8: 2300 movs r3, #0
}
800e4aa: 4618 mov r0, r3
800e4ac: 3710 adds r7, #16
800e4ae: 46bd mov sp, r7
800e4b0: bd80 pop {r7, pc}
800e4b2: bf00 nop
800e4b4: e000e400 .word 0xe000e400
800e4b8: 200006ac .word 0x200006ac
800e4bc: 200006b0 .word 0x200006b0
800e4c0: e000ed20 .word 0xe000ed20
800e4c4: 20000064 .word 0x20000064
800e4c8: e000ef34 .word 0xe000ef34
0800e4cc <vPortEnterCritical>:
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
800e4cc: b480 push {r7}
800e4ce: b083 sub sp, #12
800e4d0: af00 add r7, sp, #0
__asm volatile
800e4d2: f04f 0350 mov.w r3, #80 ; 0x50
800e4d6: b672 cpsid i
800e4d8: f383 8811 msr BASEPRI, r3
800e4dc: f3bf 8f6f isb sy
800e4e0: f3bf 8f4f dsb sy
800e4e4: b662 cpsie i
800e4e6: 607b str r3, [r7, #4]
}
800e4e8: bf00 nop
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
800e4ea: 4b10 ldr r3, [pc, #64] ; (800e52c <vPortEnterCritical+0x60>)
800e4ec: 681b ldr r3, [r3, #0]
800e4ee: 3301 adds r3, #1
800e4f0: 4a0e ldr r2, [pc, #56] ; (800e52c <vPortEnterCritical+0x60>)
800e4f2: 6013 str r3, [r2, #0]
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
800e4f4: 4b0d ldr r3, [pc, #52] ; (800e52c <vPortEnterCritical+0x60>)
800e4f6: 681b ldr r3, [r3, #0]
800e4f8: 2b01 cmp r3, #1
800e4fa: d111 bne.n 800e520 <vPortEnterCritical+0x54>
{
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
800e4fc: 4b0c ldr r3, [pc, #48] ; (800e530 <vPortEnterCritical+0x64>)
800e4fe: 681b ldr r3, [r3, #0]
800e500: b2db uxtb r3, r3
800e502: 2b00 cmp r3, #0
800e504: d00c beq.n 800e520 <vPortEnterCritical+0x54>
__asm volatile
800e506: f04f 0350 mov.w r3, #80 ; 0x50
800e50a: b672 cpsid i
800e50c: f383 8811 msr BASEPRI, r3
800e510: f3bf 8f6f isb sy
800e514: f3bf 8f4f dsb sy
800e518: b662 cpsie i
800e51a: 603b str r3, [r7, #0]
}
800e51c: bf00 nop
800e51e: e7fe b.n 800e51e <vPortEnterCritical+0x52>
}
}
800e520: bf00 nop
800e522: 370c adds r7, #12
800e524: 46bd mov sp, r7
800e526: f85d 7b04 ldr.w r7, [sp], #4
800e52a: 4770 bx lr
800e52c: 20000064 .word 0x20000064
800e530: e000ed04 .word 0xe000ed04
0800e534 <vPortExitCritical>:
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
800e534: b480 push {r7}
800e536: b083 sub sp, #12
800e538: af00 add r7, sp, #0
configASSERT( uxCriticalNesting );
800e53a: 4b13 ldr r3, [pc, #76] ; (800e588 <vPortExitCritical+0x54>)
800e53c: 681b ldr r3, [r3, #0]
800e53e: 2b00 cmp r3, #0
800e540: d10c bne.n 800e55c <vPortExitCritical+0x28>
__asm volatile
800e542: f04f 0350 mov.w r3, #80 ; 0x50
800e546: b672 cpsid i
800e548: f383 8811 msr BASEPRI, r3
800e54c: f3bf 8f6f isb sy
800e550: f3bf 8f4f dsb sy
800e554: b662 cpsie i
800e556: 607b str r3, [r7, #4]
}
800e558: bf00 nop
800e55a: e7fe b.n 800e55a <vPortExitCritical+0x26>
uxCriticalNesting--;
800e55c: 4b0a ldr r3, [pc, #40] ; (800e588 <vPortExitCritical+0x54>)
800e55e: 681b ldr r3, [r3, #0]
800e560: 3b01 subs r3, #1
800e562: 4a09 ldr r2, [pc, #36] ; (800e588 <vPortExitCritical+0x54>)
800e564: 6013 str r3, [r2, #0]
if( uxCriticalNesting == 0 )
800e566: 4b08 ldr r3, [pc, #32] ; (800e588 <vPortExitCritical+0x54>)
800e568: 681b ldr r3, [r3, #0]
800e56a: 2b00 cmp r3, #0
800e56c: d105 bne.n 800e57a <vPortExitCritical+0x46>
800e56e: 2300 movs r3, #0
800e570: 603b str r3, [r7, #0]
__asm volatile
800e572: 683b ldr r3, [r7, #0]
800e574: f383 8811 msr BASEPRI, r3
}
800e578: bf00 nop
{
portENABLE_INTERRUPTS();
}
}
800e57a: bf00 nop
800e57c: 370c adds r7, #12
800e57e: 46bd mov sp, r7
800e580: f85d 7b04 ldr.w r7, [sp], #4
800e584: 4770 bx lr
800e586: bf00 nop
800e588: 20000064 .word 0x20000064
800e58c: 00000000 .word 0x00000000
0800e590 <PendSV_Handler>:
void xPortPendSVHandler( void )
{
/* This is a naked function. */
__asm volatile
800e590: f3ef 8009 mrs r0, PSP
800e594: f3bf 8f6f isb sy
800e598: 4b15 ldr r3, [pc, #84] ; (800e5f0 <pxCurrentTCBConst>)
800e59a: 681a ldr r2, [r3, #0]
800e59c: f01e 0f10 tst.w lr, #16
800e5a0: bf08 it eq
800e5a2: ed20 8a10 vstmdbeq r0!, {s16-s31}
800e5a6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800e5aa: 6010 str r0, [r2, #0]
800e5ac: e92d 0009 stmdb sp!, {r0, r3}
800e5b0: f04f 0050 mov.w r0, #80 ; 0x50
800e5b4: b672 cpsid i
800e5b6: f380 8811 msr BASEPRI, r0
800e5ba: f3bf 8f4f dsb sy
800e5be: f3bf 8f6f isb sy
800e5c2: b662 cpsie i
800e5c4: f7ff f9c6 bl 800d954 <vTaskSwitchContext>
800e5c8: f04f 0000 mov.w r0, #0
800e5cc: f380 8811 msr BASEPRI, r0
800e5d0: bc09 pop {r0, r3}
800e5d2: 6819 ldr r1, [r3, #0]
800e5d4: 6808 ldr r0, [r1, #0]
800e5d6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800e5da: f01e 0f10 tst.w lr, #16
800e5de: bf08 it eq
800e5e0: ecb0 8a10 vldmiaeq r0!, {s16-s31}
800e5e4: f380 8809 msr PSP, r0
800e5e8: f3bf 8f6f isb sy
800e5ec: 4770 bx lr
800e5ee: bf00 nop
0800e5f0 <pxCurrentTCBConst>:
800e5f0: 20000580 .word 0x20000580
" \n"
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
);
}
800e5f4: bf00 nop
800e5f6: bf00 nop
0800e5f8 <SysTick_Handler>:
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
800e5f8: b580 push {r7, lr}
800e5fa: b082 sub sp, #8
800e5fc: af00 add r7, sp, #0
__asm volatile
800e5fe: f04f 0350 mov.w r3, #80 ; 0x50
800e602: b672 cpsid i
800e604: f383 8811 msr BASEPRI, r3
800e608: f3bf 8f6f isb sy
800e60c: f3bf 8f4f dsb sy
800e610: b662 cpsie i
800e612: 607b str r3, [r7, #4]
}
800e614: bf00 nop
save and then restore the interrupt mask value as its value is already
known. */
portDISABLE_INTERRUPTS();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
800e616: f7ff f8e3 bl 800d7e0 <xTaskIncrementTick>
800e61a: 4603 mov r3, r0
800e61c: 2b00 cmp r3, #0
800e61e: d003 beq.n 800e628 <SysTick_Handler+0x30>
{
/* A context switch is required. Context switching is performed in
the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
800e620: 4b06 ldr r3, [pc, #24] ; (800e63c <SysTick_Handler+0x44>)
800e622: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800e626: 601a str r2, [r3, #0]
800e628: 2300 movs r3, #0
800e62a: 603b str r3, [r7, #0]
__asm volatile
800e62c: 683b ldr r3, [r7, #0]
800e62e: f383 8811 msr BASEPRI, r3
}
800e632: bf00 nop
}
}
portENABLE_INTERRUPTS();
}
800e634: bf00 nop
800e636: 3708 adds r7, #8
800e638: 46bd mov sp, r7
800e63a: bd80 pop {r7, pc}
800e63c: e000ed04 .word 0xe000ed04
0800e640 <vPortSetupTimerInterrupt>:
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
800e640: b480 push {r7}
800e642: af00 add r7, sp, #0
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
800e644: 4b0b ldr r3, [pc, #44] ; (800e674 <vPortSetupTimerInterrupt+0x34>)
800e646: 2200 movs r2, #0
800e648: 601a str r2, [r3, #0]
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
800e64a: 4b0b ldr r3, [pc, #44] ; (800e678 <vPortSetupTimerInterrupt+0x38>)
800e64c: 2200 movs r2, #0
800e64e: 601a str r2, [r3, #0]
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
800e650: 4b0a ldr r3, [pc, #40] ; (800e67c <vPortSetupTimerInterrupt+0x3c>)
800e652: 681b ldr r3, [r3, #0]
800e654: 4a0a ldr r2, [pc, #40] ; (800e680 <vPortSetupTimerInterrupt+0x40>)
800e656: fba2 2303 umull r2, r3, r2, r3
800e65a: 099b lsrs r3, r3, #6
800e65c: 4a09 ldr r2, [pc, #36] ; (800e684 <vPortSetupTimerInterrupt+0x44>)
800e65e: 3b01 subs r3, #1
800e660: 6013 str r3, [r2, #0]
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
800e662: 4b04 ldr r3, [pc, #16] ; (800e674 <vPortSetupTimerInterrupt+0x34>)
800e664: 2207 movs r2, #7
800e666: 601a str r2, [r3, #0]
}
800e668: bf00 nop
800e66a: 46bd mov sp, r7
800e66c: f85d 7b04 ldr.w r7, [sp], #4
800e670: 4770 bx lr
800e672: bf00 nop
800e674: e000e010 .word 0xe000e010
800e678: e000e018 .word 0xe000e018
800e67c: 20000058 .word 0x20000058
800e680: 10624dd3 .word 0x10624dd3
800e684: e000e014 .word 0xe000e014
0800e688 <vPortEnableVFP>:
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void vPortEnableVFP( void )
{
__asm volatile
800e688: f8df 000c ldr.w r0, [pc, #12] ; 800e698 <vPortEnableVFP+0x10>
800e68c: 6801 ldr r1, [r0, #0]
800e68e: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
800e692: 6001 str r1, [r0, #0]
800e694: 4770 bx lr
" \n"
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
" str r1, [r0] \n"
" bx r14 "
);
}
800e696: bf00 nop
800e698: e000ed88 .word 0xe000ed88
0800e69c <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/
#if( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
800e69c: b480 push {r7}
800e69e: b085 sub sp, #20
800e6a0: af00 add r7, sp, #0
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
800e6a2: f3ef 8305 mrs r3, IPSR
800e6a6: 60fb str r3, [r7, #12]
/* Is the interrupt number a user defined interrupt? */
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
800e6a8: 68fb ldr r3, [r7, #12]
800e6aa: 2b0f cmp r3, #15
800e6ac: d916 bls.n 800e6dc <vPortValidateInterruptPriority+0x40>
{
/* Look up the interrupt's priority. */
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
800e6ae: 4a19 ldr r2, [pc, #100] ; (800e714 <vPortValidateInterruptPriority+0x78>)
800e6b0: 68fb ldr r3, [r7, #12]
800e6b2: 4413 add r3, r2
800e6b4: 781b ldrb r3, [r3, #0]
800e6b6: 72fb strb r3, [r7, #11]
interrupt entry is as fast and simple as possible.
The following links provide detailed information:
http://www.freertos.org/RTOS-Cortex-M3-M4.html
http://www.freertos.org/FAQHelp.html */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
800e6b8: 4b17 ldr r3, [pc, #92] ; (800e718 <vPortValidateInterruptPriority+0x7c>)
800e6ba: 781b ldrb r3, [r3, #0]
800e6bc: 7afa ldrb r2, [r7, #11]
800e6be: 429a cmp r2, r3
800e6c0: d20c bcs.n 800e6dc <vPortValidateInterruptPriority+0x40>
__asm volatile
800e6c2: f04f 0350 mov.w r3, #80 ; 0x50
800e6c6: b672 cpsid i
800e6c8: f383 8811 msr BASEPRI, r3
800e6cc: f3bf 8f6f isb sy
800e6d0: f3bf 8f4f dsb sy
800e6d4: b662 cpsie i
800e6d6: 607b str r3, [r7, #4]
}
800e6d8: bf00 nop
800e6da: e7fe b.n 800e6da <vPortValidateInterruptPriority+0x3e>
configuration then the correct setting can be achieved on all Cortex-M
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
scheduler. Note however that some vendor specific peripheral libraries
assume a non-zero priority group setting, in which cases using a value
of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
800e6dc: 4b0f ldr r3, [pc, #60] ; (800e71c <vPortValidateInterruptPriority+0x80>)
800e6de: 681b ldr r3, [r3, #0]
800e6e0: f403 62e0 and.w r2, r3, #1792 ; 0x700
800e6e4: 4b0e ldr r3, [pc, #56] ; (800e720 <vPortValidateInterruptPriority+0x84>)
800e6e6: 681b ldr r3, [r3, #0]
800e6e8: 429a cmp r2, r3
800e6ea: d90c bls.n 800e706 <vPortValidateInterruptPriority+0x6a>
__asm volatile
800e6ec: f04f 0350 mov.w r3, #80 ; 0x50
800e6f0: b672 cpsid i
800e6f2: f383 8811 msr BASEPRI, r3
800e6f6: f3bf 8f6f isb sy
800e6fa: f3bf 8f4f dsb sy
800e6fe: b662 cpsie i
800e700: 603b str r3, [r7, #0]
}
800e702: bf00 nop
800e704: e7fe b.n 800e704 <vPortValidateInterruptPriority+0x68>
}
800e706: bf00 nop
800e708: 3714 adds r7, #20
800e70a: 46bd mov sp, r7
800e70c: f85d 7b04 ldr.w r7, [sp], #4
800e710: 4770 bx lr
800e712: bf00 nop
800e714: e000e3f0 .word 0xe000e3f0
800e718: 200006ac .word 0x200006ac
800e71c: e000ed0c .word 0xe000ed0c
800e720: 200006b0 .word 0x200006b0
0800e724 <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
void *pvPortMalloc( size_t xWantedSize )
{
800e724: b580 push {r7, lr}
800e726: b08a sub sp, #40 ; 0x28
800e728: af00 add r7, sp, #0
800e72a: 6078 str r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
800e72c: 2300 movs r3, #0
800e72e: 61fb str r3, [r7, #28]
vTaskSuspendAll();
800e730: f7fe ff88 bl 800d644 <vTaskSuspendAll>
{
/* If this is the first call to malloc then the heap will require
initialisation to setup the list of free blocks. */
if( pxEnd == NULL )
800e734: 4b5e ldr r3, [pc, #376] ; (800e8b0 <pvPortMalloc+0x18c>)
800e736: 681b ldr r3, [r3, #0]
800e738: 2b00 cmp r3, #0
800e73a: d101 bne.n 800e740 <pvPortMalloc+0x1c>
{
prvHeapInit();
800e73c: f000 f920 bl 800e980 <prvHeapInit>
/* Check the requested block size is not so large that the top bit is
set. The top bit of the block size member of the BlockLink_t structure
is used to determine who owns the block - the application or the
kernel, so it must be free. */
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
800e740: 4b5c ldr r3, [pc, #368] ; (800e8b4 <pvPortMalloc+0x190>)
800e742: 681a ldr r2, [r3, #0]
800e744: 687b ldr r3, [r7, #4]
800e746: 4013 ands r3, r2
800e748: 2b00 cmp r3, #0
800e74a: f040 8092 bne.w 800e872 <pvPortMalloc+0x14e>
{
/* The wanted size is increased so it can contain a BlockLink_t
structure in addition to the requested amount of bytes. */
if( xWantedSize > 0 )
800e74e: 687b ldr r3, [r7, #4]
800e750: 2b00 cmp r3, #0
800e752: d01f beq.n 800e794 <pvPortMalloc+0x70>
{
xWantedSize += xHeapStructSize;
800e754: 2208 movs r2, #8
800e756: 687b ldr r3, [r7, #4]
800e758: 4413 add r3, r2
800e75a: 607b str r3, [r7, #4]
/* Ensure that blocks are always aligned to the required number
of bytes. */
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
800e75c: 687b ldr r3, [r7, #4]
800e75e: f003 0307 and.w r3, r3, #7
800e762: 2b00 cmp r3, #0
800e764: d016 beq.n 800e794 <pvPortMalloc+0x70>
{
/* Byte alignment required. */
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
800e766: 687b ldr r3, [r7, #4]
800e768: f023 0307 bic.w r3, r3, #7
800e76c: 3308 adds r3, #8
800e76e: 607b str r3, [r7, #4]
configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
800e770: 687b ldr r3, [r7, #4]
800e772: f003 0307 and.w r3, r3, #7
800e776: 2b00 cmp r3, #0
800e778: d00c beq.n 800e794 <pvPortMalloc+0x70>
__asm volatile
800e77a: f04f 0350 mov.w r3, #80 ; 0x50
800e77e: b672 cpsid i
800e780: f383 8811 msr BASEPRI, r3
800e784: f3bf 8f6f isb sy
800e788: f3bf 8f4f dsb sy
800e78c: b662 cpsie i
800e78e: 617b str r3, [r7, #20]
}
800e790: bf00 nop
800e792: e7fe b.n 800e792 <pvPortMalloc+0x6e>
else
{
mtCOVERAGE_TEST_MARKER();
}
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
800e794: 687b ldr r3, [r7, #4]
800e796: 2b00 cmp r3, #0
800e798: d06b beq.n 800e872 <pvPortMalloc+0x14e>
800e79a: 4b47 ldr r3, [pc, #284] ; (800e8b8 <pvPortMalloc+0x194>)
800e79c: 681b ldr r3, [r3, #0]
800e79e: 687a ldr r2, [r7, #4]
800e7a0: 429a cmp r2, r3
800e7a2: d866 bhi.n 800e872 <pvPortMalloc+0x14e>
{
/* Traverse the list from the start (lowest address) block until
one of adequate size is found. */
pxPreviousBlock = &xStart;
800e7a4: 4b45 ldr r3, [pc, #276] ; (800e8bc <pvPortMalloc+0x198>)
800e7a6: 623b str r3, [r7, #32]
pxBlock = xStart.pxNextFreeBlock;
800e7a8: 4b44 ldr r3, [pc, #272] ; (800e8bc <pvPortMalloc+0x198>)
800e7aa: 681b ldr r3, [r3, #0]
800e7ac: 627b str r3, [r7, #36] ; 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
800e7ae: e004 b.n 800e7ba <pvPortMalloc+0x96>
{
pxPreviousBlock = pxBlock;
800e7b0: 6a7b ldr r3, [r7, #36] ; 0x24
800e7b2: 623b str r3, [r7, #32]
pxBlock = pxBlock->pxNextFreeBlock;
800e7b4: 6a7b ldr r3, [r7, #36] ; 0x24
800e7b6: 681b ldr r3, [r3, #0]
800e7b8: 627b str r3, [r7, #36] ; 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
800e7ba: 6a7b ldr r3, [r7, #36] ; 0x24
800e7bc: 685b ldr r3, [r3, #4]
800e7be: 687a ldr r2, [r7, #4]
800e7c0: 429a cmp r2, r3
800e7c2: d903 bls.n 800e7cc <pvPortMalloc+0xa8>
800e7c4: 6a7b ldr r3, [r7, #36] ; 0x24
800e7c6: 681b ldr r3, [r3, #0]
800e7c8: 2b00 cmp r3, #0
800e7ca: d1f1 bne.n 800e7b0 <pvPortMalloc+0x8c>
}
/* If the end marker was reached then a block of adequate size
was not found. */
if( pxBlock != pxEnd )
800e7cc: 4b38 ldr r3, [pc, #224] ; (800e8b0 <pvPortMalloc+0x18c>)
800e7ce: 681b ldr r3, [r3, #0]
800e7d0: 6a7a ldr r2, [r7, #36] ; 0x24
800e7d2: 429a cmp r2, r3
800e7d4: d04d beq.n 800e872 <pvPortMalloc+0x14e>
{
/* Return the memory space pointed to - jumping over the
BlockLink_t structure at its start. */
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
800e7d6: 6a3b ldr r3, [r7, #32]
800e7d8: 681b ldr r3, [r3, #0]
800e7da: 2208 movs r2, #8
800e7dc: 4413 add r3, r2
800e7de: 61fb str r3, [r7, #28]
/* This block is being returned for use so must be taken out
of the list of free blocks. */
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
800e7e0: 6a7b ldr r3, [r7, #36] ; 0x24
800e7e2: 681a ldr r2, [r3, #0]
800e7e4: 6a3b ldr r3, [r7, #32]
800e7e6: 601a str r2, [r3, #0]
/* If the block is larger than required it can be split into
two. */
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
800e7e8: 6a7b ldr r3, [r7, #36] ; 0x24
800e7ea: 685a ldr r2, [r3, #4]
800e7ec: 687b ldr r3, [r7, #4]
800e7ee: 1ad2 subs r2, r2, r3
800e7f0: 2308 movs r3, #8
800e7f2: 005b lsls r3, r3, #1
800e7f4: 429a cmp r2, r3
800e7f6: d921 bls.n 800e83c <pvPortMalloc+0x118>
{
/* This block is to be split into two. Create a new
block following the number of bytes requested. The void
cast is used to prevent byte alignment warnings from the
compiler. */
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
800e7f8: 6a7a ldr r2, [r7, #36] ; 0x24
800e7fa: 687b ldr r3, [r7, #4]
800e7fc: 4413 add r3, r2
800e7fe: 61bb str r3, [r7, #24]
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
800e800: 69bb ldr r3, [r7, #24]
800e802: f003 0307 and.w r3, r3, #7
800e806: 2b00 cmp r3, #0
800e808: d00c beq.n 800e824 <pvPortMalloc+0x100>
__asm volatile
800e80a: f04f 0350 mov.w r3, #80 ; 0x50
800e80e: b672 cpsid i
800e810: f383 8811 msr BASEPRI, r3
800e814: f3bf 8f6f isb sy
800e818: f3bf 8f4f dsb sy
800e81c: b662 cpsie i
800e81e: 613b str r3, [r7, #16]
}
800e820: bf00 nop
800e822: e7fe b.n 800e822 <pvPortMalloc+0xfe>
/* Calculate the sizes of two blocks split from the
single block. */
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
800e824: 6a7b ldr r3, [r7, #36] ; 0x24
800e826: 685a ldr r2, [r3, #4]
800e828: 687b ldr r3, [r7, #4]
800e82a: 1ad2 subs r2, r2, r3
800e82c: 69bb ldr r3, [r7, #24]
800e82e: 605a str r2, [r3, #4]
pxBlock->xBlockSize = xWantedSize;
800e830: 6a7b ldr r3, [r7, #36] ; 0x24
800e832: 687a ldr r2, [r7, #4]
800e834: 605a str r2, [r3, #4]
/* Insert the new block into the list of free blocks. */
prvInsertBlockIntoFreeList( pxNewBlockLink );
800e836: 69b8 ldr r0, [r7, #24]
800e838: f000 f904 bl 800ea44 <prvInsertBlockIntoFreeList>
else
{
mtCOVERAGE_TEST_MARKER();
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
800e83c: 4b1e ldr r3, [pc, #120] ; (800e8b8 <pvPortMalloc+0x194>)
800e83e: 681a ldr r2, [r3, #0]
800e840: 6a7b ldr r3, [r7, #36] ; 0x24
800e842: 685b ldr r3, [r3, #4]
800e844: 1ad3 subs r3, r2, r3
800e846: 4a1c ldr r2, [pc, #112] ; (800e8b8 <pvPortMalloc+0x194>)
800e848: 6013 str r3, [r2, #0]
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
800e84a: 4b1b ldr r3, [pc, #108] ; (800e8b8 <pvPortMalloc+0x194>)
800e84c: 681a ldr r2, [r3, #0]
800e84e: 4b1c ldr r3, [pc, #112] ; (800e8c0 <pvPortMalloc+0x19c>)
800e850: 681b ldr r3, [r3, #0]
800e852: 429a cmp r2, r3
800e854: d203 bcs.n 800e85e <pvPortMalloc+0x13a>
{
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
800e856: 4b18 ldr r3, [pc, #96] ; (800e8b8 <pvPortMalloc+0x194>)
800e858: 681b ldr r3, [r3, #0]
800e85a: 4a19 ldr r2, [pc, #100] ; (800e8c0 <pvPortMalloc+0x19c>)
800e85c: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
/* The block is being returned - it is allocated and owned
by the application and has no "next" block. */
pxBlock->xBlockSize |= xBlockAllocatedBit;
800e85e: 6a7b ldr r3, [r7, #36] ; 0x24
800e860: 685a ldr r2, [r3, #4]
800e862: 4b14 ldr r3, [pc, #80] ; (800e8b4 <pvPortMalloc+0x190>)
800e864: 681b ldr r3, [r3, #0]
800e866: 431a orrs r2, r3
800e868: 6a7b ldr r3, [r7, #36] ; 0x24
800e86a: 605a str r2, [r3, #4]
pxBlock->pxNextFreeBlock = NULL;
800e86c: 6a7b ldr r3, [r7, #36] ; 0x24
800e86e: 2200 movs r2, #0
800e870: 601a str r2, [r3, #0]
mtCOVERAGE_TEST_MARKER();
}
traceMALLOC( pvReturn, xWantedSize );
}
( void ) xTaskResumeAll();
800e872: f7fe fef5 bl 800d660 <xTaskResumeAll>
#if( configUSE_MALLOC_FAILED_HOOK == 1 )
{
if( pvReturn == NULL )
800e876: 69fb ldr r3, [r7, #28]
800e878: 2b00 cmp r3, #0
800e87a: d101 bne.n 800e880 <pvPortMalloc+0x15c>
{
extern void vApplicationMallocFailedHook( void );
vApplicationMallocFailedHook();
800e87c: f7f1 fea6 bl 80005cc <vApplicationMallocFailedHook>
mtCOVERAGE_TEST_MARKER();
}
}
#endif
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
800e880: 69fb ldr r3, [r7, #28]
800e882: f003 0307 and.w r3, r3, #7
800e886: 2b00 cmp r3, #0
800e888: d00c beq.n 800e8a4 <pvPortMalloc+0x180>
__asm volatile
800e88a: f04f 0350 mov.w r3, #80 ; 0x50
800e88e: b672 cpsid i
800e890: f383 8811 msr BASEPRI, r3
800e894: f3bf 8f6f isb sy
800e898: f3bf 8f4f dsb sy
800e89c: b662 cpsie i
800e89e: 60fb str r3, [r7, #12]
}
800e8a0: bf00 nop
800e8a2: e7fe b.n 800e8a2 <pvPortMalloc+0x17e>
return pvReturn;
800e8a4: 69fb ldr r3, [r7, #28]
}
800e8a6: 4618 mov r0, r3
800e8a8: 3728 adds r7, #40 ; 0x28
800e8aa: 46bd mov sp, r7
800e8ac: bd80 pop {r7, pc}
800e8ae: bf00 nop
800e8b0: 200086bc .word 0x200086bc
800e8b4: 200086c8 .word 0x200086c8
800e8b8: 200086c0 .word 0x200086c0
800e8bc: 200086b4 .word 0x200086b4
800e8c0: 200086c4 .word 0x200086c4
0800e8c4 <vPortFree>:
/*-----------------------------------------------------------*/
void vPortFree( void *pv )
{
800e8c4: b580 push {r7, lr}
800e8c6: b086 sub sp, #24
800e8c8: af00 add r7, sp, #0
800e8ca: 6078 str r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
800e8cc: 687b ldr r3, [r7, #4]
800e8ce: 617b str r3, [r7, #20]
BlockLink_t *pxLink;
if( pv != NULL )
800e8d0: 687b ldr r3, [r7, #4]
800e8d2: 2b00 cmp r3, #0
800e8d4: d04c beq.n 800e970 <vPortFree+0xac>
{
/* The memory being freed will have an BlockLink_t structure immediately
before it. */
puc -= xHeapStructSize;
800e8d6: 2308 movs r3, #8
800e8d8: 425b negs r3, r3
800e8da: 697a ldr r2, [r7, #20]
800e8dc: 4413 add r3, r2
800e8de: 617b str r3, [r7, #20]
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
800e8e0: 697b ldr r3, [r7, #20]
800e8e2: 613b str r3, [r7, #16]
/* Check the block is actually allocated. */
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
800e8e4: 693b ldr r3, [r7, #16]
800e8e6: 685a ldr r2, [r3, #4]
800e8e8: 4b23 ldr r3, [pc, #140] ; (800e978 <vPortFree+0xb4>)
800e8ea: 681b ldr r3, [r3, #0]
800e8ec: 4013 ands r3, r2
800e8ee: 2b00 cmp r3, #0
800e8f0: d10c bne.n 800e90c <vPortFree+0x48>
__asm volatile
800e8f2: f04f 0350 mov.w r3, #80 ; 0x50
800e8f6: b672 cpsid i
800e8f8: f383 8811 msr BASEPRI, r3
800e8fc: f3bf 8f6f isb sy
800e900: f3bf 8f4f dsb sy
800e904: b662 cpsie i
800e906: 60fb str r3, [r7, #12]
}
800e908: bf00 nop
800e90a: e7fe b.n 800e90a <vPortFree+0x46>
configASSERT( pxLink->pxNextFreeBlock == NULL );
800e90c: 693b ldr r3, [r7, #16]
800e90e: 681b ldr r3, [r3, #0]
800e910: 2b00 cmp r3, #0
800e912: d00c beq.n 800e92e <vPortFree+0x6a>
__asm volatile
800e914: f04f 0350 mov.w r3, #80 ; 0x50
800e918: b672 cpsid i
800e91a: f383 8811 msr BASEPRI, r3
800e91e: f3bf 8f6f isb sy
800e922: f3bf 8f4f dsb sy
800e926: b662 cpsie i
800e928: 60bb str r3, [r7, #8]
}
800e92a: bf00 nop
800e92c: e7fe b.n 800e92c <vPortFree+0x68>
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
800e92e: 693b ldr r3, [r7, #16]
800e930: 685a ldr r2, [r3, #4]
800e932: 4b11 ldr r3, [pc, #68] ; (800e978 <vPortFree+0xb4>)
800e934: 681b ldr r3, [r3, #0]
800e936: 4013 ands r3, r2
800e938: 2b00 cmp r3, #0
800e93a: d019 beq.n 800e970 <vPortFree+0xac>
{
if( pxLink->pxNextFreeBlock == NULL )
800e93c: 693b ldr r3, [r7, #16]
800e93e: 681b ldr r3, [r3, #0]
800e940: 2b00 cmp r3, #0
800e942: d115 bne.n 800e970 <vPortFree+0xac>
{
/* The block is being returned to the heap - it is no longer
allocated. */
pxLink->xBlockSize &= ~xBlockAllocatedBit;
800e944: 693b ldr r3, [r7, #16]
800e946: 685a ldr r2, [r3, #4]
800e948: 4b0b ldr r3, [pc, #44] ; (800e978 <vPortFree+0xb4>)
800e94a: 681b ldr r3, [r3, #0]
800e94c: 43db mvns r3, r3
800e94e: 401a ands r2, r3
800e950: 693b ldr r3, [r7, #16]
800e952: 605a str r2, [r3, #4]
vTaskSuspendAll();
800e954: f7fe fe76 bl 800d644 <vTaskSuspendAll>
{
/* Add this block to the list of free blocks. */
xFreeBytesRemaining += pxLink->xBlockSize;
800e958: 693b ldr r3, [r7, #16]
800e95a: 685a ldr r2, [r3, #4]
800e95c: 4b07 ldr r3, [pc, #28] ; (800e97c <vPortFree+0xb8>)
800e95e: 681b ldr r3, [r3, #0]
800e960: 4413 add r3, r2
800e962: 4a06 ldr r2, [pc, #24] ; (800e97c <vPortFree+0xb8>)
800e964: 6013 str r3, [r2, #0]
traceFREE( pv, pxLink->xBlockSize );
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
800e966: 6938 ldr r0, [r7, #16]
800e968: f000 f86c bl 800ea44 <prvInsertBlockIntoFreeList>
}
( void ) xTaskResumeAll();
800e96c: f7fe fe78 bl 800d660 <xTaskResumeAll>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
800e970: bf00 nop
800e972: 3718 adds r7, #24
800e974: 46bd mov sp, r7
800e976: bd80 pop {r7, pc}
800e978: 200086c8 .word 0x200086c8
800e97c: 200086c0 .word 0x200086c0
0800e980 <prvHeapInit>:
/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
{
800e980: b480 push {r7}
800e982: b085 sub sp, #20
800e984: af00 add r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
800e986: f44f 4300 mov.w r3, #32768 ; 0x8000
800e98a: 60bb str r3, [r7, #8]
/* Ensure the heap starts on a correctly aligned boundary. */
uxAddress = ( size_t ) ucHeap;
800e98c: 4b27 ldr r3, [pc, #156] ; (800ea2c <prvHeapInit+0xac>)
800e98e: 60fb str r3, [r7, #12]
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
800e990: 68fb ldr r3, [r7, #12]
800e992: f003 0307 and.w r3, r3, #7
800e996: 2b00 cmp r3, #0
800e998: d00c beq.n 800e9b4 <prvHeapInit+0x34>
{
uxAddress += ( portBYTE_ALIGNMENT - 1 );
800e99a: 68fb ldr r3, [r7, #12]
800e99c: 3307 adds r3, #7
800e99e: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
800e9a0: 68fb ldr r3, [r7, #12]
800e9a2: f023 0307 bic.w r3, r3, #7
800e9a6: 60fb str r3, [r7, #12]
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
800e9a8: 68ba ldr r2, [r7, #8]
800e9aa: 68fb ldr r3, [r7, #12]
800e9ac: 1ad3 subs r3, r2, r3
800e9ae: 4a1f ldr r2, [pc, #124] ; (800ea2c <prvHeapInit+0xac>)
800e9b0: 4413 add r3, r2
800e9b2: 60bb str r3, [r7, #8]
}
pucAlignedHeap = ( uint8_t * ) uxAddress;
800e9b4: 68fb ldr r3, [r7, #12]
800e9b6: 607b str r3, [r7, #4]
/* xStart is used to hold a pointer to the first item in the list of free
blocks. The void cast is used to prevent compiler warnings. */
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
800e9b8: 4a1d ldr r2, [pc, #116] ; (800ea30 <prvHeapInit+0xb0>)
800e9ba: 687b ldr r3, [r7, #4]
800e9bc: 6013 str r3, [r2, #0]
xStart.xBlockSize = ( size_t ) 0;
800e9be: 4b1c ldr r3, [pc, #112] ; (800ea30 <prvHeapInit+0xb0>)
800e9c0: 2200 movs r2, #0
800e9c2: 605a str r2, [r3, #4]
/* pxEnd is used to mark the end of the list of free blocks and is inserted
at the end of the heap space. */
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
800e9c4: 687b ldr r3, [r7, #4]
800e9c6: 68ba ldr r2, [r7, #8]
800e9c8: 4413 add r3, r2
800e9ca: 60fb str r3, [r7, #12]
uxAddress -= xHeapStructSize;
800e9cc: 2208 movs r2, #8
800e9ce: 68fb ldr r3, [r7, #12]
800e9d0: 1a9b subs r3, r3, r2
800e9d2: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
800e9d4: 68fb ldr r3, [r7, #12]
800e9d6: f023 0307 bic.w r3, r3, #7
800e9da: 60fb str r3, [r7, #12]
pxEnd = ( void * ) uxAddress;
800e9dc: 68fb ldr r3, [r7, #12]
800e9de: 4a15 ldr r2, [pc, #84] ; (800ea34 <prvHeapInit+0xb4>)
800e9e0: 6013 str r3, [r2, #0]
pxEnd->xBlockSize = 0;
800e9e2: 4b14 ldr r3, [pc, #80] ; (800ea34 <prvHeapInit+0xb4>)
800e9e4: 681b ldr r3, [r3, #0]
800e9e6: 2200 movs r2, #0
800e9e8: 605a str r2, [r3, #4]
pxEnd->pxNextFreeBlock = NULL;
800e9ea: 4b12 ldr r3, [pc, #72] ; (800ea34 <prvHeapInit+0xb4>)
800e9ec: 681b ldr r3, [r3, #0]
800e9ee: 2200 movs r2, #0
800e9f0: 601a str r2, [r3, #0]
/* To start with there is a single free block that is sized to take up the
entire heap space, minus the space taken by pxEnd. */
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
800e9f2: 687b ldr r3, [r7, #4]
800e9f4: 603b str r3, [r7, #0]
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
800e9f6: 683b ldr r3, [r7, #0]
800e9f8: 68fa ldr r2, [r7, #12]
800e9fa: 1ad2 subs r2, r2, r3
800e9fc: 683b ldr r3, [r7, #0]
800e9fe: 605a str r2, [r3, #4]
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
800ea00: 4b0c ldr r3, [pc, #48] ; (800ea34 <prvHeapInit+0xb4>)
800ea02: 681a ldr r2, [r3, #0]
800ea04: 683b ldr r3, [r7, #0]
800ea06: 601a str r2, [r3, #0]
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
800ea08: 683b ldr r3, [r7, #0]
800ea0a: 685b ldr r3, [r3, #4]
800ea0c: 4a0a ldr r2, [pc, #40] ; (800ea38 <prvHeapInit+0xb8>)
800ea0e: 6013 str r3, [r2, #0]
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
800ea10: 683b ldr r3, [r7, #0]
800ea12: 685b ldr r3, [r3, #4]
800ea14: 4a09 ldr r2, [pc, #36] ; (800ea3c <prvHeapInit+0xbc>)
800ea16: 6013 str r3, [r2, #0]
/* Work out the position of the top bit in a size_t variable. */
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
800ea18: 4b09 ldr r3, [pc, #36] ; (800ea40 <prvHeapInit+0xc0>)
800ea1a: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
800ea1e: 601a str r2, [r3, #0]
}
800ea20: bf00 nop
800ea22: 3714 adds r7, #20
800ea24: 46bd mov sp, r7
800ea26: f85d 7b04 ldr.w r7, [sp], #4
800ea2a: 4770 bx lr
800ea2c: 200006b4 .word 0x200006b4
800ea30: 200086b4 .word 0x200086b4
800ea34: 200086bc .word 0x200086bc
800ea38: 200086c4 .word 0x200086c4
800ea3c: 200086c0 .word 0x200086c0
800ea40: 200086c8 .word 0x200086c8
0800ea44 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/
static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
800ea44: b480 push {r7}
800ea46: b085 sub sp, #20
800ea48: af00 add r7, sp, #0
800ea4a: 6078 str r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;
/* Iterate through the list until a block is found that has a higher address
than the block being inserted. */
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
800ea4c: 4b28 ldr r3, [pc, #160] ; (800eaf0 <prvInsertBlockIntoFreeList+0xac>)
800ea4e: 60fb str r3, [r7, #12]
800ea50: e002 b.n 800ea58 <prvInsertBlockIntoFreeList+0x14>
800ea52: 68fb ldr r3, [r7, #12]
800ea54: 681b ldr r3, [r3, #0]
800ea56: 60fb str r3, [r7, #12]
800ea58: 68fb ldr r3, [r7, #12]
800ea5a: 681b ldr r3, [r3, #0]
800ea5c: 687a ldr r2, [r7, #4]
800ea5e: 429a cmp r2, r3
800ea60: d8f7 bhi.n 800ea52 <prvInsertBlockIntoFreeList+0xe>
/* Nothing to do here, just iterate to the right position. */
}
/* Do the block being inserted, and the block it is being inserted after
make a contiguous block of memory? */
puc = ( uint8_t * ) pxIterator;
800ea62: 68fb ldr r3, [r7, #12]
800ea64: 60bb str r3, [r7, #8]
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
800ea66: 68fb ldr r3, [r7, #12]
800ea68: 685b ldr r3, [r3, #4]
800ea6a: 68ba ldr r2, [r7, #8]
800ea6c: 4413 add r3, r2
800ea6e: 687a ldr r2, [r7, #4]
800ea70: 429a cmp r2, r3
800ea72: d108 bne.n 800ea86 <prvInsertBlockIntoFreeList+0x42>
{
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
800ea74: 68fb ldr r3, [r7, #12]
800ea76: 685a ldr r2, [r3, #4]
800ea78: 687b ldr r3, [r7, #4]
800ea7a: 685b ldr r3, [r3, #4]
800ea7c: 441a add r2, r3
800ea7e: 68fb ldr r3, [r7, #12]
800ea80: 605a str r2, [r3, #4]
pxBlockToInsert = pxIterator;
800ea82: 68fb ldr r3, [r7, #12]
800ea84: 607b str r3, [r7, #4]
mtCOVERAGE_TEST_MARKER();
}
/* Do the block being inserted, and the block it is being inserted before
make a contiguous block of memory? */
puc = ( uint8_t * ) pxBlockToInsert;
800ea86: 687b ldr r3, [r7, #4]
800ea88: 60bb str r3, [r7, #8]
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
800ea8a: 687b ldr r3, [r7, #4]
800ea8c: 685b ldr r3, [r3, #4]
800ea8e: 68ba ldr r2, [r7, #8]
800ea90: 441a add r2, r3
800ea92: 68fb ldr r3, [r7, #12]
800ea94: 681b ldr r3, [r3, #0]
800ea96: 429a cmp r2, r3
800ea98: d118 bne.n 800eacc <prvInsertBlockIntoFreeList+0x88>
{
if( pxIterator->pxNextFreeBlock != pxEnd )
800ea9a: 68fb ldr r3, [r7, #12]
800ea9c: 681a ldr r2, [r3, #0]
800ea9e: 4b15 ldr r3, [pc, #84] ; (800eaf4 <prvInsertBlockIntoFreeList+0xb0>)
800eaa0: 681b ldr r3, [r3, #0]
800eaa2: 429a cmp r2, r3
800eaa4: d00d beq.n 800eac2 <prvInsertBlockIntoFreeList+0x7e>
{
/* Form one big block from the two blocks. */
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
800eaa6: 687b ldr r3, [r7, #4]
800eaa8: 685a ldr r2, [r3, #4]
800eaaa: 68fb ldr r3, [r7, #12]
800eaac: 681b ldr r3, [r3, #0]
800eaae: 685b ldr r3, [r3, #4]
800eab0: 441a add r2, r3
800eab2: 687b ldr r3, [r7, #4]
800eab4: 605a str r2, [r3, #4]
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
800eab6: 68fb ldr r3, [r7, #12]
800eab8: 681b ldr r3, [r3, #0]
800eaba: 681a ldr r2, [r3, #0]
800eabc: 687b ldr r3, [r7, #4]
800eabe: 601a str r2, [r3, #0]
800eac0: e008 b.n 800ead4 <prvInsertBlockIntoFreeList+0x90>
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxEnd;
800eac2: 4b0c ldr r3, [pc, #48] ; (800eaf4 <prvInsertBlockIntoFreeList+0xb0>)
800eac4: 681a ldr r2, [r3, #0]
800eac6: 687b ldr r3, [r7, #4]
800eac8: 601a str r2, [r3, #0]
800eaca: e003 b.n 800ead4 <prvInsertBlockIntoFreeList+0x90>
}
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
800eacc: 68fb ldr r3, [r7, #12]
800eace: 681a ldr r2, [r3, #0]
800ead0: 687b ldr r3, [r7, #4]
800ead2: 601a str r2, [r3, #0]
/* If the block being inserted plugged a gab, so was merged with the block
before and the block after, then it's pxNextFreeBlock pointer will have
already been set, and should not be set here as that would make it point
to itself. */
if( pxIterator != pxBlockToInsert )
800ead4: 68fa ldr r2, [r7, #12]
800ead6: 687b ldr r3, [r7, #4]
800ead8: 429a cmp r2, r3
800eada: d002 beq.n 800eae2 <prvInsertBlockIntoFreeList+0x9e>
{
pxIterator->pxNextFreeBlock = pxBlockToInsert;
800eadc: 68fb ldr r3, [r7, #12]
800eade: 687a ldr r2, [r7, #4]
800eae0: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800eae2: bf00 nop
800eae4: 3714 adds r7, #20
800eae6: 46bd mov sp, r7
800eae8: f85d 7b04 ldr.w r7, [sp], #4
800eaec: 4770 bx lr
800eaee: bf00 nop
800eaf0: 200086b4 .word 0x200086b4
800eaf4: 200086bc .word 0x200086bc
0800eaf8 <tcpip_timeouts_mbox_fetch>:
* @param mbox the mbox to fetch the message from
* @param msg the place to store the message
*/
static void
tcpip_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg)
{
800eaf8: b580 push {r7, lr}
800eafa: b084 sub sp, #16
800eafc: af00 add r7, sp, #0
800eafe: 6078 str r0, [r7, #4]
800eb00: 6039 str r1, [r7, #0]
u32_t sleeptime, res;
again:
LWIP_ASSERT_CORE_LOCKED();
sleeptime = sys_timeouts_sleeptime();
800eb02: f007 fa97 bl 8016034 <sys_timeouts_sleeptime>
800eb06: 60f8 str r0, [r7, #12]
if (sleeptime == SYS_TIMEOUTS_SLEEPTIME_INFINITE) {
800eb08: 68fb ldr r3, [r7, #12]
800eb0a: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800eb0e: d10b bne.n 800eb28 <tcpip_timeouts_mbox_fetch+0x30>
UNLOCK_TCPIP_CORE();
800eb10: 4813 ldr r0, [pc, #76] ; (800eb60 <tcpip_timeouts_mbox_fetch+0x68>)
800eb12: f00c f9be bl 801ae92 <sys_mutex_unlock>
sys_arch_mbox_fetch(mbox, msg, 0);
800eb16: 2200 movs r2, #0
800eb18: 6839 ldr r1, [r7, #0]
800eb1a: 6878 ldr r0, [r7, #4]
800eb1c: f00c f930 bl 801ad80 <sys_arch_mbox_fetch>
LOCK_TCPIP_CORE();
800eb20: 480f ldr r0, [pc, #60] ; (800eb60 <tcpip_timeouts_mbox_fetch+0x68>)
800eb22: f00c f9a7 bl 801ae74 <sys_mutex_lock>
return;
800eb26: e018 b.n 800eb5a <tcpip_timeouts_mbox_fetch+0x62>
} else if (sleeptime == 0) {
800eb28: 68fb ldr r3, [r7, #12]
800eb2a: 2b00 cmp r3, #0
800eb2c: d102 bne.n 800eb34 <tcpip_timeouts_mbox_fetch+0x3c>
sys_check_timeouts();
800eb2e: f007 fa47 bl 8015fc0 <sys_check_timeouts>
/* We try again to fetch a message from the mbox. */
goto again;
800eb32: e7e6 b.n 800eb02 <tcpip_timeouts_mbox_fetch+0xa>
}
UNLOCK_TCPIP_CORE();
800eb34: 480a ldr r0, [pc, #40] ; (800eb60 <tcpip_timeouts_mbox_fetch+0x68>)
800eb36: f00c f9ac bl 801ae92 <sys_mutex_unlock>
res = sys_arch_mbox_fetch(mbox, msg, sleeptime);
800eb3a: 68fa ldr r2, [r7, #12]
800eb3c: 6839 ldr r1, [r7, #0]
800eb3e: 6878 ldr r0, [r7, #4]
800eb40: f00c f91e bl 801ad80 <sys_arch_mbox_fetch>
800eb44: 60b8 str r0, [r7, #8]
LOCK_TCPIP_CORE();
800eb46: 4806 ldr r0, [pc, #24] ; (800eb60 <tcpip_timeouts_mbox_fetch+0x68>)
800eb48: f00c f994 bl 801ae74 <sys_mutex_lock>
if (res == SYS_ARCH_TIMEOUT) {
800eb4c: 68bb ldr r3, [r7, #8]
800eb4e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800eb52: d102 bne.n 800eb5a <tcpip_timeouts_mbox_fetch+0x62>
/* If a SYS_ARCH_TIMEOUT value is returned, a timeout occurred
before a message could be fetched. */
sys_check_timeouts();
800eb54: f007 fa34 bl 8015fc0 <sys_check_timeouts>
/* We try again to fetch a message from the mbox. */
goto again;
800eb58: e7d3 b.n 800eb02 <tcpip_timeouts_mbox_fetch+0xa>
}
}
800eb5a: 3710 adds r7, #16
800eb5c: 46bd mov sp, r7
800eb5e: bd80 pop {r7, pc}
800eb60: 2000c104 .word 0x2000c104
0800eb64 <tcpip_thread>:
*
* @param arg unused argument
*/
static void
tcpip_thread(void *arg)
{
800eb64: b580 push {r7, lr}
800eb66: b084 sub sp, #16
800eb68: af00 add r7, sp, #0
800eb6a: 6078 str r0, [r7, #4]
struct tcpip_msg *msg;
LWIP_UNUSED_ARG(arg);
LWIP_MARK_TCPIP_THREAD();
LOCK_TCPIP_CORE();
800eb6c: 4810 ldr r0, [pc, #64] ; (800ebb0 <tcpip_thread+0x4c>)
800eb6e: f00c f981 bl 801ae74 <sys_mutex_lock>
if (tcpip_init_done != NULL) {
800eb72: 4b10 ldr r3, [pc, #64] ; (800ebb4 <tcpip_thread+0x50>)
800eb74: 681b ldr r3, [r3, #0]
800eb76: 2b00 cmp r3, #0
800eb78: d005 beq.n 800eb86 <tcpip_thread+0x22>
tcpip_init_done(tcpip_init_done_arg);
800eb7a: 4b0e ldr r3, [pc, #56] ; (800ebb4 <tcpip_thread+0x50>)
800eb7c: 681b ldr r3, [r3, #0]
800eb7e: 4a0e ldr r2, [pc, #56] ; (800ebb8 <tcpip_thread+0x54>)
800eb80: 6812 ldr r2, [r2, #0]
800eb82: 4610 mov r0, r2
800eb84: 4798 blx r3
}
while (1) { /* MAIN Loop */
LWIP_TCPIP_THREAD_ALIVE();
/* wait for a message, timeouts are processed while waiting */
TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg);
800eb86: f107 030c add.w r3, r7, #12
800eb8a: 4619 mov r1, r3
800eb8c: 480b ldr r0, [pc, #44] ; (800ebbc <tcpip_thread+0x58>)
800eb8e: f7ff ffb3 bl 800eaf8 <tcpip_timeouts_mbox_fetch>
if (msg == NULL) {
800eb92: 68fb ldr r3, [r7, #12]
800eb94: 2b00 cmp r3, #0
800eb96: d106 bne.n 800eba6 <tcpip_thread+0x42>
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: NULL\n"));
LWIP_ASSERT("tcpip_thread: invalid message", 0);
800eb98: 4b09 ldr r3, [pc, #36] ; (800ebc0 <tcpip_thread+0x5c>)
800eb9a: 2291 movs r2, #145 ; 0x91
800eb9c: 4909 ldr r1, [pc, #36] ; (800ebc4 <tcpip_thread+0x60>)
800eb9e: 480a ldr r0, [pc, #40] ; (800ebc8 <tcpip_thread+0x64>)
800eba0: f00c fa10 bl 801afc4 <iprintf>
continue;
800eba4: e003 b.n 800ebae <tcpip_thread+0x4a>
}
tcpip_thread_handle_msg(msg);
800eba6: 68fb ldr r3, [r7, #12]
800eba8: 4618 mov r0, r3
800ebaa: f000 f80f bl 800ebcc <tcpip_thread_handle_msg>
TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg);
800ebae: e7ea b.n 800eb86 <tcpip_thread+0x22>
800ebb0: 2000c104 .word 0x2000c104
800ebb4: 200086cc .word 0x200086cc
800ebb8: 200086d0 .word 0x200086d0
800ebbc: 200086d4 .word 0x200086d4
800ebc0: 0801c1a8 .word 0x0801c1a8
800ebc4: 0801c1d8 .word 0x0801c1d8
800ebc8: 0801c1f8 .word 0x0801c1f8
0800ebcc <tcpip_thread_handle_msg>:
/* Handle a single tcpip_msg
* This is in its own function for access by tests only.
*/
static void
tcpip_thread_handle_msg(struct tcpip_msg *msg)
{
800ebcc: b580 push {r7, lr}
800ebce: b082 sub sp, #8
800ebd0: af00 add r7, sp, #0
800ebd2: 6078 str r0, [r7, #4]
switch (msg->type) {
800ebd4: 687b ldr r3, [r7, #4]
800ebd6: 781b ldrb r3, [r3, #0]
800ebd8: 2b02 cmp r3, #2
800ebda: d026 beq.n 800ec2a <tcpip_thread_handle_msg+0x5e>
800ebdc: 2b02 cmp r3, #2
800ebde: dc2b bgt.n 800ec38 <tcpip_thread_handle_msg+0x6c>
800ebe0: 2b00 cmp r3, #0
800ebe2: d002 beq.n 800ebea <tcpip_thread_handle_msg+0x1e>
800ebe4: 2b01 cmp r3, #1
800ebe6: d015 beq.n 800ec14 <tcpip_thread_handle_msg+0x48>
800ebe8: e026 b.n 800ec38 <tcpip_thread_handle_msg+0x6c>
#endif /* !LWIP_TCPIP_CORE_LOCKING */
#if !LWIP_TCPIP_CORE_LOCKING_INPUT
case TCPIP_MSG_INPKT:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg));
if (msg->msg.inp.input_fn(msg->msg.inp.p, msg->msg.inp.netif) != ERR_OK) {
800ebea: 687b ldr r3, [r7, #4]
800ebec: 68db ldr r3, [r3, #12]
800ebee: 687a ldr r2, [r7, #4]
800ebf0: 6850 ldr r0, [r2, #4]
800ebf2: 687a ldr r2, [r7, #4]
800ebf4: 6892 ldr r2, [r2, #8]
800ebf6: 4611 mov r1, r2
800ebf8: 4798 blx r3
800ebfa: 4603 mov r3, r0
800ebfc: 2b00 cmp r3, #0
800ebfe: d004 beq.n 800ec0a <tcpip_thread_handle_msg+0x3e>
pbuf_free(msg->msg.inp.p);
800ec00: 687b ldr r3, [r7, #4]
800ec02: 685b ldr r3, [r3, #4]
800ec04: 4618 mov r0, r3
800ec06: f001 fcd1 bl 80105ac <pbuf_free>
}
memp_free(MEMP_TCPIP_MSG_INPKT, msg);
800ec0a: 6879 ldr r1, [r7, #4]
800ec0c: 2009 movs r0, #9
800ec0e: f000 fe1d bl 800f84c <memp_free>
break;
800ec12: e018 b.n 800ec46 <tcpip_thread_handle_msg+0x7a>
break;
#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
case TCPIP_MSG_CALLBACK:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
msg->msg.cb.function(msg->msg.cb.ctx);
800ec14: 687b ldr r3, [r7, #4]
800ec16: 685b ldr r3, [r3, #4]
800ec18: 687a ldr r2, [r7, #4]
800ec1a: 6892 ldr r2, [r2, #8]
800ec1c: 4610 mov r0, r2
800ec1e: 4798 blx r3
memp_free(MEMP_TCPIP_MSG_API, msg);
800ec20: 6879 ldr r1, [r7, #4]
800ec22: 2008 movs r0, #8
800ec24: f000 fe12 bl 800f84c <memp_free>
break;
800ec28: e00d b.n 800ec46 <tcpip_thread_handle_msg+0x7a>
case TCPIP_MSG_CALLBACK_STATIC:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK_STATIC %p\n", (void *)msg));
msg->msg.cb.function(msg->msg.cb.ctx);
800ec2a: 687b ldr r3, [r7, #4]
800ec2c: 685b ldr r3, [r3, #4]
800ec2e: 687a ldr r2, [r7, #4]
800ec30: 6892 ldr r2, [r2, #8]
800ec32: 4610 mov r0, r2
800ec34: 4798 blx r3
break;
800ec36: e006 b.n 800ec46 <tcpip_thread_handle_msg+0x7a>
default:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: %d\n", msg->type));
LWIP_ASSERT("tcpip_thread: invalid message", 0);
800ec38: 4b05 ldr r3, [pc, #20] ; (800ec50 <tcpip_thread_handle_msg+0x84>)
800ec3a: 22cf movs r2, #207 ; 0xcf
800ec3c: 4905 ldr r1, [pc, #20] ; (800ec54 <tcpip_thread_handle_msg+0x88>)
800ec3e: 4806 ldr r0, [pc, #24] ; (800ec58 <tcpip_thread_handle_msg+0x8c>)
800ec40: f00c f9c0 bl 801afc4 <iprintf>
break;
800ec44: bf00 nop
}
}
800ec46: bf00 nop
800ec48: 3708 adds r7, #8
800ec4a: 46bd mov sp, r7
800ec4c: bd80 pop {r7, pc}
800ec4e: bf00 nop
800ec50: 0801c1a8 .word 0x0801c1a8
800ec54: 0801c1d8 .word 0x0801c1d8
800ec58: 0801c1f8 .word 0x0801c1f8
0800ec5c <tcpip_inpkt>:
* @param inp the network interface on which the packet was received
* @param input_fn input function to call
*/
err_t
tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn)
{
800ec5c: b580 push {r7, lr}
800ec5e: b086 sub sp, #24
800ec60: af00 add r7, sp, #0
800ec62: 60f8 str r0, [r7, #12]
800ec64: 60b9 str r1, [r7, #8]
800ec66: 607a str r2, [r7, #4]
UNLOCK_TCPIP_CORE();
return ret;
#else /* LWIP_TCPIP_CORE_LOCKING_INPUT */
struct tcpip_msg *msg;
LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
800ec68: 481a ldr r0, [pc, #104] ; (800ecd4 <tcpip_inpkt+0x78>)
800ec6a: f00c f8c8 bl 801adfe <sys_mbox_valid>
800ec6e: 4603 mov r3, r0
800ec70: 2b00 cmp r3, #0
800ec72: d105 bne.n 800ec80 <tcpip_inpkt+0x24>
800ec74: 4b18 ldr r3, [pc, #96] ; (800ecd8 <tcpip_inpkt+0x7c>)
800ec76: 22fc movs r2, #252 ; 0xfc
800ec78: 4918 ldr r1, [pc, #96] ; (800ecdc <tcpip_inpkt+0x80>)
800ec7a: 4819 ldr r0, [pc, #100] ; (800ece0 <tcpip_inpkt+0x84>)
800ec7c: f00c f9a2 bl 801afc4 <iprintf>
msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_INPKT);
800ec80: 2009 movs r0, #9
800ec82: f000 fd91 bl 800f7a8 <memp_malloc>
800ec86: 6178 str r0, [r7, #20]
if (msg == NULL) {
800ec88: 697b ldr r3, [r7, #20]
800ec8a: 2b00 cmp r3, #0
800ec8c: d102 bne.n 800ec94 <tcpip_inpkt+0x38>
return ERR_MEM;
800ec8e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
800ec92: e01a b.n 800ecca <tcpip_inpkt+0x6e>
}
msg->type = TCPIP_MSG_INPKT;
800ec94: 697b ldr r3, [r7, #20]
800ec96: 2200 movs r2, #0
800ec98: 701a strb r2, [r3, #0]
msg->msg.inp.p = p;
800ec9a: 697b ldr r3, [r7, #20]
800ec9c: 68fa ldr r2, [r7, #12]
800ec9e: 605a str r2, [r3, #4]
msg->msg.inp.netif = inp;
800eca0: 697b ldr r3, [r7, #20]
800eca2: 68ba ldr r2, [r7, #8]
800eca4: 609a str r2, [r3, #8]
msg->msg.inp.input_fn = input_fn;
800eca6: 697b ldr r3, [r7, #20]
800eca8: 687a ldr r2, [r7, #4]
800ecaa: 60da str r2, [r3, #12]
if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) {
800ecac: 6979 ldr r1, [r7, #20]
800ecae: 4809 ldr r0, [pc, #36] ; (800ecd4 <tcpip_inpkt+0x78>)
800ecb0: f00c f84c bl 801ad4c <sys_mbox_trypost>
800ecb4: 4603 mov r3, r0
800ecb6: 2b00 cmp r3, #0
800ecb8: d006 beq.n 800ecc8 <tcpip_inpkt+0x6c>
memp_free(MEMP_TCPIP_MSG_INPKT, msg);
800ecba: 6979 ldr r1, [r7, #20]
800ecbc: 2009 movs r0, #9
800ecbe: f000 fdc5 bl 800f84c <memp_free>
return ERR_MEM;
800ecc2: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
800ecc6: e000 b.n 800ecca <tcpip_inpkt+0x6e>
}
return ERR_OK;
800ecc8: 2300 movs r3, #0
#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */
}
800ecca: 4618 mov r0, r3
800eccc: 3718 adds r7, #24
800ecce: 46bd mov sp, r7
800ecd0: bd80 pop {r7, pc}
800ecd2: bf00 nop
800ecd4: 200086d4 .word 0x200086d4
800ecd8: 0801c1a8 .word 0x0801c1a8
800ecdc: 0801c220 .word 0x0801c220
800ece0: 0801c1f8 .word 0x0801c1f8
0800ece4 <tcpip_input>:
* NETIF_FLAG_ETHERNET flags)
* @param inp the network interface on which the packet was received
*/
err_t
tcpip_input(struct pbuf *p, struct netif *inp)
{
800ece4: b580 push {r7, lr}
800ece6: b082 sub sp, #8
800ece8: af00 add r7, sp, #0
800ecea: 6078 str r0, [r7, #4]
800ecec: 6039 str r1, [r7, #0]
#if LWIP_ETHERNET
if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) {
800ecee: 683b ldr r3, [r7, #0]
800ecf0: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800ecf4: f003 0318 and.w r3, r3, #24
800ecf8: 2b00 cmp r3, #0
800ecfa: d006 beq.n 800ed0a <tcpip_input+0x26>
return tcpip_inpkt(p, inp, ethernet_input);
800ecfc: 4a08 ldr r2, [pc, #32] ; (800ed20 <tcpip_input+0x3c>)
800ecfe: 6839 ldr r1, [r7, #0]
800ed00: 6878 ldr r0, [r7, #4]
800ed02: f7ff ffab bl 800ec5c <tcpip_inpkt>
800ed06: 4603 mov r3, r0
800ed08: e005 b.n 800ed16 <tcpip_input+0x32>
} else
#endif /* LWIP_ETHERNET */
return tcpip_inpkt(p, inp, ip_input);
800ed0a: 4a06 ldr r2, [pc, #24] ; (800ed24 <tcpip_input+0x40>)
800ed0c: 6839 ldr r1, [r7, #0]
800ed0e: 6878 ldr r0, [r7, #4]
800ed10: f7ff ffa4 bl 800ec5c <tcpip_inpkt>
800ed14: 4603 mov r3, r0
}
800ed16: 4618 mov r0, r3
800ed18: 3708 adds r7, #8
800ed1a: 46bd mov sp, r7
800ed1c: bd80 pop {r7, pc}
800ed1e: bf00 nop
800ed20: 0801ab5d .word 0x0801ab5d
800ed24: 08019a35 .word 0x08019a35
0800ed28 <tcpip_try_callback>:
*
* @see tcpip_callback
*/
err_t
tcpip_try_callback(tcpip_callback_fn function, void *ctx)
{
800ed28: b580 push {r7, lr}
800ed2a: b084 sub sp, #16
800ed2c: af00 add r7, sp, #0
800ed2e: 6078 str r0, [r7, #4]
800ed30: 6039 str r1, [r7, #0]
struct tcpip_msg *msg;
LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
800ed32: 4819 ldr r0, [pc, #100] ; (800ed98 <tcpip_try_callback+0x70>)
800ed34: f00c f863 bl 801adfe <sys_mbox_valid>
800ed38: 4603 mov r3, r0
800ed3a: 2b00 cmp r3, #0
800ed3c: d106 bne.n 800ed4c <tcpip_try_callback+0x24>
800ed3e: 4b17 ldr r3, [pc, #92] ; (800ed9c <tcpip_try_callback+0x74>)
800ed40: f240 125d movw r2, #349 ; 0x15d
800ed44: 4916 ldr r1, [pc, #88] ; (800eda0 <tcpip_try_callback+0x78>)
800ed46: 4817 ldr r0, [pc, #92] ; (800eda4 <tcpip_try_callback+0x7c>)
800ed48: f00c f93c bl 801afc4 <iprintf>
msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
800ed4c: 2008 movs r0, #8
800ed4e: f000 fd2b bl 800f7a8 <memp_malloc>
800ed52: 60f8 str r0, [r7, #12]
if (msg == NULL) {
800ed54: 68fb ldr r3, [r7, #12]
800ed56: 2b00 cmp r3, #0
800ed58: d102 bne.n 800ed60 <tcpip_try_callback+0x38>
return ERR_MEM;
800ed5a: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
800ed5e: e017 b.n 800ed90 <tcpip_try_callback+0x68>
}
msg->type = TCPIP_MSG_CALLBACK;
800ed60: 68fb ldr r3, [r7, #12]
800ed62: 2201 movs r2, #1
800ed64: 701a strb r2, [r3, #0]
msg->msg.cb.function = function;
800ed66: 68fb ldr r3, [r7, #12]
800ed68: 687a ldr r2, [r7, #4]
800ed6a: 605a str r2, [r3, #4]
msg->msg.cb.ctx = ctx;
800ed6c: 68fb ldr r3, [r7, #12]
800ed6e: 683a ldr r2, [r7, #0]
800ed70: 609a str r2, [r3, #8]
if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) {
800ed72: 68f9 ldr r1, [r7, #12]
800ed74: 4808 ldr r0, [pc, #32] ; (800ed98 <tcpip_try_callback+0x70>)
800ed76: f00b ffe9 bl 801ad4c <sys_mbox_trypost>
800ed7a: 4603 mov r3, r0
800ed7c: 2b00 cmp r3, #0
800ed7e: d006 beq.n 800ed8e <tcpip_try_callback+0x66>
memp_free(MEMP_TCPIP_MSG_API, msg);
800ed80: 68f9 ldr r1, [r7, #12]
800ed82: 2008 movs r0, #8
800ed84: f000 fd62 bl 800f84c <memp_free>
return ERR_MEM;
800ed88: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
800ed8c: e000 b.n 800ed90 <tcpip_try_callback+0x68>
}
return ERR_OK;
800ed8e: 2300 movs r3, #0
}
800ed90: 4618 mov r0, r3
800ed92: 3710 adds r7, #16
800ed94: 46bd mov sp, r7
800ed96: bd80 pop {r7, pc}
800ed98: 200086d4 .word 0x200086d4
800ed9c: 0801c1a8 .word 0x0801c1a8
800eda0: 0801c220 .word 0x0801c220
800eda4: 0801c1f8 .word 0x0801c1f8
0800eda8 <tcpip_init>:
* @param initfunc a function to call when tcpip_thread is running and finished initializing
* @param arg argument to pass to initfunc
*/
void
tcpip_init(tcpip_init_done_fn initfunc, void *arg)
{
800eda8: b580 push {r7, lr}
800edaa: b084 sub sp, #16
800edac: af02 add r7, sp, #8
800edae: 6078 str r0, [r7, #4]
800edb0: 6039 str r1, [r7, #0]
lwip_init();
800edb2: f000 f871 bl 800ee98 <lwip_init>
tcpip_init_done = initfunc;
800edb6: 4a17 ldr r2, [pc, #92] ; (800ee14 <tcpip_init+0x6c>)
800edb8: 687b ldr r3, [r7, #4]
800edba: 6013 str r3, [r2, #0]
tcpip_init_done_arg = arg;
800edbc: 4a16 ldr r2, [pc, #88] ; (800ee18 <tcpip_init+0x70>)
800edbe: 683b ldr r3, [r7, #0]
800edc0: 6013 str r3, [r2, #0]
if (sys_mbox_new(&tcpip_mbox, TCPIP_MBOX_SIZE) != ERR_OK) {
800edc2: 2106 movs r1, #6
800edc4: 4815 ldr r0, [pc, #84] ; (800ee1c <tcpip_init+0x74>)
800edc6: f00b ff9f bl 801ad08 <sys_mbox_new>
800edca: 4603 mov r3, r0
800edcc: 2b00 cmp r3, #0
800edce: d006 beq.n 800edde <tcpip_init+0x36>
LWIP_ASSERT("failed to create tcpip_thread mbox", 0);
800edd0: 4b13 ldr r3, [pc, #76] ; (800ee20 <tcpip_init+0x78>)
800edd2: f240 2261 movw r2, #609 ; 0x261
800edd6: 4913 ldr r1, [pc, #76] ; (800ee24 <tcpip_init+0x7c>)
800edd8: 4813 ldr r0, [pc, #76] ; (800ee28 <tcpip_init+0x80>)
800edda: f00c f8f3 bl 801afc4 <iprintf>
}
#if LWIP_TCPIP_CORE_LOCKING
if (sys_mutex_new(&lock_tcpip_core) != ERR_OK) {
800edde: 4813 ldr r0, [pc, #76] ; (800ee2c <tcpip_init+0x84>)
800ede0: f00c f82c bl 801ae3c <sys_mutex_new>
800ede4: 4603 mov r3, r0
800ede6: 2b00 cmp r3, #0
800ede8: d006 beq.n 800edf8 <tcpip_init+0x50>
LWIP_ASSERT("failed to create lock_tcpip_core", 0);
800edea: 4b0d ldr r3, [pc, #52] ; (800ee20 <tcpip_init+0x78>)
800edec: f240 2265 movw r2, #613 ; 0x265
800edf0: 490f ldr r1, [pc, #60] ; (800ee30 <tcpip_init+0x88>)
800edf2: 480d ldr r0, [pc, #52] ; (800ee28 <tcpip_init+0x80>)
800edf4: f00c f8e6 bl 801afc4 <iprintf>
}
#endif /* LWIP_TCPIP_CORE_LOCKING */
sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO);
800edf8: 2300 movs r3, #0
800edfa: 9300 str r3, [sp, #0]
800edfc: f44f 6380 mov.w r3, #1024 ; 0x400
800ee00: 2200 movs r2, #0
800ee02: 490c ldr r1, [pc, #48] ; (800ee34 <tcpip_init+0x8c>)
800ee04: 480c ldr r0, [pc, #48] ; (800ee38 <tcpip_init+0x90>)
800ee06: f00c f851 bl 801aeac <sys_thread_new>
}
800ee0a: bf00 nop
800ee0c: 3708 adds r7, #8
800ee0e: 46bd mov sp, r7
800ee10: bd80 pop {r7, pc}
800ee12: bf00 nop
800ee14: 200086cc .word 0x200086cc
800ee18: 200086d0 .word 0x200086d0
800ee1c: 200086d4 .word 0x200086d4
800ee20: 0801c1a8 .word 0x0801c1a8
800ee24: 0801c230 .word 0x0801c230
800ee28: 0801c1f8 .word 0x0801c1f8
800ee2c: 2000c104 .word 0x2000c104
800ee30: 0801c254 .word 0x0801c254
800ee34: 0800eb65 .word 0x0800eb65
800ee38: 0801c278 .word 0x0801c278
0800ee3c <lwip_htons>:
* @param n u16_t in host byte order
* @return n in network byte order
*/
u16_t
lwip_htons(u16_t n)
{
800ee3c: b480 push {r7}
800ee3e: b083 sub sp, #12
800ee40: af00 add r7, sp, #0
800ee42: 4603 mov r3, r0
800ee44: 80fb strh r3, [r7, #6]
return PP_HTONS(n);
800ee46: 88fb ldrh r3, [r7, #6]
800ee48: 021b lsls r3, r3, #8
800ee4a: b21a sxth r2, r3
800ee4c: 88fb ldrh r3, [r7, #6]
800ee4e: 0a1b lsrs r3, r3, #8
800ee50: b29b uxth r3, r3
800ee52: b21b sxth r3, r3
800ee54: 4313 orrs r3, r2
800ee56: b21b sxth r3, r3
800ee58: b29b uxth r3, r3
}
800ee5a: 4618 mov r0, r3
800ee5c: 370c adds r7, #12
800ee5e: 46bd mov sp, r7
800ee60: f85d 7b04 ldr.w r7, [sp], #4
800ee64: 4770 bx lr
0800ee66 <lwip_htonl>:
* @param n u32_t in host byte order
* @return n in network byte order
*/
u32_t
lwip_htonl(u32_t n)
{
800ee66: b480 push {r7}
800ee68: b083 sub sp, #12
800ee6a: af00 add r7, sp, #0
800ee6c: 6078 str r0, [r7, #4]
return PP_HTONL(n);
800ee6e: 687b ldr r3, [r7, #4]
800ee70: 061a lsls r2, r3, #24
800ee72: 687b ldr r3, [r7, #4]
800ee74: 021b lsls r3, r3, #8
800ee76: f403 037f and.w r3, r3, #16711680 ; 0xff0000
800ee7a: 431a orrs r2, r3
800ee7c: 687b ldr r3, [r7, #4]
800ee7e: 0a1b lsrs r3, r3, #8
800ee80: f403 437f and.w r3, r3, #65280 ; 0xff00
800ee84: 431a orrs r2, r3
800ee86: 687b ldr r3, [r7, #4]
800ee88: 0e1b lsrs r3, r3, #24
800ee8a: 4313 orrs r3, r2
}
800ee8c: 4618 mov r0, r3
800ee8e: 370c adds r7, #12
800ee90: 46bd mov sp, r7
800ee92: f85d 7b04 ldr.w r7, [sp], #4
800ee96: 4770 bx lr
0800ee98 <lwip_init>:
* Initialize all modules.
* Use this in NO_SYS mode. Use tcpip_init() otherwise.
*/
void
lwip_init(void)
{
800ee98: b580 push {r7, lr}
800ee9a: b082 sub sp, #8
800ee9c: af00 add r7, sp, #0
#ifndef LWIP_SKIP_CONST_CHECK
int a = 0;
800ee9e: 2300 movs r3, #0
800eea0: 607b str r3, [r7, #4]
#endif
/* Modules initialization */
stats_init();
#if !NO_SYS
sys_init();
800eea2: f00b ffbd bl 801ae20 <sys_init>
#endif /* !NO_SYS */
mem_init();
800eea6: f000 f8d5 bl 800f054 <mem_init>
memp_init();
800eeaa: f000 fc31 bl 800f710 <memp_init>
pbuf_init();
netif_init();
800eeae: f000 fcf7 bl 800f8a0 <netif_init>
#endif /* LWIP_IPV4 */
#if LWIP_RAW
raw_init();
#endif /* LWIP_RAW */
#if LWIP_UDP
udp_init();
800eeb2: f007 f8f7 bl 80160a4 <udp_init>
#endif /* LWIP_UDP */
#if LWIP_TCP
tcp_init();
800eeb6: f001 fe23 bl 8010b00 <tcp_init>
#if PPP_SUPPORT
ppp_init();
#endif
#if LWIP_TIMERS
sys_timeouts_init();
800eeba: f007 f839 bl 8015f30 <sys_timeouts_init>
#endif /* LWIP_TIMERS */
}
800eebe: bf00 nop
800eec0: 3708 adds r7, #8
800eec2: 46bd mov sp, r7
800eec4: bd80 pop {r7, pc}
...
0800eec8 <ptr_to_mem>:
#define mem_overflow_check_element(mem)
#endif /* MEM_OVERFLOW_CHECK */
static struct mem *
ptr_to_mem(mem_size_t ptr)
{
800eec8: b480 push {r7}
800eeca: b083 sub sp, #12
800eecc: af00 add r7, sp, #0
800eece: 4603 mov r3, r0
800eed0: 80fb strh r3, [r7, #6]
return (struct mem *)(void *)&ram[ptr];
800eed2: 4b05 ldr r3, [pc, #20] ; (800eee8 <ptr_to_mem+0x20>)
800eed4: 681a ldr r2, [r3, #0]
800eed6: 88fb ldrh r3, [r7, #6]
800eed8: 4413 add r3, r2
}
800eeda: 4618 mov r0, r3
800eedc: 370c adds r7, #12
800eede: 46bd mov sp, r7
800eee0: f85d 7b04 ldr.w r7, [sp], #4
800eee4: 4770 bx lr
800eee6: bf00 nop
800eee8: 200086d8 .word 0x200086d8
0800eeec <mem_to_ptr>:
static mem_size_t
mem_to_ptr(void *mem)
{
800eeec: b480 push {r7}
800eeee: b083 sub sp, #12
800eef0: af00 add r7, sp, #0
800eef2: 6078 str r0, [r7, #4]
return (mem_size_t)((u8_t *)mem - ram);
800eef4: 4b05 ldr r3, [pc, #20] ; (800ef0c <mem_to_ptr+0x20>)
800eef6: 681b ldr r3, [r3, #0]
800eef8: 687a ldr r2, [r7, #4]
800eefa: 1ad3 subs r3, r2, r3
800eefc: b29b uxth r3, r3
}
800eefe: 4618 mov r0, r3
800ef00: 370c adds r7, #12
800ef02: 46bd mov sp, r7
800ef04: f85d 7b04 ldr.w r7, [sp], #4
800ef08: 4770 bx lr
800ef0a: bf00 nop
800ef0c: 200086d8 .word 0x200086d8
0800ef10 <plug_holes>:
* This assumes access to the heap is protected by the calling function
* already.
*/
static void
plug_holes(struct mem *mem)
{
800ef10: b590 push {r4, r7, lr}
800ef12: b085 sub sp, #20
800ef14: af00 add r7, sp, #0
800ef16: 6078 str r0, [r7, #4]
struct mem *nmem;
struct mem *pmem;
LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
800ef18: 4b45 ldr r3, [pc, #276] ; (800f030 <plug_holes+0x120>)
800ef1a: 681b ldr r3, [r3, #0]
800ef1c: 687a ldr r2, [r7, #4]
800ef1e: 429a cmp r2, r3
800ef20: d206 bcs.n 800ef30 <plug_holes+0x20>
800ef22: 4b44 ldr r3, [pc, #272] ; (800f034 <plug_holes+0x124>)
800ef24: f240 12df movw r2, #479 ; 0x1df
800ef28: 4943 ldr r1, [pc, #268] ; (800f038 <plug_holes+0x128>)
800ef2a: 4844 ldr r0, [pc, #272] ; (800f03c <plug_holes+0x12c>)
800ef2c: f00c f84a bl 801afc4 <iprintf>
LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
800ef30: 4b43 ldr r3, [pc, #268] ; (800f040 <plug_holes+0x130>)
800ef32: 681b ldr r3, [r3, #0]
800ef34: 687a ldr r2, [r7, #4]
800ef36: 429a cmp r2, r3
800ef38: d306 bcc.n 800ef48 <plug_holes+0x38>
800ef3a: 4b3e ldr r3, [pc, #248] ; (800f034 <plug_holes+0x124>)
800ef3c: f44f 72f0 mov.w r2, #480 ; 0x1e0
800ef40: 4940 ldr r1, [pc, #256] ; (800f044 <plug_holes+0x134>)
800ef42: 483e ldr r0, [pc, #248] ; (800f03c <plug_holes+0x12c>)
800ef44: f00c f83e bl 801afc4 <iprintf>
LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
800ef48: 687b ldr r3, [r7, #4]
800ef4a: 791b ldrb r3, [r3, #4]
800ef4c: 2b00 cmp r3, #0
800ef4e: d006 beq.n 800ef5e <plug_holes+0x4e>
800ef50: 4b38 ldr r3, [pc, #224] ; (800f034 <plug_holes+0x124>)
800ef52: f240 12e1 movw r2, #481 ; 0x1e1
800ef56: 493c ldr r1, [pc, #240] ; (800f048 <plug_holes+0x138>)
800ef58: 4838 ldr r0, [pc, #224] ; (800f03c <plug_holes+0x12c>)
800ef5a: f00c f833 bl 801afc4 <iprintf>
/* plug hole forward */
LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED);
800ef5e: 687b ldr r3, [r7, #4]
800ef60: 881b ldrh r3, [r3, #0]
800ef62: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800ef66: d906 bls.n 800ef76 <plug_holes+0x66>
800ef68: 4b32 ldr r3, [pc, #200] ; (800f034 <plug_holes+0x124>)
800ef6a: f44f 72f2 mov.w r2, #484 ; 0x1e4
800ef6e: 4937 ldr r1, [pc, #220] ; (800f04c <plug_holes+0x13c>)
800ef70: 4832 ldr r0, [pc, #200] ; (800f03c <plug_holes+0x12c>)
800ef72: f00c f827 bl 801afc4 <iprintf>
nmem = ptr_to_mem(mem->next);
800ef76: 687b ldr r3, [r7, #4]
800ef78: 881b ldrh r3, [r3, #0]
800ef7a: 4618 mov r0, r3
800ef7c: f7ff ffa4 bl 800eec8 <ptr_to_mem>
800ef80: 60f8 str r0, [r7, #12]
if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
800ef82: 687a ldr r2, [r7, #4]
800ef84: 68fb ldr r3, [r7, #12]
800ef86: 429a cmp r2, r3
800ef88: d024 beq.n 800efd4 <plug_holes+0xc4>
800ef8a: 68fb ldr r3, [r7, #12]
800ef8c: 791b ldrb r3, [r3, #4]
800ef8e: 2b00 cmp r3, #0
800ef90: d120 bne.n 800efd4 <plug_holes+0xc4>
800ef92: 4b2b ldr r3, [pc, #172] ; (800f040 <plug_holes+0x130>)
800ef94: 681b ldr r3, [r3, #0]
800ef96: 68fa ldr r2, [r7, #12]
800ef98: 429a cmp r2, r3
800ef9a: d01b beq.n 800efd4 <plug_holes+0xc4>
/* if mem->next is unused and not end of ram, combine mem and mem->next */
if (lfree == nmem) {
800ef9c: 4b2c ldr r3, [pc, #176] ; (800f050 <plug_holes+0x140>)
800ef9e: 681b ldr r3, [r3, #0]
800efa0: 68fa ldr r2, [r7, #12]
800efa2: 429a cmp r2, r3
800efa4: d102 bne.n 800efac <plug_holes+0x9c>
lfree = mem;
800efa6: 4a2a ldr r2, [pc, #168] ; (800f050 <plug_holes+0x140>)
800efa8: 687b ldr r3, [r7, #4]
800efaa: 6013 str r3, [r2, #0]
}
mem->next = nmem->next;
800efac: 68fb ldr r3, [r7, #12]
800efae: 881a ldrh r2, [r3, #0]
800efb0: 687b ldr r3, [r7, #4]
800efb2: 801a strh r2, [r3, #0]
if (nmem->next != MEM_SIZE_ALIGNED) {
800efb4: 68fb ldr r3, [r7, #12]
800efb6: 881b ldrh r3, [r3, #0]
800efb8: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800efbc: d00a beq.n 800efd4 <plug_holes+0xc4>
ptr_to_mem(nmem->next)->prev = mem_to_ptr(mem);
800efbe: 68fb ldr r3, [r7, #12]
800efc0: 881b ldrh r3, [r3, #0]
800efc2: 4618 mov r0, r3
800efc4: f7ff ff80 bl 800eec8 <ptr_to_mem>
800efc8: 4604 mov r4, r0
800efca: 6878 ldr r0, [r7, #4]
800efcc: f7ff ff8e bl 800eeec <mem_to_ptr>
800efd0: 4603 mov r3, r0
800efd2: 8063 strh r3, [r4, #2]
}
}
/* plug hole backward */
pmem = ptr_to_mem(mem->prev);
800efd4: 687b ldr r3, [r7, #4]
800efd6: 885b ldrh r3, [r3, #2]
800efd8: 4618 mov r0, r3
800efda: f7ff ff75 bl 800eec8 <ptr_to_mem>
800efde: 60b8 str r0, [r7, #8]
if (pmem != mem && pmem->used == 0) {
800efe0: 68ba ldr r2, [r7, #8]
800efe2: 687b ldr r3, [r7, #4]
800efe4: 429a cmp r2, r3
800efe6: d01f beq.n 800f028 <plug_holes+0x118>
800efe8: 68bb ldr r3, [r7, #8]
800efea: 791b ldrb r3, [r3, #4]
800efec: 2b00 cmp r3, #0
800efee: d11b bne.n 800f028 <plug_holes+0x118>
/* if mem->prev is unused, combine mem and mem->prev */
if (lfree == mem) {
800eff0: 4b17 ldr r3, [pc, #92] ; (800f050 <plug_holes+0x140>)
800eff2: 681b ldr r3, [r3, #0]
800eff4: 687a ldr r2, [r7, #4]
800eff6: 429a cmp r2, r3
800eff8: d102 bne.n 800f000 <plug_holes+0xf0>
lfree = pmem;
800effa: 4a15 ldr r2, [pc, #84] ; (800f050 <plug_holes+0x140>)
800effc: 68bb ldr r3, [r7, #8]
800effe: 6013 str r3, [r2, #0]
}
pmem->next = mem->next;
800f000: 687b ldr r3, [r7, #4]
800f002: 881a ldrh r2, [r3, #0]
800f004: 68bb ldr r3, [r7, #8]
800f006: 801a strh r2, [r3, #0]
if (mem->next != MEM_SIZE_ALIGNED) {
800f008: 687b ldr r3, [r7, #4]
800f00a: 881b ldrh r3, [r3, #0]
800f00c: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f010: d00a beq.n 800f028 <plug_holes+0x118>
ptr_to_mem(mem->next)->prev = mem_to_ptr(pmem);
800f012: 687b ldr r3, [r7, #4]
800f014: 881b ldrh r3, [r3, #0]
800f016: 4618 mov r0, r3
800f018: f7ff ff56 bl 800eec8 <ptr_to_mem>
800f01c: 4604 mov r4, r0
800f01e: 68b8 ldr r0, [r7, #8]
800f020: f7ff ff64 bl 800eeec <mem_to_ptr>
800f024: 4603 mov r3, r0
800f026: 8063 strh r3, [r4, #2]
}
}
}
800f028: bf00 nop
800f02a: 3714 adds r7, #20
800f02c: 46bd mov sp, r7
800f02e: bd90 pop {r4, r7, pc}
800f030: 200086d8 .word 0x200086d8
800f034: 0801c288 .word 0x0801c288
800f038: 0801c2b8 .word 0x0801c2b8
800f03c: 0801c2d0 .word 0x0801c2d0
800f040: 200086dc .word 0x200086dc
800f044: 0801c2f8 .word 0x0801c2f8
800f048: 0801c314 .word 0x0801c314
800f04c: 0801c330 .word 0x0801c330
800f050: 200086e4 .word 0x200086e4
0800f054 <mem_init>:
/**
* Zero the heap and initialize start, end and lowest-free
*/
void
mem_init(void)
{
800f054: b580 push {r7, lr}
800f056: b082 sub sp, #8
800f058: af00 add r7, sp, #0
LWIP_ASSERT("Sanity check alignment",
(SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT - 1)) == 0);
/* align the heap */
ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER);
800f05a: 4b1f ldr r3, [pc, #124] ; (800f0d8 <mem_init+0x84>)
800f05c: 3303 adds r3, #3
800f05e: f023 0303 bic.w r3, r3, #3
800f062: 461a mov r2, r3
800f064: 4b1d ldr r3, [pc, #116] ; (800f0dc <mem_init+0x88>)
800f066: 601a str r2, [r3, #0]
/* initialize the start of the heap */
mem = (struct mem *)(void *)ram;
800f068: 4b1c ldr r3, [pc, #112] ; (800f0dc <mem_init+0x88>)
800f06a: 681b ldr r3, [r3, #0]
800f06c: 607b str r3, [r7, #4]
mem->next = MEM_SIZE_ALIGNED;
800f06e: 687b ldr r3, [r7, #4]
800f070: f44f 62c8 mov.w r2, #1600 ; 0x640
800f074: 801a strh r2, [r3, #0]
mem->prev = 0;
800f076: 687b ldr r3, [r7, #4]
800f078: 2200 movs r2, #0
800f07a: 805a strh r2, [r3, #2]
mem->used = 0;
800f07c: 687b ldr r3, [r7, #4]
800f07e: 2200 movs r2, #0
800f080: 711a strb r2, [r3, #4]
/* initialize the end of the heap */
ram_end = ptr_to_mem(MEM_SIZE_ALIGNED);
800f082: f44f 60c8 mov.w r0, #1600 ; 0x640
800f086: f7ff ff1f bl 800eec8 <ptr_to_mem>
800f08a: 4603 mov r3, r0
800f08c: 4a14 ldr r2, [pc, #80] ; (800f0e0 <mem_init+0x8c>)
800f08e: 6013 str r3, [r2, #0]
ram_end->used = 1;
800f090: 4b13 ldr r3, [pc, #76] ; (800f0e0 <mem_init+0x8c>)
800f092: 681b ldr r3, [r3, #0]
800f094: 2201 movs r2, #1
800f096: 711a strb r2, [r3, #4]
ram_end->next = MEM_SIZE_ALIGNED;
800f098: 4b11 ldr r3, [pc, #68] ; (800f0e0 <mem_init+0x8c>)
800f09a: 681b ldr r3, [r3, #0]
800f09c: f44f 62c8 mov.w r2, #1600 ; 0x640
800f0a0: 801a strh r2, [r3, #0]
ram_end->prev = MEM_SIZE_ALIGNED;
800f0a2: 4b0f ldr r3, [pc, #60] ; (800f0e0 <mem_init+0x8c>)
800f0a4: 681b ldr r3, [r3, #0]
800f0a6: f44f 62c8 mov.w r2, #1600 ; 0x640
800f0aa: 805a strh r2, [r3, #2]
MEM_SANITY();
/* initialize the lowest-free pointer to the start of the heap */
lfree = (struct mem *)(void *)ram;
800f0ac: 4b0b ldr r3, [pc, #44] ; (800f0dc <mem_init+0x88>)
800f0ae: 681b ldr r3, [r3, #0]
800f0b0: 4a0c ldr r2, [pc, #48] ; (800f0e4 <mem_init+0x90>)
800f0b2: 6013 str r3, [r2, #0]
MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED);
if (sys_mutex_new(&mem_mutex) != ERR_OK) {
800f0b4: 480c ldr r0, [pc, #48] ; (800f0e8 <mem_init+0x94>)
800f0b6: f00b fec1 bl 801ae3c <sys_mutex_new>
800f0ba: 4603 mov r3, r0
800f0bc: 2b00 cmp r3, #0
800f0be: d006 beq.n 800f0ce <mem_init+0x7a>
LWIP_ASSERT("failed to create mem_mutex", 0);
800f0c0: 4b0a ldr r3, [pc, #40] ; (800f0ec <mem_init+0x98>)
800f0c2: f240 221f movw r2, #543 ; 0x21f
800f0c6: 490a ldr r1, [pc, #40] ; (800f0f0 <mem_init+0x9c>)
800f0c8: 480a ldr r0, [pc, #40] ; (800f0f4 <mem_init+0xa0>)
800f0ca: f00b ff7b bl 801afc4 <iprintf>
}
}
800f0ce: bf00 nop
800f0d0: 3708 adds r7, #8
800f0d2: 46bd mov sp, r7
800f0d4: bd80 pop {r7, pc}
800f0d6: bf00 nop
800f0d8: 2000c120 .word 0x2000c120
800f0dc: 200086d8 .word 0x200086d8
800f0e0: 200086dc .word 0x200086dc
800f0e4: 200086e4 .word 0x200086e4
800f0e8: 200086e0 .word 0x200086e0
800f0ec: 0801c288 .word 0x0801c288
800f0f0: 0801c35c .word 0x0801c35c
800f0f4: 0801c2d0 .word 0x0801c2d0
0800f0f8 <mem_link_valid>:
/* Check if a struct mem is correctly linked.
* If not, double-free is a possible reason.
*/
static int
mem_link_valid(struct mem *mem)
{
800f0f8: b580 push {r7, lr}
800f0fa: b086 sub sp, #24
800f0fc: af00 add r7, sp, #0
800f0fe: 6078 str r0, [r7, #4]
struct mem *nmem, *pmem;
mem_size_t rmem_idx;
rmem_idx = mem_to_ptr(mem);
800f100: 6878 ldr r0, [r7, #4]
800f102: f7ff fef3 bl 800eeec <mem_to_ptr>
800f106: 4603 mov r3, r0
800f108: 82fb strh r3, [r7, #22]
nmem = ptr_to_mem(mem->next);
800f10a: 687b ldr r3, [r7, #4]
800f10c: 881b ldrh r3, [r3, #0]
800f10e: 4618 mov r0, r3
800f110: f7ff feda bl 800eec8 <ptr_to_mem>
800f114: 6138 str r0, [r7, #16]
pmem = ptr_to_mem(mem->prev);
800f116: 687b ldr r3, [r7, #4]
800f118: 885b ldrh r3, [r3, #2]
800f11a: 4618 mov r0, r3
800f11c: f7ff fed4 bl 800eec8 <ptr_to_mem>
800f120: 60f8 str r0, [r7, #12]
if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
800f122: 687b ldr r3, [r7, #4]
800f124: 881b ldrh r3, [r3, #0]
800f126: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f12a: d818 bhi.n 800f15e <mem_link_valid+0x66>
800f12c: 687b ldr r3, [r7, #4]
800f12e: 885b ldrh r3, [r3, #2]
800f130: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f134: d813 bhi.n 800f15e <mem_link_valid+0x66>
((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
800f136: 687b ldr r3, [r7, #4]
800f138: 885b ldrh r3, [r3, #2]
if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
800f13a: 8afa ldrh r2, [r7, #22]
800f13c: 429a cmp r2, r3
800f13e: d004 beq.n 800f14a <mem_link_valid+0x52>
((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
800f140: 68fb ldr r3, [r7, #12]
800f142: 881b ldrh r3, [r3, #0]
800f144: 8afa ldrh r2, [r7, #22]
800f146: 429a cmp r2, r3
800f148: d109 bne.n 800f15e <mem_link_valid+0x66>
((nmem != ram_end) && (nmem->prev != rmem_idx))) {
800f14a: 4b08 ldr r3, [pc, #32] ; (800f16c <mem_link_valid+0x74>)
800f14c: 681b ldr r3, [r3, #0]
((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
800f14e: 693a ldr r2, [r7, #16]
800f150: 429a cmp r2, r3
800f152: d006 beq.n 800f162 <mem_link_valid+0x6a>
((nmem != ram_end) && (nmem->prev != rmem_idx))) {
800f154: 693b ldr r3, [r7, #16]
800f156: 885b ldrh r3, [r3, #2]
800f158: 8afa ldrh r2, [r7, #22]
800f15a: 429a cmp r2, r3
800f15c: d001 beq.n 800f162 <mem_link_valid+0x6a>
return 0;
800f15e: 2300 movs r3, #0
800f160: e000 b.n 800f164 <mem_link_valid+0x6c>
}
return 1;
800f162: 2301 movs r3, #1
}
800f164: 4618 mov r0, r3
800f166: 3718 adds r7, #24
800f168: 46bd mov sp, r7
800f16a: bd80 pop {r7, pc}
800f16c: 200086dc .word 0x200086dc
0800f170 <mem_free>:
* @param rmem is the data portion of a struct mem as returned by a previous
* call to mem_malloc()
*/
void
mem_free(void *rmem)
{
800f170: b580 push {r7, lr}
800f172: b088 sub sp, #32
800f174: af00 add r7, sp, #0
800f176: 6078 str r0, [r7, #4]
struct mem *mem;
LWIP_MEM_FREE_DECL_PROTECT();
if (rmem == NULL) {
800f178: 687b ldr r3, [r7, #4]
800f17a: 2b00 cmp r3, #0
800f17c: d070 beq.n 800f260 <mem_free+0xf0>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n"));
return;
}
if ((((mem_ptr_t)rmem) & (MEM_ALIGNMENT - 1)) != 0) {
800f17e: 687b ldr r3, [r7, #4]
800f180: f003 0303 and.w r3, r3, #3
800f184: 2b00 cmp r3, #0
800f186: d00d beq.n 800f1a4 <mem_free+0x34>
LWIP_MEM_ILLEGAL_FREE("mem_free: sanity check alignment");
800f188: 4b37 ldr r3, [pc, #220] ; (800f268 <mem_free+0xf8>)
800f18a: f240 2273 movw r2, #627 ; 0x273
800f18e: 4937 ldr r1, [pc, #220] ; (800f26c <mem_free+0xfc>)
800f190: 4837 ldr r0, [pc, #220] ; (800f270 <mem_free+0x100>)
800f192: f00b ff17 bl 801afc4 <iprintf>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: sanity check alignment\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f196: f00b feaf bl 801aef8 <sys_arch_protect>
800f19a: 60f8 str r0, [r7, #12]
800f19c: 68f8 ldr r0, [r7, #12]
800f19e: f00b feb9 bl 801af14 <sys_arch_unprotect>
return;
800f1a2: e05e b.n 800f262 <mem_free+0xf2>
}
/* Get the corresponding struct mem: */
/* cast through void* to get rid of alignment warnings */
mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
800f1a4: 687b ldr r3, [r7, #4]
800f1a6: 3b08 subs r3, #8
800f1a8: 61fb str r3, [r7, #28]
if ((u8_t *)mem < ram || (u8_t *)rmem + MIN_SIZE_ALIGNED > (u8_t *)ram_end) {
800f1aa: 4b32 ldr r3, [pc, #200] ; (800f274 <mem_free+0x104>)
800f1ac: 681b ldr r3, [r3, #0]
800f1ae: 69fa ldr r2, [r7, #28]
800f1b0: 429a cmp r2, r3
800f1b2: d306 bcc.n 800f1c2 <mem_free+0x52>
800f1b4: 687b ldr r3, [r7, #4]
800f1b6: f103 020c add.w r2, r3, #12
800f1ba: 4b2f ldr r3, [pc, #188] ; (800f278 <mem_free+0x108>)
800f1bc: 681b ldr r3, [r3, #0]
800f1be: 429a cmp r2, r3
800f1c0: d90d bls.n 800f1de <mem_free+0x6e>
LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory");
800f1c2: 4b29 ldr r3, [pc, #164] ; (800f268 <mem_free+0xf8>)
800f1c4: f240 227f movw r2, #639 ; 0x27f
800f1c8: 492c ldr r1, [pc, #176] ; (800f27c <mem_free+0x10c>)
800f1ca: 4829 ldr r0, [pc, #164] ; (800f270 <mem_free+0x100>)
800f1cc: f00b fefa bl 801afc4 <iprintf>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f1d0: f00b fe92 bl 801aef8 <sys_arch_protect>
800f1d4: 6138 str r0, [r7, #16]
800f1d6: 6938 ldr r0, [r7, #16]
800f1d8: f00b fe9c bl 801af14 <sys_arch_unprotect>
return;
800f1dc: e041 b.n 800f262 <mem_free+0xf2>
}
#if MEM_OVERFLOW_CHECK
mem_overflow_check_element(mem);
#endif
/* protect the heap from concurrent access */
LWIP_MEM_FREE_PROTECT();
800f1de: 4828 ldr r0, [pc, #160] ; (800f280 <mem_free+0x110>)
800f1e0: f00b fe48 bl 801ae74 <sys_mutex_lock>
/* mem has to be in a used state */
if (!mem->used) {
800f1e4: 69fb ldr r3, [r7, #28]
800f1e6: 791b ldrb r3, [r3, #4]
800f1e8: 2b00 cmp r3, #0
800f1ea: d110 bne.n 800f20e <mem_free+0x9e>
LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: double free");
800f1ec: 4b1e ldr r3, [pc, #120] ; (800f268 <mem_free+0xf8>)
800f1ee: f44f 7223 mov.w r2, #652 ; 0x28c
800f1f2: 4924 ldr r1, [pc, #144] ; (800f284 <mem_free+0x114>)
800f1f4: 481e ldr r0, [pc, #120] ; (800f270 <mem_free+0x100>)
800f1f6: f00b fee5 bl 801afc4 <iprintf>
LWIP_MEM_FREE_UNPROTECT();
800f1fa: 4821 ldr r0, [pc, #132] ; (800f280 <mem_free+0x110>)
800f1fc: f00b fe49 bl 801ae92 <sys_mutex_unlock>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: double free?\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f200: f00b fe7a bl 801aef8 <sys_arch_protect>
800f204: 6178 str r0, [r7, #20]
800f206: 6978 ldr r0, [r7, #20]
800f208: f00b fe84 bl 801af14 <sys_arch_unprotect>
return;
800f20c: e029 b.n 800f262 <mem_free+0xf2>
}
if (!mem_link_valid(mem)) {
800f20e: 69f8 ldr r0, [r7, #28]
800f210: f7ff ff72 bl 800f0f8 <mem_link_valid>
800f214: 4603 mov r3, r0
800f216: 2b00 cmp r3, #0
800f218: d110 bne.n 800f23c <mem_free+0xcc>
LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: non-linked: double free");
800f21a: 4b13 ldr r3, [pc, #76] ; (800f268 <mem_free+0xf8>)
800f21c: f240 2295 movw r2, #661 ; 0x295
800f220: 4919 ldr r1, [pc, #100] ; (800f288 <mem_free+0x118>)
800f222: 4813 ldr r0, [pc, #76] ; (800f270 <mem_free+0x100>)
800f224: f00b fece bl 801afc4 <iprintf>
LWIP_MEM_FREE_UNPROTECT();
800f228: 4815 ldr r0, [pc, #84] ; (800f280 <mem_free+0x110>)
800f22a: f00b fe32 bl 801ae92 <sys_mutex_unlock>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: non-linked: double free?\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f22e: f00b fe63 bl 801aef8 <sys_arch_protect>
800f232: 61b8 str r0, [r7, #24]
800f234: 69b8 ldr r0, [r7, #24]
800f236: f00b fe6d bl 801af14 <sys_arch_unprotect>
return;
800f23a: e012 b.n 800f262 <mem_free+0xf2>
}
/* mem is now unused. */
mem->used = 0;
800f23c: 69fb ldr r3, [r7, #28]
800f23e: 2200 movs r2, #0
800f240: 711a strb r2, [r3, #4]
if (mem < lfree) {
800f242: 4b12 ldr r3, [pc, #72] ; (800f28c <mem_free+0x11c>)
800f244: 681b ldr r3, [r3, #0]
800f246: 69fa ldr r2, [r7, #28]
800f248: 429a cmp r2, r3
800f24a: d202 bcs.n 800f252 <mem_free+0xe2>
/* the newly freed struct is now the lowest */
lfree = mem;
800f24c: 4a0f ldr r2, [pc, #60] ; (800f28c <mem_free+0x11c>)
800f24e: 69fb ldr r3, [r7, #28]
800f250: 6013 str r3, [r2, #0]
}
MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram)));
/* finally, see if prev or next are free also */
plug_holes(mem);
800f252: 69f8 ldr r0, [r7, #28]
800f254: f7ff fe5c bl 800ef10 <plug_holes>
MEM_SANITY();
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
mem_free_count = 1;
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
LWIP_MEM_FREE_UNPROTECT();
800f258: 4809 ldr r0, [pc, #36] ; (800f280 <mem_free+0x110>)
800f25a: f00b fe1a bl 801ae92 <sys_mutex_unlock>
800f25e: e000 b.n 800f262 <mem_free+0xf2>
return;
800f260: bf00 nop
}
800f262: 3720 adds r7, #32
800f264: 46bd mov sp, r7
800f266: bd80 pop {r7, pc}
800f268: 0801c288 .word 0x0801c288
800f26c: 0801c378 .word 0x0801c378
800f270: 0801c2d0 .word 0x0801c2d0
800f274: 200086d8 .word 0x200086d8
800f278: 200086dc .word 0x200086dc
800f27c: 0801c39c .word 0x0801c39c
800f280: 200086e0 .word 0x200086e0
800f284: 0801c3b8 .word 0x0801c3b8
800f288: 0801c3e0 .word 0x0801c3e0
800f28c: 200086e4 .word 0x200086e4
0800f290 <mem_trim>:
* or NULL if newsize is > old size, in which case rmem is NOT touched
* or freed!
*/
void *
mem_trim(void *rmem, mem_size_t new_size)
{
800f290: b580 push {r7, lr}
800f292: b088 sub sp, #32
800f294: af00 add r7, sp, #0
800f296: 6078 str r0, [r7, #4]
800f298: 460b mov r3, r1
800f29a: 807b strh r3, [r7, #2]
/* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */
LWIP_MEM_FREE_DECL_PROTECT();
/* Expand the size of the allocated memory region so that we can
adjust for alignment. */
newsize = (mem_size_t)LWIP_MEM_ALIGN_SIZE(new_size);
800f29c: 887b ldrh r3, [r7, #2]
800f29e: 3303 adds r3, #3
800f2a0: b29b uxth r3, r3
800f2a2: f023 0303 bic.w r3, r3, #3
800f2a6: 83fb strh r3, [r7, #30]
if (newsize < MIN_SIZE_ALIGNED) {
800f2a8: 8bfb ldrh r3, [r7, #30]
800f2aa: 2b0b cmp r3, #11
800f2ac: d801 bhi.n 800f2b2 <mem_trim+0x22>
/* every data block must be at least MIN_SIZE_ALIGNED long */
newsize = MIN_SIZE_ALIGNED;
800f2ae: 230c movs r3, #12
800f2b0: 83fb strh r3, [r7, #30]
}
#if MEM_OVERFLOW_CHECK
newsize += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
#endif
if ((newsize > MEM_SIZE_ALIGNED) || (newsize < new_size)) {
800f2b2: 8bfb ldrh r3, [r7, #30]
800f2b4: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f2b8: d803 bhi.n 800f2c2 <mem_trim+0x32>
800f2ba: 8bfa ldrh r2, [r7, #30]
800f2bc: 887b ldrh r3, [r7, #2]
800f2be: 429a cmp r2, r3
800f2c0: d201 bcs.n 800f2c6 <mem_trim+0x36>
return NULL;
800f2c2: 2300 movs r3, #0
800f2c4: e0d8 b.n 800f478 <mem_trim+0x1e8>
}
LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
800f2c6: 4b6e ldr r3, [pc, #440] ; (800f480 <mem_trim+0x1f0>)
800f2c8: 681b ldr r3, [r3, #0]
800f2ca: 687a ldr r2, [r7, #4]
800f2cc: 429a cmp r2, r3
800f2ce: d304 bcc.n 800f2da <mem_trim+0x4a>
800f2d0: 4b6c ldr r3, [pc, #432] ; (800f484 <mem_trim+0x1f4>)
800f2d2: 681b ldr r3, [r3, #0]
800f2d4: 687a ldr r2, [r7, #4]
800f2d6: 429a cmp r2, r3
800f2d8: d306 bcc.n 800f2e8 <mem_trim+0x58>
800f2da: 4b6b ldr r3, [pc, #428] ; (800f488 <mem_trim+0x1f8>)
800f2dc: f240 22d1 movw r2, #721 ; 0x2d1
800f2e0: 496a ldr r1, [pc, #424] ; (800f48c <mem_trim+0x1fc>)
800f2e2: 486b ldr r0, [pc, #428] ; (800f490 <mem_trim+0x200>)
800f2e4: f00b fe6e bl 801afc4 <iprintf>
(u8_t *)rmem < (u8_t *)ram_end);
if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
800f2e8: 4b65 ldr r3, [pc, #404] ; (800f480 <mem_trim+0x1f0>)
800f2ea: 681b ldr r3, [r3, #0]
800f2ec: 687a ldr r2, [r7, #4]
800f2ee: 429a cmp r2, r3
800f2f0: d304 bcc.n 800f2fc <mem_trim+0x6c>
800f2f2: 4b64 ldr r3, [pc, #400] ; (800f484 <mem_trim+0x1f4>)
800f2f4: 681b ldr r3, [r3, #0]
800f2f6: 687a ldr r2, [r7, #4]
800f2f8: 429a cmp r2, r3
800f2fa: d307 bcc.n 800f30c <mem_trim+0x7c>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f2fc: f00b fdfc bl 801aef8 <sys_arch_protect>
800f300: 60b8 str r0, [r7, #8]
800f302: 68b8 ldr r0, [r7, #8]
800f304: f00b fe06 bl 801af14 <sys_arch_unprotect>
return rmem;
800f308: 687b ldr r3, [r7, #4]
800f30a: e0b5 b.n 800f478 <mem_trim+0x1e8>
}
/* Get the corresponding struct mem ... */
/* cast through void* to get rid of alignment warnings */
mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
800f30c: 687b ldr r3, [r7, #4]
800f30e: 3b08 subs r3, #8
800f310: 61bb str r3, [r7, #24]
#if MEM_OVERFLOW_CHECK
mem_overflow_check_element(mem);
#endif
/* ... and its offset pointer */
ptr = mem_to_ptr(mem);
800f312: 69b8 ldr r0, [r7, #24]
800f314: f7ff fdea bl 800eeec <mem_to_ptr>
800f318: 4603 mov r3, r0
800f31a: 82fb strh r3, [r7, #22]
size = (mem_size_t)((mem_size_t)(mem->next - ptr) - (SIZEOF_STRUCT_MEM + MEM_SANITY_OVERHEAD));
800f31c: 69bb ldr r3, [r7, #24]
800f31e: 881a ldrh r2, [r3, #0]
800f320: 8afb ldrh r3, [r7, #22]
800f322: 1ad3 subs r3, r2, r3
800f324: b29b uxth r3, r3
800f326: 3b08 subs r3, #8
800f328: 82bb strh r3, [r7, #20]
LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size);
800f32a: 8bfa ldrh r2, [r7, #30]
800f32c: 8abb ldrh r3, [r7, #20]
800f32e: 429a cmp r2, r3
800f330: d906 bls.n 800f340 <mem_trim+0xb0>
800f332: 4b55 ldr r3, [pc, #340] ; (800f488 <mem_trim+0x1f8>)
800f334: f44f 7239 mov.w r2, #740 ; 0x2e4
800f338: 4956 ldr r1, [pc, #344] ; (800f494 <mem_trim+0x204>)
800f33a: 4855 ldr r0, [pc, #340] ; (800f490 <mem_trim+0x200>)
800f33c: f00b fe42 bl 801afc4 <iprintf>
if (newsize > size) {
800f340: 8bfa ldrh r2, [r7, #30]
800f342: 8abb ldrh r3, [r7, #20]
800f344: 429a cmp r2, r3
800f346: d901 bls.n 800f34c <mem_trim+0xbc>
/* not supported */
return NULL;
800f348: 2300 movs r3, #0
800f34a: e095 b.n 800f478 <mem_trim+0x1e8>
}
if (newsize == size) {
800f34c: 8bfa ldrh r2, [r7, #30]
800f34e: 8abb ldrh r3, [r7, #20]
800f350: 429a cmp r2, r3
800f352: d101 bne.n 800f358 <mem_trim+0xc8>
/* No change in size, simply return */
return rmem;
800f354: 687b ldr r3, [r7, #4]
800f356: e08f b.n 800f478 <mem_trim+0x1e8>
}
/* protect the heap from concurrent access */
LWIP_MEM_FREE_PROTECT();
800f358: 484f ldr r0, [pc, #316] ; (800f498 <mem_trim+0x208>)
800f35a: f00b fd8b bl 801ae74 <sys_mutex_lock>
mem2 = ptr_to_mem(mem->next);
800f35e: 69bb ldr r3, [r7, #24]
800f360: 881b ldrh r3, [r3, #0]
800f362: 4618 mov r0, r3
800f364: f7ff fdb0 bl 800eec8 <ptr_to_mem>
800f368: 6138 str r0, [r7, #16]
if (mem2->used == 0) {
800f36a: 693b ldr r3, [r7, #16]
800f36c: 791b ldrb r3, [r3, #4]
800f36e: 2b00 cmp r3, #0
800f370: d13f bne.n 800f3f2 <mem_trim+0x162>
/* The next struct is unused, we can simply move it at little */
mem_size_t next;
LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
800f372: 69bb ldr r3, [r7, #24]
800f374: 881b ldrh r3, [r3, #0]
800f376: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f37a: d106 bne.n 800f38a <mem_trim+0xfa>
800f37c: 4b42 ldr r3, [pc, #264] ; (800f488 <mem_trim+0x1f8>)
800f37e: f240 22f5 movw r2, #757 ; 0x2f5
800f382: 4946 ldr r1, [pc, #280] ; (800f49c <mem_trim+0x20c>)
800f384: 4842 ldr r0, [pc, #264] ; (800f490 <mem_trim+0x200>)
800f386: f00b fe1d bl 801afc4 <iprintf>
/* remember the old next pointer */
next = mem2->next;
800f38a: 693b ldr r3, [r7, #16]
800f38c: 881b ldrh r3, [r3, #0]
800f38e: 81bb strh r3, [r7, #12]
/* create new struct mem which is moved directly after the shrinked mem */
ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
800f390: 8afa ldrh r2, [r7, #22]
800f392: 8bfb ldrh r3, [r7, #30]
800f394: 4413 add r3, r2
800f396: b29b uxth r3, r3
800f398: 3308 adds r3, #8
800f39a: 81fb strh r3, [r7, #14]
if (lfree == mem2) {
800f39c: 4b40 ldr r3, [pc, #256] ; (800f4a0 <mem_trim+0x210>)
800f39e: 681b ldr r3, [r3, #0]
800f3a0: 693a ldr r2, [r7, #16]
800f3a2: 429a cmp r2, r3
800f3a4: d106 bne.n 800f3b4 <mem_trim+0x124>
lfree = ptr_to_mem(ptr2);
800f3a6: 89fb ldrh r3, [r7, #14]
800f3a8: 4618 mov r0, r3
800f3aa: f7ff fd8d bl 800eec8 <ptr_to_mem>
800f3ae: 4603 mov r3, r0
800f3b0: 4a3b ldr r2, [pc, #236] ; (800f4a0 <mem_trim+0x210>)
800f3b2: 6013 str r3, [r2, #0]
}
mem2 = ptr_to_mem(ptr2);
800f3b4: 89fb ldrh r3, [r7, #14]
800f3b6: 4618 mov r0, r3
800f3b8: f7ff fd86 bl 800eec8 <ptr_to_mem>
800f3bc: 6138 str r0, [r7, #16]
mem2->used = 0;
800f3be: 693b ldr r3, [r7, #16]
800f3c0: 2200 movs r2, #0
800f3c2: 711a strb r2, [r3, #4]
/* restore the next pointer */
mem2->next = next;
800f3c4: 693b ldr r3, [r7, #16]
800f3c6: 89ba ldrh r2, [r7, #12]
800f3c8: 801a strh r2, [r3, #0]
/* link it back to mem */
mem2->prev = ptr;
800f3ca: 693b ldr r3, [r7, #16]
800f3cc: 8afa ldrh r2, [r7, #22]
800f3ce: 805a strh r2, [r3, #2]
/* link mem to it */
mem->next = ptr2;
800f3d0: 69bb ldr r3, [r7, #24]
800f3d2: 89fa ldrh r2, [r7, #14]
800f3d4: 801a strh r2, [r3, #0]
/* last thing to restore linked list: as we have moved mem2,
* let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not
* the end of the heap */
if (mem2->next != MEM_SIZE_ALIGNED) {
800f3d6: 693b ldr r3, [r7, #16]
800f3d8: 881b ldrh r3, [r3, #0]
800f3da: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f3de: d047 beq.n 800f470 <mem_trim+0x1e0>
ptr_to_mem(mem2->next)->prev = ptr2;
800f3e0: 693b ldr r3, [r7, #16]
800f3e2: 881b ldrh r3, [r3, #0]
800f3e4: 4618 mov r0, r3
800f3e6: f7ff fd6f bl 800eec8 <ptr_to_mem>
800f3ea: 4602 mov r2, r0
800f3ec: 89fb ldrh r3, [r7, #14]
800f3ee: 8053 strh r3, [r2, #2]
800f3f0: e03e b.n 800f470 <mem_trim+0x1e0>
}
MEM_STATS_DEC_USED(used, (size - newsize));
/* no need to plug holes, we've already done that */
} else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) {
800f3f2: 8bfb ldrh r3, [r7, #30]
800f3f4: f103 0214 add.w r2, r3, #20
800f3f8: 8abb ldrh r3, [r7, #20]
800f3fa: 429a cmp r2, r3
800f3fc: d838 bhi.n 800f470 <mem_trim+0x1e0>
* Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem
* ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED').
* @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
* region that couldn't hold data, but when mem->next gets freed,
* the 2 regions would be combined, resulting in more free memory */
ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
800f3fe: 8afa ldrh r2, [r7, #22]
800f400: 8bfb ldrh r3, [r7, #30]
800f402: 4413 add r3, r2
800f404: b29b uxth r3, r3
800f406: 3308 adds r3, #8
800f408: 81fb strh r3, [r7, #14]
LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
800f40a: 69bb ldr r3, [r7, #24]
800f40c: 881b ldrh r3, [r3, #0]
800f40e: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f412: d106 bne.n 800f422 <mem_trim+0x192>
800f414: 4b1c ldr r3, [pc, #112] ; (800f488 <mem_trim+0x1f8>)
800f416: f240 3216 movw r2, #790 ; 0x316
800f41a: 4920 ldr r1, [pc, #128] ; (800f49c <mem_trim+0x20c>)
800f41c: 481c ldr r0, [pc, #112] ; (800f490 <mem_trim+0x200>)
800f41e: f00b fdd1 bl 801afc4 <iprintf>
mem2 = ptr_to_mem(ptr2);
800f422: 89fb ldrh r3, [r7, #14]
800f424: 4618 mov r0, r3
800f426: f7ff fd4f bl 800eec8 <ptr_to_mem>
800f42a: 6138 str r0, [r7, #16]
if (mem2 < lfree) {
800f42c: 4b1c ldr r3, [pc, #112] ; (800f4a0 <mem_trim+0x210>)
800f42e: 681b ldr r3, [r3, #0]
800f430: 693a ldr r2, [r7, #16]
800f432: 429a cmp r2, r3
800f434: d202 bcs.n 800f43c <mem_trim+0x1ac>
lfree = mem2;
800f436: 4a1a ldr r2, [pc, #104] ; (800f4a0 <mem_trim+0x210>)
800f438: 693b ldr r3, [r7, #16]
800f43a: 6013 str r3, [r2, #0]
}
mem2->used = 0;
800f43c: 693b ldr r3, [r7, #16]
800f43e: 2200 movs r2, #0
800f440: 711a strb r2, [r3, #4]
mem2->next = mem->next;
800f442: 69bb ldr r3, [r7, #24]
800f444: 881a ldrh r2, [r3, #0]
800f446: 693b ldr r3, [r7, #16]
800f448: 801a strh r2, [r3, #0]
mem2->prev = ptr;
800f44a: 693b ldr r3, [r7, #16]
800f44c: 8afa ldrh r2, [r7, #22]
800f44e: 805a strh r2, [r3, #2]
mem->next = ptr2;
800f450: 69bb ldr r3, [r7, #24]
800f452: 89fa ldrh r2, [r7, #14]
800f454: 801a strh r2, [r3, #0]
if (mem2->next != MEM_SIZE_ALIGNED) {
800f456: 693b ldr r3, [r7, #16]
800f458: 881b ldrh r3, [r3, #0]
800f45a: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f45e: d007 beq.n 800f470 <mem_trim+0x1e0>
ptr_to_mem(mem2->next)->prev = ptr2;
800f460: 693b ldr r3, [r7, #16]
800f462: 881b ldrh r3, [r3, #0]
800f464: 4618 mov r0, r3
800f466: f7ff fd2f bl 800eec8 <ptr_to_mem>
800f46a: 4602 mov r2, r0
800f46c: 89fb ldrh r3, [r7, #14]
800f46e: 8053 strh r3, [r2, #2]
#endif
MEM_SANITY();
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
mem_free_count = 1;
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
LWIP_MEM_FREE_UNPROTECT();
800f470: 4809 ldr r0, [pc, #36] ; (800f498 <mem_trim+0x208>)
800f472: f00b fd0e bl 801ae92 <sys_mutex_unlock>
return rmem;
800f476: 687b ldr r3, [r7, #4]
}
800f478: 4618 mov r0, r3
800f47a: 3720 adds r7, #32
800f47c: 46bd mov sp, r7
800f47e: bd80 pop {r7, pc}
800f480: 200086d8 .word 0x200086d8
800f484: 200086dc .word 0x200086dc
800f488: 0801c288 .word 0x0801c288
800f48c: 0801c414 .word 0x0801c414
800f490: 0801c2d0 .word 0x0801c2d0
800f494: 0801c42c .word 0x0801c42c
800f498: 200086e0 .word 0x200086e0
800f49c: 0801c44c .word 0x0801c44c
800f4a0: 200086e4 .word 0x200086e4
0800f4a4 <mem_malloc>:
*
* Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT).
*/
void *
mem_malloc(mem_size_t size_in)
{
800f4a4: b580 push {r7, lr}
800f4a6: b088 sub sp, #32
800f4a8: af00 add r7, sp, #0
800f4aa: 4603 mov r3, r0
800f4ac: 80fb strh r3, [r7, #6]
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
u8_t local_mem_free_count = 0;
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
LWIP_MEM_ALLOC_DECL_PROTECT();
if (size_in == 0) {
800f4ae: 88fb ldrh r3, [r7, #6]
800f4b0: 2b00 cmp r3, #0
800f4b2: d101 bne.n 800f4b8 <mem_malloc+0x14>
return NULL;
800f4b4: 2300 movs r3, #0
800f4b6: e0e2 b.n 800f67e <mem_malloc+0x1da>
}
/* Expand the size of the allocated memory region so that we can
adjust for alignment. */
size = (mem_size_t)LWIP_MEM_ALIGN_SIZE(size_in);
800f4b8: 88fb ldrh r3, [r7, #6]
800f4ba: 3303 adds r3, #3
800f4bc: b29b uxth r3, r3
800f4be: f023 0303 bic.w r3, r3, #3
800f4c2: 83bb strh r3, [r7, #28]
if (size < MIN_SIZE_ALIGNED) {
800f4c4: 8bbb ldrh r3, [r7, #28]
800f4c6: 2b0b cmp r3, #11
800f4c8: d801 bhi.n 800f4ce <mem_malloc+0x2a>
/* every data block must be at least MIN_SIZE_ALIGNED long */
size = MIN_SIZE_ALIGNED;
800f4ca: 230c movs r3, #12
800f4cc: 83bb strh r3, [r7, #28]
}
#if MEM_OVERFLOW_CHECK
size += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
#endif
if ((size > MEM_SIZE_ALIGNED) || (size < size_in)) {
800f4ce: 8bbb ldrh r3, [r7, #28]
800f4d0: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f4d4: d803 bhi.n 800f4de <mem_malloc+0x3a>
800f4d6: 8bba ldrh r2, [r7, #28]
800f4d8: 88fb ldrh r3, [r7, #6]
800f4da: 429a cmp r2, r3
800f4dc: d201 bcs.n 800f4e2 <mem_malloc+0x3e>
return NULL;
800f4de: 2300 movs r3, #0
800f4e0: e0cd b.n 800f67e <mem_malloc+0x1da>
}
/* protect the heap from concurrent access */
sys_mutex_lock(&mem_mutex);
800f4e2: 4869 ldr r0, [pc, #420] ; (800f688 <mem_malloc+0x1e4>)
800f4e4: f00b fcc6 bl 801ae74 <sys_mutex_lock>
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
/* Scan through the heap searching for a free block that is big enough,
* beginning with the lowest free block.
*/
for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
800f4e8: 4b68 ldr r3, [pc, #416] ; (800f68c <mem_malloc+0x1e8>)
800f4ea: 681b ldr r3, [r3, #0]
800f4ec: 4618 mov r0, r3
800f4ee: f7ff fcfd bl 800eeec <mem_to_ptr>
800f4f2: 4603 mov r3, r0
800f4f4: 83fb strh r3, [r7, #30]
800f4f6: e0b7 b.n 800f668 <mem_malloc+0x1c4>
ptr = ptr_to_mem(ptr)->next) {
mem = ptr_to_mem(ptr);
800f4f8: 8bfb ldrh r3, [r7, #30]
800f4fa: 4618 mov r0, r3
800f4fc: f7ff fce4 bl 800eec8 <ptr_to_mem>
800f500: 6178 str r0, [r7, #20]
local_mem_free_count = 1;
break;
}
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
if ((!mem->used) &&
800f502: 697b ldr r3, [r7, #20]
800f504: 791b ldrb r3, [r3, #4]
800f506: 2b00 cmp r3, #0
800f508: f040 80a7 bne.w 800f65a <mem_malloc+0x1b6>
(mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) {
800f50c: 697b ldr r3, [r7, #20]
800f50e: 881b ldrh r3, [r3, #0]
800f510: 461a mov r2, r3
800f512: 8bfb ldrh r3, [r7, #30]
800f514: 1ad3 subs r3, r2, r3
800f516: f1a3 0208 sub.w r2, r3, #8
800f51a: 8bbb ldrh r3, [r7, #28]
if ((!mem->used) &&
800f51c: 429a cmp r2, r3
800f51e: f0c0 809c bcc.w 800f65a <mem_malloc+0x1b6>
/* mem is not used and at least perfect fit is possible:
* mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */
if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) {
800f522: 697b ldr r3, [r7, #20]
800f524: 881b ldrh r3, [r3, #0]
800f526: 461a mov r2, r3
800f528: 8bfb ldrh r3, [r7, #30]
800f52a: 1ad3 subs r3, r2, r3
800f52c: f1a3 0208 sub.w r2, r3, #8
800f530: 8bbb ldrh r3, [r7, #28]
800f532: 3314 adds r3, #20
800f534: 429a cmp r2, r3
800f536: d333 bcc.n 800f5a0 <mem_malloc+0xfc>
* struct mem would fit in but no data between mem2 and mem2->next
* @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
* region that couldn't hold data, but when mem->next gets freed,
* the 2 regions would be combined, resulting in more free memory
*/
ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + size);
800f538: 8bfa ldrh r2, [r7, #30]
800f53a: 8bbb ldrh r3, [r7, #28]
800f53c: 4413 add r3, r2
800f53e: b29b uxth r3, r3
800f540: 3308 adds r3, #8
800f542: 827b strh r3, [r7, #18]
LWIP_ASSERT("invalid next ptr",ptr2 != MEM_SIZE_ALIGNED);
800f544: 8a7b ldrh r3, [r7, #18]
800f546: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f54a: d106 bne.n 800f55a <mem_malloc+0xb6>
800f54c: 4b50 ldr r3, [pc, #320] ; (800f690 <mem_malloc+0x1ec>)
800f54e: f240 3287 movw r2, #903 ; 0x387
800f552: 4950 ldr r1, [pc, #320] ; (800f694 <mem_malloc+0x1f0>)
800f554: 4850 ldr r0, [pc, #320] ; (800f698 <mem_malloc+0x1f4>)
800f556: f00b fd35 bl 801afc4 <iprintf>
/* create mem2 struct */
mem2 = ptr_to_mem(ptr2);
800f55a: 8a7b ldrh r3, [r7, #18]
800f55c: 4618 mov r0, r3
800f55e: f7ff fcb3 bl 800eec8 <ptr_to_mem>
800f562: 60f8 str r0, [r7, #12]
mem2->used = 0;
800f564: 68fb ldr r3, [r7, #12]
800f566: 2200 movs r2, #0
800f568: 711a strb r2, [r3, #4]
mem2->next = mem->next;
800f56a: 697b ldr r3, [r7, #20]
800f56c: 881a ldrh r2, [r3, #0]
800f56e: 68fb ldr r3, [r7, #12]
800f570: 801a strh r2, [r3, #0]
mem2->prev = ptr;
800f572: 68fb ldr r3, [r7, #12]
800f574: 8bfa ldrh r2, [r7, #30]
800f576: 805a strh r2, [r3, #2]
/* and insert it between mem and mem->next */
mem->next = ptr2;
800f578: 697b ldr r3, [r7, #20]
800f57a: 8a7a ldrh r2, [r7, #18]
800f57c: 801a strh r2, [r3, #0]
mem->used = 1;
800f57e: 697b ldr r3, [r7, #20]
800f580: 2201 movs r2, #1
800f582: 711a strb r2, [r3, #4]
if (mem2->next != MEM_SIZE_ALIGNED) {
800f584: 68fb ldr r3, [r7, #12]
800f586: 881b ldrh r3, [r3, #0]
800f588: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f58c: d00b beq.n 800f5a6 <mem_malloc+0x102>
ptr_to_mem(mem2->next)->prev = ptr2;
800f58e: 68fb ldr r3, [r7, #12]
800f590: 881b ldrh r3, [r3, #0]
800f592: 4618 mov r0, r3
800f594: f7ff fc98 bl 800eec8 <ptr_to_mem>
800f598: 4602 mov r2, r0
800f59a: 8a7b ldrh r3, [r7, #18]
800f59c: 8053 strh r3, [r2, #2]
800f59e: e002 b.n 800f5a6 <mem_malloc+0x102>
* take care of this).
* -> near fit or exact fit: do not split, no mem2 creation
* also can't move mem->next directly behind mem, since mem->next
* will always be used at this point!
*/
mem->used = 1;
800f5a0: 697b ldr r3, [r7, #20]
800f5a2: 2201 movs r2, #1
800f5a4: 711a strb r2, [r3, #4]
MEM_STATS_INC_USED(used, mem->next - mem_to_ptr(mem));
}
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
mem_malloc_adjust_lfree:
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
if (mem == lfree) {
800f5a6: 4b39 ldr r3, [pc, #228] ; (800f68c <mem_malloc+0x1e8>)
800f5a8: 681b ldr r3, [r3, #0]
800f5aa: 697a ldr r2, [r7, #20]
800f5ac: 429a cmp r2, r3
800f5ae: d127 bne.n 800f600 <mem_malloc+0x15c>
struct mem *cur = lfree;
800f5b0: 4b36 ldr r3, [pc, #216] ; (800f68c <mem_malloc+0x1e8>)
800f5b2: 681b ldr r3, [r3, #0]
800f5b4: 61bb str r3, [r7, #24]
/* Find next free block after mem and update lowest free pointer */
while (cur->used && cur != ram_end) {
800f5b6: e005 b.n 800f5c4 <mem_malloc+0x120>
/* If mem_free or mem_trim have run, we have to restart since they
could have altered our current struct mem or lfree. */
goto mem_malloc_adjust_lfree;
}
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
cur = ptr_to_mem(cur->next);
800f5b8: 69bb ldr r3, [r7, #24]
800f5ba: 881b ldrh r3, [r3, #0]
800f5bc: 4618 mov r0, r3
800f5be: f7ff fc83 bl 800eec8 <ptr_to_mem>
800f5c2: 61b8 str r0, [r7, #24]
while (cur->used && cur != ram_end) {
800f5c4: 69bb ldr r3, [r7, #24]
800f5c6: 791b ldrb r3, [r3, #4]
800f5c8: 2b00 cmp r3, #0
800f5ca: d004 beq.n 800f5d6 <mem_malloc+0x132>
800f5cc: 4b33 ldr r3, [pc, #204] ; (800f69c <mem_malloc+0x1f8>)
800f5ce: 681b ldr r3, [r3, #0]
800f5d0: 69ba ldr r2, [r7, #24]
800f5d2: 429a cmp r2, r3
800f5d4: d1f0 bne.n 800f5b8 <mem_malloc+0x114>
}
lfree = cur;
800f5d6: 4a2d ldr r2, [pc, #180] ; (800f68c <mem_malloc+0x1e8>)
800f5d8: 69bb ldr r3, [r7, #24]
800f5da: 6013 str r3, [r2, #0]
LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used)));
800f5dc: 4b2b ldr r3, [pc, #172] ; (800f68c <mem_malloc+0x1e8>)
800f5de: 681a ldr r2, [r3, #0]
800f5e0: 4b2e ldr r3, [pc, #184] ; (800f69c <mem_malloc+0x1f8>)
800f5e2: 681b ldr r3, [r3, #0]
800f5e4: 429a cmp r2, r3
800f5e6: d00b beq.n 800f600 <mem_malloc+0x15c>
800f5e8: 4b28 ldr r3, [pc, #160] ; (800f68c <mem_malloc+0x1e8>)
800f5ea: 681b ldr r3, [r3, #0]
800f5ec: 791b ldrb r3, [r3, #4]
800f5ee: 2b00 cmp r3, #0
800f5f0: d006 beq.n 800f600 <mem_malloc+0x15c>
800f5f2: 4b27 ldr r3, [pc, #156] ; (800f690 <mem_malloc+0x1ec>)
800f5f4: f240 32b5 movw r2, #949 ; 0x3b5
800f5f8: 4929 ldr r1, [pc, #164] ; (800f6a0 <mem_malloc+0x1fc>)
800f5fa: 4827 ldr r0, [pc, #156] ; (800f698 <mem_malloc+0x1f4>)
800f5fc: f00b fce2 bl 801afc4 <iprintf>
}
LWIP_MEM_ALLOC_UNPROTECT();
sys_mutex_unlock(&mem_mutex);
800f600: 4821 ldr r0, [pc, #132] ; (800f688 <mem_malloc+0x1e4>)
800f602: f00b fc46 bl 801ae92 <sys_mutex_unlock>
LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
800f606: 8bba ldrh r2, [r7, #28]
800f608: 697b ldr r3, [r7, #20]
800f60a: 4413 add r3, r2
800f60c: 3308 adds r3, #8
800f60e: 4a23 ldr r2, [pc, #140] ; (800f69c <mem_malloc+0x1f8>)
800f610: 6812 ldr r2, [r2, #0]
800f612: 4293 cmp r3, r2
800f614: d906 bls.n 800f624 <mem_malloc+0x180>
800f616: 4b1e ldr r3, [pc, #120] ; (800f690 <mem_malloc+0x1ec>)
800f618: f240 32b9 movw r2, #953 ; 0x3b9
800f61c: 4921 ldr r1, [pc, #132] ; (800f6a4 <mem_malloc+0x200>)
800f61e: 481e ldr r0, [pc, #120] ; (800f698 <mem_malloc+0x1f4>)
800f620: f00b fcd0 bl 801afc4 <iprintf>
(mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
800f624: 697b ldr r3, [r7, #20]
800f626: f003 0303 and.w r3, r3, #3
800f62a: 2b00 cmp r3, #0
800f62c: d006 beq.n 800f63c <mem_malloc+0x198>
800f62e: 4b18 ldr r3, [pc, #96] ; (800f690 <mem_malloc+0x1ec>)
800f630: f240 32bb movw r2, #955 ; 0x3bb
800f634: 491c ldr r1, [pc, #112] ; (800f6a8 <mem_malloc+0x204>)
800f636: 4818 ldr r0, [pc, #96] ; (800f698 <mem_malloc+0x1f4>)
800f638: f00b fcc4 bl 801afc4 <iprintf>
((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
LWIP_ASSERT("mem_malloc: sanity check alignment",
800f63c: 697b ldr r3, [r7, #20]
800f63e: f003 0303 and.w r3, r3, #3
800f642: 2b00 cmp r3, #0
800f644: d006 beq.n 800f654 <mem_malloc+0x1b0>
800f646: 4b12 ldr r3, [pc, #72] ; (800f690 <mem_malloc+0x1ec>)
800f648: f240 32bd movw r2, #957 ; 0x3bd
800f64c: 4917 ldr r1, [pc, #92] ; (800f6ac <mem_malloc+0x208>)
800f64e: 4812 ldr r0, [pc, #72] ; (800f698 <mem_malloc+0x1f4>)
800f650: f00b fcb8 bl 801afc4 <iprintf>
#if MEM_OVERFLOW_CHECK
mem_overflow_init_element(mem, size_in);
#endif
MEM_SANITY();
return (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET;
800f654: 697b ldr r3, [r7, #20]
800f656: 3308 adds r3, #8
800f658: e011 b.n 800f67e <mem_malloc+0x1da>
ptr = ptr_to_mem(ptr)->next) {
800f65a: 8bfb ldrh r3, [r7, #30]
800f65c: 4618 mov r0, r3
800f65e: f7ff fc33 bl 800eec8 <ptr_to_mem>
800f662: 4603 mov r3, r0
800f664: 881b ldrh r3, [r3, #0]
800f666: 83fb strh r3, [r7, #30]
for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
800f668: 8bfa ldrh r2, [r7, #30]
800f66a: 8bbb ldrh r3, [r7, #28]
800f66c: f5c3 63c8 rsb r3, r3, #1600 ; 0x640
800f670: 429a cmp r2, r3
800f672: f4ff af41 bcc.w 800f4f8 <mem_malloc+0x54>
/* if we got interrupted by a mem_free, try again */
} while (local_mem_free_count != 0);
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
MEM_STATS_INC(err);
LWIP_MEM_ALLOC_UNPROTECT();
sys_mutex_unlock(&mem_mutex);
800f676: 4804 ldr r0, [pc, #16] ; (800f688 <mem_malloc+0x1e4>)
800f678: f00b fc0b bl 801ae92 <sys_mutex_unlock>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
return NULL;
800f67c: 2300 movs r3, #0
}
800f67e: 4618 mov r0, r3
800f680: 3720 adds r7, #32
800f682: 46bd mov sp, r7
800f684: bd80 pop {r7, pc}
800f686: bf00 nop
800f688: 200086e0 .word 0x200086e0
800f68c: 200086e4 .word 0x200086e4
800f690: 0801c288 .word 0x0801c288
800f694: 0801c44c .word 0x0801c44c
800f698: 0801c2d0 .word 0x0801c2d0
800f69c: 200086dc .word 0x200086dc
800f6a0: 0801c460 .word 0x0801c460
800f6a4: 0801c47c .word 0x0801c47c
800f6a8: 0801c4ac .word 0x0801c4ac
800f6ac: 0801c4dc .word 0x0801c4dc
0800f6b0 <memp_init_pool>:
*
* @param desc pool to initialize
*/
void
memp_init_pool(const struct memp_desc *desc)
{
800f6b0: b480 push {r7}
800f6b2: b085 sub sp, #20
800f6b4: af00 add r7, sp, #0
800f6b6: 6078 str r0, [r7, #4]
LWIP_UNUSED_ARG(desc);
#else
int i;
struct memp *memp;
*desc->tab = NULL;
800f6b8: 687b ldr r3, [r7, #4]
800f6ba: 689b ldr r3, [r3, #8]
800f6bc: 2200 movs r2, #0
800f6be: 601a str r2, [r3, #0]
memp = (struct memp *)LWIP_MEM_ALIGN(desc->base);
800f6c0: 687b ldr r3, [r7, #4]
800f6c2: 685b ldr r3, [r3, #4]
800f6c4: 3303 adds r3, #3
800f6c6: f023 0303 bic.w r3, r3, #3
800f6ca: 60bb str r3, [r7, #8]
+ MEM_SANITY_REGION_AFTER_ALIGNED
#endif
));
#endif
/* create a linked list of memp elements */
for (i = 0; i < desc->num; ++i) {
800f6cc: 2300 movs r3, #0
800f6ce: 60fb str r3, [r7, #12]
800f6d0: e011 b.n 800f6f6 <memp_init_pool+0x46>
memp->next = *desc->tab;
800f6d2: 687b ldr r3, [r7, #4]
800f6d4: 689b ldr r3, [r3, #8]
800f6d6: 681a ldr r2, [r3, #0]
800f6d8: 68bb ldr r3, [r7, #8]
800f6da: 601a str r2, [r3, #0]
*desc->tab = memp;
800f6dc: 687b ldr r3, [r7, #4]
800f6de: 689b ldr r3, [r3, #8]
800f6e0: 68ba ldr r2, [r7, #8]
800f6e2: 601a str r2, [r3, #0]
#if MEMP_OVERFLOW_CHECK
memp_overflow_init_element(memp, desc);
#endif /* MEMP_OVERFLOW_CHECK */
/* cast through void* to get rid of alignment warnings */
memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + desc->size
800f6e4: 687b ldr r3, [r7, #4]
800f6e6: 881b ldrh r3, [r3, #0]
800f6e8: 461a mov r2, r3
800f6ea: 68bb ldr r3, [r7, #8]
800f6ec: 4413 add r3, r2
800f6ee: 60bb str r3, [r7, #8]
for (i = 0; i < desc->num; ++i) {
800f6f0: 68fb ldr r3, [r7, #12]
800f6f2: 3301 adds r3, #1
800f6f4: 60fb str r3, [r7, #12]
800f6f6: 687b ldr r3, [r7, #4]
800f6f8: 885b ldrh r3, [r3, #2]
800f6fa: 461a mov r2, r3
800f6fc: 68fb ldr r3, [r7, #12]
800f6fe: 4293 cmp r3, r2
800f700: dbe7 blt.n 800f6d2 <memp_init_pool+0x22>
#endif /* !MEMP_MEM_MALLOC */
#if MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY)
desc->stats->name = desc->desc;
#endif /* MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) */
}
800f702: bf00 nop
800f704: bf00 nop
800f706: 3714 adds r7, #20
800f708: 46bd mov sp, r7
800f70a: f85d 7b04 ldr.w r7, [sp], #4
800f70e: 4770 bx lr
0800f710 <memp_init>:
*
* Carves out memp_memory into linked lists for each pool-type.
*/
void
memp_init(void)
{
800f710: b580 push {r7, lr}
800f712: b082 sub sp, #8
800f714: af00 add r7, sp, #0
u16_t i;
/* for every pool: */
for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
800f716: 2300 movs r3, #0
800f718: 80fb strh r3, [r7, #6]
800f71a: e009 b.n 800f730 <memp_init+0x20>
memp_init_pool(memp_pools[i]);
800f71c: 88fb ldrh r3, [r7, #6]
800f71e: 4a08 ldr r2, [pc, #32] ; (800f740 <memp_init+0x30>)
800f720: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800f724: 4618 mov r0, r3
800f726: f7ff ffc3 bl 800f6b0 <memp_init_pool>
for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
800f72a: 88fb ldrh r3, [r7, #6]
800f72c: 3301 adds r3, #1
800f72e: 80fb strh r3, [r7, #6]
800f730: 88fb ldrh r3, [r7, #6]
800f732: 2b0c cmp r3, #12
800f734: d9f2 bls.n 800f71c <memp_init+0xc>
#if MEMP_OVERFLOW_CHECK >= 2
/* check everything a first time to see if it worked */
memp_overflow_check_all();
#endif /* MEMP_OVERFLOW_CHECK >= 2 */
}
800f736: bf00 nop
800f738: bf00 nop
800f73a: 3708 adds r7, #8
800f73c: 46bd mov sp, r7
800f73e: bd80 pop {r7, pc}
800f740: 08020fb8 .word 0x08020fb8
0800f744 <do_memp_malloc_pool>:
#if !MEMP_OVERFLOW_CHECK
do_memp_malloc_pool(const struct memp_desc *desc)
#else
do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line)
#endif
{
800f744: b580 push {r7, lr}
800f746: b084 sub sp, #16
800f748: af00 add r7, sp, #0
800f74a: 6078 str r0, [r7, #4]
#if MEMP_MEM_MALLOC
memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size));
SYS_ARCH_PROTECT(old_level);
#else /* MEMP_MEM_MALLOC */
SYS_ARCH_PROTECT(old_level);
800f74c: f00b fbd4 bl 801aef8 <sys_arch_protect>
800f750: 60f8 str r0, [r7, #12]
memp = *desc->tab;
800f752: 687b ldr r3, [r7, #4]
800f754: 689b ldr r3, [r3, #8]
800f756: 681b ldr r3, [r3, #0]
800f758: 60bb str r3, [r7, #8]
#endif /* MEMP_MEM_MALLOC */
if (memp != NULL) {
800f75a: 68bb ldr r3, [r7, #8]
800f75c: 2b00 cmp r3, #0
800f75e: d015 beq.n 800f78c <do_memp_malloc_pool+0x48>
#if !MEMP_MEM_MALLOC
#if MEMP_OVERFLOW_CHECK == 1
memp_overflow_check_element(memp, desc);
#endif /* MEMP_OVERFLOW_CHECK */
*desc->tab = memp->next;
800f760: 687b ldr r3, [r7, #4]
800f762: 689b ldr r3, [r3, #8]
800f764: 68ba ldr r2, [r7, #8]
800f766: 6812 ldr r2, [r2, #0]
800f768: 601a str r2, [r3, #0]
memp->line = line;
#if MEMP_MEM_MALLOC
memp_overflow_init_element(memp, desc);
#endif /* MEMP_MEM_MALLOC */
#endif /* MEMP_OVERFLOW_CHECK */
LWIP_ASSERT("memp_malloc: memp properly aligned",
800f76a: 68bb ldr r3, [r7, #8]
800f76c: f003 0303 and.w r3, r3, #3
800f770: 2b00 cmp r3, #0
800f772: d006 beq.n 800f782 <do_memp_malloc_pool+0x3e>
800f774: 4b09 ldr r3, [pc, #36] ; (800f79c <do_memp_malloc_pool+0x58>)
800f776: f44f 728c mov.w r2, #280 ; 0x118
800f77a: 4909 ldr r1, [pc, #36] ; (800f7a0 <do_memp_malloc_pool+0x5c>)
800f77c: 4809 ldr r0, [pc, #36] ; (800f7a4 <do_memp_malloc_pool+0x60>)
800f77e: f00b fc21 bl 801afc4 <iprintf>
desc->stats->used++;
if (desc->stats->used > desc->stats->max) {
desc->stats->max = desc->stats->used;
}
#endif
SYS_ARCH_UNPROTECT(old_level);
800f782: 68f8 ldr r0, [r7, #12]
800f784: f00b fbc6 bl 801af14 <sys_arch_unprotect>
/* cast through u8_t* to get rid of alignment warnings */
return ((u8_t *)memp + MEMP_SIZE);
800f788: 68bb ldr r3, [r7, #8]
800f78a: e003 b.n 800f794 <do_memp_malloc_pool+0x50>
} else {
#if MEMP_STATS
desc->stats->err++;
#endif
SYS_ARCH_UNPROTECT(old_level);
800f78c: 68f8 ldr r0, [r7, #12]
800f78e: f00b fbc1 bl 801af14 <sys_arch_unprotect>
LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", desc->desc));
}
return NULL;
800f792: 2300 movs r3, #0
}
800f794: 4618 mov r0, r3
800f796: 3710 adds r7, #16
800f798: 46bd mov sp, r7
800f79a: bd80 pop {r7, pc}
800f79c: 0801c500 .word 0x0801c500
800f7a0: 0801c530 .word 0x0801c530
800f7a4: 0801c554 .word 0x0801c554
0800f7a8 <memp_malloc>:
#if !MEMP_OVERFLOW_CHECK
memp_malloc(memp_t type)
#else
memp_malloc_fn(memp_t type, const char *file, const int line)
#endif
{
800f7a8: b580 push {r7, lr}
800f7aa: b084 sub sp, #16
800f7ac: af00 add r7, sp, #0
800f7ae: 4603 mov r3, r0
800f7b0: 71fb strb r3, [r7, #7]
void *memp;
LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;);
800f7b2: 79fb ldrb r3, [r7, #7]
800f7b4: 2b0c cmp r3, #12
800f7b6: d908 bls.n 800f7ca <memp_malloc+0x22>
800f7b8: 4b0a ldr r3, [pc, #40] ; (800f7e4 <memp_malloc+0x3c>)
800f7ba: f240 1257 movw r2, #343 ; 0x157
800f7be: 490a ldr r1, [pc, #40] ; (800f7e8 <memp_malloc+0x40>)
800f7c0: 480a ldr r0, [pc, #40] ; (800f7ec <memp_malloc+0x44>)
800f7c2: f00b fbff bl 801afc4 <iprintf>
800f7c6: 2300 movs r3, #0
800f7c8: e008 b.n 800f7dc <memp_malloc+0x34>
#if MEMP_OVERFLOW_CHECK >= 2
memp_overflow_check_all();
#endif /* MEMP_OVERFLOW_CHECK >= 2 */
#if !MEMP_OVERFLOW_CHECK
memp = do_memp_malloc_pool(memp_pools[type]);
800f7ca: 79fb ldrb r3, [r7, #7]
800f7cc: 4a08 ldr r2, [pc, #32] ; (800f7f0 <memp_malloc+0x48>)
800f7ce: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800f7d2: 4618 mov r0, r3
800f7d4: f7ff ffb6 bl 800f744 <do_memp_malloc_pool>
800f7d8: 60f8 str r0, [r7, #12]
#else
memp = do_memp_malloc_pool_fn(memp_pools[type], file, line);
#endif
return memp;
800f7da: 68fb ldr r3, [r7, #12]
}
800f7dc: 4618 mov r0, r3
800f7de: 3710 adds r7, #16
800f7e0: 46bd mov sp, r7
800f7e2: bd80 pop {r7, pc}
800f7e4: 0801c500 .word 0x0801c500
800f7e8: 0801c590 .word 0x0801c590
800f7ec: 0801c554 .word 0x0801c554
800f7f0: 08020fb8 .word 0x08020fb8
0800f7f4 <do_memp_free_pool>:
static void
do_memp_free_pool(const struct memp_desc *desc, void *mem)
{
800f7f4: b580 push {r7, lr}
800f7f6: b084 sub sp, #16
800f7f8: af00 add r7, sp, #0
800f7fa: 6078 str r0, [r7, #4]
800f7fc: 6039 str r1, [r7, #0]
struct memp *memp;
SYS_ARCH_DECL_PROTECT(old_level);
LWIP_ASSERT("memp_free: mem properly aligned",
800f7fe: 683b ldr r3, [r7, #0]
800f800: f003 0303 and.w r3, r3, #3
800f804: 2b00 cmp r3, #0
800f806: d006 beq.n 800f816 <do_memp_free_pool+0x22>
800f808: 4b0d ldr r3, [pc, #52] ; (800f840 <do_memp_free_pool+0x4c>)
800f80a: f44f 72b6 mov.w r2, #364 ; 0x16c
800f80e: 490d ldr r1, [pc, #52] ; (800f844 <do_memp_free_pool+0x50>)
800f810: 480d ldr r0, [pc, #52] ; (800f848 <do_memp_free_pool+0x54>)
800f812: f00b fbd7 bl 801afc4 <iprintf>
((mem_ptr_t)mem % MEM_ALIGNMENT) == 0);
/* cast through void* to get rid of alignment warnings */
memp = (struct memp *)(void *)((u8_t *)mem - MEMP_SIZE);
800f816: 683b ldr r3, [r7, #0]
800f818: 60fb str r3, [r7, #12]
SYS_ARCH_PROTECT(old_level);
800f81a: f00b fb6d bl 801aef8 <sys_arch_protect>
800f81e: 60b8 str r0, [r7, #8]
#if MEMP_MEM_MALLOC
LWIP_UNUSED_ARG(desc);
SYS_ARCH_UNPROTECT(old_level);
mem_free(memp);
#else /* MEMP_MEM_MALLOC */
memp->next = *desc->tab;
800f820: 687b ldr r3, [r7, #4]
800f822: 689b ldr r3, [r3, #8]
800f824: 681a ldr r2, [r3, #0]
800f826: 68fb ldr r3, [r7, #12]
800f828: 601a str r2, [r3, #0]
*desc->tab = memp;
800f82a: 687b ldr r3, [r7, #4]
800f82c: 689b ldr r3, [r3, #8]
800f82e: 68fa ldr r2, [r7, #12]
800f830: 601a str r2, [r3, #0]
#if MEMP_SANITY_CHECK
LWIP_ASSERT("memp sanity", memp_sanity(desc));
#endif /* MEMP_SANITY_CHECK */
SYS_ARCH_UNPROTECT(old_level);
800f832: 68b8 ldr r0, [r7, #8]
800f834: f00b fb6e bl 801af14 <sys_arch_unprotect>
#endif /* !MEMP_MEM_MALLOC */
}
800f838: bf00 nop
800f83a: 3710 adds r7, #16
800f83c: 46bd mov sp, r7
800f83e: bd80 pop {r7, pc}
800f840: 0801c500 .word 0x0801c500
800f844: 0801c5b0 .word 0x0801c5b0
800f848: 0801c554 .word 0x0801c554
0800f84c <memp_free>:
* @param type the pool where to put mem
* @param mem the memp element to free
*/
void
memp_free(memp_t type, void *mem)
{
800f84c: b580 push {r7, lr}
800f84e: b082 sub sp, #8
800f850: af00 add r7, sp, #0
800f852: 4603 mov r3, r0
800f854: 6039 str r1, [r7, #0]
800f856: 71fb strb r3, [r7, #7]
#ifdef LWIP_HOOK_MEMP_AVAILABLE
struct memp *old_first;
#endif
LWIP_ERROR("memp_free: type < MEMP_MAX", (type < MEMP_MAX), return;);
800f858: 79fb ldrb r3, [r7, #7]
800f85a: 2b0c cmp r3, #12
800f85c: d907 bls.n 800f86e <memp_free+0x22>
800f85e: 4b0c ldr r3, [pc, #48] ; (800f890 <memp_free+0x44>)
800f860: f44f 72d5 mov.w r2, #426 ; 0x1aa
800f864: 490b ldr r1, [pc, #44] ; (800f894 <memp_free+0x48>)
800f866: 480c ldr r0, [pc, #48] ; (800f898 <memp_free+0x4c>)
800f868: f00b fbac bl 801afc4 <iprintf>
800f86c: e00c b.n 800f888 <memp_free+0x3c>
if (mem == NULL) {
800f86e: 683b ldr r3, [r7, #0]
800f870: 2b00 cmp r3, #0
800f872: d008 beq.n 800f886 <memp_free+0x3a>
#ifdef LWIP_HOOK_MEMP_AVAILABLE
old_first = *memp_pools[type]->tab;
#endif
do_memp_free_pool(memp_pools[type], mem);
800f874: 79fb ldrb r3, [r7, #7]
800f876: 4a09 ldr r2, [pc, #36] ; (800f89c <memp_free+0x50>)
800f878: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800f87c: 6839 ldr r1, [r7, #0]
800f87e: 4618 mov r0, r3
800f880: f7ff ffb8 bl 800f7f4 <do_memp_free_pool>
800f884: e000 b.n 800f888 <memp_free+0x3c>
return;
800f886: bf00 nop
#ifdef LWIP_HOOK_MEMP_AVAILABLE
if (old_first == NULL) {
LWIP_HOOK_MEMP_AVAILABLE(type);
}
#endif
}
800f888: 3708 adds r7, #8
800f88a: 46bd mov sp, r7
800f88c: bd80 pop {r7, pc}
800f88e: bf00 nop
800f890: 0801c500 .word 0x0801c500
800f894: 0801c5d0 .word 0x0801c5d0
800f898: 0801c554 .word 0x0801c554
800f89c: 08020fb8 .word 0x08020fb8
0800f8a0 <netif_init>:
}
#endif /* LWIP_HAVE_LOOPIF */
void
netif_init(void)
{
800f8a0: b480 push {r7}
800f8a2: af00 add r7, sp, #0
netif_set_link_up(&loop_netif);
netif_set_up(&loop_netif);
#endif /* LWIP_HAVE_LOOPIF */
}
800f8a4: bf00 nop
800f8a6: 46bd mov sp, r7
800f8a8: f85d 7b04 ldr.w r7, [sp], #4
800f8ac: 4770 bx lr
...
0800f8b0 <netif_add>:
netif_add(struct netif *netif,
#if LWIP_IPV4
const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
#endif /* LWIP_IPV4 */
void *state, netif_init_fn init, netif_input_fn input)
{
800f8b0: b580 push {r7, lr}
800f8b2: b086 sub sp, #24
800f8b4: af00 add r7, sp, #0
800f8b6: 60f8 str r0, [r7, #12]
800f8b8: 60b9 str r1, [r7, #8]
800f8ba: 607a str r2, [r7, #4]
800f8bc: 603b str r3, [r7, #0]
LWIP_ASSERT("single netif already set", 0);
return NULL;
}
#endif
LWIP_ERROR("netif_add: invalid netif", netif != NULL, return NULL);
800f8be: 68fb ldr r3, [r7, #12]
800f8c0: 2b00 cmp r3, #0
800f8c2: d108 bne.n 800f8d6 <netif_add+0x26>
800f8c4: 4b5b ldr r3, [pc, #364] ; (800fa34 <netif_add+0x184>)
800f8c6: f240 1227 movw r2, #295 ; 0x127
800f8ca: 495b ldr r1, [pc, #364] ; (800fa38 <netif_add+0x188>)
800f8cc: 485b ldr r0, [pc, #364] ; (800fa3c <netif_add+0x18c>)
800f8ce: f00b fb79 bl 801afc4 <iprintf>
800f8d2: 2300 movs r3, #0
800f8d4: e0a9 b.n 800fa2a <netif_add+0x17a>
LWIP_ERROR("netif_add: No init function given", init != NULL, return NULL);
800f8d6: 6a7b ldr r3, [r7, #36] ; 0x24
800f8d8: 2b00 cmp r3, #0
800f8da: d108 bne.n 800f8ee <netif_add+0x3e>
800f8dc: 4b55 ldr r3, [pc, #340] ; (800fa34 <netif_add+0x184>)
800f8de: f44f 7294 mov.w r2, #296 ; 0x128
800f8e2: 4957 ldr r1, [pc, #348] ; (800fa40 <netif_add+0x190>)
800f8e4: 4855 ldr r0, [pc, #340] ; (800fa3c <netif_add+0x18c>)
800f8e6: f00b fb6d bl 801afc4 <iprintf>
800f8ea: 2300 movs r3, #0
800f8ec: e09d b.n 800fa2a <netif_add+0x17a>
#if LWIP_IPV4
if (ipaddr == NULL) {
800f8ee: 68bb ldr r3, [r7, #8]
800f8f0: 2b00 cmp r3, #0
800f8f2: d101 bne.n 800f8f8 <netif_add+0x48>
ipaddr = ip_2_ip4(IP4_ADDR_ANY);
800f8f4: 4b53 ldr r3, [pc, #332] ; (800fa44 <netif_add+0x194>)
800f8f6: 60bb str r3, [r7, #8]
}
if (netmask == NULL) {
800f8f8: 687b ldr r3, [r7, #4]
800f8fa: 2b00 cmp r3, #0
800f8fc: d101 bne.n 800f902 <netif_add+0x52>
netmask = ip_2_ip4(IP4_ADDR_ANY);
800f8fe: 4b51 ldr r3, [pc, #324] ; (800fa44 <netif_add+0x194>)
800f900: 607b str r3, [r7, #4]
}
if (gw == NULL) {
800f902: 683b ldr r3, [r7, #0]
800f904: 2b00 cmp r3, #0
800f906: d101 bne.n 800f90c <netif_add+0x5c>
gw = ip_2_ip4(IP4_ADDR_ANY);
800f908: 4b4e ldr r3, [pc, #312] ; (800fa44 <netif_add+0x194>)
800f90a: 603b str r3, [r7, #0]
}
/* reset new interface configuration state */
ip_addr_set_zero_ip4(&netif->ip_addr);
800f90c: 68fb ldr r3, [r7, #12]
800f90e: 2200 movs r2, #0
800f910: 605a str r2, [r3, #4]
ip_addr_set_zero_ip4(&netif->netmask);
800f912: 68fb ldr r3, [r7, #12]
800f914: 2200 movs r2, #0
800f916: 609a str r2, [r3, #8]
ip_addr_set_zero_ip4(&netif->gw);
800f918: 68fb ldr r3, [r7, #12]
800f91a: 2200 movs r2, #0
800f91c: 60da str r2, [r3, #12]
netif->output = netif_null_output_ip4;
800f91e: 68fb ldr r3, [r7, #12]
800f920: 4a49 ldr r2, [pc, #292] ; (800fa48 <netif_add+0x198>)
800f922: 615a str r2, [r3, #20]
#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
}
netif->output_ip6 = netif_null_output_ip6;
#endif /* LWIP_IPV6 */
NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_ENABLE_ALL);
netif->mtu = 0;
800f924: 68fb ldr r3, [r7, #12]
800f926: 2200 movs r2, #0
800f928: 851a strh r2, [r3, #40] ; 0x28
netif->flags = 0;
800f92a: 68fb ldr r3, [r7, #12]
800f92c: 2200 movs r2, #0
800f92e: f883 2031 strb.w r2, [r3, #49] ; 0x31
#ifdef netif_get_client_data
memset(netif->client_data, 0, sizeof(netif->client_data));
800f932: 68fb ldr r3, [r7, #12]
800f934: 3324 adds r3, #36 ; 0x24
800f936: 2204 movs r2, #4
800f938: 2100 movs r1, #0
800f93a: 4618 mov r0, r3
800f93c: f00b fb3a bl 801afb4 <memset>
#endif /* LWIP_IPV6 */
#if LWIP_NETIF_STATUS_CALLBACK
netif->status_callback = NULL;
#endif /* LWIP_NETIF_STATUS_CALLBACK */
#if LWIP_NETIF_LINK_CALLBACK
netif->link_callback = NULL;
800f940: 68fb ldr r3, [r7, #12]
800f942: 2200 movs r2, #0
800f944: 61da str r2, [r3, #28]
netif->loop_first = NULL;
netif->loop_last = NULL;
#endif /* ENABLE_LOOPBACK */
/* remember netif specific state information data */
netif->state = state;
800f946: 68fb ldr r3, [r7, #12]
800f948: 6a3a ldr r2, [r7, #32]
800f94a: 621a str r2, [r3, #32]
netif->num = netif_num;
800f94c: 4b3f ldr r3, [pc, #252] ; (800fa4c <netif_add+0x19c>)
800f94e: 781a ldrb r2, [r3, #0]
800f950: 68fb ldr r3, [r7, #12]
800f952: f883 2034 strb.w r2, [r3, #52] ; 0x34
netif->input = input;
800f956: 68fb ldr r3, [r7, #12]
800f958: 6aba ldr r2, [r7, #40] ; 0x28
800f95a: 611a str r2, [r3, #16]
#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS
netif->loop_cnt_current = 0;
#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */
#if LWIP_IPV4
netif_set_addr(netif, ipaddr, netmask, gw);
800f95c: 683b ldr r3, [r7, #0]
800f95e: 687a ldr r2, [r7, #4]
800f960: 68b9 ldr r1, [r7, #8]
800f962: 68f8 ldr r0, [r7, #12]
800f964: f000 f914 bl 800fb90 <netif_set_addr>
#endif /* LWIP_IPV4 */
/* call user specified initialization function for netif */
if (init(netif) != ERR_OK) {
800f968: 6a7b ldr r3, [r7, #36] ; 0x24
800f96a: 68f8 ldr r0, [r7, #12]
800f96c: 4798 blx r3
800f96e: 4603 mov r3, r0
800f970: 2b00 cmp r3, #0
800f972: d001 beq.n 800f978 <netif_add+0xc8>
return NULL;
800f974: 2300 movs r3, #0
800f976: e058 b.n 800fa2a <netif_add+0x17a>
*/
{
struct netif *netif2;
int num_netifs;
do {
if (netif->num == 255) {
800f978: 68fb ldr r3, [r7, #12]
800f97a: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800f97e: 2bff cmp r3, #255 ; 0xff
800f980: d103 bne.n 800f98a <netif_add+0xda>
netif->num = 0;
800f982: 68fb ldr r3, [r7, #12]
800f984: 2200 movs r2, #0
800f986: f883 2034 strb.w r2, [r3, #52] ; 0x34
}
num_netifs = 0;
800f98a: 2300 movs r3, #0
800f98c: 613b str r3, [r7, #16]
for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
800f98e: 4b30 ldr r3, [pc, #192] ; (800fa50 <netif_add+0x1a0>)
800f990: 681b ldr r3, [r3, #0]
800f992: 617b str r3, [r7, #20]
800f994: e02b b.n 800f9ee <netif_add+0x13e>
LWIP_ASSERT("netif already added", netif2 != netif);
800f996: 697a ldr r2, [r7, #20]
800f998: 68fb ldr r3, [r7, #12]
800f99a: 429a cmp r2, r3
800f99c: d106 bne.n 800f9ac <netif_add+0xfc>
800f99e: 4b25 ldr r3, [pc, #148] ; (800fa34 <netif_add+0x184>)
800f9a0: f240 128b movw r2, #395 ; 0x18b
800f9a4: 492b ldr r1, [pc, #172] ; (800fa54 <netif_add+0x1a4>)
800f9a6: 4825 ldr r0, [pc, #148] ; (800fa3c <netif_add+0x18c>)
800f9a8: f00b fb0c bl 801afc4 <iprintf>
num_netifs++;
800f9ac: 693b ldr r3, [r7, #16]
800f9ae: 3301 adds r3, #1
800f9b0: 613b str r3, [r7, #16]
LWIP_ASSERT("too many netifs, max. supported number is 255", num_netifs <= 255);
800f9b2: 693b ldr r3, [r7, #16]
800f9b4: 2bff cmp r3, #255 ; 0xff
800f9b6: dd06 ble.n 800f9c6 <netif_add+0x116>
800f9b8: 4b1e ldr r3, [pc, #120] ; (800fa34 <netif_add+0x184>)
800f9ba: f240 128d movw r2, #397 ; 0x18d
800f9be: 4926 ldr r1, [pc, #152] ; (800fa58 <netif_add+0x1a8>)
800f9c0: 481e ldr r0, [pc, #120] ; (800fa3c <netif_add+0x18c>)
800f9c2: f00b faff bl 801afc4 <iprintf>
if (netif2->num == netif->num) {
800f9c6: 697b ldr r3, [r7, #20]
800f9c8: f893 2034 ldrb.w r2, [r3, #52] ; 0x34
800f9cc: 68fb ldr r3, [r7, #12]
800f9ce: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800f9d2: 429a cmp r2, r3
800f9d4: d108 bne.n 800f9e8 <netif_add+0x138>
netif->num++;
800f9d6: 68fb ldr r3, [r7, #12]
800f9d8: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800f9dc: 3301 adds r3, #1
800f9de: b2da uxtb r2, r3
800f9e0: 68fb ldr r3, [r7, #12]
800f9e2: f883 2034 strb.w r2, [r3, #52] ; 0x34
break;
800f9e6: e005 b.n 800f9f4 <netif_add+0x144>
for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
800f9e8: 697b ldr r3, [r7, #20]
800f9ea: 681b ldr r3, [r3, #0]
800f9ec: 617b str r3, [r7, #20]
800f9ee: 697b ldr r3, [r7, #20]
800f9f0: 2b00 cmp r3, #0
800f9f2: d1d0 bne.n 800f996 <netif_add+0xe6>
}
}
} while (netif2 != NULL);
800f9f4: 697b ldr r3, [r7, #20]
800f9f6: 2b00 cmp r3, #0
800f9f8: d1be bne.n 800f978 <netif_add+0xc8>
}
if (netif->num == 254) {
800f9fa: 68fb ldr r3, [r7, #12]
800f9fc: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800fa00: 2bfe cmp r3, #254 ; 0xfe
800fa02: d103 bne.n 800fa0c <netif_add+0x15c>
netif_num = 0;
800fa04: 4b11 ldr r3, [pc, #68] ; (800fa4c <netif_add+0x19c>)
800fa06: 2200 movs r2, #0
800fa08: 701a strb r2, [r3, #0]
800fa0a: e006 b.n 800fa1a <netif_add+0x16a>
} else {
netif_num = (u8_t)(netif->num + 1);
800fa0c: 68fb ldr r3, [r7, #12]
800fa0e: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800fa12: 3301 adds r3, #1
800fa14: b2da uxtb r2, r3
800fa16: 4b0d ldr r3, [pc, #52] ; (800fa4c <netif_add+0x19c>)
800fa18: 701a strb r2, [r3, #0]
}
/* add this netif to the list */
netif->next = netif_list;
800fa1a: 4b0d ldr r3, [pc, #52] ; (800fa50 <netif_add+0x1a0>)
800fa1c: 681a ldr r2, [r3, #0]
800fa1e: 68fb ldr r3, [r7, #12]
800fa20: 601a str r2, [r3, #0]
netif_list = netif;
800fa22: 4a0b ldr r2, [pc, #44] ; (800fa50 <netif_add+0x1a0>)
800fa24: 68fb ldr r3, [r7, #12]
800fa26: 6013 str r3, [r2, #0]
#endif /* LWIP_IPV4 */
LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_ADDED, NULL);
return netif;
800fa28: 68fb ldr r3, [r7, #12]
}
800fa2a: 4618 mov r0, r3
800fa2c: 3718 adds r7, #24
800fa2e: 46bd mov sp, r7
800fa30: bd80 pop {r7, pc}
800fa32: bf00 nop
800fa34: 0801c5ec .word 0x0801c5ec
800fa38: 0801c680 .word 0x0801c680
800fa3c: 0801c63c .word 0x0801c63c
800fa40: 0801c69c .word 0x0801c69c
800fa44: 0802103c .word 0x0802103c
800fa48: 0800fe73 .word 0x0800fe73
800fa4c: 2000871c .word 0x2000871c
800fa50: 2000f82c .word 0x2000f82c
800fa54: 0801c6c0 .word 0x0801c6c0
800fa58: 0801c6d4 .word 0x0801c6d4
0800fa5c <netif_do_ip_addr_changed>:
static void
netif_do_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
{
800fa5c: b580 push {r7, lr}
800fa5e: b082 sub sp, #8
800fa60: af00 add r7, sp, #0
800fa62: 6078 str r0, [r7, #4]
800fa64: 6039 str r1, [r7, #0]
#if LWIP_TCP
tcp_netif_ip_addr_changed(old_addr, new_addr);
800fa66: 6839 ldr r1, [r7, #0]
800fa68: 6878 ldr r0, [r7, #4]
800fa6a: f002 fb91 bl 8012190 <tcp_netif_ip_addr_changed>
#endif /* LWIP_TCP */
#if LWIP_UDP
udp_netif_ip_addr_changed(old_addr, new_addr);
800fa6e: 6839 ldr r1, [r7, #0]
800fa70: 6878 ldr r0, [r7, #4]
800fa72: f006 ffa3 bl 80169bc <udp_netif_ip_addr_changed>
#endif /* LWIP_UDP */
#if LWIP_RAW
raw_netif_ip_addr_changed(old_addr, new_addr);
#endif /* LWIP_RAW */
}
800fa76: bf00 nop
800fa78: 3708 adds r7, #8
800fa7a: 46bd mov sp, r7
800fa7c: bd80 pop {r7, pc}
...
0800fa80 <netif_do_set_ipaddr>:
#if LWIP_IPV4
static int
netif_do_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr, ip_addr_t *old_addr)
{
800fa80: b580 push {r7, lr}
800fa82: b086 sub sp, #24
800fa84: af00 add r7, sp, #0
800fa86: 60f8 str r0, [r7, #12]
800fa88: 60b9 str r1, [r7, #8]
800fa8a: 607a str r2, [r7, #4]
LWIP_ASSERT("invalid pointer", ipaddr != NULL);
800fa8c: 68bb ldr r3, [r7, #8]
800fa8e: 2b00 cmp r3, #0
800fa90: d106 bne.n 800faa0 <netif_do_set_ipaddr+0x20>
800fa92: 4b1d ldr r3, [pc, #116] ; (800fb08 <netif_do_set_ipaddr+0x88>)
800fa94: f240 12cb movw r2, #459 ; 0x1cb
800fa98: 491c ldr r1, [pc, #112] ; (800fb0c <netif_do_set_ipaddr+0x8c>)
800fa9a: 481d ldr r0, [pc, #116] ; (800fb10 <netif_do_set_ipaddr+0x90>)
800fa9c: f00b fa92 bl 801afc4 <iprintf>
LWIP_ASSERT("invalid pointer", old_addr != NULL);
800faa0: 687b ldr r3, [r7, #4]
800faa2: 2b00 cmp r3, #0
800faa4: d106 bne.n 800fab4 <netif_do_set_ipaddr+0x34>
800faa6: 4b18 ldr r3, [pc, #96] ; (800fb08 <netif_do_set_ipaddr+0x88>)
800faa8: f44f 72e6 mov.w r2, #460 ; 0x1cc
800faac: 4917 ldr r1, [pc, #92] ; (800fb0c <netif_do_set_ipaddr+0x8c>)
800faae: 4818 ldr r0, [pc, #96] ; (800fb10 <netif_do_set_ipaddr+0x90>)
800fab0: f00b fa88 bl 801afc4 <iprintf>
/* address is actually being changed? */
if (ip4_addr_cmp(ipaddr, netif_ip4_addr(netif)) == 0) {
800fab4: 68bb ldr r3, [r7, #8]
800fab6: 681a ldr r2, [r3, #0]
800fab8: 68fb ldr r3, [r7, #12]
800faba: 3304 adds r3, #4
800fabc: 681b ldr r3, [r3, #0]
800fabe: 429a cmp r2, r3
800fac0: d01c beq.n 800fafc <netif_do_set_ipaddr+0x7c>
ip_addr_t new_addr;
*ip_2_ip4(&new_addr) = *ipaddr;
800fac2: 68bb ldr r3, [r7, #8]
800fac4: 681b ldr r3, [r3, #0]
800fac6: 617b str r3, [r7, #20]
IP_SET_TYPE_VAL(new_addr, IPADDR_TYPE_V4);
ip_addr_copy(*old_addr, *netif_ip_addr4(netif));
800fac8: 68fb ldr r3, [r7, #12]
800faca: 3304 adds r3, #4
800facc: 681a ldr r2, [r3, #0]
800face: 687b ldr r3, [r7, #4]
800fad0: 601a str r2, [r3, #0]
LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n"));
netif_do_ip_addr_changed(old_addr, &new_addr);
800fad2: f107 0314 add.w r3, r7, #20
800fad6: 4619 mov r1, r3
800fad8: 6878 ldr r0, [r7, #4]
800fada: f7ff ffbf bl 800fa5c <netif_do_ip_addr_changed>
mib2_remove_ip4(netif);
mib2_remove_route_ip4(0, netif);
/* set new IP address to netif */
ip4_addr_set(ip_2_ip4(&netif->ip_addr), ipaddr);
800fade: 68bb ldr r3, [r7, #8]
800fae0: 2b00 cmp r3, #0
800fae2: d002 beq.n 800faea <netif_do_set_ipaddr+0x6a>
800fae4: 68bb ldr r3, [r7, #8]
800fae6: 681b ldr r3, [r3, #0]
800fae8: e000 b.n 800faec <netif_do_set_ipaddr+0x6c>
800faea: 2300 movs r3, #0
800faec: 68fa ldr r2, [r7, #12]
800faee: 6053 str r3, [r2, #4]
IP_SET_TYPE_VAL(netif->ip_addr, IPADDR_TYPE_V4);
mib2_add_ip4(netif);
mib2_add_route_ip4(0, netif);
netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4);
800faf0: 2101 movs r1, #1
800faf2: 68f8 ldr r0, [r7, #12]
800faf4: f000 f8d2 bl 800fc9c <netif_issue_reports>
NETIF_STATUS_CALLBACK(netif);
return 1; /* address changed */
800faf8: 2301 movs r3, #1
800fafa: e000 b.n 800fafe <netif_do_set_ipaddr+0x7e>
}
return 0; /* address unchanged */
800fafc: 2300 movs r3, #0
}
800fafe: 4618 mov r0, r3
800fb00: 3718 adds r7, #24
800fb02: 46bd mov sp, r7
800fb04: bd80 pop {r7, pc}
800fb06: bf00 nop
800fb08: 0801c5ec .word 0x0801c5ec
800fb0c: 0801c704 .word 0x0801c704
800fb10: 0801c63c .word 0x0801c63c
0800fb14 <netif_do_set_netmask>:
}
}
static int
netif_do_set_netmask(struct netif *netif, const ip4_addr_t *netmask, ip_addr_t *old_nm)
{
800fb14: b480 push {r7}
800fb16: b085 sub sp, #20
800fb18: af00 add r7, sp, #0
800fb1a: 60f8 str r0, [r7, #12]
800fb1c: 60b9 str r1, [r7, #8]
800fb1e: 607a str r2, [r7, #4]
/* address is actually being changed? */
if (ip4_addr_cmp(netmask, netif_ip4_netmask(netif)) == 0) {
800fb20: 68bb ldr r3, [r7, #8]
800fb22: 681a ldr r2, [r3, #0]
800fb24: 68fb ldr r3, [r7, #12]
800fb26: 3308 adds r3, #8
800fb28: 681b ldr r3, [r3, #0]
800fb2a: 429a cmp r2, r3
800fb2c: d00a beq.n 800fb44 <netif_do_set_netmask+0x30>
#else
LWIP_UNUSED_ARG(old_nm);
#endif
mib2_remove_route_ip4(0, netif);
/* set new netmask to netif */
ip4_addr_set(ip_2_ip4(&netif->netmask), netmask);
800fb2e: 68bb ldr r3, [r7, #8]
800fb30: 2b00 cmp r3, #0
800fb32: d002 beq.n 800fb3a <netif_do_set_netmask+0x26>
800fb34: 68bb ldr r3, [r7, #8]
800fb36: 681b ldr r3, [r3, #0]
800fb38: e000 b.n 800fb3c <netif_do_set_netmask+0x28>
800fb3a: 2300 movs r3, #0
800fb3c: 68fa ldr r2, [r7, #12]
800fb3e: 6093 str r3, [r2, #8]
netif->name[0], netif->name[1],
ip4_addr1_16(netif_ip4_netmask(netif)),
ip4_addr2_16(netif_ip4_netmask(netif)),
ip4_addr3_16(netif_ip4_netmask(netif)),
ip4_addr4_16(netif_ip4_netmask(netif))));
return 1; /* netmask changed */
800fb40: 2301 movs r3, #1
800fb42: e000 b.n 800fb46 <netif_do_set_netmask+0x32>
}
return 0; /* netmask unchanged */
800fb44: 2300 movs r3, #0
}
800fb46: 4618 mov r0, r3
800fb48: 3714 adds r7, #20
800fb4a: 46bd mov sp, r7
800fb4c: f85d 7b04 ldr.w r7, [sp], #4
800fb50: 4770 bx lr
0800fb52 <netif_do_set_gw>:
}
}
static int
netif_do_set_gw(struct netif *netif, const ip4_addr_t *gw, ip_addr_t *old_gw)
{
800fb52: b480 push {r7}
800fb54: b085 sub sp, #20
800fb56: af00 add r7, sp, #0
800fb58: 60f8 str r0, [r7, #12]
800fb5a: 60b9 str r1, [r7, #8]
800fb5c: 607a str r2, [r7, #4]
/* address is actually being changed? */
if (ip4_addr_cmp(gw, netif_ip4_gw(netif)) == 0) {
800fb5e: 68bb ldr r3, [r7, #8]
800fb60: 681a ldr r2, [r3, #0]
800fb62: 68fb ldr r3, [r7, #12]
800fb64: 330c adds r3, #12
800fb66: 681b ldr r3, [r3, #0]
800fb68: 429a cmp r2, r3
800fb6a: d00a beq.n 800fb82 <netif_do_set_gw+0x30>
ip_addr_copy(*old_gw, *netif_ip_gw4(netif));
#else
LWIP_UNUSED_ARG(old_gw);
#endif
ip4_addr_set(ip_2_ip4(&netif->gw), gw);
800fb6c: 68bb ldr r3, [r7, #8]
800fb6e: 2b00 cmp r3, #0
800fb70: d002 beq.n 800fb78 <netif_do_set_gw+0x26>
800fb72: 68bb ldr r3, [r7, #8]
800fb74: 681b ldr r3, [r3, #0]
800fb76: e000 b.n 800fb7a <netif_do_set_gw+0x28>
800fb78: 2300 movs r3, #0
800fb7a: 68fa ldr r2, [r7, #12]
800fb7c: 60d3 str r3, [r2, #12]
netif->name[0], netif->name[1],
ip4_addr1_16(netif_ip4_gw(netif)),
ip4_addr2_16(netif_ip4_gw(netif)),
ip4_addr3_16(netif_ip4_gw(netif)),
ip4_addr4_16(netif_ip4_gw(netif))));
return 1; /* gateway changed */
800fb7e: 2301 movs r3, #1
800fb80: e000 b.n 800fb84 <netif_do_set_gw+0x32>
}
return 0; /* gateway unchanged */
800fb82: 2300 movs r3, #0
}
800fb84: 4618 mov r0, r3
800fb86: 3714 adds r7, #20
800fb88: 46bd mov sp, r7
800fb8a: f85d 7b04 ldr.w r7, [sp], #4
800fb8e: 4770 bx lr
0800fb90 <netif_set_addr>:
* @param gw the new default gateway
*/
void
netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask,
const ip4_addr_t *gw)
{
800fb90: b580 push {r7, lr}
800fb92: b088 sub sp, #32
800fb94: af00 add r7, sp, #0
800fb96: 60f8 str r0, [r7, #12]
800fb98: 60b9 str r1, [r7, #8]
800fb9a: 607a str r2, [r7, #4]
800fb9c: 603b str r3, [r7, #0]
ip_addr_t old_nm_val;
ip_addr_t old_gw_val;
ip_addr_t *old_nm = &old_nm_val;
ip_addr_t *old_gw = &old_gw_val;
#else
ip_addr_t *old_nm = NULL;
800fb9e: 2300 movs r3, #0
800fba0: 61fb str r3, [r7, #28]
ip_addr_t *old_gw = NULL;
800fba2: 2300 movs r3, #0
800fba4: 61bb str r3, [r7, #24]
int remove;
LWIP_ASSERT_CORE_LOCKED();
/* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
if (ipaddr == NULL) {
800fba6: 68bb ldr r3, [r7, #8]
800fba8: 2b00 cmp r3, #0
800fbaa: d101 bne.n 800fbb0 <netif_set_addr+0x20>
ipaddr = IP4_ADDR_ANY4;
800fbac: 4b1c ldr r3, [pc, #112] ; (800fc20 <netif_set_addr+0x90>)
800fbae: 60bb str r3, [r7, #8]
}
if (netmask == NULL) {
800fbb0: 687b ldr r3, [r7, #4]
800fbb2: 2b00 cmp r3, #0
800fbb4: d101 bne.n 800fbba <netif_set_addr+0x2a>
netmask = IP4_ADDR_ANY4;
800fbb6: 4b1a ldr r3, [pc, #104] ; (800fc20 <netif_set_addr+0x90>)
800fbb8: 607b str r3, [r7, #4]
}
if (gw == NULL) {
800fbba: 683b ldr r3, [r7, #0]
800fbbc: 2b00 cmp r3, #0
800fbbe: d101 bne.n 800fbc4 <netif_set_addr+0x34>
gw = IP4_ADDR_ANY4;
800fbc0: 4b17 ldr r3, [pc, #92] ; (800fc20 <netif_set_addr+0x90>)
800fbc2: 603b str r3, [r7, #0]
}
remove = ip4_addr_isany(ipaddr);
800fbc4: 68bb ldr r3, [r7, #8]
800fbc6: 2b00 cmp r3, #0
800fbc8: d003 beq.n 800fbd2 <netif_set_addr+0x42>
800fbca: 68bb ldr r3, [r7, #8]
800fbcc: 681b ldr r3, [r3, #0]
800fbce: 2b00 cmp r3, #0
800fbd0: d101 bne.n 800fbd6 <netif_set_addr+0x46>
800fbd2: 2301 movs r3, #1
800fbd4: e000 b.n 800fbd8 <netif_set_addr+0x48>
800fbd6: 2300 movs r3, #0
800fbd8: 617b str r3, [r7, #20]
if (remove) {
800fbda: 697b ldr r3, [r7, #20]
800fbdc: 2b00 cmp r3, #0
800fbde: d006 beq.n 800fbee <netif_set_addr+0x5e>
/* when removing an address, we have to remove it *before* changing netmask/gw
to ensure that tcp RST segment can be sent correctly */
if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
800fbe0: f107 0310 add.w r3, r7, #16
800fbe4: 461a mov r2, r3
800fbe6: 68b9 ldr r1, [r7, #8]
800fbe8: 68f8 ldr r0, [r7, #12]
800fbea: f7ff ff49 bl 800fa80 <netif_do_set_ipaddr>
change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED;
cb_args.ipv4_changed.old_address = &old_addr;
#endif
}
}
if (netif_do_set_netmask(netif, netmask, old_nm)) {
800fbee: 69fa ldr r2, [r7, #28]
800fbf0: 6879 ldr r1, [r7, #4]
800fbf2: 68f8 ldr r0, [r7, #12]
800fbf4: f7ff ff8e bl 800fb14 <netif_do_set_netmask>
#if LWIP_NETIF_EXT_STATUS_CALLBACK
change_reason |= LWIP_NSC_IPV4_NETMASK_CHANGED;
cb_args.ipv4_changed.old_netmask = old_nm;
#endif
}
if (netif_do_set_gw(netif, gw, old_gw)) {
800fbf8: 69ba ldr r2, [r7, #24]
800fbfa: 6839 ldr r1, [r7, #0]
800fbfc: 68f8 ldr r0, [r7, #12]
800fbfe: f7ff ffa8 bl 800fb52 <netif_do_set_gw>
#if LWIP_NETIF_EXT_STATUS_CALLBACK
change_reason |= LWIP_NSC_IPV4_GATEWAY_CHANGED;
cb_args.ipv4_changed.old_gw = old_gw;
#endif
}
if (!remove) {
800fc02: 697b ldr r3, [r7, #20]
800fc04: 2b00 cmp r3, #0
800fc06: d106 bne.n 800fc16 <netif_set_addr+0x86>
/* set ipaddr last to ensure netmask/gw have been set when status callback is called */
if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
800fc08: f107 0310 add.w r3, r7, #16
800fc0c: 461a mov r2, r3
800fc0e: 68b9 ldr r1, [r7, #8]
800fc10: 68f8 ldr r0, [r7, #12]
800fc12: f7ff ff35 bl 800fa80 <netif_do_set_ipaddr>
if (change_reason != LWIP_NSC_NONE) {
change_reason |= LWIP_NSC_IPV4_SETTINGS_CHANGED;
netif_invoke_ext_callback(netif, change_reason, &cb_args);
}
#endif
}
800fc16: bf00 nop
800fc18: 3720 adds r7, #32
800fc1a: 46bd mov sp, r7
800fc1c: bd80 pop {r7, pc}
800fc1e: bf00 nop
800fc20: 0802103c .word 0x0802103c
0800fc24 <netif_set_default>:
*
* @param netif the default network interface
*/
void
netif_set_default(struct netif *netif)
{
800fc24: b480 push {r7}
800fc26: b083 sub sp, #12
800fc28: af00 add r7, sp, #0
800fc2a: 6078 str r0, [r7, #4]
mib2_remove_route_ip4(1, netif);
} else {
/* install default route */
mib2_add_route_ip4(1, netif);
}
netif_default = netif;
800fc2c: 4a04 ldr r2, [pc, #16] ; (800fc40 <netif_set_default+0x1c>)
800fc2e: 687b ldr r3, [r7, #4]
800fc30: 6013 str r3, [r2, #0]
LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
}
800fc32: bf00 nop
800fc34: 370c adds r7, #12
800fc36: 46bd mov sp, r7
800fc38: f85d 7b04 ldr.w r7, [sp], #4
800fc3c: 4770 bx lr
800fc3e: bf00 nop
800fc40: 2000f830 .word 0x2000f830
0800fc44 <netif_set_up>:
* Bring an interface up, available for processing
* traffic.
*/
void
netif_set_up(struct netif *netif)
{
800fc44: b580 push {r7, lr}
800fc46: b082 sub sp, #8
800fc48: af00 add r7, sp, #0
800fc4a: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif_set_up: invalid netif", netif != NULL, return);
800fc4c: 687b ldr r3, [r7, #4]
800fc4e: 2b00 cmp r3, #0
800fc50: d107 bne.n 800fc62 <netif_set_up+0x1e>
800fc52: 4b0f ldr r3, [pc, #60] ; (800fc90 <netif_set_up+0x4c>)
800fc54: f44f 7254 mov.w r2, #848 ; 0x350
800fc58: 490e ldr r1, [pc, #56] ; (800fc94 <netif_set_up+0x50>)
800fc5a: 480f ldr r0, [pc, #60] ; (800fc98 <netif_set_up+0x54>)
800fc5c: f00b f9b2 bl 801afc4 <iprintf>
800fc60: e013 b.n 800fc8a <netif_set_up+0x46>
if (!(netif->flags & NETIF_FLAG_UP)) {
800fc62: 687b ldr r3, [r7, #4]
800fc64: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fc68: f003 0301 and.w r3, r3, #1
800fc6c: 2b00 cmp r3, #0
800fc6e: d10c bne.n 800fc8a <netif_set_up+0x46>
netif_set_flags(netif, NETIF_FLAG_UP);
800fc70: 687b ldr r3, [r7, #4]
800fc72: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fc76: f043 0301 orr.w r3, r3, #1
800fc7a: b2da uxtb r2, r3
800fc7c: 687b ldr r3, [r7, #4]
800fc7e: f883 2031 strb.w r2, [r3, #49] ; 0x31
args.status_changed.state = 1;
netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
}
#endif
netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
800fc82: 2103 movs r1, #3
800fc84: 6878 ldr r0, [r7, #4]
800fc86: f000 f809 bl 800fc9c <netif_issue_reports>
#if LWIP_IPV6
nd6_restart_netif(netif);
#endif /* LWIP_IPV6 */
}
}
800fc8a: 3708 adds r7, #8
800fc8c: 46bd mov sp, r7
800fc8e: bd80 pop {r7, pc}
800fc90: 0801c5ec .word 0x0801c5ec
800fc94: 0801c774 .word 0x0801c774
800fc98: 0801c63c .word 0x0801c63c
0800fc9c <netif_issue_reports>:
/** Send ARP/IGMP/MLD/RS events, e.g. on link-up/netif-up or addr-change
*/
static void
netif_issue_reports(struct netif *netif, u8_t report_type)
{
800fc9c: b580 push {r7, lr}
800fc9e: b082 sub sp, #8
800fca0: af00 add r7, sp, #0
800fca2: 6078 str r0, [r7, #4]
800fca4: 460b mov r3, r1
800fca6: 70fb strb r3, [r7, #3]
LWIP_ASSERT("netif_issue_reports: invalid netif", netif != NULL);
800fca8: 687b ldr r3, [r7, #4]
800fcaa: 2b00 cmp r3, #0
800fcac: d106 bne.n 800fcbc <netif_issue_reports+0x20>
800fcae: 4b18 ldr r3, [pc, #96] ; (800fd10 <netif_issue_reports+0x74>)
800fcb0: f240 326d movw r2, #877 ; 0x36d
800fcb4: 4917 ldr r1, [pc, #92] ; (800fd14 <netif_issue_reports+0x78>)
800fcb6: 4818 ldr r0, [pc, #96] ; (800fd18 <netif_issue_reports+0x7c>)
800fcb8: f00b f984 bl 801afc4 <iprintf>
/* Only send reports when both link and admin states are up */
if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
800fcbc: 687b ldr r3, [r7, #4]
800fcbe: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fcc2: f003 0304 and.w r3, r3, #4
800fcc6: 2b00 cmp r3, #0
800fcc8: d01e beq.n 800fd08 <netif_issue_reports+0x6c>
!(netif->flags & NETIF_FLAG_UP)) {
800fcca: 687b ldr r3, [r7, #4]
800fccc: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fcd0: f003 0301 and.w r3, r3, #1
if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
800fcd4: 2b00 cmp r3, #0
800fcd6: d017 beq.n 800fd08 <netif_issue_reports+0x6c>
return;
}
#if LWIP_IPV4
if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
800fcd8: 78fb ldrb r3, [r7, #3]
800fcda: f003 0301 and.w r3, r3, #1
800fcde: 2b00 cmp r3, #0
800fce0: d013 beq.n 800fd0a <netif_issue_reports+0x6e>
!ip4_addr_isany_val(*netif_ip4_addr(netif))) {
800fce2: 687b ldr r3, [r7, #4]
800fce4: 3304 adds r3, #4
800fce6: 681b ldr r3, [r3, #0]
if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
800fce8: 2b00 cmp r3, #0
800fcea: d00e beq.n 800fd0a <netif_issue_reports+0x6e>
#if LWIP_ARP
/* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */
if (netif->flags & (NETIF_FLAG_ETHARP)) {
800fcec: 687b ldr r3, [r7, #4]
800fcee: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fcf2: f003 0308 and.w r3, r3, #8
800fcf6: 2b00 cmp r3, #0
800fcf8: d007 beq.n 800fd0a <netif_issue_reports+0x6e>
etharp_gratuitous(netif);
800fcfa: 687b ldr r3, [r7, #4]
800fcfc: 3304 adds r3, #4
800fcfe: 4619 mov r1, r3
800fd00: 6878 ldr r0, [r7, #4]
800fd02: f009 fc5d bl 80195c0 <etharp_request>
800fd06: e000 b.n 800fd0a <netif_issue_reports+0x6e>
return;
800fd08: bf00 nop
/* send mld memberships */
mld6_report_groups(netif);
#endif /* LWIP_IPV6_MLD */
}
#endif /* LWIP_IPV6 */
}
800fd0a: 3708 adds r7, #8
800fd0c: 46bd mov sp, r7
800fd0e: bd80 pop {r7, pc}
800fd10: 0801c5ec .word 0x0801c5ec
800fd14: 0801c790 .word 0x0801c790
800fd18: 0801c63c .word 0x0801c63c
0800fd1c <netif_set_down>:
* @ingroup netif
* Bring an interface down, disabling any traffic processing.
*/
void
netif_set_down(struct netif *netif)
{
800fd1c: b580 push {r7, lr}
800fd1e: b082 sub sp, #8
800fd20: af00 add r7, sp, #0
800fd22: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif_set_down: invalid netif", netif != NULL, return);
800fd24: 687b ldr r3, [r7, #4]
800fd26: 2b00 cmp r3, #0
800fd28: d107 bne.n 800fd3a <netif_set_down+0x1e>
800fd2a: 4b12 ldr r3, [pc, #72] ; (800fd74 <netif_set_down+0x58>)
800fd2c: f240 329b movw r2, #923 ; 0x39b
800fd30: 4911 ldr r1, [pc, #68] ; (800fd78 <netif_set_down+0x5c>)
800fd32: 4812 ldr r0, [pc, #72] ; (800fd7c <netif_set_down+0x60>)
800fd34: f00b f946 bl 801afc4 <iprintf>
800fd38: e019 b.n 800fd6e <netif_set_down+0x52>
if (netif->flags & NETIF_FLAG_UP) {
800fd3a: 687b ldr r3, [r7, #4]
800fd3c: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fd40: f003 0301 and.w r3, r3, #1
800fd44: 2b00 cmp r3, #0
800fd46: d012 beq.n 800fd6e <netif_set_down+0x52>
args.status_changed.state = 0;
netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
}
#endif
netif_clear_flags(netif, NETIF_FLAG_UP);
800fd48: 687b ldr r3, [r7, #4]
800fd4a: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fd4e: f023 0301 bic.w r3, r3, #1
800fd52: b2da uxtb r2, r3
800fd54: 687b ldr r3, [r7, #4]
800fd56: f883 2031 strb.w r2, [r3, #49] ; 0x31
MIB2_COPY_SYSUPTIME_TO(&netif->ts);
#if LWIP_IPV4 && LWIP_ARP
if (netif->flags & NETIF_FLAG_ETHARP) {
800fd5a: 687b ldr r3, [r7, #4]
800fd5c: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fd60: f003 0308 and.w r3, r3, #8
800fd64: 2b00 cmp r3, #0
800fd66: d002 beq.n 800fd6e <netif_set_down+0x52>
etharp_cleanup_netif(netif);
800fd68: 6878 ldr r0, [r7, #4]
800fd6a: f008 ffe3 bl 8018d34 <etharp_cleanup_netif>
nd6_cleanup_netif(netif);
#endif /* LWIP_IPV6 */
NETIF_STATUS_CALLBACK(netif);
}
}
800fd6e: 3708 adds r7, #8
800fd70: 46bd mov sp, r7
800fd72: bd80 pop {r7, pc}
800fd74: 0801c5ec .word 0x0801c5ec
800fd78: 0801c7b4 .word 0x0801c7b4
800fd7c: 0801c63c .word 0x0801c63c
0800fd80 <netif_set_link_up>:
* @ingroup netif
* Called by a driver when its link goes up
*/
void
netif_set_link_up(struct netif *netif)
{
800fd80: b580 push {r7, lr}
800fd82: b082 sub sp, #8
800fd84: af00 add r7, sp, #0
800fd86: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif_set_link_up: invalid netif", netif != NULL, return);
800fd88: 687b ldr r3, [r7, #4]
800fd8a: 2b00 cmp r3, #0
800fd8c: d107 bne.n 800fd9e <netif_set_link_up+0x1e>
800fd8e: 4b15 ldr r3, [pc, #84] ; (800fde4 <netif_set_link_up+0x64>)
800fd90: f44f 7278 mov.w r2, #992 ; 0x3e0
800fd94: 4914 ldr r1, [pc, #80] ; (800fde8 <netif_set_link_up+0x68>)
800fd96: 4815 ldr r0, [pc, #84] ; (800fdec <netif_set_link_up+0x6c>)
800fd98: f00b f914 bl 801afc4 <iprintf>
800fd9c: e01e b.n 800fddc <netif_set_link_up+0x5c>
if (!(netif->flags & NETIF_FLAG_LINK_UP)) {
800fd9e: 687b ldr r3, [r7, #4]
800fda0: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fda4: f003 0304 and.w r3, r3, #4
800fda8: 2b00 cmp r3, #0
800fdaa: d117 bne.n 800fddc <netif_set_link_up+0x5c>
netif_set_flags(netif, NETIF_FLAG_LINK_UP);
800fdac: 687b ldr r3, [r7, #4]
800fdae: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fdb2: f043 0304 orr.w r3, r3, #4
800fdb6: b2da uxtb r2, r3
800fdb8: 687b ldr r3, [r7, #4]
800fdba: f883 2031 strb.w r2, [r3, #49] ; 0x31
#if LWIP_DHCP
dhcp_network_changed(netif);
800fdbe: 6878 ldr r0, [r7, #4]
800fdc0: f007 fa28 bl 8017214 <dhcp_network_changed>
#if LWIP_AUTOIP
autoip_network_changed(netif);
#endif /* LWIP_AUTOIP */
netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
800fdc4: 2103 movs r1, #3
800fdc6: 6878 ldr r0, [r7, #4]
800fdc8: f7ff ff68 bl 800fc9c <netif_issue_reports>
#if LWIP_IPV6
nd6_restart_netif(netif);
#endif /* LWIP_IPV6 */
NETIF_LINK_CALLBACK(netif);
800fdcc: 687b ldr r3, [r7, #4]
800fdce: 69db ldr r3, [r3, #28]
800fdd0: 2b00 cmp r3, #0
800fdd2: d003 beq.n 800fddc <netif_set_link_up+0x5c>
800fdd4: 687b ldr r3, [r7, #4]
800fdd6: 69db ldr r3, [r3, #28]
800fdd8: 6878 ldr r0, [r7, #4]
800fdda: 4798 blx r3
args.link_changed.state = 1;
netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
}
#endif
}
}
800fddc: 3708 adds r7, #8
800fdde: 46bd mov sp, r7
800fde0: bd80 pop {r7, pc}
800fde2: bf00 nop
800fde4: 0801c5ec .word 0x0801c5ec
800fde8: 0801c7d4 .word 0x0801c7d4
800fdec: 0801c63c .word 0x0801c63c
0800fdf0 <netif_set_link_down>:
* @ingroup netif
* Called by a driver when its link goes down
*/
void
netif_set_link_down(struct netif *netif)
{
800fdf0: b580 push {r7, lr}
800fdf2: b082 sub sp, #8
800fdf4: af00 add r7, sp, #0
800fdf6: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif_set_link_down: invalid netif", netif != NULL, return);
800fdf8: 687b ldr r3, [r7, #4]
800fdfa: 2b00 cmp r3, #0
800fdfc: d107 bne.n 800fe0e <netif_set_link_down+0x1e>
800fdfe: 4b11 ldr r3, [pc, #68] ; (800fe44 <netif_set_link_down+0x54>)
800fe00: f240 4206 movw r2, #1030 ; 0x406
800fe04: 4910 ldr r1, [pc, #64] ; (800fe48 <netif_set_link_down+0x58>)
800fe06: 4811 ldr r0, [pc, #68] ; (800fe4c <netif_set_link_down+0x5c>)
800fe08: f00b f8dc bl 801afc4 <iprintf>
800fe0c: e017 b.n 800fe3e <netif_set_link_down+0x4e>
if (netif->flags & NETIF_FLAG_LINK_UP) {
800fe0e: 687b ldr r3, [r7, #4]
800fe10: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fe14: f003 0304 and.w r3, r3, #4
800fe18: 2b00 cmp r3, #0
800fe1a: d010 beq.n 800fe3e <netif_set_link_down+0x4e>
netif_clear_flags(netif, NETIF_FLAG_LINK_UP);
800fe1c: 687b ldr r3, [r7, #4]
800fe1e: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fe22: f023 0304 bic.w r3, r3, #4
800fe26: b2da uxtb r2, r3
800fe28: 687b ldr r3, [r7, #4]
800fe2a: f883 2031 strb.w r2, [r3, #49] ; 0x31
NETIF_LINK_CALLBACK(netif);
800fe2e: 687b ldr r3, [r7, #4]
800fe30: 69db ldr r3, [r3, #28]
800fe32: 2b00 cmp r3, #0
800fe34: d003 beq.n 800fe3e <netif_set_link_down+0x4e>
800fe36: 687b ldr r3, [r7, #4]
800fe38: 69db ldr r3, [r3, #28]
800fe3a: 6878 ldr r0, [r7, #4]
800fe3c: 4798 blx r3
args.link_changed.state = 0;
netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
}
#endif
}
}
800fe3e: 3708 adds r7, #8
800fe40: 46bd mov sp, r7
800fe42: bd80 pop {r7, pc}
800fe44: 0801c5ec .word 0x0801c5ec
800fe48: 0801c7f8 .word 0x0801c7f8
800fe4c: 0801c63c .word 0x0801c63c
0800fe50 <netif_set_link_callback>:
* @ingroup netif
* Set callback to be called when link is brought up/down
*/
void
netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback)
{
800fe50: b480 push {r7}
800fe52: b083 sub sp, #12
800fe54: af00 add r7, sp, #0
800fe56: 6078 str r0, [r7, #4]
800fe58: 6039 str r1, [r7, #0]
LWIP_ASSERT_CORE_LOCKED();
if (netif) {
800fe5a: 687b ldr r3, [r7, #4]
800fe5c: 2b00 cmp r3, #0
800fe5e: d002 beq.n 800fe66 <netif_set_link_callback+0x16>
netif->link_callback = link_callback;
800fe60: 687b ldr r3, [r7, #4]
800fe62: 683a ldr r2, [r7, #0]
800fe64: 61da str r2, [r3, #28]
}
}
800fe66: bf00 nop
800fe68: 370c adds r7, #12
800fe6a: 46bd mov sp, r7
800fe6c: f85d 7b04 ldr.w r7, [sp], #4
800fe70: 4770 bx lr
0800fe72 <netif_null_output_ip4>:
#if LWIP_IPV4
/** Dummy IPv4 output function for netifs not supporting IPv4
*/
static err_t
netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr)
{
800fe72: b480 push {r7}
800fe74: b085 sub sp, #20
800fe76: af00 add r7, sp, #0
800fe78: 60f8 str r0, [r7, #12]
800fe7a: 60b9 str r1, [r7, #8]
800fe7c: 607a str r2, [r7, #4]
LWIP_UNUSED_ARG(netif);
LWIP_UNUSED_ARG(p);
LWIP_UNUSED_ARG(ipaddr);
return ERR_IF;
800fe7e: f06f 030b mvn.w r3, #11
}
800fe82: 4618 mov r0, r3
800fe84: 3714 adds r7, #20
800fe86: 46bd mov sp, r7
800fe88: f85d 7b04 ldr.w r7, [sp], #4
800fe8c: 4770 bx lr
...
0800fe90 <netif_get_by_index>:
*
* @param idx index of netif to find
*/
struct netif *
netif_get_by_index(u8_t idx)
{
800fe90: b480 push {r7}
800fe92: b085 sub sp, #20
800fe94: af00 add r7, sp, #0
800fe96: 4603 mov r3, r0
800fe98: 71fb strb r3, [r7, #7]
struct netif *netif;
LWIP_ASSERT_CORE_LOCKED();
if (idx != NETIF_NO_INDEX) {
800fe9a: 79fb ldrb r3, [r7, #7]
800fe9c: 2b00 cmp r3, #0
800fe9e: d013 beq.n 800fec8 <netif_get_by_index+0x38>
NETIF_FOREACH(netif) {
800fea0: 4b0d ldr r3, [pc, #52] ; (800fed8 <netif_get_by_index+0x48>)
800fea2: 681b ldr r3, [r3, #0]
800fea4: 60fb str r3, [r7, #12]
800fea6: e00c b.n 800fec2 <netif_get_by_index+0x32>
if (idx == netif_get_index(netif)) {
800fea8: 68fb ldr r3, [r7, #12]
800feaa: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800feae: 3301 adds r3, #1
800feb0: b2db uxtb r3, r3
800feb2: 79fa ldrb r2, [r7, #7]
800feb4: 429a cmp r2, r3
800feb6: d101 bne.n 800febc <netif_get_by_index+0x2c>
return netif; /* found! */
800feb8: 68fb ldr r3, [r7, #12]
800feba: e006 b.n 800feca <netif_get_by_index+0x3a>
NETIF_FOREACH(netif) {
800febc: 68fb ldr r3, [r7, #12]
800febe: 681b ldr r3, [r3, #0]
800fec0: 60fb str r3, [r7, #12]
800fec2: 68fb ldr r3, [r7, #12]
800fec4: 2b00 cmp r3, #0
800fec6: d1ef bne.n 800fea8 <netif_get_by_index+0x18>
}
}
}
return NULL;
800fec8: 2300 movs r3, #0
}
800feca: 4618 mov r0, r3
800fecc: 3714 adds r7, #20
800fece: 46bd mov sp, r7
800fed0: f85d 7b04 ldr.w r7, [sp], #4
800fed4: 4770 bx lr
800fed6: bf00 nop
800fed8: 2000f82c .word 0x2000f82c
0800fedc <pbuf_free_ooseq>:
#if !NO_SYS
static
#endif /* !NO_SYS */
void
pbuf_free_ooseq(void)
{
800fedc: b580 push {r7, lr}
800fede: b082 sub sp, #8
800fee0: af00 add r7, sp, #0
struct tcp_pcb *pcb;
SYS_ARCH_SET(pbuf_free_ooseq_pending, 0);
800fee2: f00b f809 bl 801aef8 <sys_arch_protect>
800fee6: 6038 str r0, [r7, #0]
800fee8: 4b0d ldr r3, [pc, #52] ; (800ff20 <pbuf_free_ooseq+0x44>)
800feea: 2200 movs r2, #0
800feec: 701a strb r2, [r3, #0]
800feee: 6838 ldr r0, [r7, #0]
800fef0: f00b f810 bl 801af14 <sys_arch_unprotect>
for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
800fef4: 4b0b ldr r3, [pc, #44] ; (800ff24 <pbuf_free_ooseq+0x48>)
800fef6: 681b ldr r3, [r3, #0]
800fef8: 607b str r3, [r7, #4]
800fefa: e00a b.n 800ff12 <pbuf_free_ooseq+0x36>
if (pcb->ooseq != NULL) {
800fefc: 687b ldr r3, [r7, #4]
800fefe: 6f5b ldr r3, [r3, #116] ; 0x74
800ff00: 2b00 cmp r3, #0
800ff02: d003 beq.n 800ff0c <pbuf_free_ooseq+0x30>
/** Free the ooseq pbufs of one PCB only */
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n"));
tcp_free_ooseq(pcb);
800ff04: 6878 ldr r0, [r7, #4]
800ff06: f002 f981 bl 801220c <tcp_free_ooseq>
return;
800ff0a: e005 b.n 800ff18 <pbuf_free_ooseq+0x3c>
for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
800ff0c: 687b ldr r3, [r7, #4]
800ff0e: 68db ldr r3, [r3, #12]
800ff10: 607b str r3, [r7, #4]
800ff12: 687b ldr r3, [r7, #4]
800ff14: 2b00 cmp r3, #0
800ff16: d1f1 bne.n 800fefc <pbuf_free_ooseq+0x20>
}
}
}
800ff18: 3708 adds r7, #8
800ff1a: 46bd mov sp, r7
800ff1c: bd80 pop {r7, pc}
800ff1e: bf00 nop
800ff20: 2000f834 .word 0x2000f834
800ff24: 2000f83c .word 0x2000f83c
0800ff28 <pbuf_free_ooseq_callback>:
/**
* Just a callback function for tcpip_callback() that calls pbuf_free_ooseq().
*/
static void
pbuf_free_ooseq_callback(void *arg)
{
800ff28: b580 push {r7, lr}
800ff2a: b082 sub sp, #8
800ff2c: af00 add r7, sp, #0
800ff2e: 6078 str r0, [r7, #4]
LWIP_UNUSED_ARG(arg);
pbuf_free_ooseq();
800ff30: f7ff ffd4 bl 800fedc <pbuf_free_ooseq>
}
800ff34: bf00 nop
800ff36: 3708 adds r7, #8
800ff38: 46bd mov sp, r7
800ff3a: bd80 pop {r7, pc}
0800ff3c <pbuf_pool_is_empty>:
#endif /* !NO_SYS */
/** Queue a call to pbuf_free_ooseq if not already queued. */
static void
pbuf_pool_is_empty(void)
{
800ff3c: b580 push {r7, lr}
800ff3e: b082 sub sp, #8
800ff40: af00 add r7, sp, #0
#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL
SYS_ARCH_SET(pbuf_free_ooseq_pending, 1);
#else /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
u8_t queued;
SYS_ARCH_DECL_PROTECT(old_level);
SYS_ARCH_PROTECT(old_level);
800ff42: f00a ffd9 bl 801aef8 <sys_arch_protect>
800ff46: 6078 str r0, [r7, #4]
queued = pbuf_free_ooseq_pending;
800ff48: 4b0f ldr r3, [pc, #60] ; (800ff88 <pbuf_pool_is_empty+0x4c>)
800ff4a: 781b ldrb r3, [r3, #0]
800ff4c: 70fb strb r3, [r7, #3]
pbuf_free_ooseq_pending = 1;
800ff4e: 4b0e ldr r3, [pc, #56] ; (800ff88 <pbuf_pool_is_empty+0x4c>)
800ff50: 2201 movs r2, #1
800ff52: 701a strb r2, [r3, #0]
SYS_ARCH_UNPROTECT(old_level);
800ff54: 6878 ldr r0, [r7, #4]
800ff56: f00a ffdd bl 801af14 <sys_arch_unprotect>
if (!queued) {
800ff5a: 78fb ldrb r3, [r7, #3]
800ff5c: 2b00 cmp r3, #0
800ff5e: d10f bne.n 800ff80 <pbuf_pool_is_empty+0x44>
/* queue a call to pbuf_free_ooseq if not already queued */
PBUF_POOL_FREE_OOSEQ_QUEUE_CALL();
800ff60: 2100 movs r1, #0
800ff62: 480a ldr r0, [pc, #40] ; (800ff8c <pbuf_pool_is_empty+0x50>)
800ff64: f7fe fee0 bl 800ed28 <tcpip_try_callback>
800ff68: 4603 mov r3, r0
800ff6a: 2b00 cmp r3, #0
800ff6c: d008 beq.n 800ff80 <pbuf_pool_is_empty+0x44>
800ff6e: f00a ffc3 bl 801aef8 <sys_arch_protect>
800ff72: 6078 str r0, [r7, #4]
800ff74: 4b04 ldr r3, [pc, #16] ; (800ff88 <pbuf_pool_is_empty+0x4c>)
800ff76: 2200 movs r2, #0
800ff78: 701a strb r2, [r3, #0]
800ff7a: 6878 ldr r0, [r7, #4]
800ff7c: f00a ffca bl 801af14 <sys_arch_unprotect>
}
#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
}
800ff80: bf00 nop
800ff82: 3708 adds r7, #8
800ff84: 46bd mov sp, r7
800ff86: bd80 pop {r7, pc}
800ff88: 2000f834 .word 0x2000f834
800ff8c: 0800ff29 .word 0x0800ff29
0800ff90 <pbuf_init_alloced_pbuf>:
#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */
/* Initialize members of struct pbuf after allocation */
static void
pbuf_init_alloced_pbuf(struct pbuf *p, void *payload, u16_t tot_len, u16_t len, pbuf_type type, u8_t flags)
{
800ff90: b480 push {r7}
800ff92: b085 sub sp, #20
800ff94: af00 add r7, sp, #0
800ff96: 60f8 str r0, [r7, #12]
800ff98: 60b9 str r1, [r7, #8]
800ff9a: 4611 mov r1, r2
800ff9c: 461a mov r2, r3
800ff9e: 460b mov r3, r1
800ffa0: 80fb strh r3, [r7, #6]
800ffa2: 4613 mov r3, r2
800ffa4: 80bb strh r3, [r7, #4]
p->next = NULL;
800ffa6: 68fb ldr r3, [r7, #12]
800ffa8: 2200 movs r2, #0
800ffaa: 601a str r2, [r3, #0]
p->payload = payload;
800ffac: 68fb ldr r3, [r7, #12]
800ffae: 68ba ldr r2, [r7, #8]
800ffb0: 605a str r2, [r3, #4]
p->tot_len = tot_len;
800ffb2: 68fb ldr r3, [r7, #12]
800ffb4: 88fa ldrh r2, [r7, #6]
800ffb6: 811a strh r2, [r3, #8]
p->len = len;
800ffb8: 68fb ldr r3, [r7, #12]
800ffba: 88ba ldrh r2, [r7, #4]
800ffbc: 815a strh r2, [r3, #10]
p->type_internal = (u8_t)type;
800ffbe: 8b3b ldrh r3, [r7, #24]
800ffc0: b2da uxtb r2, r3
800ffc2: 68fb ldr r3, [r7, #12]
800ffc4: 731a strb r2, [r3, #12]
p->flags = flags;
800ffc6: 68fb ldr r3, [r7, #12]
800ffc8: 7f3a ldrb r2, [r7, #28]
800ffca: 735a strb r2, [r3, #13]
p->ref = 1;
800ffcc: 68fb ldr r3, [r7, #12]
800ffce: 2201 movs r2, #1
800ffd0: 739a strb r2, [r3, #14]
p->if_idx = NETIF_NO_INDEX;
800ffd2: 68fb ldr r3, [r7, #12]
800ffd4: 2200 movs r2, #0
800ffd6: 73da strb r2, [r3, #15]
}
800ffd8: bf00 nop
800ffda: 3714 adds r7, #20
800ffdc: 46bd mov sp, r7
800ffde: f85d 7b04 ldr.w r7, [sp], #4
800ffe2: 4770 bx lr
0800ffe4 <pbuf_alloc>:
* @return the allocated pbuf. If multiple pbufs where allocated, this
* is the first pbuf of a pbuf chain.
*/
struct pbuf *
pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type)
{
800ffe4: b580 push {r7, lr}
800ffe6: b08c sub sp, #48 ; 0x30
800ffe8: af02 add r7, sp, #8
800ffea: 4603 mov r3, r0
800ffec: 71fb strb r3, [r7, #7]
800ffee: 460b mov r3, r1
800fff0: 80bb strh r3, [r7, #4]
800fff2: 4613 mov r3, r2
800fff4: 807b strh r3, [r7, #2]
struct pbuf *p;
u16_t offset = (u16_t)layer;
800fff6: 79fb ldrb r3, [r7, #7]
800fff8: 847b strh r3, [r7, #34] ; 0x22
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length));
switch (type) {
800fffa: 887b ldrh r3, [r7, #2]
800fffc: f5b3 7f20 cmp.w r3, #640 ; 0x280
8010000: d07f beq.n 8010102 <pbuf_alloc+0x11e>
8010002: f5b3 7f20 cmp.w r3, #640 ; 0x280
8010006: f300 80c8 bgt.w 801019a <pbuf_alloc+0x1b6>
801000a: f5b3 7fc1 cmp.w r3, #386 ; 0x182
801000e: d010 beq.n 8010032 <pbuf_alloc+0x4e>
8010010: f5b3 7fc1 cmp.w r3, #386 ; 0x182
8010014: f300 80c1 bgt.w 801019a <pbuf_alloc+0x1b6>
8010018: 2b01 cmp r3, #1
801001a: d002 beq.n 8010022 <pbuf_alloc+0x3e>
801001c: 2b41 cmp r3, #65 ; 0x41
801001e: f040 80bc bne.w 801019a <pbuf_alloc+0x1b6>
case PBUF_REF: /* fall through */
case PBUF_ROM:
p = pbuf_alloc_reference(NULL, length, type);
8010022: 887a ldrh r2, [r7, #2]
8010024: 88bb ldrh r3, [r7, #4]
8010026: 4619 mov r1, r3
8010028: 2000 movs r0, #0
801002a: f000 f8d1 bl 80101d0 <pbuf_alloc_reference>
801002e: 6278 str r0, [r7, #36] ; 0x24
break;
8010030: e0bd b.n 80101ae <pbuf_alloc+0x1ca>
case PBUF_POOL: {
struct pbuf *q, *last;
u16_t rem_len; /* remaining length */
p = NULL;
8010032: 2300 movs r3, #0
8010034: 627b str r3, [r7, #36] ; 0x24
last = NULL;
8010036: 2300 movs r3, #0
8010038: 61fb str r3, [r7, #28]
rem_len = length;
801003a: 88bb ldrh r3, [r7, #4]
801003c: 837b strh r3, [r7, #26]
do {
u16_t qlen;
q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL);
801003e: 200c movs r0, #12
8010040: f7ff fbb2 bl 800f7a8 <memp_malloc>
8010044: 6138 str r0, [r7, #16]
if (q == NULL) {
8010046: 693b ldr r3, [r7, #16]
8010048: 2b00 cmp r3, #0
801004a: d109 bne.n 8010060 <pbuf_alloc+0x7c>
PBUF_POOL_IS_EMPTY();
801004c: f7ff ff76 bl 800ff3c <pbuf_pool_is_empty>
/* free chain so far allocated */
if (p) {
8010050: 6a7b ldr r3, [r7, #36] ; 0x24
8010052: 2b00 cmp r3, #0
8010054: d002 beq.n 801005c <pbuf_alloc+0x78>
pbuf_free(p);
8010056: 6a78 ldr r0, [r7, #36] ; 0x24
8010058: f000 faa8 bl 80105ac <pbuf_free>
}
/* bail out unsuccessfully */
return NULL;
801005c: 2300 movs r3, #0
801005e: e0a7 b.n 80101b0 <pbuf_alloc+0x1cc>
}
qlen = LWIP_MIN(rem_len, (u16_t)(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)));
8010060: 8c7b ldrh r3, [r7, #34] ; 0x22
8010062: 3303 adds r3, #3
8010064: b29b uxth r3, r3
8010066: f023 0303 bic.w r3, r3, #3
801006a: b29b uxth r3, r3
801006c: f5c3 7314 rsb r3, r3, #592 ; 0x250
8010070: b29b uxth r3, r3
8010072: 8b7a ldrh r2, [r7, #26]
8010074: 4293 cmp r3, r2
8010076: bf28 it cs
8010078: 4613 movcs r3, r2
801007a: 81fb strh r3, [r7, #14]
pbuf_init_alloced_pbuf(q, LWIP_MEM_ALIGN((void *)((u8_t *)q + SIZEOF_STRUCT_PBUF + offset)),
801007c: 8c7b ldrh r3, [r7, #34] ; 0x22
801007e: 3310 adds r3, #16
8010080: 693a ldr r2, [r7, #16]
8010082: 4413 add r3, r2
8010084: 3303 adds r3, #3
8010086: f023 0303 bic.w r3, r3, #3
801008a: 4618 mov r0, r3
801008c: 89f9 ldrh r1, [r7, #14]
801008e: 8b7a ldrh r2, [r7, #26]
8010090: 2300 movs r3, #0
8010092: 9301 str r3, [sp, #4]
8010094: 887b ldrh r3, [r7, #2]
8010096: 9300 str r3, [sp, #0]
8010098: 460b mov r3, r1
801009a: 4601 mov r1, r0
801009c: 6938 ldr r0, [r7, #16]
801009e: f7ff ff77 bl 800ff90 <pbuf_init_alloced_pbuf>
rem_len, qlen, type, 0);
LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
80100a2: 693b ldr r3, [r7, #16]
80100a4: 685b ldr r3, [r3, #4]
80100a6: f003 0303 and.w r3, r3, #3
80100aa: 2b00 cmp r3, #0
80100ac: d006 beq.n 80100bc <pbuf_alloc+0xd8>
80100ae: 4b42 ldr r3, [pc, #264] ; (80101b8 <pbuf_alloc+0x1d4>)
80100b0: f44f 7280 mov.w r2, #256 ; 0x100
80100b4: 4941 ldr r1, [pc, #260] ; (80101bc <pbuf_alloc+0x1d8>)
80100b6: 4842 ldr r0, [pc, #264] ; (80101c0 <pbuf_alloc+0x1dc>)
80100b8: f00a ff84 bl 801afc4 <iprintf>
((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT",
80100bc: 8c7b ldrh r3, [r7, #34] ; 0x22
80100be: 3303 adds r3, #3
80100c0: f023 0303 bic.w r3, r3, #3
80100c4: f5b3 7f14 cmp.w r3, #592 ; 0x250
80100c8: d106 bne.n 80100d8 <pbuf_alloc+0xf4>
80100ca: 4b3b ldr r3, [pc, #236] ; (80101b8 <pbuf_alloc+0x1d4>)
80100cc: f44f 7281 mov.w r2, #258 ; 0x102
80100d0: 493c ldr r1, [pc, #240] ; (80101c4 <pbuf_alloc+0x1e0>)
80100d2: 483b ldr r0, [pc, #236] ; (80101c0 <pbuf_alloc+0x1dc>)
80100d4: f00a ff76 bl 801afc4 <iprintf>
(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 );
if (p == NULL) {
80100d8: 6a7b ldr r3, [r7, #36] ; 0x24
80100da: 2b00 cmp r3, #0
80100dc: d102 bne.n 80100e4 <pbuf_alloc+0x100>
/* allocated head of pbuf chain (into p) */
p = q;
80100de: 693b ldr r3, [r7, #16]
80100e0: 627b str r3, [r7, #36] ; 0x24
80100e2: e002 b.n 80100ea <pbuf_alloc+0x106>
} else {
/* make previous pbuf point to this pbuf */
last->next = q;
80100e4: 69fb ldr r3, [r7, #28]
80100e6: 693a ldr r2, [r7, #16]
80100e8: 601a str r2, [r3, #0]
}
last = q;
80100ea: 693b ldr r3, [r7, #16]
80100ec: 61fb str r3, [r7, #28]
rem_len = (u16_t)(rem_len - qlen);
80100ee: 8b7a ldrh r2, [r7, #26]
80100f0: 89fb ldrh r3, [r7, #14]
80100f2: 1ad3 subs r3, r2, r3
80100f4: 837b strh r3, [r7, #26]
offset = 0;
80100f6: 2300 movs r3, #0
80100f8: 847b strh r3, [r7, #34] ; 0x22
} while (rem_len > 0);
80100fa: 8b7b ldrh r3, [r7, #26]
80100fc: 2b00 cmp r3, #0
80100fe: d19e bne.n 801003e <pbuf_alloc+0x5a>
break;
8010100: e055 b.n 80101ae <pbuf_alloc+0x1ca>
}
case PBUF_RAM: {
u16_t payload_len = (u16_t)(LWIP_MEM_ALIGN_SIZE(offset) + LWIP_MEM_ALIGN_SIZE(length));
8010102: 8c7b ldrh r3, [r7, #34] ; 0x22
8010104: 3303 adds r3, #3
8010106: b29b uxth r3, r3
8010108: f023 0303 bic.w r3, r3, #3
801010c: b29a uxth r2, r3
801010e: 88bb ldrh r3, [r7, #4]
8010110: 3303 adds r3, #3
8010112: b29b uxth r3, r3
8010114: f023 0303 bic.w r3, r3, #3
8010118: b29b uxth r3, r3
801011a: 4413 add r3, r2
801011c: 833b strh r3, [r7, #24]
mem_size_t alloc_len = (mem_size_t)(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF) + payload_len);
801011e: 8b3b ldrh r3, [r7, #24]
8010120: 3310 adds r3, #16
8010122: 82fb strh r3, [r7, #22]
/* bug #50040: Check for integer overflow when calculating alloc_len */
if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
8010124: 8b3a ldrh r2, [r7, #24]
8010126: 88bb ldrh r3, [r7, #4]
8010128: 3303 adds r3, #3
801012a: f023 0303 bic.w r3, r3, #3
801012e: 429a cmp r2, r3
8010130: d306 bcc.n 8010140 <pbuf_alloc+0x15c>
(alloc_len < LWIP_MEM_ALIGN_SIZE(length))) {
8010132: 8afa ldrh r2, [r7, #22]
8010134: 88bb ldrh r3, [r7, #4]
8010136: 3303 adds r3, #3
8010138: f023 0303 bic.w r3, r3, #3
if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
801013c: 429a cmp r2, r3
801013e: d201 bcs.n 8010144 <pbuf_alloc+0x160>
return NULL;
8010140: 2300 movs r3, #0
8010142: e035 b.n 80101b0 <pbuf_alloc+0x1cc>
}
/* If pbuf is to be allocated in RAM, allocate memory for it. */
p = (struct pbuf *)mem_malloc(alloc_len);
8010144: 8afb ldrh r3, [r7, #22]
8010146: 4618 mov r0, r3
8010148: f7ff f9ac bl 800f4a4 <mem_malloc>
801014c: 6278 str r0, [r7, #36] ; 0x24
if (p == NULL) {
801014e: 6a7b ldr r3, [r7, #36] ; 0x24
8010150: 2b00 cmp r3, #0
8010152: d101 bne.n 8010158 <pbuf_alloc+0x174>
return NULL;
8010154: 2300 movs r3, #0
8010156: e02b b.n 80101b0 <pbuf_alloc+0x1cc>
}
pbuf_init_alloced_pbuf(p, LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)),
8010158: 8c7b ldrh r3, [r7, #34] ; 0x22
801015a: 3310 adds r3, #16
801015c: 6a7a ldr r2, [r7, #36] ; 0x24
801015e: 4413 add r3, r2
8010160: 3303 adds r3, #3
8010162: f023 0303 bic.w r3, r3, #3
8010166: 4618 mov r0, r3
8010168: 88b9 ldrh r1, [r7, #4]
801016a: 88ba ldrh r2, [r7, #4]
801016c: 2300 movs r3, #0
801016e: 9301 str r3, [sp, #4]
8010170: 887b ldrh r3, [r7, #2]
8010172: 9300 str r3, [sp, #0]
8010174: 460b mov r3, r1
8010176: 4601 mov r1, r0
8010178: 6a78 ldr r0, [r7, #36] ; 0x24
801017a: f7ff ff09 bl 800ff90 <pbuf_init_alloced_pbuf>
length, length, type, 0);
LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
801017e: 6a7b ldr r3, [r7, #36] ; 0x24
8010180: 685b ldr r3, [r3, #4]
8010182: f003 0303 and.w r3, r3, #3
8010186: 2b00 cmp r3, #0
8010188: d010 beq.n 80101ac <pbuf_alloc+0x1c8>
801018a: 4b0b ldr r3, [pc, #44] ; (80101b8 <pbuf_alloc+0x1d4>)
801018c: f44f 7291 mov.w r2, #290 ; 0x122
8010190: 490d ldr r1, [pc, #52] ; (80101c8 <pbuf_alloc+0x1e4>)
8010192: 480b ldr r0, [pc, #44] ; (80101c0 <pbuf_alloc+0x1dc>)
8010194: f00a ff16 bl 801afc4 <iprintf>
((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
break;
8010198: e008 b.n 80101ac <pbuf_alloc+0x1c8>
}
default:
LWIP_ASSERT("pbuf_alloc: erroneous type", 0);
801019a: 4b07 ldr r3, [pc, #28] ; (80101b8 <pbuf_alloc+0x1d4>)
801019c: f240 1227 movw r2, #295 ; 0x127
80101a0: 490a ldr r1, [pc, #40] ; (80101cc <pbuf_alloc+0x1e8>)
80101a2: 4807 ldr r0, [pc, #28] ; (80101c0 <pbuf_alloc+0x1dc>)
80101a4: f00a ff0e bl 801afc4 <iprintf>
return NULL;
80101a8: 2300 movs r3, #0
80101aa: e001 b.n 80101b0 <pbuf_alloc+0x1cc>
break;
80101ac: bf00 nop
}
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
return p;
80101ae: 6a7b ldr r3, [r7, #36] ; 0x24
}
80101b0: 4618 mov r0, r3
80101b2: 3728 adds r7, #40 ; 0x28
80101b4: 46bd mov sp, r7
80101b6: bd80 pop {r7, pc}
80101b8: 0801c81c .word 0x0801c81c
80101bc: 0801c84c .word 0x0801c84c
80101c0: 0801c87c .word 0x0801c87c
80101c4: 0801c8a4 .word 0x0801c8a4
80101c8: 0801c8d8 .word 0x0801c8d8
80101cc: 0801c904 .word 0x0801c904
080101d0 <pbuf_alloc_reference>:
*
* @return the allocated pbuf.
*/
struct pbuf *
pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type)
{
80101d0: b580 push {r7, lr}
80101d2: b086 sub sp, #24
80101d4: af02 add r7, sp, #8
80101d6: 6078 str r0, [r7, #4]
80101d8: 460b mov r3, r1
80101da: 807b strh r3, [r7, #2]
80101dc: 4613 mov r3, r2
80101de: 803b strh r3, [r7, #0]
struct pbuf *p;
LWIP_ASSERT("invalid pbuf_type", (type == PBUF_REF) || (type == PBUF_ROM));
80101e0: 883b ldrh r3, [r7, #0]
80101e2: 2b41 cmp r3, #65 ; 0x41
80101e4: d009 beq.n 80101fa <pbuf_alloc_reference+0x2a>
80101e6: 883b ldrh r3, [r7, #0]
80101e8: 2b01 cmp r3, #1
80101ea: d006 beq.n 80101fa <pbuf_alloc_reference+0x2a>
80101ec: 4b0f ldr r3, [pc, #60] ; (801022c <pbuf_alloc_reference+0x5c>)
80101ee: f44f 72a5 mov.w r2, #330 ; 0x14a
80101f2: 490f ldr r1, [pc, #60] ; (8010230 <pbuf_alloc_reference+0x60>)
80101f4: 480f ldr r0, [pc, #60] ; (8010234 <pbuf_alloc_reference+0x64>)
80101f6: f00a fee5 bl 801afc4 <iprintf>
/* only allocate memory for the pbuf structure */
p = (struct pbuf *)memp_malloc(MEMP_PBUF);
80101fa: 200b movs r0, #11
80101fc: f7ff fad4 bl 800f7a8 <memp_malloc>
8010200: 60f8 str r0, [r7, #12]
if (p == NULL) {
8010202: 68fb ldr r3, [r7, #12]
8010204: 2b00 cmp r3, #0
8010206: d101 bne.n 801020c <pbuf_alloc_reference+0x3c>
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
("pbuf_alloc_reference: Could not allocate MEMP_PBUF for PBUF_%s.\n",
(type == PBUF_ROM) ? "ROM" : "REF"));
return NULL;
8010208: 2300 movs r3, #0
801020a: e00b b.n 8010224 <pbuf_alloc_reference+0x54>
}
pbuf_init_alloced_pbuf(p, payload, length, length, type, 0);
801020c: 8879 ldrh r1, [r7, #2]
801020e: 887a ldrh r2, [r7, #2]
8010210: 2300 movs r3, #0
8010212: 9301 str r3, [sp, #4]
8010214: 883b ldrh r3, [r7, #0]
8010216: 9300 str r3, [sp, #0]
8010218: 460b mov r3, r1
801021a: 6879 ldr r1, [r7, #4]
801021c: 68f8 ldr r0, [r7, #12]
801021e: f7ff feb7 bl 800ff90 <pbuf_init_alloced_pbuf>
return p;
8010222: 68fb ldr r3, [r7, #12]
}
8010224: 4618 mov r0, r3
8010226: 3710 adds r7, #16
8010228: 46bd mov sp, r7
801022a: bd80 pop {r7, pc}
801022c: 0801c81c .word 0x0801c81c
8010230: 0801c920 .word 0x0801c920
8010234: 0801c87c .word 0x0801c87c
08010238 <pbuf_alloced_custom>:
* big enough to hold 'length' plus the header size
*/
struct pbuf *
pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p,
void *payload_mem, u16_t payload_mem_len)
{
8010238: b580 push {r7, lr}
801023a: b088 sub sp, #32
801023c: af02 add r7, sp, #8
801023e: 607b str r3, [r7, #4]
8010240: 4603 mov r3, r0
8010242: 73fb strb r3, [r7, #15]
8010244: 460b mov r3, r1
8010246: 81bb strh r3, [r7, #12]
8010248: 4613 mov r3, r2
801024a: 817b strh r3, [r7, #10]
u16_t offset = (u16_t)l;
801024c: 7bfb ldrb r3, [r7, #15]
801024e: 827b strh r3, [r7, #18]
void *payload;
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length));
if (LWIP_MEM_ALIGN_SIZE(offset) + length > payload_mem_len) {
8010250: 8a7b ldrh r3, [r7, #18]
8010252: 3303 adds r3, #3
8010254: f023 0203 bic.w r2, r3, #3
8010258: 89bb ldrh r3, [r7, #12]
801025a: 441a add r2, r3
801025c: 8cbb ldrh r3, [r7, #36] ; 0x24
801025e: 429a cmp r2, r3
8010260: d901 bls.n 8010266 <pbuf_alloced_custom+0x2e>
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length));
return NULL;
8010262: 2300 movs r3, #0
8010264: e018 b.n 8010298 <pbuf_alloced_custom+0x60>
}
if (payload_mem != NULL) {
8010266: 6a3b ldr r3, [r7, #32]
8010268: 2b00 cmp r3, #0
801026a: d007 beq.n 801027c <pbuf_alloced_custom+0x44>
payload = (u8_t *)payload_mem + LWIP_MEM_ALIGN_SIZE(offset);
801026c: 8a7b ldrh r3, [r7, #18]
801026e: 3303 adds r3, #3
8010270: f023 0303 bic.w r3, r3, #3
8010274: 6a3a ldr r2, [r7, #32]
8010276: 4413 add r3, r2
8010278: 617b str r3, [r7, #20]
801027a: e001 b.n 8010280 <pbuf_alloced_custom+0x48>
} else {
payload = NULL;
801027c: 2300 movs r3, #0
801027e: 617b str r3, [r7, #20]
}
pbuf_init_alloced_pbuf(&p->pbuf, payload, length, length, type, PBUF_FLAG_IS_CUSTOM);
8010280: 6878 ldr r0, [r7, #4]
8010282: 89b9 ldrh r1, [r7, #12]
8010284: 89ba ldrh r2, [r7, #12]
8010286: 2302 movs r3, #2
8010288: 9301 str r3, [sp, #4]
801028a: 897b ldrh r3, [r7, #10]
801028c: 9300 str r3, [sp, #0]
801028e: 460b mov r3, r1
8010290: 6979 ldr r1, [r7, #20]
8010292: f7ff fe7d bl 800ff90 <pbuf_init_alloced_pbuf>
return &p->pbuf;
8010296: 687b ldr r3, [r7, #4]
}
8010298: 4618 mov r0, r3
801029a: 3718 adds r7, #24
801029c: 46bd mov sp, r7
801029e: bd80 pop {r7, pc}
080102a0 <pbuf_realloc>:
*
* @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain).
*/
void
pbuf_realloc(struct pbuf *p, u16_t new_len)
{
80102a0: b580 push {r7, lr}
80102a2: b084 sub sp, #16
80102a4: af00 add r7, sp, #0
80102a6: 6078 str r0, [r7, #4]
80102a8: 460b mov r3, r1
80102aa: 807b strh r3, [r7, #2]
struct pbuf *q;
u16_t rem_len; /* remaining length */
u16_t shrink;
LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL);
80102ac: 687b ldr r3, [r7, #4]
80102ae: 2b00 cmp r3, #0
80102b0: d106 bne.n 80102c0 <pbuf_realloc+0x20>
80102b2: 4b3a ldr r3, [pc, #232] ; (801039c <pbuf_realloc+0xfc>)
80102b4: f44f 72cc mov.w r2, #408 ; 0x198
80102b8: 4939 ldr r1, [pc, #228] ; (80103a0 <pbuf_realloc+0x100>)
80102ba: 483a ldr r0, [pc, #232] ; (80103a4 <pbuf_realloc+0x104>)
80102bc: f00a fe82 bl 801afc4 <iprintf>
/* desired length larger than current length? */
if (new_len >= p->tot_len) {
80102c0: 687b ldr r3, [r7, #4]
80102c2: 891b ldrh r3, [r3, #8]
80102c4: 887a ldrh r2, [r7, #2]
80102c6: 429a cmp r2, r3
80102c8: d263 bcs.n 8010392 <pbuf_realloc+0xf2>
return;
}
/* the pbuf chain grows by (new_len - p->tot_len) bytes
* (which may be negative in case of shrinking) */
shrink = (u16_t)(p->tot_len - new_len);
80102ca: 687b ldr r3, [r7, #4]
80102cc: 891a ldrh r2, [r3, #8]
80102ce: 887b ldrh r3, [r7, #2]
80102d0: 1ad3 subs r3, r2, r3
80102d2: 813b strh r3, [r7, #8]
/* first, step over any pbufs that should remain in the chain */
rem_len = new_len;
80102d4: 887b ldrh r3, [r7, #2]
80102d6: 817b strh r3, [r7, #10]
q = p;
80102d8: 687b ldr r3, [r7, #4]
80102da: 60fb str r3, [r7, #12]
/* should this pbuf be kept? */
while (rem_len > q->len) {
80102dc: e018 b.n 8010310 <pbuf_realloc+0x70>
/* decrease remaining length by pbuf length */
rem_len = (u16_t)(rem_len - q->len);
80102de: 68fb ldr r3, [r7, #12]
80102e0: 895b ldrh r3, [r3, #10]
80102e2: 897a ldrh r2, [r7, #10]
80102e4: 1ad3 subs r3, r2, r3
80102e6: 817b strh r3, [r7, #10]
/* decrease total length indicator */
q->tot_len = (u16_t)(q->tot_len - shrink);
80102e8: 68fb ldr r3, [r7, #12]
80102ea: 891a ldrh r2, [r3, #8]
80102ec: 893b ldrh r3, [r7, #8]
80102ee: 1ad3 subs r3, r2, r3
80102f0: b29a uxth r2, r3
80102f2: 68fb ldr r3, [r7, #12]
80102f4: 811a strh r2, [r3, #8]
/* proceed to next pbuf in chain */
q = q->next;
80102f6: 68fb ldr r3, [r7, #12]
80102f8: 681b ldr r3, [r3, #0]
80102fa: 60fb str r3, [r7, #12]
LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL);
80102fc: 68fb ldr r3, [r7, #12]
80102fe: 2b00 cmp r3, #0
8010300: d106 bne.n 8010310 <pbuf_realloc+0x70>
8010302: 4b26 ldr r3, [pc, #152] ; (801039c <pbuf_realloc+0xfc>)
8010304: f240 12af movw r2, #431 ; 0x1af
8010308: 4927 ldr r1, [pc, #156] ; (80103a8 <pbuf_realloc+0x108>)
801030a: 4826 ldr r0, [pc, #152] ; (80103a4 <pbuf_realloc+0x104>)
801030c: f00a fe5a bl 801afc4 <iprintf>
while (rem_len > q->len) {
8010310: 68fb ldr r3, [r7, #12]
8010312: 895b ldrh r3, [r3, #10]
8010314: 897a ldrh r2, [r7, #10]
8010316: 429a cmp r2, r3
8010318: d8e1 bhi.n 80102de <pbuf_realloc+0x3e>
/* we have now reached the new last pbuf (in q) */
/* rem_len == desired length for pbuf q */
/* shrink allocated memory for PBUF_RAM */
/* (other types merely adjust their length fields */
if (pbuf_match_allocsrc(q, PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) && (rem_len != q->len)
801031a: 68fb ldr r3, [r7, #12]
801031c: 7b1b ldrb r3, [r3, #12]
801031e: f003 030f and.w r3, r3, #15
8010322: 2b00 cmp r3, #0
8010324: d121 bne.n 801036a <pbuf_realloc+0xca>
8010326: 68fb ldr r3, [r7, #12]
8010328: 895b ldrh r3, [r3, #10]
801032a: 897a ldrh r2, [r7, #10]
801032c: 429a cmp r2, r3
801032e: d01c beq.n 801036a <pbuf_realloc+0xca>
#if LWIP_SUPPORT_CUSTOM_PBUF
&& ((q->flags & PBUF_FLAG_IS_CUSTOM) == 0)
8010330: 68fb ldr r3, [r7, #12]
8010332: 7b5b ldrb r3, [r3, #13]
8010334: f003 0302 and.w r3, r3, #2
8010338: 2b00 cmp r3, #0
801033a: d116 bne.n 801036a <pbuf_realloc+0xca>
#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
) {
/* reallocate and adjust the length of the pbuf that will be split */
q = (struct pbuf *)mem_trim(q, (mem_size_t)(((u8_t *)q->payload - (u8_t *)q) + rem_len));
801033c: 68fb ldr r3, [r7, #12]
801033e: 685a ldr r2, [r3, #4]
8010340: 68fb ldr r3, [r7, #12]
8010342: 1ad3 subs r3, r2, r3
8010344: b29a uxth r2, r3
8010346: 897b ldrh r3, [r7, #10]
8010348: 4413 add r3, r2
801034a: b29b uxth r3, r3
801034c: 4619 mov r1, r3
801034e: 68f8 ldr r0, [r7, #12]
8010350: f7fe ff9e bl 800f290 <mem_trim>
8010354: 60f8 str r0, [r7, #12]
LWIP_ASSERT("mem_trim returned q == NULL", q != NULL);
8010356: 68fb ldr r3, [r7, #12]
8010358: 2b00 cmp r3, #0
801035a: d106 bne.n 801036a <pbuf_realloc+0xca>
801035c: 4b0f ldr r3, [pc, #60] ; (801039c <pbuf_realloc+0xfc>)
801035e: f240 12bd movw r2, #445 ; 0x1bd
8010362: 4912 ldr r1, [pc, #72] ; (80103ac <pbuf_realloc+0x10c>)
8010364: 480f ldr r0, [pc, #60] ; (80103a4 <pbuf_realloc+0x104>)
8010366: f00a fe2d bl 801afc4 <iprintf>
}
/* adjust length fields for new last pbuf */
q->len = rem_len;
801036a: 68fb ldr r3, [r7, #12]
801036c: 897a ldrh r2, [r7, #10]
801036e: 815a strh r2, [r3, #10]
q->tot_len = q->len;
8010370: 68fb ldr r3, [r7, #12]
8010372: 895a ldrh r2, [r3, #10]
8010374: 68fb ldr r3, [r7, #12]
8010376: 811a strh r2, [r3, #8]
/* any remaining pbufs in chain? */
if (q->next != NULL) {
8010378: 68fb ldr r3, [r7, #12]
801037a: 681b ldr r3, [r3, #0]
801037c: 2b00 cmp r3, #0
801037e: d004 beq.n 801038a <pbuf_realloc+0xea>
/* free remaining pbufs in chain */
pbuf_free(q->next);
8010380: 68fb ldr r3, [r7, #12]
8010382: 681b ldr r3, [r3, #0]
8010384: 4618 mov r0, r3
8010386: f000 f911 bl 80105ac <pbuf_free>
}
/* q is last packet in chain */
q->next = NULL;
801038a: 68fb ldr r3, [r7, #12]
801038c: 2200 movs r2, #0
801038e: 601a str r2, [r3, #0]
8010390: e000 b.n 8010394 <pbuf_realloc+0xf4>
return;
8010392: bf00 nop
}
8010394: 3710 adds r7, #16
8010396: 46bd mov sp, r7
8010398: bd80 pop {r7, pc}
801039a: bf00 nop
801039c: 0801c81c .word 0x0801c81c
80103a0: 0801c934 .word 0x0801c934
80103a4: 0801c87c .word 0x0801c87c
80103a8: 0801c94c .word 0x0801c94c
80103ac: 0801c964 .word 0x0801c964
080103b0 <pbuf_add_header_impl>:
* @return non-zero on failure, zero on success.
*
*/
static u8_t
pbuf_add_header_impl(struct pbuf *p, size_t header_size_increment, u8_t force)
{
80103b0: b580 push {r7, lr}
80103b2: b086 sub sp, #24
80103b4: af00 add r7, sp, #0
80103b6: 60f8 str r0, [r7, #12]
80103b8: 60b9 str r1, [r7, #8]
80103ba: 4613 mov r3, r2
80103bc: 71fb strb r3, [r7, #7]
u16_t type_internal;
void *payload;
u16_t increment_magnitude;
LWIP_ASSERT("p != NULL", p != NULL);
80103be: 68fb ldr r3, [r7, #12]
80103c0: 2b00 cmp r3, #0
80103c2: d106 bne.n 80103d2 <pbuf_add_header_impl+0x22>
80103c4: 4b2b ldr r3, [pc, #172] ; (8010474 <pbuf_add_header_impl+0xc4>)
80103c6: f240 12df movw r2, #479 ; 0x1df
80103ca: 492b ldr r1, [pc, #172] ; (8010478 <pbuf_add_header_impl+0xc8>)
80103cc: 482b ldr r0, [pc, #172] ; (801047c <pbuf_add_header_impl+0xcc>)
80103ce: f00a fdf9 bl 801afc4 <iprintf>
if ((p == NULL) || (header_size_increment > 0xFFFF)) {
80103d2: 68fb ldr r3, [r7, #12]
80103d4: 2b00 cmp r3, #0
80103d6: d003 beq.n 80103e0 <pbuf_add_header_impl+0x30>
80103d8: 68bb ldr r3, [r7, #8]
80103da: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80103de: d301 bcc.n 80103e4 <pbuf_add_header_impl+0x34>
return 1;
80103e0: 2301 movs r3, #1
80103e2: e043 b.n 801046c <pbuf_add_header_impl+0xbc>
}
if (header_size_increment == 0) {
80103e4: 68bb ldr r3, [r7, #8]
80103e6: 2b00 cmp r3, #0
80103e8: d101 bne.n 80103ee <pbuf_add_header_impl+0x3e>
return 0;
80103ea: 2300 movs r3, #0
80103ec: e03e b.n 801046c <pbuf_add_header_impl+0xbc>
}
increment_magnitude = (u16_t)header_size_increment;
80103ee: 68bb ldr r3, [r7, #8]
80103f0: 827b strh r3, [r7, #18]
/* Do not allow tot_len to wrap as a result. */
if ((u16_t)(increment_magnitude + p->tot_len) < increment_magnitude) {
80103f2: 68fb ldr r3, [r7, #12]
80103f4: 891a ldrh r2, [r3, #8]
80103f6: 8a7b ldrh r3, [r7, #18]
80103f8: 4413 add r3, r2
80103fa: b29b uxth r3, r3
80103fc: 8a7a ldrh r2, [r7, #18]
80103fe: 429a cmp r2, r3
8010400: d901 bls.n 8010406 <pbuf_add_header_impl+0x56>
return 1;
8010402: 2301 movs r3, #1
8010404: e032 b.n 801046c <pbuf_add_header_impl+0xbc>
}
type_internal = p->type_internal;
8010406: 68fb ldr r3, [r7, #12]
8010408: 7b1b ldrb r3, [r3, #12]
801040a: 823b strh r3, [r7, #16]
/* pbuf types containing payloads? */
if (type_internal & PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS) {
801040c: 8a3b ldrh r3, [r7, #16]
801040e: f003 0380 and.w r3, r3, #128 ; 0x80
8010412: 2b00 cmp r3, #0
8010414: d00c beq.n 8010430 <pbuf_add_header_impl+0x80>
/* set new payload pointer */
payload = (u8_t *)p->payload - header_size_increment;
8010416: 68fb ldr r3, [r7, #12]
8010418: 685a ldr r2, [r3, #4]
801041a: 68bb ldr r3, [r7, #8]
801041c: 425b negs r3, r3
801041e: 4413 add r3, r2
8010420: 617b str r3, [r7, #20]
/* boundary check fails? */
if ((u8_t *)payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) {
8010422: 68fb ldr r3, [r7, #12]
8010424: 3310 adds r3, #16
8010426: 697a ldr r2, [r7, #20]
8010428: 429a cmp r2, r3
801042a: d20d bcs.n 8010448 <pbuf_add_header_impl+0x98>
LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE,
("pbuf_add_header: failed as %p < %p (not enough space for new header size)\n",
(void *)payload, (void *)((u8_t *)p + SIZEOF_STRUCT_PBUF)));
/* bail out unsuccessfully */
return 1;
801042c: 2301 movs r3, #1
801042e: e01d b.n 801046c <pbuf_add_header_impl+0xbc>
}
/* pbuf types referring to external payloads? */
} else {
/* hide a header in the payload? */
if (force) {
8010430: 79fb ldrb r3, [r7, #7]
8010432: 2b00 cmp r3, #0
8010434: d006 beq.n 8010444 <pbuf_add_header_impl+0x94>
payload = (u8_t *)p->payload - header_size_increment;
8010436: 68fb ldr r3, [r7, #12]
8010438: 685a ldr r2, [r3, #4]
801043a: 68bb ldr r3, [r7, #8]
801043c: 425b negs r3, r3
801043e: 4413 add r3, r2
8010440: 617b str r3, [r7, #20]
8010442: e001 b.n 8010448 <pbuf_add_header_impl+0x98>
} else {
/* cannot expand payload to front (yet!)
* bail out unsuccessfully */
return 1;
8010444: 2301 movs r3, #1
8010446: e011 b.n 801046c <pbuf_add_header_impl+0xbc>
}
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_add_header: old %p new %p (%"U16_F")\n",
(void *)p->payload, (void *)payload, increment_magnitude));
/* modify pbuf fields */
p->payload = payload;
8010448: 68fb ldr r3, [r7, #12]
801044a: 697a ldr r2, [r7, #20]
801044c: 605a str r2, [r3, #4]
p->len = (u16_t)(p->len + increment_magnitude);
801044e: 68fb ldr r3, [r7, #12]
8010450: 895a ldrh r2, [r3, #10]
8010452: 8a7b ldrh r3, [r7, #18]
8010454: 4413 add r3, r2
8010456: b29a uxth r2, r3
8010458: 68fb ldr r3, [r7, #12]
801045a: 815a strh r2, [r3, #10]
p->tot_len = (u16_t)(p->tot_len + increment_magnitude);
801045c: 68fb ldr r3, [r7, #12]
801045e: 891a ldrh r2, [r3, #8]
8010460: 8a7b ldrh r3, [r7, #18]
8010462: 4413 add r3, r2
8010464: b29a uxth r2, r3
8010466: 68fb ldr r3, [r7, #12]
8010468: 811a strh r2, [r3, #8]
return 0;
801046a: 2300 movs r3, #0
}
801046c: 4618 mov r0, r3
801046e: 3718 adds r7, #24
8010470: 46bd mov sp, r7
8010472: bd80 pop {r7, pc}
8010474: 0801c81c .word 0x0801c81c
8010478: 0801c980 .word 0x0801c980
801047c: 0801c87c .word 0x0801c87c
08010480 <pbuf_add_header>:
* @return non-zero on failure, zero on success.
*
*/
u8_t
pbuf_add_header(struct pbuf *p, size_t header_size_increment)
{
8010480: b580 push {r7, lr}
8010482: b082 sub sp, #8
8010484: af00 add r7, sp, #0
8010486: 6078 str r0, [r7, #4]
8010488: 6039 str r1, [r7, #0]
return pbuf_add_header_impl(p, header_size_increment, 0);
801048a: 2200 movs r2, #0
801048c: 6839 ldr r1, [r7, #0]
801048e: 6878 ldr r0, [r7, #4]
8010490: f7ff ff8e bl 80103b0 <pbuf_add_header_impl>
8010494: 4603 mov r3, r0
}
8010496: 4618 mov r0, r3
8010498: 3708 adds r7, #8
801049a: 46bd mov sp, r7
801049c: bd80 pop {r7, pc}
...
080104a0 <pbuf_remove_header>:
* @return non-zero on failure, zero on success.
*
*/
u8_t
pbuf_remove_header(struct pbuf *p, size_t header_size_decrement)
{
80104a0: b580 push {r7, lr}
80104a2: b084 sub sp, #16
80104a4: af00 add r7, sp, #0
80104a6: 6078 str r0, [r7, #4]
80104a8: 6039 str r1, [r7, #0]
void *payload;
u16_t increment_magnitude;
LWIP_ASSERT("p != NULL", p != NULL);
80104aa: 687b ldr r3, [r7, #4]
80104ac: 2b00 cmp r3, #0
80104ae: d106 bne.n 80104be <pbuf_remove_header+0x1e>
80104b0: 4b20 ldr r3, [pc, #128] ; (8010534 <pbuf_remove_header+0x94>)
80104b2: f240 224b movw r2, #587 ; 0x24b
80104b6: 4920 ldr r1, [pc, #128] ; (8010538 <pbuf_remove_header+0x98>)
80104b8: 4820 ldr r0, [pc, #128] ; (801053c <pbuf_remove_header+0x9c>)
80104ba: f00a fd83 bl 801afc4 <iprintf>
if ((p == NULL) || (header_size_decrement > 0xFFFF)) {
80104be: 687b ldr r3, [r7, #4]
80104c0: 2b00 cmp r3, #0
80104c2: d003 beq.n 80104cc <pbuf_remove_header+0x2c>
80104c4: 683b ldr r3, [r7, #0]
80104c6: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80104ca: d301 bcc.n 80104d0 <pbuf_remove_header+0x30>
return 1;
80104cc: 2301 movs r3, #1
80104ce: e02c b.n 801052a <pbuf_remove_header+0x8a>
}
if (header_size_decrement == 0) {
80104d0: 683b ldr r3, [r7, #0]
80104d2: 2b00 cmp r3, #0
80104d4: d101 bne.n 80104da <pbuf_remove_header+0x3a>
return 0;
80104d6: 2300 movs r3, #0
80104d8: e027 b.n 801052a <pbuf_remove_header+0x8a>
}
increment_magnitude = (u16_t)header_size_decrement;
80104da: 683b ldr r3, [r7, #0]
80104dc: 81fb strh r3, [r7, #14]
/* Check that we aren't going to move off the end of the pbuf */
LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;);
80104de: 687b ldr r3, [r7, #4]
80104e0: 895b ldrh r3, [r3, #10]
80104e2: 89fa ldrh r2, [r7, #14]
80104e4: 429a cmp r2, r3
80104e6: d908 bls.n 80104fa <pbuf_remove_header+0x5a>
80104e8: 4b12 ldr r3, [pc, #72] ; (8010534 <pbuf_remove_header+0x94>)
80104ea: f240 2255 movw r2, #597 ; 0x255
80104ee: 4914 ldr r1, [pc, #80] ; (8010540 <pbuf_remove_header+0xa0>)
80104f0: 4812 ldr r0, [pc, #72] ; (801053c <pbuf_remove_header+0x9c>)
80104f2: f00a fd67 bl 801afc4 <iprintf>
80104f6: 2301 movs r3, #1
80104f8: e017 b.n 801052a <pbuf_remove_header+0x8a>
/* remember current payload pointer */
payload = p->payload;
80104fa: 687b ldr r3, [r7, #4]
80104fc: 685b ldr r3, [r3, #4]
80104fe: 60bb str r3, [r7, #8]
LWIP_UNUSED_ARG(payload); /* only used in LWIP_DEBUGF below */
/* increase payload pointer (guarded by length check above) */
p->payload = (u8_t *)p->payload + header_size_decrement;
8010500: 687b ldr r3, [r7, #4]
8010502: 685a ldr r2, [r3, #4]
8010504: 683b ldr r3, [r7, #0]
8010506: 441a add r2, r3
8010508: 687b ldr r3, [r7, #4]
801050a: 605a str r2, [r3, #4]
/* modify pbuf length fields */
p->len = (u16_t)(p->len - increment_magnitude);
801050c: 687b ldr r3, [r7, #4]
801050e: 895a ldrh r2, [r3, #10]
8010510: 89fb ldrh r3, [r7, #14]
8010512: 1ad3 subs r3, r2, r3
8010514: b29a uxth r2, r3
8010516: 687b ldr r3, [r7, #4]
8010518: 815a strh r2, [r3, #10]
p->tot_len = (u16_t)(p->tot_len - increment_magnitude);
801051a: 687b ldr r3, [r7, #4]
801051c: 891a ldrh r2, [r3, #8]
801051e: 89fb ldrh r3, [r7, #14]
8010520: 1ad3 subs r3, r2, r3
8010522: b29a uxth r2, r3
8010524: 687b ldr r3, [r7, #4]
8010526: 811a strh r2, [r3, #8]
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_remove_header: old %p new %p (%"U16_F")\n",
(void *)payload, (void *)p->payload, increment_magnitude));
return 0;
8010528: 2300 movs r3, #0
}
801052a: 4618 mov r0, r3
801052c: 3710 adds r7, #16
801052e: 46bd mov sp, r7
8010530: bd80 pop {r7, pc}
8010532: bf00 nop
8010534: 0801c81c .word 0x0801c81c
8010538: 0801c980 .word 0x0801c980
801053c: 0801c87c .word 0x0801c87c
8010540: 0801c98c .word 0x0801c98c
08010544 <pbuf_header_impl>:
static u8_t
pbuf_header_impl(struct pbuf *p, s16_t header_size_increment, u8_t force)
{
8010544: b580 push {r7, lr}
8010546: b082 sub sp, #8
8010548: af00 add r7, sp, #0
801054a: 6078 str r0, [r7, #4]
801054c: 460b mov r3, r1
801054e: 807b strh r3, [r7, #2]
8010550: 4613 mov r3, r2
8010552: 707b strb r3, [r7, #1]
if (header_size_increment < 0) {
8010554: f9b7 3002 ldrsh.w r3, [r7, #2]
8010558: 2b00 cmp r3, #0
801055a: da08 bge.n 801056e <pbuf_header_impl+0x2a>
return pbuf_remove_header(p, (size_t) - header_size_increment);
801055c: f9b7 3002 ldrsh.w r3, [r7, #2]
8010560: 425b negs r3, r3
8010562: 4619 mov r1, r3
8010564: 6878 ldr r0, [r7, #4]
8010566: f7ff ff9b bl 80104a0 <pbuf_remove_header>
801056a: 4603 mov r3, r0
801056c: e007 b.n 801057e <pbuf_header_impl+0x3a>
} else {
return pbuf_add_header_impl(p, (size_t)header_size_increment, force);
801056e: f9b7 3002 ldrsh.w r3, [r7, #2]
8010572: 787a ldrb r2, [r7, #1]
8010574: 4619 mov r1, r3
8010576: 6878 ldr r0, [r7, #4]
8010578: f7ff ff1a bl 80103b0 <pbuf_add_header_impl>
801057c: 4603 mov r3, r0
}
}
801057e: 4618 mov r0, r3
8010580: 3708 adds r7, #8
8010582: 46bd mov sp, r7
8010584: bd80 pop {r7, pc}
08010586 <pbuf_header_force>:
* Same as pbuf_header but does not check if 'header_size > 0' is allowed.
* This is used internally only, to allow PBUF_REF for RX.
*/
u8_t
pbuf_header_force(struct pbuf *p, s16_t header_size_increment)
{
8010586: b580 push {r7, lr}
8010588: b082 sub sp, #8
801058a: af00 add r7, sp, #0
801058c: 6078 str r0, [r7, #4]
801058e: 460b mov r3, r1
8010590: 807b strh r3, [r7, #2]
return pbuf_header_impl(p, header_size_increment, 1);
8010592: f9b7 3002 ldrsh.w r3, [r7, #2]
8010596: 2201 movs r2, #1
8010598: 4619 mov r1, r3
801059a: 6878 ldr r0, [r7, #4]
801059c: f7ff ffd2 bl 8010544 <pbuf_header_impl>
80105a0: 4603 mov r3, r0
}
80105a2: 4618 mov r0, r3
80105a4: 3708 adds r7, #8
80105a6: 46bd mov sp, r7
80105a8: bd80 pop {r7, pc}
...
080105ac <pbuf_free>:
* 1->1->1 becomes .......
*
*/
u8_t
pbuf_free(struct pbuf *p)
{
80105ac: b580 push {r7, lr}
80105ae: b088 sub sp, #32
80105b0: af00 add r7, sp, #0
80105b2: 6078 str r0, [r7, #4]
u8_t alloc_src;
struct pbuf *q;
u8_t count;
if (p == NULL) {
80105b4: 687b ldr r3, [r7, #4]
80105b6: 2b00 cmp r3, #0
80105b8: d10b bne.n 80105d2 <pbuf_free+0x26>
LWIP_ASSERT("p != NULL", p != NULL);
80105ba: 687b ldr r3, [r7, #4]
80105bc: 2b00 cmp r3, #0
80105be: d106 bne.n 80105ce <pbuf_free+0x22>
80105c0: 4b3b ldr r3, [pc, #236] ; (80106b0 <pbuf_free+0x104>)
80105c2: f44f 7237 mov.w r2, #732 ; 0x2dc
80105c6: 493b ldr r1, [pc, #236] ; (80106b4 <pbuf_free+0x108>)
80105c8: 483b ldr r0, [pc, #236] ; (80106b8 <pbuf_free+0x10c>)
80105ca: f00a fcfb bl 801afc4 <iprintf>
/* if assertions are disabled, proceed with debug output */
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
("pbuf_free(p == NULL) was called.\n"));
return 0;
80105ce: 2300 movs r3, #0
80105d0: e069 b.n 80106a6 <pbuf_free+0xfa>
}
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p));
PERF_START;
count = 0;
80105d2: 2300 movs r3, #0
80105d4: 77fb strb r3, [r7, #31]
/* de-allocate all consecutive pbufs from the head of the chain that
* obtain a zero reference count after decrementing*/
while (p != NULL) {
80105d6: e062 b.n 801069e <pbuf_free+0xf2>
LWIP_PBUF_REF_T ref;
SYS_ARCH_DECL_PROTECT(old_level);
/* Since decrementing ref cannot be guaranteed to be a single machine operation
* we must protect it. We put the new ref into a local variable to prevent
* further protection. */
SYS_ARCH_PROTECT(old_level);
80105d8: f00a fc8e bl 801aef8 <sys_arch_protect>
80105dc: 61b8 str r0, [r7, #24]
/* all pbufs in a chain are referenced at least once */
LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
80105de: 687b ldr r3, [r7, #4]
80105e0: 7b9b ldrb r3, [r3, #14]
80105e2: 2b00 cmp r3, #0
80105e4: d106 bne.n 80105f4 <pbuf_free+0x48>
80105e6: 4b32 ldr r3, [pc, #200] ; (80106b0 <pbuf_free+0x104>)
80105e8: f240 22f1 movw r2, #753 ; 0x2f1
80105ec: 4933 ldr r1, [pc, #204] ; (80106bc <pbuf_free+0x110>)
80105ee: 4832 ldr r0, [pc, #200] ; (80106b8 <pbuf_free+0x10c>)
80105f0: f00a fce8 bl 801afc4 <iprintf>
/* decrease reference count (number of pointers to pbuf) */
ref = --(p->ref);
80105f4: 687b ldr r3, [r7, #4]
80105f6: 7b9b ldrb r3, [r3, #14]
80105f8: 3b01 subs r3, #1
80105fa: b2da uxtb r2, r3
80105fc: 687b ldr r3, [r7, #4]
80105fe: 739a strb r2, [r3, #14]
8010600: 687b ldr r3, [r7, #4]
8010602: 7b9b ldrb r3, [r3, #14]
8010604: 75fb strb r3, [r7, #23]
SYS_ARCH_UNPROTECT(old_level);
8010606: 69b8 ldr r0, [r7, #24]
8010608: f00a fc84 bl 801af14 <sys_arch_unprotect>
/* this pbuf is no longer referenced to? */
if (ref == 0) {
801060c: 7dfb ldrb r3, [r7, #23]
801060e: 2b00 cmp r3, #0
8010610: d143 bne.n 801069a <pbuf_free+0xee>
/* remember next pbuf in chain for next iteration */
q = p->next;
8010612: 687b ldr r3, [r7, #4]
8010614: 681b ldr r3, [r3, #0]
8010616: 613b str r3, [r7, #16]
LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p));
alloc_src = pbuf_get_allocsrc(p);
8010618: 687b ldr r3, [r7, #4]
801061a: 7b1b ldrb r3, [r3, #12]
801061c: f003 030f and.w r3, r3, #15
8010620: 73fb strb r3, [r7, #15]
#if LWIP_SUPPORT_CUSTOM_PBUF
/* is this a custom pbuf? */
if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) {
8010622: 687b ldr r3, [r7, #4]
8010624: 7b5b ldrb r3, [r3, #13]
8010626: f003 0302 and.w r3, r3, #2
801062a: 2b00 cmp r3, #0
801062c: d011 beq.n 8010652 <pbuf_free+0xa6>
struct pbuf_custom *pc = (struct pbuf_custom *)p;
801062e: 687b ldr r3, [r7, #4]
8010630: 60bb str r3, [r7, #8]
LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL);
8010632: 68bb ldr r3, [r7, #8]
8010634: 691b ldr r3, [r3, #16]
8010636: 2b00 cmp r3, #0
8010638: d106 bne.n 8010648 <pbuf_free+0x9c>
801063a: 4b1d ldr r3, [pc, #116] ; (80106b0 <pbuf_free+0x104>)
801063c: f240 22ff movw r2, #767 ; 0x2ff
8010640: 491f ldr r1, [pc, #124] ; (80106c0 <pbuf_free+0x114>)
8010642: 481d ldr r0, [pc, #116] ; (80106b8 <pbuf_free+0x10c>)
8010644: f00a fcbe bl 801afc4 <iprintf>
pc->custom_free_function(p);
8010648: 68bb ldr r3, [r7, #8]
801064a: 691b ldr r3, [r3, #16]
801064c: 6878 ldr r0, [r7, #4]
801064e: 4798 blx r3
8010650: e01d b.n 801068e <pbuf_free+0xe2>
} else
#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
{
/* is this a pbuf from the pool? */
if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL) {
8010652: 7bfb ldrb r3, [r7, #15]
8010654: 2b02 cmp r3, #2
8010656: d104 bne.n 8010662 <pbuf_free+0xb6>
memp_free(MEMP_PBUF_POOL, p);
8010658: 6879 ldr r1, [r7, #4]
801065a: 200c movs r0, #12
801065c: f7ff f8f6 bl 800f84c <memp_free>
8010660: e015 b.n 801068e <pbuf_free+0xe2>
/* is this a ROM or RAM referencing pbuf? */
} else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF) {
8010662: 7bfb ldrb r3, [r7, #15]
8010664: 2b01 cmp r3, #1
8010666: d104 bne.n 8010672 <pbuf_free+0xc6>
memp_free(MEMP_PBUF, p);
8010668: 6879 ldr r1, [r7, #4]
801066a: 200b movs r0, #11
801066c: f7ff f8ee bl 800f84c <memp_free>
8010670: e00d b.n 801068e <pbuf_free+0xe2>
/* type == PBUF_RAM */
} else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) {
8010672: 7bfb ldrb r3, [r7, #15]
8010674: 2b00 cmp r3, #0
8010676: d103 bne.n 8010680 <pbuf_free+0xd4>
mem_free(p);
8010678: 6878 ldr r0, [r7, #4]
801067a: f7fe fd79 bl 800f170 <mem_free>
801067e: e006 b.n 801068e <pbuf_free+0xe2>
} else {
/* @todo: support freeing other types */
LWIP_ASSERT("invalid pbuf type", 0);
8010680: 4b0b ldr r3, [pc, #44] ; (80106b0 <pbuf_free+0x104>)
8010682: f240 320f movw r2, #783 ; 0x30f
8010686: 490f ldr r1, [pc, #60] ; (80106c4 <pbuf_free+0x118>)
8010688: 480b ldr r0, [pc, #44] ; (80106b8 <pbuf_free+0x10c>)
801068a: f00a fc9b bl 801afc4 <iprintf>
}
}
count++;
801068e: 7ffb ldrb r3, [r7, #31]
8010690: 3301 adds r3, #1
8010692: 77fb strb r3, [r7, #31]
/* proceed to next pbuf */
p = q;
8010694: 693b ldr r3, [r7, #16]
8010696: 607b str r3, [r7, #4]
8010698: e001 b.n 801069e <pbuf_free+0xf2>
/* p->ref > 0, this pbuf is still referenced to */
/* (and so the remaining pbufs in chain as well) */
} else {
LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)ref));
/* stop walking through the chain */
p = NULL;
801069a: 2300 movs r3, #0
801069c: 607b str r3, [r7, #4]
while (p != NULL) {
801069e: 687b ldr r3, [r7, #4]
80106a0: 2b00 cmp r3, #0
80106a2: d199 bne.n 80105d8 <pbuf_free+0x2c>
}
}
PERF_STOP("pbuf_free");
/* return number of de-allocated pbufs */
return count;
80106a4: 7ffb ldrb r3, [r7, #31]
}
80106a6: 4618 mov r0, r3
80106a8: 3720 adds r7, #32
80106aa: 46bd mov sp, r7
80106ac: bd80 pop {r7, pc}
80106ae: bf00 nop
80106b0: 0801c81c .word 0x0801c81c
80106b4: 0801c980 .word 0x0801c980
80106b8: 0801c87c .word 0x0801c87c
80106bc: 0801c9ac .word 0x0801c9ac
80106c0: 0801c9c4 .word 0x0801c9c4
80106c4: 0801c9e8 .word 0x0801c9e8
080106c8 <pbuf_clen>:
* @param p first pbuf of chain
* @return the number of pbufs in a chain
*/
u16_t
pbuf_clen(const struct pbuf *p)
{
80106c8: b480 push {r7}
80106ca: b085 sub sp, #20
80106cc: af00 add r7, sp, #0
80106ce: 6078 str r0, [r7, #4]
u16_t len;
len = 0;
80106d0: 2300 movs r3, #0
80106d2: 81fb strh r3, [r7, #14]
while (p != NULL) {
80106d4: e005 b.n 80106e2 <pbuf_clen+0x1a>
++len;
80106d6: 89fb ldrh r3, [r7, #14]
80106d8: 3301 adds r3, #1
80106da: 81fb strh r3, [r7, #14]
p = p->next;
80106dc: 687b ldr r3, [r7, #4]
80106de: 681b ldr r3, [r3, #0]
80106e0: 607b str r3, [r7, #4]
while (p != NULL) {
80106e2: 687b ldr r3, [r7, #4]
80106e4: 2b00 cmp r3, #0
80106e6: d1f6 bne.n 80106d6 <pbuf_clen+0xe>
}
return len;
80106e8: 89fb ldrh r3, [r7, #14]
}
80106ea: 4618 mov r0, r3
80106ec: 3714 adds r7, #20
80106ee: 46bd mov sp, r7
80106f0: f85d 7b04 ldr.w r7, [sp], #4
80106f4: 4770 bx lr
...
080106f8 <pbuf_ref>:
* @param p pbuf to increase reference counter of
*
*/
void
pbuf_ref(struct pbuf *p)
{
80106f8: b580 push {r7, lr}
80106fa: b084 sub sp, #16
80106fc: af00 add r7, sp, #0
80106fe: 6078 str r0, [r7, #4]
/* pbuf given? */
if (p != NULL) {
8010700: 687b ldr r3, [r7, #4]
8010702: 2b00 cmp r3, #0
8010704: d016 beq.n 8010734 <pbuf_ref+0x3c>
SYS_ARCH_SET(p->ref, (LWIP_PBUF_REF_T)(p->ref + 1));
8010706: f00a fbf7 bl 801aef8 <sys_arch_protect>
801070a: 60f8 str r0, [r7, #12]
801070c: 687b ldr r3, [r7, #4]
801070e: 7b9b ldrb r3, [r3, #14]
8010710: 3301 adds r3, #1
8010712: b2da uxtb r2, r3
8010714: 687b ldr r3, [r7, #4]
8010716: 739a strb r2, [r3, #14]
8010718: 68f8 ldr r0, [r7, #12]
801071a: f00a fbfb bl 801af14 <sys_arch_unprotect>
LWIP_ASSERT("pbuf ref overflow", p->ref > 0);
801071e: 687b ldr r3, [r7, #4]
8010720: 7b9b ldrb r3, [r3, #14]
8010722: 2b00 cmp r3, #0
8010724: d106 bne.n 8010734 <pbuf_ref+0x3c>
8010726: 4b05 ldr r3, [pc, #20] ; (801073c <pbuf_ref+0x44>)
8010728: f240 3242 movw r2, #834 ; 0x342
801072c: 4904 ldr r1, [pc, #16] ; (8010740 <pbuf_ref+0x48>)
801072e: 4805 ldr r0, [pc, #20] ; (8010744 <pbuf_ref+0x4c>)
8010730: f00a fc48 bl 801afc4 <iprintf>
}
}
8010734: bf00 nop
8010736: 3710 adds r7, #16
8010738: 46bd mov sp, r7
801073a: bd80 pop {r7, pc}
801073c: 0801c81c .word 0x0801c81c
8010740: 0801c9fc .word 0x0801c9fc
8010744: 0801c87c .word 0x0801c87c
08010748 <pbuf_cat>:
*
* @see pbuf_chain()
*/
void
pbuf_cat(struct pbuf *h, struct pbuf *t)
{
8010748: b580 push {r7, lr}
801074a: b084 sub sp, #16
801074c: af00 add r7, sp, #0
801074e: 6078 str r0, [r7, #4]
8010750: 6039 str r1, [r7, #0]
struct pbuf *p;
LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)",
8010752: 687b ldr r3, [r7, #4]
8010754: 2b00 cmp r3, #0
8010756: d002 beq.n 801075e <pbuf_cat+0x16>
8010758: 683b ldr r3, [r7, #0]
801075a: 2b00 cmp r3, #0
801075c: d107 bne.n 801076e <pbuf_cat+0x26>
801075e: 4b20 ldr r3, [pc, #128] ; (80107e0 <pbuf_cat+0x98>)
8010760: f240 3259 movw r2, #857 ; 0x359
8010764: 491f ldr r1, [pc, #124] ; (80107e4 <pbuf_cat+0x9c>)
8010766: 4820 ldr r0, [pc, #128] ; (80107e8 <pbuf_cat+0xa0>)
8010768: f00a fc2c bl 801afc4 <iprintf>
801076c: e034 b.n 80107d8 <pbuf_cat+0x90>
((h != NULL) && (t != NULL)), return;);
/* proceed to last pbuf of chain */
for (p = h; p->next != NULL; p = p->next) {
801076e: 687b ldr r3, [r7, #4]
8010770: 60fb str r3, [r7, #12]
8010772: e00a b.n 801078a <pbuf_cat+0x42>
/* add total length of second chain to all totals of first chain */
p->tot_len = (u16_t)(p->tot_len + t->tot_len);
8010774: 68fb ldr r3, [r7, #12]
8010776: 891a ldrh r2, [r3, #8]
8010778: 683b ldr r3, [r7, #0]
801077a: 891b ldrh r3, [r3, #8]
801077c: 4413 add r3, r2
801077e: b29a uxth r2, r3
8010780: 68fb ldr r3, [r7, #12]
8010782: 811a strh r2, [r3, #8]
for (p = h; p->next != NULL; p = p->next) {
8010784: 68fb ldr r3, [r7, #12]
8010786: 681b ldr r3, [r3, #0]
8010788: 60fb str r3, [r7, #12]
801078a: 68fb ldr r3, [r7, #12]
801078c: 681b ldr r3, [r3, #0]
801078e: 2b00 cmp r3, #0
8010790: d1f0 bne.n 8010774 <pbuf_cat+0x2c>
}
/* { p is last pbuf of first h chain, p->next == NULL } */
LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
8010792: 68fb ldr r3, [r7, #12]
8010794: 891a ldrh r2, [r3, #8]
8010796: 68fb ldr r3, [r7, #12]
8010798: 895b ldrh r3, [r3, #10]
801079a: 429a cmp r2, r3
801079c: d006 beq.n 80107ac <pbuf_cat+0x64>
801079e: 4b10 ldr r3, [pc, #64] ; (80107e0 <pbuf_cat+0x98>)
80107a0: f240 3262 movw r2, #866 ; 0x362
80107a4: 4911 ldr r1, [pc, #68] ; (80107ec <pbuf_cat+0xa4>)
80107a6: 4810 ldr r0, [pc, #64] ; (80107e8 <pbuf_cat+0xa0>)
80107a8: f00a fc0c bl 801afc4 <iprintf>
LWIP_ASSERT("p->next == NULL", p->next == NULL);
80107ac: 68fb ldr r3, [r7, #12]
80107ae: 681b ldr r3, [r3, #0]
80107b0: 2b00 cmp r3, #0
80107b2: d006 beq.n 80107c2 <pbuf_cat+0x7a>
80107b4: 4b0a ldr r3, [pc, #40] ; (80107e0 <pbuf_cat+0x98>)
80107b6: f240 3263 movw r2, #867 ; 0x363
80107ba: 490d ldr r1, [pc, #52] ; (80107f0 <pbuf_cat+0xa8>)
80107bc: 480a ldr r0, [pc, #40] ; (80107e8 <pbuf_cat+0xa0>)
80107be: f00a fc01 bl 801afc4 <iprintf>
/* add total length of second chain to last pbuf total of first chain */
p->tot_len = (u16_t)(p->tot_len + t->tot_len);
80107c2: 68fb ldr r3, [r7, #12]
80107c4: 891a ldrh r2, [r3, #8]
80107c6: 683b ldr r3, [r7, #0]
80107c8: 891b ldrh r3, [r3, #8]
80107ca: 4413 add r3, r2
80107cc: b29a uxth r2, r3
80107ce: 68fb ldr r3, [r7, #12]
80107d0: 811a strh r2, [r3, #8]
/* chain last pbuf of head (p) with first of tail (t) */
p->next = t;
80107d2: 68fb ldr r3, [r7, #12]
80107d4: 683a ldr r2, [r7, #0]
80107d6: 601a str r2, [r3, #0]
/* p->next now references t, but the caller will drop its reference to t,
* so netto there is no change to the reference count of t.
*/
}
80107d8: 3710 adds r7, #16
80107da: 46bd mov sp, r7
80107dc: bd80 pop {r7, pc}
80107de: bf00 nop
80107e0: 0801c81c .word 0x0801c81c
80107e4: 0801ca10 .word 0x0801ca10
80107e8: 0801c87c .word 0x0801c87c
80107ec: 0801ca48 .word 0x0801ca48
80107f0: 0801ca78 .word 0x0801ca78
080107f4 <pbuf_chain>:
* The ->ref field of the first pbuf of the tail chain is adjusted.
*
*/
void
pbuf_chain(struct pbuf *h, struct pbuf *t)
{
80107f4: b580 push {r7, lr}
80107f6: b082 sub sp, #8
80107f8: af00 add r7, sp, #0
80107fa: 6078 str r0, [r7, #4]
80107fc: 6039 str r1, [r7, #0]
pbuf_cat(h, t);
80107fe: 6839 ldr r1, [r7, #0]
8010800: 6878 ldr r0, [r7, #4]
8010802: f7ff ffa1 bl 8010748 <pbuf_cat>
/* t is now referenced by h */
pbuf_ref(t);
8010806: 6838 ldr r0, [r7, #0]
8010808: f7ff ff76 bl 80106f8 <pbuf_ref>
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
}
801080c: bf00 nop
801080e: 3708 adds r7, #8
8010810: 46bd mov sp, r7
8010812: bd80 pop {r7, pc}
08010814 <pbuf_copy>:
* ERR_ARG if one of the pbufs is NULL or p_to is not big
* enough to hold p_from
*/
err_t
pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from)
{
8010814: b580 push {r7, lr}
8010816: b086 sub sp, #24
8010818: af00 add r7, sp, #0
801081a: 6078 str r0, [r7, #4]
801081c: 6039 str r1, [r7, #0]
size_t offset_to = 0, offset_from = 0, len;
801081e: 2300 movs r3, #0
8010820: 617b str r3, [r7, #20]
8010822: 2300 movs r3, #0
8010824: 613b str r3, [r7, #16]
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n",
(const void *)p_to, (const void *)p_from));
/* is the target big enough to hold the source? */
LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) &&
8010826: 687b ldr r3, [r7, #4]
8010828: 2b00 cmp r3, #0
801082a: d008 beq.n 801083e <pbuf_copy+0x2a>
801082c: 683b ldr r3, [r7, #0]
801082e: 2b00 cmp r3, #0
8010830: d005 beq.n 801083e <pbuf_copy+0x2a>
8010832: 687b ldr r3, [r7, #4]
8010834: 891a ldrh r2, [r3, #8]
8010836: 683b ldr r3, [r7, #0]
8010838: 891b ldrh r3, [r3, #8]
801083a: 429a cmp r2, r3
801083c: d209 bcs.n 8010852 <pbuf_copy+0x3e>
801083e: 4b57 ldr r3, [pc, #348] ; (801099c <pbuf_copy+0x188>)
8010840: f240 32c9 movw r2, #969 ; 0x3c9
8010844: 4956 ldr r1, [pc, #344] ; (80109a0 <pbuf_copy+0x18c>)
8010846: 4857 ldr r0, [pc, #348] ; (80109a4 <pbuf_copy+0x190>)
8010848: f00a fbbc bl 801afc4 <iprintf>
801084c: f06f 030f mvn.w r3, #15
8010850: e09f b.n 8010992 <pbuf_copy+0x17e>
(p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;);
/* iterate through pbuf chain */
do {
/* copy one part of the original chain */
if ((p_to->len - offset_to) >= (p_from->len - offset_from)) {
8010852: 687b ldr r3, [r7, #4]
8010854: 895b ldrh r3, [r3, #10]
8010856: 461a mov r2, r3
8010858: 697b ldr r3, [r7, #20]
801085a: 1ad2 subs r2, r2, r3
801085c: 683b ldr r3, [r7, #0]
801085e: 895b ldrh r3, [r3, #10]
8010860: 4619 mov r1, r3
8010862: 693b ldr r3, [r7, #16]
8010864: 1acb subs r3, r1, r3
8010866: 429a cmp r2, r3
8010868: d306 bcc.n 8010878 <pbuf_copy+0x64>
/* complete current p_from fits into current p_to */
len = p_from->len - offset_from;
801086a: 683b ldr r3, [r7, #0]
801086c: 895b ldrh r3, [r3, #10]
801086e: 461a mov r2, r3
8010870: 693b ldr r3, [r7, #16]
8010872: 1ad3 subs r3, r2, r3
8010874: 60fb str r3, [r7, #12]
8010876: e005 b.n 8010884 <pbuf_copy+0x70>
} else {
/* current p_from does not fit into current p_to */
len = p_to->len - offset_to;
8010878: 687b ldr r3, [r7, #4]
801087a: 895b ldrh r3, [r3, #10]
801087c: 461a mov r2, r3
801087e: 697b ldr r3, [r7, #20]
8010880: 1ad3 subs r3, r2, r3
8010882: 60fb str r3, [r7, #12]
}
MEMCPY((u8_t *)p_to->payload + offset_to, (u8_t *)p_from->payload + offset_from, len);
8010884: 687b ldr r3, [r7, #4]
8010886: 685a ldr r2, [r3, #4]
8010888: 697b ldr r3, [r7, #20]
801088a: 18d0 adds r0, r2, r3
801088c: 683b ldr r3, [r7, #0]
801088e: 685a ldr r2, [r3, #4]
8010890: 693b ldr r3, [r7, #16]
8010892: 4413 add r3, r2
8010894: 68fa ldr r2, [r7, #12]
8010896: 4619 mov r1, r3
8010898: f00a fb7e bl 801af98 <memcpy>
offset_to += len;
801089c: 697a ldr r2, [r7, #20]
801089e: 68fb ldr r3, [r7, #12]
80108a0: 4413 add r3, r2
80108a2: 617b str r3, [r7, #20]
offset_from += len;
80108a4: 693a ldr r2, [r7, #16]
80108a6: 68fb ldr r3, [r7, #12]
80108a8: 4413 add r3, r2
80108aa: 613b str r3, [r7, #16]
LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len);
80108ac: 687b ldr r3, [r7, #4]
80108ae: 895b ldrh r3, [r3, #10]
80108b0: 461a mov r2, r3
80108b2: 697b ldr r3, [r7, #20]
80108b4: 4293 cmp r3, r2
80108b6: d906 bls.n 80108c6 <pbuf_copy+0xb2>
80108b8: 4b38 ldr r3, [pc, #224] ; (801099c <pbuf_copy+0x188>)
80108ba: f240 32d9 movw r2, #985 ; 0x3d9
80108be: 493a ldr r1, [pc, #232] ; (80109a8 <pbuf_copy+0x194>)
80108c0: 4838 ldr r0, [pc, #224] ; (80109a4 <pbuf_copy+0x190>)
80108c2: f00a fb7f bl 801afc4 <iprintf>
LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len);
80108c6: 683b ldr r3, [r7, #0]
80108c8: 895b ldrh r3, [r3, #10]
80108ca: 461a mov r2, r3
80108cc: 693b ldr r3, [r7, #16]
80108ce: 4293 cmp r3, r2
80108d0: d906 bls.n 80108e0 <pbuf_copy+0xcc>
80108d2: 4b32 ldr r3, [pc, #200] ; (801099c <pbuf_copy+0x188>)
80108d4: f240 32da movw r2, #986 ; 0x3da
80108d8: 4934 ldr r1, [pc, #208] ; (80109ac <pbuf_copy+0x198>)
80108da: 4832 ldr r0, [pc, #200] ; (80109a4 <pbuf_copy+0x190>)
80108dc: f00a fb72 bl 801afc4 <iprintf>
if (offset_from >= p_from->len) {
80108e0: 683b ldr r3, [r7, #0]
80108e2: 895b ldrh r3, [r3, #10]
80108e4: 461a mov r2, r3
80108e6: 693b ldr r3, [r7, #16]
80108e8: 4293 cmp r3, r2
80108ea: d304 bcc.n 80108f6 <pbuf_copy+0xe2>
/* on to next p_from (if any) */
offset_from = 0;
80108ec: 2300 movs r3, #0
80108ee: 613b str r3, [r7, #16]
p_from = p_from->next;
80108f0: 683b ldr r3, [r7, #0]
80108f2: 681b ldr r3, [r3, #0]
80108f4: 603b str r3, [r7, #0]
}
if (offset_to == p_to->len) {
80108f6: 687b ldr r3, [r7, #4]
80108f8: 895b ldrh r3, [r3, #10]
80108fa: 461a mov r2, r3
80108fc: 697b ldr r3, [r7, #20]
80108fe: 4293 cmp r3, r2
8010900: d114 bne.n 801092c <pbuf_copy+0x118>
/* on to next p_to (if any) */
offset_to = 0;
8010902: 2300 movs r3, #0
8010904: 617b str r3, [r7, #20]
p_to = p_to->next;
8010906: 687b ldr r3, [r7, #4]
8010908: 681b ldr r3, [r3, #0]
801090a: 607b str r3, [r7, #4]
LWIP_ERROR("p_to != NULL", (p_to != NULL) || (p_from == NULL), return ERR_ARG;);
801090c: 687b ldr r3, [r7, #4]
801090e: 2b00 cmp r3, #0
8010910: d10c bne.n 801092c <pbuf_copy+0x118>
8010912: 683b ldr r3, [r7, #0]
8010914: 2b00 cmp r3, #0
8010916: d009 beq.n 801092c <pbuf_copy+0x118>
8010918: 4b20 ldr r3, [pc, #128] ; (801099c <pbuf_copy+0x188>)
801091a: f44f 7279 mov.w r2, #996 ; 0x3e4
801091e: 4924 ldr r1, [pc, #144] ; (80109b0 <pbuf_copy+0x19c>)
8010920: 4820 ldr r0, [pc, #128] ; (80109a4 <pbuf_copy+0x190>)
8010922: f00a fb4f bl 801afc4 <iprintf>
8010926: f06f 030f mvn.w r3, #15
801092a: e032 b.n 8010992 <pbuf_copy+0x17e>
}
if ((p_from != NULL) && (p_from->len == p_from->tot_len)) {
801092c: 683b ldr r3, [r7, #0]
801092e: 2b00 cmp r3, #0
8010930: d013 beq.n 801095a <pbuf_copy+0x146>
8010932: 683b ldr r3, [r7, #0]
8010934: 895a ldrh r2, [r3, #10]
8010936: 683b ldr r3, [r7, #0]
8010938: 891b ldrh r3, [r3, #8]
801093a: 429a cmp r2, r3
801093c: d10d bne.n 801095a <pbuf_copy+0x146>
/* don't copy more than one packet! */
LWIP_ERROR("pbuf_copy() does not allow packet queues!",
801093e: 683b ldr r3, [r7, #0]
8010940: 681b ldr r3, [r3, #0]
8010942: 2b00 cmp r3, #0
8010944: d009 beq.n 801095a <pbuf_copy+0x146>
8010946: 4b15 ldr r3, [pc, #84] ; (801099c <pbuf_copy+0x188>)
8010948: f240 32e9 movw r2, #1001 ; 0x3e9
801094c: 4919 ldr r1, [pc, #100] ; (80109b4 <pbuf_copy+0x1a0>)
801094e: 4815 ldr r0, [pc, #84] ; (80109a4 <pbuf_copy+0x190>)
8010950: f00a fb38 bl 801afc4 <iprintf>
8010954: f06f 0305 mvn.w r3, #5
8010958: e01b b.n 8010992 <pbuf_copy+0x17e>
(p_from->next == NULL), return ERR_VAL;);
}
if ((p_to != NULL) && (p_to->len == p_to->tot_len)) {
801095a: 687b ldr r3, [r7, #4]
801095c: 2b00 cmp r3, #0
801095e: d013 beq.n 8010988 <pbuf_copy+0x174>
8010960: 687b ldr r3, [r7, #4]
8010962: 895a ldrh r2, [r3, #10]
8010964: 687b ldr r3, [r7, #4]
8010966: 891b ldrh r3, [r3, #8]
8010968: 429a cmp r2, r3
801096a: d10d bne.n 8010988 <pbuf_copy+0x174>
/* don't copy more than one packet! */
LWIP_ERROR("pbuf_copy() does not allow packet queues!",
801096c: 687b ldr r3, [r7, #4]
801096e: 681b ldr r3, [r3, #0]
8010970: 2b00 cmp r3, #0
8010972: d009 beq.n 8010988 <pbuf_copy+0x174>
8010974: 4b09 ldr r3, [pc, #36] ; (801099c <pbuf_copy+0x188>)
8010976: f240 32ee movw r2, #1006 ; 0x3ee
801097a: 490e ldr r1, [pc, #56] ; (80109b4 <pbuf_copy+0x1a0>)
801097c: 4809 ldr r0, [pc, #36] ; (80109a4 <pbuf_copy+0x190>)
801097e: f00a fb21 bl 801afc4 <iprintf>
8010982: f06f 0305 mvn.w r3, #5
8010986: e004 b.n 8010992 <pbuf_copy+0x17e>
(p_to->next == NULL), return ERR_VAL;);
}
} while (p_from);
8010988: 683b ldr r3, [r7, #0]
801098a: 2b00 cmp r3, #0
801098c: f47f af61 bne.w 8010852 <pbuf_copy+0x3e>
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n"));
return ERR_OK;
8010990: 2300 movs r3, #0
}
8010992: 4618 mov r0, r3
8010994: 3718 adds r7, #24
8010996: 46bd mov sp, r7
8010998: bd80 pop {r7, pc}
801099a: bf00 nop
801099c: 0801c81c .word 0x0801c81c
80109a0: 0801cac4 .word 0x0801cac4
80109a4: 0801c87c .word 0x0801c87c
80109a8: 0801caf4 .word 0x0801caf4
80109ac: 0801cb0c .word 0x0801cb0c
80109b0: 0801cb28 .word 0x0801cb28
80109b4: 0801cb38 .word 0x0801cb38
080109b8 <pbuf_copy_partial>:
* @param offset offset into the packet buffer from where to begin copying len bytes
* @return the number of bytes copied, or 0 on failure
*/
u16_t
pbuf_copy_partial(const struct pbuf *buf, void *dataptr, u16_t len, u16_t offset)
{
80109b8: b580 push {r7, lr}
80109ba: b088 sub sp, #32
80109bc: af00 add r7, sp, #0
80109be: 60f8 str r0, [r7, #12]
80109c0: 60b9 str r1, [r7, #8]
80109c2: 4611 mov r1, r2
80109c4: 461a mov r2, r3
80109c6: 460b mov r3, r1
80109c8: 80fb strh r3, [r7, #6]
80109ca: 4613 mov r3, r2
80109cc: 80bb strh r3, [r7, #4]
const struct pbuf *p;
u16_t left = 0;
80109ce: 2300 movs r3, #0
80109d0: 837b strh r3, [r7, #26]
u16_t buf_copy_len;
u16_t copied_total = 0;
80109d2: 2300 movs r3, #0
80109d4: 82fb strh r3, [r7, #22]
LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;);
80109d6: 68fb ldr r3, [r7, #12]
80109d8: 2b00 cmp r3, #0
80109da: d108 bne.n 80109ee <pbuf_copy_partial+0x36>
80109dc: 4b2b ldr r3, [pc, #172] ; (8010a8c <pbuf_copy_partial+0xd4>)
80109de: f240 420a movw r2, #1034 ; 0x40a
80109e2: 492b ldr r1, [pc, #172] ; (8010a90 <pbuf_copy_partial+0xd8>)
80109e4: 482b ldr r0, [pc, #172] ; (8010a94 <pbuf_copy_partial+0xdc>)
80109e6: f00a faed bl 801afc4 <iprintf>
80109ea: 2300 movs r3, #0
80109ec: e04a b.n 8010a84 <pbuf_copy_partial+0xcc>
LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;);
80109ee: 68bb ldr r3, [r7, #8]
80109f0: 2b00 cmp r3, #0
80109f2: d108 bne.n 8010a06 <pbuf_copy_partial+0x4e>
80109f4: 4b25 ldr r3, [pc, #148] ; (8010a8c <pbuf_copy_partial+0xd4>)
80109f6: f240 420b movw r2, #1035 ; 0x40b
80109fa: 4927 ldr r1, [pc, #156] ; (8010a98 <pbuf_copy_partial+0xe0>)
80109fc: 4825 ldr r0, [pc, #148] ; (8010a94 <pbuf_copy_partial+0xdc>)
80109fe: f00a fae1 bl 801afc4 <iprintf>
8010a02: 2300 movs r3, #0
8010a04: e03e b.n 8010a84 <pbuf_copy_partial+0xcc>
/* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
for (p = buf; len != 0 && p != NULL; p = p->next) {
8010a06: 68fb ldr r3, [r7, #12]
8010a08: 61fb str r3, [r7, #28]
8010a0a: e034 b.n 8010a76 <pbuf_copy_partial+0xbe>
if ((offset != 0) && (offset >= p->len)) {
8010a0c: 88bb ldrh r3, [r7, #4]
8010a0e: 2b00 cmp r3, #0
8010a10: d00a beq.n 8010a28 <pbuf_copy_partial+0x70>
8010a12: 69fb ldr r3, [r7, #28]
8010a14: 895b ldrh r3, [r3, #10]
8010a16: 88ba ldrh r2, [r7, #4]
8010a18: 429a cmp r2, r3
8010a1a: d305 bcc.n 8010a28 <pbuf_copy_partial+0x70>
/* don't copy from this buffer -> on to the next */
offset = (u16_t)(offset - p->len);
8010a1c: 69fb ldr r3, [r7, #28]
8010a1e: 895b ldrh r3, [r3, #10]
8010a20: 88ba ldrh r2, [r7, #4]
8010a22: 1ad3 subs r3, r2, r3
8010a24: 80bb strh r3, [r7, #4]
8010a26: e023 b.n 8010a70 <pbuf_copy_partial+0xb8>
} else {
/* copy from this buffer. maybe only partially. */
buf_copy_len = (u16_t)(p->len - offset);
8010a28: 69fb ldr r3, [r7, #28]
8010a2a: 895a ldrh r2, [r3, #10]
8010a2c: 88bb ldrh r3, [r7, #4]
8010a2e: 1ad3 subs r3, r2, r3
8010a30: 833b strh r3, [r7, #24]
if (buf_copy_len > len) {
8010a32: 8b3a ldrh r2, [r7, #24]
8010a34: 88fb ldrh r3, [r7, #6]
8010a36: 429a cmp r2, r3
8010a38: d901 bls.n 8010a3e <pbuf_copy_partial+0x86>
buf_copy_len = len;
8010a3a: 88fb ldrh r3, [r7, #6]
8010a3c: 833b strh r3, [r7, #24]
}
/* copy the necessary parts of the buffer */
MEMCPY(&((char *)dataptr)[left], &((char *)p->payload)[offset], buf_copy_len);
8010a3e: 8b7b ldrh r3, [r7, #26]
8010a40: 68ba ldr r2, [r7, #8]
8010a42: 18d0 adds r0, r2, r3
8010a44: 69fb ldr r3, [r7, #28]
8010a46: 685a ldr r2, [r3, #4]
8010a48: 88bb ldrh r3, [r7, #4]
8010a4a: 4413 add r3, r2
8010a4c: 8b3a ldrh r2, [r7, #24]
8010a4e: 4619 mov r1, r3
8010a50: f00a faa2 bl 801af98 <memcpy>
copied_total = (u16_t)(copied_total + buf_copy_len);
8010a54: 8afa ldrh r2, [r7, #22]
8010a56: 8b3b ldrh r3, [r7, #24]
8010a58: 4413 add r3, r2
8010a5a: 82fb strh r3, [r7, #22]
left = (u16_t)(left + buf_copy_len);
8010a5c: 8b7a ldrh r2, [r7, #26]
8010a5e: 8b3b ldrh r3, [r7, #24]
8010a60: 4413 add r3, r2
8010a62: 837b strh r3, [r7, #26]
len = (u16_t)(len - buf_copy_len);
8010a64: 88fa ldrh r2, [r7, #6]
8010a66: 8b3b ldrh r3, [r7, #24]
8010a68: 1ad3 subs r3, r2, r3
8010a6a: 80fb strh r3, [r7, #6]
offset = 0;
8010a6c: 2300 movs r3, #0
8010a6e: 80bb strh r3, [r7, #4]
for (p = buf; len != 0 && p != NULL; p = p->next) {
8010a70: 69fb ldr r3, [r7, #28]
8010a72: 681b ldr r3, [r3, #0]
8010a74: 61fb str r3, [r7, #28]
8010a76: 88fb ldrh r3, [r7, #6]
8010a78: 2b00 cmp r3, #0
8010a7a: d002 beq.n 8010a82 <pbuf_copy_partial+0xca>
8010a7c: 69fb ldr r3, [r7, #28]
8010a7e: 2b00 cmp r3, #0
8010a80: d1c4 bne.n 8010a0c <pbuf_copy_partial+0x54>
}
}
return copied_total;
8010a82: 8afb ldrh r3, [r7, #22]
}
8010a84: 4618 mov r0, r3
8010a86: 3720 adds r7, #32
8010a88: 46bd mov sp, r7
8010a8a: bd80 pop {r7, pc}
8010a8c: 0801c81c .word 0x0801c81c
8010a90: 0801cb64 .word 0x0801cb64
8010a94: 0801c87c .word 0x0801c87c
8010a98: 0801cb84 .word 0x0801cb84
08010a9c <pbuf_clone>:
*
* @return a new pbuf or NULL if allocation fails
*/
struct pbuf *
pbuf_clone(pbuf_layer layer, pbuf_type type, struct pbuf *p)
{
8010a9c: b580 push {r7, lr}
8010a9e: b084 sub sp, #16
8010aa0: af00 add r7, sp, #0
8010aa2: 4603 mov r3, r0
8010aa4: 603a str r2, [r7, #0]
8010aa6: 71fb strb r3, [r7, #7]
8010aa8: 460b mov r3, r1
8010aaa: 80bb strh r3, [r7, #4]
struct pbuf *q;
err_t err;
q = pbuf_alloc(layer, p->tot_len, type);
8010aac: 683b ldr r3, [r7, #0]
8010aae: 8919 ldrh r1, [r3, #8]
8010ab0: 88ba ldrh r2, [r7, #4]
8010ab2: 79fb ldrb r3, [r7, #7]
8010ab4: 4618 mov r0, r3
8010ab6: f7ff fa95 bl 800ffe4 <pbuf_alloc>
8010aba: 60f8 str r0, [r7, #12]
if (q == NULL) {
8010abc: 68fb ldr r3, [r7, #12]
8010abe: 2b00 cmp r3, #0
8010ac0: d101 bne.n 8010ac6 <pbuf_clone+0x2a>
return NULL;
8010ac2: 2300 movs r3, #0
8010ac4: e011 b.n 8010aea <pbuf_clone+0x4e>
}
err = pbuf_copy(q, p);
8010ac6: 6839 ldr r1, [r7, #0]
8010ac8: 68f8 ldr r0, [r7, #12]
8010aca: f7ff fea3 bl 8010814 <pbuf_copy>
8010ace: 4603 mov r3, r0
8010ad0: 72fb strb r3, [r7, #11]
LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */
LWIP_ASSERT("pbuf_copy failed", err == ERR_OK);
8010ad2: f997 300b ldrsb.w r3, [r7, #11]
8010ad6: 2b00 cmp r3, #0
8010ad8: d006 beq.n 8010ae8 <pbuf_clone+0x4c>
8010ada: 4b06 ldr r3, [pc, #24] ; (8010af4 <pbuf_clone+0x58>)
8010adc: f240 5224 movw r2, #1316 ; 0x524
8010ae0: 4905 ldr r1, [pc, #20] ; (8010af8 <pbuf_clone+0x5c>)
8010ae2: 4806 ldr r0, [pc, #24] ; (8010afc <pbuf_clone+0x60>)
8010ae4: f00a fa6e bl 801afc4 <iprintf>
return q;
8010ae8: 68fb ldr r3, [r7, #12]
}
8010aea: 4618 mov r0, r3
8010aec: 3710 adds r7, #16
8010aee: 46bd mov sp, r7
8010af0: bd80 pop {r7, pc}
8010af2: bf00 nop
8010af4: 0801c81c .word 0x0801c81c
8010af8: 0801cc90 .word 0x0801cc90
8010afc: 0801c87c .word 0x0801c87c
08010b00 <tcp_init>:
/**
* Initialize this module.
*/
void
tcp_init(void)
{
8010b00: b580 push {r7, lr}
8010b02: af00 add r7, sp, #0
#ifdef LWIP_RAND
tcp_port = TCP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
8010b04: f00a fa76 bl 801aff4 <rand>
8010b08: 4603 mov r3, r0
8010b0a: b29b uxth r3, r3
8010b0c: f3c3 030d ubfx r3, r3, #0, #14
8010b10: b29b uxth r3, r3
8010b12: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000
8010b16: b29a uxth r2, r3
8010b18: 4b01 ldr r3, [pc, #4] ; (8010b20 <tcp_init+0x20>)
8010b1a: 801a strh r2, [r3, #0]
#endif /* LWIP_RAND */
}
8010b1c: bf00 nop
8010b1e: bd80 pop {r7, pc}
8010b20: 20000068 .word 0x20000068
08010b24 <tcp_free>:
/** Free a tcp pcb */
void
tcp_free(struct tcp_pcb *pcb)
{
8010b24: b580 push {r7, lr}
8010b26: b082 sub sp, #8
8010b28: af00 add r7, sp, #0
8010b2a: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_free: LISTEN", pcb->state != LISTEN);
8010b2c: 687b ldr r3, [r7, #4]
8010b2e: 7d1b ldrb r3, [r3, #20]
8010b30: 2b01 cmp r3, #1
8010b32: d105 bne.n 8010b40 <tcp_free+0x1c>
8010b34: 4b06 ldr r3, [pc, #24] ; (8010b50 <tcp_free+0x2c>)
8010b36: 22d4 movs r2, #212 ; 0xd4
8010b38: 4906 ldr r1, [pc, #24] ; (8010b54 <tcp_free+0x30>)
8010b3a: 4807 ldr r0, [pc, #28] ; (8010b58 <tcp_free+0x34>)
8010b3c: f00a fa42 bl 801afc4 <iprintf>
#if LWIP_TCP_PCB_NUM_EXT_ARGS
tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
#endif
memp_free(MEMP_TCP_PCB, pcb);
8010b40: 6879 ldr r1, [r7, #4]
8010b42: 2001 movs r0, #1
8010b44: f7fe fe82 bl 800f84c <memp_free>
}
8010b48: bf00 nop
8010b4a: 3708 adds r7, #8
8010b4c: 46bd mov sp, r7
8010b4e: bd80 pop {r7, pc}
8010b50: 0801cd1c .word 0x0801cd1c
8010b54: 0801cd4c .word 0x0801cd4c
8010b58: 0801cd60 .word 0x0801cd60
08010b5c <tcp_free_listen>:
/** Free a tcp listen pcb */
static void
tcp_free_listen(struct tcp_pcb *pcb)
{
8010b5c: b580 push {r7, lr}
8010b5e: b082 sub sp, #8
8010b60: af00 add r7, sp, #0
8010b62: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_free_listen: !LISTEN", pcb->state != LISTEN);
8010b64: 687b ldr r3, [r7, #4]
8010b66: 7d1b ldrb r3, [r3, #20]
8010b68: 2b01 cmp r3, #1
8010b6a: d105 bne.n 8010b78 <tcp_free_listen+0x1c>
8010b6c: 4b06 ldr r3, [pc, #24] ; (8010b88 <tcp_free_listen+0x2c>)
8010b6e: 22df movs r2, #223 ; 0xdf
8010b70: 4906 ldr r1, [pc, #24] ; (8010b8c <tcp_free_listen+0x30>)
8010b72: 4807 ldr r0, [pc, #28] ; (8010b90 <tcp_free_listen+0x34>)
8010b74: f00a fa26 bl 801afc4 <iprintf>
#if LWIP_TCP_PCB_NUM_EXT_ARGS
tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
#endif
memp_free(MEMP_TCP_PCB_LISTEN, pcb);
8010b78: 6879 ldr r1, [r7, #4]
8010b7a: 2002 movs r0, #2
8010b7c: f7fe fe66 bl 800f84c <memp_free>
}
8010b80: bf00 nop
8010b82: 3708 adds r7, #8
8010b84: 46bd mov sp, r7
8010b86: bd80 pop {r7, pc}
8010b88: 0801cd1c .word 0x0801cd1c
8010b8c: 0801cd88 .word 0x0801cd88
8010b90: 0801cd60 .word 0x0801cd60
08010b94 <tcp_tmr>:
/**
* Called periodically to dispatch TCP timers.
*/
void
tcp_tmr(void)
{
8010b94: b580 push {r7, lr}
8010b96: af00 add r7, sp, #0
/* Call tcp_fasttmr() every 250 ms */
tcp_fasttmr();
8010b98: f000 fea2 bl 80118e0 <tcp_fasttmr>
if (++tcp_timer & 1) {
8010b9c: 4b07 ldr r3, [pc, #28] ; (8010bbc <tcp_tmr+0x28>)
8010b9e: 781b ldrb r3, [r3, #0]
8010ba0: 3301 adds r3, #1
8010ba2: b2da uxtb r2, r3
8010ba4: 4b05 ldr r3, [pc, #20] ; (8010bbc <tcp_tmr+0x28>)
8010ba6: 701a strb r2, [r3, #0]
8010ba8: 4b04 ldr r3, [pc, #16] ; (8010bbc <tcp_tmr+0x28>)
8010baa: 781b ldrb r3, [r3, #0]
8010bac: f003 0301 and.w r3, r3, #1
8010bb0: 2b00 cmp r3, #0
8010bb2: d001 beq.n 8010bb8 <tcp_tmr+0x24>
/* Call tcp_slowtmr() every 500 ms, i.e., every other timer
tcp_tmr() is called. */
tcp_slowtmr();
8010bb4: f000 fb54 bl 8011260 <tcp_slowtmr>
}
}
8010bb8: bf00 nop
8010bba: bd80 pop {r7, pc}
8010bbc: 2000871d .word 0x2000871d
08010bc0 <tcp_remove_listener>:
/** Called when a listen pcb is closed. Iterates one pcb list and removes the
* closed listener pcb from pcb->listener if matching.
*/
static void
tcp_remove_listener(struct tcp_pcb *list, struct tcp_pcb_listen *lpcb)
{
8010bc0: b580 push {r7, lr}
8010bc2: b084 sub sp, #16
8010bc4: af00 add r7, sp, #0
8010bc6: 6078 str r0, [r7, #4]
8010bc8: 6039 str r1, [r7, #0]
struct tcp_pcb *pcb;
LWIP_ASSERT("tcp_remove_listener: invalid listener", lpcb != NULL);
8010bca: 683b ldr r3, [r7, #0]
8010bcc: 2b00 cmp r3, #0
8010bce: d105 bne.n 8010bdc <tcp_remove_listener+0x1c>
8010bd0: 4b0d ldr r3, [pc, #52] ; (8010c08 <tcp_remove_listener+0x48>)
8010bd2: 22ff movs r2, #255 ; 0xff
8010bd4: 490d ldr r1, [pc, #52] ; (8010c0c <tcp_remove_listener+0x4c>)
8010bd6: 480e ldr r0, [pc, #56] ; (8010c10 <tcp_remove_listener+0x50>)
8010bd8: f00a f9f4 bl 801afc4 <iprintf>
for (pcb = list; pcb != NULL; pcb = pcb->next) {
8010bdc: 687b ldr r3, [r7, #4]
8010bde: 60fb str r3, [r7, #12]
8010be0: e00a b.n 8010bf8 <tcp_remove_listener+0x38>
if (pcb->listener == lpcb) {
8010be2: 68fb ldr r3, [r7, #12]
8010be4: 6fdb ldr r3, [r3, #124] ; 0x7c
8010be6: 683a ldr r2, [r7, #0]
8010be8: 429a cmp r2, r3
8010bea: d102 bne.n 8010bf2 <tcp_remove_listener+0x32>
pcb->listener = NULL;
8010bec: 68fb ldr r3, [r7, #12]
8010bee: 2200 movs r2, #0
8010bf0: 67da str r2, [r3, #124] ; 0x7c
for (pcb = list; pcb != NULL; pcb = pcb->next) {
8010bf2: 68fb ldr r3, [r7, #12]
8010bf4: 68db ldr r3, [r3, #12]
8010bf6: 60fb str r3, [r7, #12]
8010bf8: 68fb ldr r3, [r7, #12]
8010bfa: 2b00 cmp r3, #0
8010bfc: d1f1 bne.n 8010be2 <tcp_remove_listener+0x22>
}
}
}
8010bfe: bf00 nop
8010c00: bf00 nop
8010c02: 3710 adds r7, #16
8010c04: 46bd mov sp, r7
8010c06: bd80 pop {r7, pc}
8010c08: 0801cd1c .word 0x0801cd1c
8010c0c: 0801cda4 .word 0x0801cda4
8010c10: 0801cd60 .word 0x0801cd60
08010c14 <tcp_listen_closed>:
/** Called when a listen pcb is closed. Iterates all pcb lists and removes the
* closed listener pcb from pcb->listener if matching.
*/
static void
tcp_listen_closed(struct tcp_pcb *pcb)
{
8010c14: b580 push {r7, lr}
8010c16: b084 sub sp, #16
8010c18: af00 add r7, sp, #0
8010c1a: 6078 str r0, [r7, #4]
#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
size_t i;
LWIP_ASSERT("pcb != NULL", pcb != NULL);
8010c1c: 687b ldr r3, [r7, #4]
8010c1e: 2b00 cmp r3, #0
8010c20: d106 bne.n 8010c30 <tcp_listen_closed+0x1c>
8010c22: 4b14 ldr r3, [pc, #80] ; (8010c74 <tcp_listen_closed+0x60>)
8010c24: f240 1211 movw r2, #273 ; 0x111
8010c28: 4913 ldr r1, [pc, #76] ; (8010c78 <tcp_listen_closed+0x64>)
8010c2a: 4814 ldr r0, [pc, #80] ; (8010c7c <tcp_listen_closed+0x68>)
8010c2c: f00a f9ca bl 801afc4 <iprintf>
LWIP_ASSERT("pcb->state == LISTEN", pcb->state == LISTEN);
8010c30: 687b ldr r3, [r7, #4]
8010c32: 7d1b ldrb r3, [r3, #20]
8010c34: 2b01 cmp r3, #1
8010c36: d006 beq.n 8010c46 <tcp_listen_closed+0x32>
8010c38: 4b0e ldr r3, [pc, #56] ; (8010c74 <tcp_listen_closed+0x60>)
8010c3a: f44f 7289 mov.w r2, #274 ; 0x112
8010c3e: 4910 ldr r1, [pc, #64] ; (8010c80 <tcp_listen_closed+0x6c>)
8010c40: 480e ldr r0, [pc, #56] ; (8010c7c <tcp_listen_closed+0x68>)
8010c42: f00a f9bf bl 801afc4 <iprintf>
for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
8010c46: 2301 movs r3, #1
8010c48: 60fb str r3, [r7, #12]
8010c4a: e00b b.n 8010c64 <tcp_listen_closed+0x50>
tcp_remove_listener(*tcp_pcb_lists[i], (struct tcp_pcb_listen *)pcb);
8010c4c: 4a0d ldr r2, [pc, #52] ; (8010c84 <tcp_listen_closed+0x70>)
8010c4e: 68fb ldr r3, [r7, #12]
8010c50: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8010c54: 681b ldr r3, [r3, #0]
8010c56: 6879 ldr r1, [r7, #4]
8010c58: 4618 mov r0, r3
8010c5a: f7ff ffb1 bl 8010bc0 <tcp_remove_listener>
for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
8010c5e: 68fb ldr r3, [r7, #12]
8010c60: 3301 adds r3, #1
8010c62: 60fb str r3, [r7, #12]
8010c64: 68fb ldr r3, [r7, #12]
8010c66: 2b03 cmp r3, #3
8010c68: d9f0 bls.n 8010c4c <tcp_listen_closed+0x38>
}
#endif
LWIP_UNUSED_ARG(pcb);
}
8010c6a: bf00 nop
8010c6c: bf00 nop
8010c6e: 3710 adds r7, #16
8010c70: 46bd mov sp, r7
8010c72: bd80 pop {r7, pc}
8010c74: 0801cd1c .word 0x0801cd1c
8010c78: 0801cdcc .word 0x0801cdcc
8010c7c: 0801cd60 .word 0x0801cd60
8010c80: 0801cdd8 .word 0x0801cdd8
8010c84: 08021004 .word 0x08021004
08010c88 <tcp_close_shutdown>:
* @return ERR_OK if connection has been closed
* another err_t if closing failed and pcb is not freed
*/
static err_t
tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data)
{
8010c88: b5b0 push {r4, r5, r7, lr}
8010c8a: b088 sub sp, #32
8010c8c: af04 add r7, sp, #16
8010c8e: 6078 str r0, [r7, #4]
8010c90: 460b mov r3, r1
8010c92: 70fb strb r3, [r7, #3]
LWIP_ASSERT("tcp_close_shutdown: invalid pcb", pcb != NULL);
8010c94: 687b ldr r3, [r7, #4]
8010c96: 2b00 cmp r3, #0
8010c98: d106 bne.n 8010ca8 <tcp_close_shutdown+0x20>
8010c9a: 4b63 ldr r3, [pc, #396] ; (8010e28 <tcp_close_shutdown+0x1a0>)
8010c9c: f44f 72af mov.w r2, #350 ; 0x15e
8010ca0: 4962 ldr r1, [pc, #392] ; (8010e2c <tcp_close_shutdown+0x1a4>)
8010ca2: 4863 ldr r0, [pc, #396] ; (8010e30 <tcp_close_shutdown+0x1a8>)
8010ca4: f00a f98e bl 801afc4 <iprintf>
if (rst_on_unacked_data && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
8010ca8: 78fb ldrb r3, [r7, #3]
8010caa: 2b00 cmp r3, #0
8010cac: d066 beq.n 8010d7c <tcp_close_shutdown+0xf4>
8010cae: 687b ldr r3, [r7, #4]
8010cb0: 7d1b ldrb r3, [r3, #20]
8010cb2: 2b04 cmp r3, #4
8010cb4: d003 beq.n 8010cbe <tcp_close_shutdown+0x36>
8010cb6: 687b ldr r3, [r7, #4]
8010cb8: 7d1b ldrb r3, [r3, #20]
8010cba: 2b07 cmp r3, #7
8010cbc: d15e bne.n 8010d7c <tcp_close_shutdown+0xf4>
if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND_MAX(pcb))) {
8010cbe: 687b ldr r3, [r7, #4]
8010cc0: 6f9b ldr r3, [r3, #120] ; 0x78
8010cc2: 2b00 cmp r3, #0
8010cc4: d104 bne.n 8010cd0 <tcp_close_shutdown+0x48>
8010cc6: 687b ldr r3, [r7, #4]
8010cc8: 8d1b ldrh r3, [r3, #40] ; 0x28
8010cca: f5b3 6f06 cmp.w r3, #2144 ; 0x860
8010cce: d055 beq.n 8010d7c <tcp_close_shutdown+0xf4>
/* Not all data received by application, send RST to tell the remote
side about this. */
LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED);
8010cd0: 687b ldr r3, [r7, #4]
8010cd2: 8b5b ldrh r3, [r3, #26]
8010cd4: f003 0310 and.w r3, r3, #16
8010cd8: 2b00 cmp r3, #0
8010cda: d106 bne.n 8010cea <tcp_close_shutdown+0x62>
8010cdc: 4b52 ldr r3, [pc, #328] ; (8010e28 <tcp_close_shutdown+0x1a0>)
8010cde: f44f 72b2 mov.w r2, #356 ; 0x164
8010ce2: 4954 ldr r1, [pc, #336] ; (8010e34 <tcp_close_shutdown+0x1ac>)
8010ce4: 4852 ldr r0, [pc, #328] ; (8010e30 <tcp_close_shutdown+0x1a8>)
8010ce6: f00a f96d bl 801afc4 <iprintf>
/* don't call tcp_abort here: we must not deallocate the pcb since
that might not be expected when calling tcp_close */
tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
8010cea: 687b ldr r3, [r7, #4]
8010cec: 6d18 ldr r0, [r3, #80] ; 0x50
8010cee: 687b ldr r3, [r7, #4]
8010cf0: 6a5c ldr r4, [r3, #36] ; 0x24
8010cf2: 687d ldr r5, [r7, #4]
8010cf4: 687b ldr r3, [r7, #4]
8010cf6: 3304 adds r3, #4
8010cf8: 687a ldr r2, [r7, #4]
8010cfa: 8ad2 ldrh r2, [r2, #22]
8010cfc: 6879 ldr r1, [r7, #4]
8010cfe: 8b09 ldrh r1, [r1, #24]
8010d00: 9102 str r1, [sp, #8]
8010d02: 9201 str r2, [sp, #4]
8010d04: 9300 str r3, [sp, #0]
8010d06: 462b mov r3, r5
8010d08: 4622 mov r2, r4
8010d0a: 4601 mov r1, r0
8010d0c: 6878 ldr r0, [r7, #4]
8010d0e: f004 fe8d bl 8015a2c <tcp_rst>
pcb->local_port, pcb->remote_port);
tcp_pcb_purge(pcb);
8010d12: 6878 ldr r0, [r7, #4]
8010d14: f001 f8c6 bl 8011ea4 <tcp_pcb_purge>
TCP_RMV_ACTIVE(pcb);
8010d18: 4b47 ldr r3, [pc, #284] ; (8010e38 <tcp_close_shutdown+0x1b0>)
8010d1a: 681b ldr r3, [r3, #0]
8010d1c: 687a ldr r2, [r7, #4]
8010d1e: 429a cmp r2, r3
8010d20: d105 bne.n 8010d2e <tcp_close_shutdown+0xa6>
8010d22: 4b45 ldr r3, [pc, #276] ; (8010e38 <tcp_close_shutdown+0x1b0>)
8010d24: 681b ldr r3, [r3, #0]
8010d26: 68db ldr r3, [r3, #12]
8010d28: 4a43 ldr r2, [pc, #268] ; (8010e38 <tcp_close_shutdown+0x1b0>)
8010d2a: 6013 str r3, [r2, #0]
8010d2c: e013 b.n 8010d56 <tcp_close_shutdown+0xce>
8010d2e: 4b42 ldr r3, [pc, #264] ; (8010e38 <tcp_close_shutdown+0x1b0>)
8010d30: 681b ldr r3, [r3, #0]
8010d32: 60fb str r3, [r7, #12]
8010d34: e00c b.n 8010d50 <tcp_close_shutdown+0xc8>
8010d36: 68fb ldr r3, [r7, #12]
8010d38: 68db ldr r3, [r3, #12]
8010d3a: 687a ldr r2, [r7, #4]
8010d3c: 429a cmp r2, r3
8010d3e: d104 bne.n 8010d4a <tcp_close_shutdown+0xc2>
8010d40: 687b ldr r3, [r7, #4]
8010d42: 68da ldr r2, [r3, #12]
8010d44: 68fb ldr r3, [r7, #12]
8010d46: 60da str r2, [r3, #12]
8010d48: e005 b.n 8010d56 <tcp_close_shutdown+0xce>
8010d4a: 68fb ldr r3, [r7, #12]
8010d4c: 68db ldr r3, [r3, #12]
8010d4e: 60fb str r3, [r7, #12]
8010d50: 68fb ldr r3, [r7, #12]
8010d52: 2b00 cmp r3, #0
8010d54: d1ef bne.n 8010d36 <tcp_close_shutdown+0xae>
8010d56: 687b ldr r3, [r7, #4]
8010d58: 2200 movs r2, #0
8010d5a: 60da str r2, [r3, #12]
8010d5c: 4b37 ldr r3, [pc, #220] ; (8010e3c <tcp_close_shutdown+0x1b4>)
8010d5e: 2201 movs r2, #1
8010d60: 701a strb r2, [r3, #0]
/* Deallocate the pcb since we already sent a RST for it */
if (tcp_input_pcb == pcb) {
8010d62: 4b37 ldr r3, [pc, #220] ; (8010e40 <tcp_close_shutdown+0x1b8>)
8010d64: 681b ldr r3, [r3, #0]
8010d66: 687a ldr r2, [r7, #4]
8010d68: 429a cmp r2, r3
8010d6a: d102 bne.n 8010d72 <tcp_close_shutdown+0xea>
/* prevent using a deallocated pcb: free it from tcp_input later */
tcp_trigger_input_pcb_close();
8010d6c: f003 fd5a bl 8014824 <tcp_trigger_input_pcb_close>
8010d70: e002 b.n 8010d78 <tcp_close_shutdown+0xf0>
} else {
tcp_free(pcb);
8010d72: 6878 ldr r0, [r7, #4]
8010d74: f7ff fed6 bl 8010b24 <tcp_free>
}
return ERR_OK;
8010d78: 2300 movs r3, #0
8010d7a: e050 b.n 8010e1e <tcp_close_shutdown+0x196>
}
}
/* - states which free the pcb are handled here,
- states which send FIN and change state are handled in tcp_close_shutdown_fin() */
switch (pcb->state) {
8010d7c: 687b ldr r3, [r7, #4]
8010d7e: 7d1b ldrb r3, [r3, #20]
8010d80: 2b02 cmp r3, #2
8010d82: d03b beq.n 8010dfc <tcp_close_shutdown+0x174>
8010d84: 2b02 cmp r3, #2
8010d86: dc44 bgt.n 8010e12 <tcp_close_shutdown+0x18a>
8010d88: 2b00 cmp r3, #0
8010d8a: d002 beq.n 8010d92 <tcp_close_shutdown+0x10a>
8010d8c: 2b01 cmp r3, #1
8010d8e: d02a beq.n 8010de6 <tcp_close_shutdown+0x15e>
8010d90: e03f b.n 8010e12 <tcp_close_shutdown+0x18a>
* and the user needs some way to free it should the need arise.
* Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
* or for a pcb that has been used and then entered the CLOSED state
* is erroneous, but this should never happen as the pcb has in those cases
* been freed, and so any remaining handles are bogus. */
if (pcb->local_port != 0) {
8010d92: 687b ldr r3, [r7, #4]
8010d94: 8adb ldrh r3, [r3, #22]
8010d96: 2b00 cmp r3, #0
8010d98: d021 beq.n 8010dde <tcp_close_shutdown+0x156>
TCP_RMV(&tcp_bound_pcbs, pcb);
8010d9a: 4b2a ldr r3, [pc, #168] ; (8010e44 <tcp_close_shutdown+0x1bc>)
8010d9c: 681b ldr r3, [r3, #0]
8010d9e: 687a ldr r2, [r7, #4]
8010da0: 429a cmp r2, r3
8010da2: d105 bne.n 8010db0 <tcp_close_shutdown+0x128>
8010da4: 4b27 ldr r3, [pc, #156] ; (8010e44 <tcp_close_shutdown+0x1bc>)
8010da6: 681b ldr r3, [r3, #0]
8010da8: 68db ldr r3, [r3, #12]
8010daa: 4a26 ldr r2, [pc, #152] ; (8010e44 <tcp_close_shutdown+0x1bc>)
8010dac: 6013 str r3, [r2, #0]
8010dae: e013 b.n 8010dd8 <tcp_close_shutdown+0x150>
8010db0: 4b24 ldr r3, [pc, #144] ; (8010e44 <tcp_close_shutdown+0x1bc>)
8010db2: 681b ldr r3, [r3, #0]
8010db4: 60bb str r3, [r7, #8]
8010db6: e00c b.n 8010dd2 <tcp_close_shutdown+0x14a>
8010db8: 68bb ldr r3, [r7, #8]
8010dba: 68db ldr r3, [r3, #12]
8010dbc: 687a ldr r2, [r7, #4]
8010dbe: 429a cmp r2, r3
8010dc0: d104 bne.n 8010dcc <tcp_close_shutdown+0x144>
8010dc2: 687b ldr r3, [r7, #4]
8010dc4: 68da ldr r2, [r3, #12]
8010dc6: 68bb ldr r3, [r7, #8]
8010dc8: 60da str r2, [r3, #12]
8010dca: e005 b.n 8010dd8 <tcp_close_shutdown+0x150>
8010dcc: 68bb ldr r3, [r7, #8]
8010dce: 68db ldr r3, [r3, #12]
8010dd0: 60bb str r3, [r7, #8]
8010dd2: 68bb ldr r3, [r7, #8]
8010dd4: 2b00 cmp r3, #0
8010dd6: d1ef bne.n 8010db8 <tcp_close_shutdown+0x130>
8010dd8: 687b ldr r3, [r7, #4]
8010dda: 2200 movs r2, #0
8010ddc: 60da str r2, [r3, #12]
}
tcp_free(pcb);
8010dde: 6878 ldr r0, [r7, #4]
8010de0: f7ff fea0 bl 8010b24 <tcp_free>
break;
8010de4: e01a b.n 8010e1c <tcp_close_shutdown+0x194>
case LISTEN:
tcp_listen_closed(pcb);
8010de6: 6878 ldr r0, [r7, #4]
8010de8: f7ff ff14 bl 8010c14 <tcp_listen_closed>
tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb);
8010dec: 6879 ldr r1, [r7, #4]
8010dee: 4816 ldr r0, [pc, #88] ; (8010e48 <tcp_close_shutdown+0x1c0>)
8010df0: f001 f8a8 bl 8011f44 <tcp_pcb_remove>
tcp_free_listen(pcb);
8010df4: 6878 ldr r0, [r7, #4]
8010df6: f7ff feb1 bl 8010b5c <tcp_free_listen>
break;
8010dfa: e00f b.n 8010e1c <tcp_close_shutdown+0x194>
case SYN_SENT:
TCP_PCB_REMOVE_ACTIVE(pcb);
8010dfc: 6879 ldr r1, [r7, #4]
8010dfe: 480e ldr r0, [pc, #56] ; (8010e38 <tcp_close_shutdown+0x1b0>)
8010e00: f001 f8a0 bl 8011f44 <tcp_pcb_remove>
8010e04: 4b0d ldr r3, [pc, #52] ; (8010e3c <tcp_close_shutdown+0x1b4>)
8010e06: 2201 movs r2, #1
8010e08: 701a strb r2, [r3, #0]
tcp_free(pcb);
8010e0a: 6878 ldr r0, [r7, #4]
8010e0c: f7ff fe8a bl 8010b24 <tcp_free>
MIB2_STATS_INC(mib2.tcpattemptfails);
break;
8010e10: e004 b.n 8010e1c <tcp_close_shutdown+0x194>
default:
return tcp_close_shutdown_fin(pcb);
8010e12: 6878 ldr r0, [r7, #4]
8010e14: f000 f81a bl 8010e4c <tcp_close_shutdown_fin>
8010e18: 4603 mov r3, r0
8010e1a: e000 b.n 8010e1e <tcp_close_shutdown+0x196>
}
return ERR_OK;
8010e1c: 2300 movs r3, #0
}
8010e1e: 4618 mov r0, r3
8010e20: 3710 adds r7, #16
8010e22: 46bd mov sp, r7
8010e24: bdb0 pop {r4, r5, r7, pc}
8010e26: bf00 nop
8010e28: 0801cd1c .word 0x0801cd1c
8010e2c: 0801cdf0 .word 0x0801cdf0
8010e30: 0801cd60 .word 0x0801cd60
8010e34: 0801ce10 .word 0x0801ce10
8010e38: 2000f83c .word 0x2000f83c
8010e3c: 2000f838 .word 0x2000f838
8010e40: 2000f850 .word 0x2000f850
8010e44: 2000f848 .word 0x2000f848
8010e48: 2000f844 .word 0x2000f844
08010e4c <tcp_close_shutdown_fin>:
static err_t
tcp_close_shutdown_fin(struct tcp_pcb *pcb)
{
8010e4c: b580 push {r7, lr}
8010e4e: b084 sub sp, #16
8010e50: af00 add r7, sp, #0
8010e52: 6078 str r0, [r7, #4]
err_t err;
LWIP_ASSERT("pcb != NULL", pcb != NULL);
8010e54: 687b ldr r3, [r7, #4]
8010e56: 2b00 cmp r3, #0
8010e58: d106 bne.n 8010e68 <tcp_close_shutdown_fin+0x1c>
8010e5a: 4b2e ldr r3, [pc, #184] ; (8010f14 <tcp_close_shutdown_fin+0xc8>)
8010e5c: f44f 72ce mov.w r2, #412 ; 0x19c
8010e60: 492d ldr r1, [pc, #180] ; (8010f18 <tcp_close_shutdown_fin+0xcc>)
8010e62: 482e ldr r0, [pc, #184] ; (8010f1c <tcp_close_shutdown_fin+0xd0>)
8010e64: f00a f8ae bl 801afc4 <iprintf>
switch (pcb->state) {
8010e68: 687b ldr r3, [r7, #4]
8010e6a: 7d1b ldrb r3, [r3, #20]
8010e6c: 2b07 cmp r3, #7
8010e6e: d020 beq.n 8010eb2 <tcp_close_shutdown_fin+0x66>
8010e70: 2b07 cmp r3, #7
8010e72: dc2b bgt.n 8010ecc <tcp_close_shutdown_fin+0x80>
8010e74: 2b03 cmp r3, #3
8010e76: d002 beq.n 8010e7e <tcp_close_shutdown_fin+0x32>
8010e78: 2b04 cmp r3, #4
8010e7a: d00d beq.n 8010e98 <tcp_close_shutdown_fin+0x4c>
8010e7c: e026 b.n 8010ecc <tcp_close_shutdown_fin+0x80>
case SYN_RCVD:
err = tcp_send_fin(pcb);
8010e7e: 6878 ldr r0, [r7, #4]
8010e80: f003 fee2 bl 8014c48 <tcp_send_fin>
8010e84: 4603 mov r3, r0
8010e86: 73fb strb r3, [r7, #15]
if (err == ERR_OK) {
8010e88: f997 300f ldrsb.w r3, [r7, #15]
8010e8c: 2b00 cmp r3, #0
8010e8e: d11f bne.n 8010ed0 <tcp_close_shutdown_fin+0x84>
tcp_backlog_accepted(pcb);
MIB2_STATS_INC(mib2.tcpattemptfails);
pcb->state = FIN_WAIT_1;
8010e90: 687b ldr r3, [r7, #4]
8010e92: 2205 movs r2, #5
8010e94: 751a strb r2, [r3, #20]
}
break;
8010e96: e01b b.n 8010ed0 <tcp_close_shutdown_fin+0x84>
case ESTABLISHED:
err = tcp_send_fin(pcb);
8010e98: 6878 ldr r0, [r7, #4]
8010e9a: f003 fed5 bl 8014c48 <tcp_send_fin>
8010e9e: 4603 mov r3, r0
8010ea0: 73fb strb r3, [r7, #15]
if (err == ERR_OK) {
8010ea2: f997 300f ldrsb.w r3, [r7, #15]
8010ea6: 2b00 cmp r3, #0
8010ea8: d114 bne.n 8010ed4 <tcp_close_shutdown_fin+0x88>
MIB2_STATS_INC(mib2.tcpestabresets);
pcb->state = FIN_WAIT_1;
8010eaa: 687b ldr r3, [r7, #4]
8010eac: 2205 movs r2, #5
8010eae: 751a strb r2, [r3, #20]
}
break;
8010eb0: e010 b.n 8010ed4 <tcp_close_shutdown_fin+0x88>
case CLOSE_WAIT:
err = tcp_send_fin(pcb);
8010eb2: 6878 ldr r0, [r7, #4]
8010eb4: f003 fec8 bl 8014c48 <tcp_send_fin>
8010eb8: 4603 mov r3, r0
8010eba: 73fb strb r3, [r7, #15]
if (err == ERR_OK) {
8010ebc: f997 300f ldrsb.w r3, [r7, #15]
8010ec0: 2b00 cmp r3, #0
8010ec2: d109 bne.n 8010ed8 <tcp_close_shutdown_fin+0x8c>
MIB2_STATS_INC(mib2.tcpestabresets);
pcb->state = LAST_ACK;
8010ec4: 687b ldr r3, [r7, #4]
8010ec6: 2209 movs r2, #9
8010ec8: 751a strb r2, [r3, #20]
}
break;
8010eca: e005 b.n 8010ed8 <tcp_close_shutdown_fin+0x8c>
default:
/* Has already been closed, do nothing. */
return ERR_OK;
8010ecc: 2300 movs r3, #0
8010ece: e01c b.n 8010f0a <tcp_close_shutdown_fin+0xbe>
break;
8010ed0: bf00 nop
8010ed2: e002 b.n 8010eda <tcp_close_shutdown_fin+0x8e>
break;
8010ed4: bf00 nop
8010ed6: e000 b.n 8010eda <tcp_close_shutdown_fin+0x8e>
break;
8010ed8: bf00 nop
}
if (err == ERR_OK) {
8010eda: f997 300f ldrsb.w r3, [r7, #15]
8010ede: 2b00 cmp r3, #0
8010ee0: d103 bne.n 8010eea <tcp_close_shutdown_fin+0x9e>
/* To ensure all data has been sent when tcp_close returns, we have
to make sure tcp_output doesn't fail.
Since we don't really have to ensure all data has been sent when tcp_close
returns (unsent data is sent from tcp timer functions, also), we don't care
for the return value of tcp_output for now. */
tcp_output(pcb);
8010ee2: 6878 ldr r0, [r7, #4]
8010ee4: f003 ffee bl 8014ec4 <tcp_output>
8010ee8: e00d b.n 8010f06 <tcp_close_shutdown_fin+0xba>
} else if (err == ERR_MEM) {
8010eea: f997 300f ldrsb.w r3, [r7, #15]
8010eee: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8010ef2: d108 bne.n 8010f06 <tcp_close_shutdown_fin+0xba>
/* Mark this pcb for closing. Closing is retried from tcp_tmr. */
tcp_set_flags(pcb, TF_CLOSEPEND);
8010ef4: 687b ldr r3, [r7, #4]
8010ef6: 8b5b ldrh r3, [r3, #26]
8010ef8: f043 0308 orr.w r3, r3, #8
8010efc: b29a uxth r2, r3
8010efe: 687b ldr r3, [r7, #4]
8010f00: 835a strh r2, [r3, #26]
/* We have to return ERR_OK from here to indicate to the callers that this
pcb should not be used any more as it will be freed soon via tcp_tmr.
This is OK here since sending FIN does not guarantee a time frime for
actually freeing the pcb, either (it is left in closure states for
remote ACK or timeout) */
return ERR_OK;
8010f02: 2300 movs r3, #0
8010f04: e001 b.n 8010f0a <tcp_close_shutdown_fin+0xbe>
}
return err;
8010f06: f997 300f ldrsb.w r3, [r7, #15]
}
8010f0a: 4618 mov r0, r3
8010f0c: 3710 adds r7, #16
8010f0e: 46bd mov sp, r7
8010f10: bd80 pop {r7, pc}
8010f12: bf00 nop
8010f14: 0801cd1c .word 0x0801cd1c
8010f18: 0801cdcc .word 0x0801cdcc
8010f1c: 0801cd60 .word 0x0801cd60
08010f20 <tcp_close>:
* @return ERR_OK if connection has been closed
* another err_t if closing failed and pcb is not freed
*/
err_t
tcp_close(struct tcp_pcb *pcb)
{
8010f20: b580 push {r7, lr}
8010f22: b082 sub sp, #8
8010f24: af00 add r7, sp, #0
8010f26: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("tcp_close: invalid pcb", pcb != NULL, return ERR_ARG);
8010f28: 687b ldr r3, [r7, #4]
8010f2a: 2b00 cmp r3, #0
8010f2c: d109 bne.n 8010f42 <tcp_close+0x22>
8010f2e: 4b0f ldr r3, [pc, #60] ; (8010f6c <tcp_close+0x4c>)
8010f30: f44f 72f4 mov.w r2, #488 ; 0x1e8
8010f34: 490e ldr r1, [pc, #56] ; (8010f70 <tcp_close+0x50>)
8010f36: 480f ldr r0, [pc, #60] ; (8010f74 <tcp_close+0x54>)
8010f38: f00a f844 bl 801afc4 <iprintf>
8010f3c: f06f 030f mvn.w r3, #15
8010f40: e00f b.n 8010f62 <tcp_close+0x42>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in "));
tcp_debug_print_state(pcb->state);
if (pcb->state != LISTEN) {
8010f42: 687b ldr r3, [r7, #4]
8010f44: 7d1b ldrb r3, [r3, #20]
8010f46: 2b01 cmp r3, #1
8010f48: d006 beq.n 8010f58 <tcp_close+0x38>
/* Set a flag not to receive any more data... */
tcp_set_flags(pcb, TF_RXCLOSED);
8010f4a: 687b ldr r3, [r7, #4]
8010f4c: 8b5b ldrh r3, [r3, #26]
8010f4e: f043 0310 orr.w r3, r3, #16
8010f52: b29a uxth r2, r3
8010f54: 687b ldr r3, [r7, #4]
8010f56: 835a strh r2, [r3, #26]
}
/* ... and close */
return tcp_close_shutdown(pcb, 1);
8010f58: 2101 movs r1, #1
8010f5a: 6878 ldr r0, [r7, #4]
8010f5c: f7ff fe94 bl 8010c88 <tcp_close_shutdown>
8010f60: 4603 mov r3, r0
}
8010f62: 4618 mov r0, r3
8010f64: 3708 adds r7, #8
8010f66: 46bd mov sp, r7
8010f68: bd80 pop {r7, pc}
8010f6a: bf00 nop
8010f6c: 0801cd1c .word 0x0801cd1c
8010f70: 0801ce2c .word 0x0801ce2c
8010f74: 0801cd60 .word 0x0801cd60
08010f78 <tcp_abandon>:
* @param pcb the tcp_pcb to abort
* @param reset boolean to indicate whether a reset should be sent
*/
void
tcp_abandon(struct tcp_pcb *pcb, int reset)
{
8010f78: b580 push {r7, lr}
8010f7a: b08e sub sp, #56 ; 0x38
8010f7c: af04 add r7, sp, #16
8010f7e: 6078 str r0, [r7, #4]
8010f80: 6039 str r1, [r7, #0]
#endif /* LWIP_CALLBACK_API */
void *errf_arg;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("tcp_abandon: invalid pcb", pcb != NULL, return);
8010f82: 687b ldr r3, [r7, #4]
8010f84: 2b00 cmp r3, #0
8010f86: d107 bne.n 8010f98 <tcp_abandon+0x20>
8010f88: 4b52 ldr r3, [pc, #328] ; (80110d4 <tcp_abandon+0x15c>)
8010f8a: f240 223d movw r2, #573 ; 0x23d
8010f8e: 4952 ldr r1, [pc, #328] ; (80110d8 <tcp_abandon+0x160>)
8010f90: 4852 ldr r0, [pc, #328] ; (80110dc <tcp_abandon+0x164>)
8010f92: f00a f817 bl 801afc4 <iprintf>
8010f96: e099 b.n 80110cc <tcp_abandon+0x154>
/* pcb->state LISTEN not allowed here */
LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs",
8010f98: 687b ldr r3, [r7, #4]
8010f9a: 7d1b ldrb r3, [r3, #20]
8010f9c: 2b01 cmp r3, #1
8010f9e: d106 bne.n 8010fae <tcp_abandon+0x36>
8010fa0: 4b4c ldr r3, [pc, #304] ; (80110d4 <tcp_abandon+0x15c>)
8010fa2: f44f 7210 mov.w r2, #576 ; 0x240
8010fa6: 494e ldr r1, [pc, #312] ; (80110e0 <tcp_abandon+0x168>)
8010fa8: 484c ldr r0, [pc, #304] ; (80110dc <tcp_abandon+0x164>)
8010faa: f00a f80b bl 801afc4 <iprintf>
pcb->state != LISTEN);
/* Figure out on which TCP PCB list we are, and remove us. If we
are in an active state, call the receive function associated with
the PCB with a NULL argument, and send an RST to the remote end. */
if (pcb->state == TIME_WAIT) {
8010fae: 687b ldr r3, [r7, #4]
8010fb0: 7d1b ldrb r3, [r3, #20]
8010fb2: 2b0a cmp r3, #10
8010fb4: d107 bne.n 8010fc6 <tcp_abandon+0x4e>
tcp_pcb_remove(&tcp_tw_pcbs, pcb);
8010fb6: 6879 ldr r1, [r7, #4]
8010fb8: 484a ldr r0, [pc, #296] ; (80110e4 <tcp_abandon+0x16c>)
8010fba: f000 ffc3 bl 8011f44 <tcp_pcb_remove>
tcp_free(pcb);
8010fbe: 6878 ldr r0, [r7, #4]
8010fc0: f7ff fdb0 bl 8010b24 <tcp_free>
8010fc4: e082 b.n 80110cc <tcp_abandon+0x154>
} else {
int send_rst = 0;
8010fc6: 2300 movs r3, #0
8010fc8: 627b str r3, [r7, #36] ; 0x24
u16_t local_port = 0;
8010fca: 2300 movs r3, #0
8010fcc: 847b strh r3, [r7, #34] ; 0x22
enum tcp_state last_state;
seqno = pcb->snd_nxt;
8010fce: 687b ldr r3, [r7, #4]
8010fd0: 6d1b ldr r3, [r3, #80] ; 0x50
8010fd2: 61bb str r3, [r7, #24]
ackno = pcb->rcv_nxt;
8010fd4: 687b ldr r3, [r7, #4]
8010fd6: 6a5b ldr r3, [r3, #36] ; 0x24
8010fd8: 617b str r3, [r7, #20]
#if LWIP_CALLBACK_API
errf = pcb->errf;
8010fda: 687b ldr r3, [r7, #4]
8010fdc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8010fe0: 613b str r3, [r7, #16]
#endif /* LWIP_CALLBACK_API */
errf_arg = pcb->callback_arg;
8010fe2: 687b ldr r3, [r7, #4]
8010fe4: 691b ldr r3, [r3, #16]
8010fe6: 60fb str r3, [r7, #12]
if (pcb->state == CLOSED) {
8010fe8: 687b ldr r3, [r7, #4]
8010fea: 7d1b ldrb r3, [r3, #20]
8010fec: 2b00 cmp r3, #0
8010fee: d126 bne.n 801103e <tcp_abandon+0xc6>
if (pcb->local_port != 0) {
8010ff0: 687b ldr r3, [r7, #4]
8010ff2: 8adb ldrh r3, [r3, #22]
8010ff4: 2b00 cmp r3, #0
8010ff6: d02e beq.n 8011056 <tcp_abandon+0xde>
/* bound, not yet opened */
TCP_RMV(&tcp_bound_pcbs, pcb);
8010ff8: 4b3b ldr r3, [pc, #236] ; (80110e8 <tcp_abandon+0x170>)
8010ffa: 681b ldr r3, [r3, #0]
8010ffc: 687a ldr r2, [r7, #4]
8010ffe: 429a cmp r2, r3
8011000: d105 bne.n 801100e <tcp_abandon+0x96>
8011002: 4b39 ldr r3, [pc, #228] ; (80110e8 <tcp_abandon+0x170>)
8011004: 681b ldr r3, [r3, #0]
8011006: 68db ldr r3, [r3, #12]
8011008: 4a37 ldr r2, [pc, #220] ; (80110e8 <tcp_abandon+0x170>)
801100a: 6013 str r3, [r2, #0]
801100c: e013 b.n 8011036 <tcp_abandon+0xbe>
801100e: 4b36 ldr r3, [pc, #216] ; (80110e8 <tcp_abandon+0x170>)
8011010: 681b ldr r3, [r3, #0]
8011012: 61fb str r3, [r7, #28]
8011014: e00c b.n 8011030 <tcp_abandon+0xb8>
8011016: 69fb ldr r3, [r7, #28]
8011018: 68db ldr r3, [r3, #12]
801101a: 687a ldr r2, [r7, #4]
801101c: 429a cmp r2, r3
801101e: d104 bne.n 801102a <tcp_abandon+0xb2>
8011020: 687b ldr r3, [r7, #4]
8011022: 68da ldr r2, [r3, #12]
8011024: 69fb ldr r3, [r7, #28]
8011026: 60da str r2, [r3, #12]
8011028: e005 b.n 8011036 <tcp_abandon+0xbe>
801102a: 69fb ldr r3, [r7, #28]
801102c: 68db ldr r3, [r3, #12]
801102e: 61fb str r3, [r7, #28]
8011030: 69fb ldr r3, [r7, #28]
8011032: 2b00 cmp r3, #0
8011034: d1ef bne.n 8011016 <tcp_abandon+0x9e>
8011036: 687b ldr r3, [r7, #4]
8011038: 2200 movs r2, #0
801103a: 60da str r2, [r3, #12]
801103c: e00b b.n 8011056 <tcp_abandon+0xde>
}
} else {
send_rst = reset;
801103e: 683b ldr r3, [r7, #0]
8011040: 627b str r3, [r7, #36] ; 0x24
local_port = pcb->local_port;
8011042: 687b ldr r3, [r7, #4]
8011044: 8adb ldrh r3, [r3, #22]
8011046: 847b strh r3, [r7, #34] ; 0x22
TCP_PCB_REMOVE_ACTIVE(pcb);
8011048: 6879 ldr r1, [r7, #4]
801104a: 4828 ldr r0, [pc, #160] ; (80110ec <tcp_abandon+0x174>)
801104c: f000 ff7a bl 8011f44 <tcp_pcb_remove>
8011050: 4b27 ldr r3, [pc, #156] ; (80110f0 <tcp_abandon+0x178>)
8011052: 2201 movs r2, #1
8011054: 701a strb r2, [r3, #0]
}
if (pcb->unacked != NULL) {
8011056: 687b ldr r3, [r7, #4]
8011058: 6f1b ldr r3, [r3, #112] ; 0x70
801105a: 2b00 cmp r3, #0
801105c: d004 beq.n 8011068 <tcp_abandon+0xf0>
tcp_segs_free(pcb->unacked);
801105e: 687b ldr r3, [r7, #4]
8011060: 6f1b ldr r3, [r3, #112] ; 0x70
8011062: 4618 mov r0, r3
8011064: f000 fd1c bl 8011aa0 <tcp_segs_free>
}
if (pcb->unsent != NULL) {
8011068: 687b ldr r3, [r7, #4]
801106a: 6edb ldr r3, [r3, #108] ; 0x6c
801106c: 2b00 cmp r3, #0
801106e: d004 beq.n 801107a <tcp_abandon+0x102>
tcp_segs_free(pcb->unsent);
8011070: 687b ldr r3, [r7, #4]
8011072: 6edb ldr r3, [r3, #108] ; 0x6c
8011074: 4618 mov r0, r3
8011076: f000 fd13 bl 8011aa0 <tcp_segs_free>
}
#if TCP_QUEUE_OOSEQ
if (pcb->ooseq != NULL) {
801107a: 687b ldr r3, [r7, #4]
801107c: 6f5b ldr r3, [r3, #116] ; 0x74
801107e: 2b00 cmp r3, #0
8011080: d004 beq.n 801108c <tcp_abandon+0x114>
tcp_segs_free(pcb->ooseq);
8011082: 687b ldr r3, [r7, #4]
8011084: 6f5b ldr r3, [r3, #116] ; 0x74
8011086: 4618 mov r0, r3
8011088: f000 fd0a bl 8011aa0 <tcp_segs_free>
}
#endif /* TCP_QUEUE_OOSEQ */
tcp_backlog_accepted(pcb);
if (send_rst) {
801108c: 6a7b ldr r3, [r7, #36] ; 0x24
801108e: 2b00 cmp r3, #0
8011090: d00e beq.n 80110b0 <tcp_abandon+0x138>
LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n"));
tcp_rst(pcb, seqno, ackno, &pcb->local_ip, &pcb->remote_ip, local_port, pcb->remote_port);
8011092: 6879 ldr r1, [r7, #4]
8011094: 687b ldr r3, [r7, #4]
8011096: 3304 adds r3, #4
8011098: 687a ldr r2, [r7, #4]
801109a: 8b12 ldrh r2, [r2, #24]
801109c: 9202 str r2, [sp, #8]
801109e: 8c7a ldrh r2, [r7, #34] ; 0x22
80110a0: 9201 str r2, [sp, #4]
80110a2: 9300 str r3, [sp, #0]
80110a4: 460b mov r3, r1
80110a6: 697a ldr r2, [r7, #20]
80110a8: 69b9 ldr r1, [r7, #24]
80110aa: 6878 ldr r0, [r7, #4]
80110ac: f004 fcbe bl 8015a2c <tcp_rst>
}
last_state = pcb->state;
80110b0: 687b ldr r3, [r7, #4]
80110b2: 7d1b ldrb r3, [r3, #20]
80110b4: 72fb strb r3, [r7, #11]
tcp_free(pcb);
80110b6: 6878 ldr r0, [r7, #4]
80110b8: f7ff fd34 bl 8010b24 <tcp_free>
TCP_EVENT_ERR(last_state, errf, errf_arg, ERR_ABRT);
80110bc: 693b ldr r3, [r7, #16]
80110be: 2b00 cmp r3, #0
80110c0: d004 beq.n 80110cc <tcp_abandon+0x154>
80110c2: 693b ldr r3, [r7, #16]
80110c4: f06f 010c mvn.w r1, #12
80110c8: 68f8 ldr r0, [r7, #12]
80110ca: 4798 blx r3
}
}
80110cc: 3728 adds r7, #40 ; 0x28
80110ce: 46bd mov sp, r7
80110d0: bd80 pop {r7, pc}
80110d2: bf00 nop
80110d4: 0801cd1c .word 0x0801cd1c
80110d8: 0801ce60 .word 0x0801ce60
80110dc: 0801cd60 .word 0x0801cd60
80110e0: 0801ce7c .word 0x0801ce7c
80110e4: 2000f84c .word 0x2000f84c
80110e8: 2000f848 .word 0x2000f848
80110ec: 2000f83c .word 0x2000f83c
80110f0: 2000f838 .word 0x2000f838
080110f4 <tcp_abort>:
*
* @param pcb the tcp pcb to abort
*/
void
tcp_abort(struct tcp_pcb *pcb)
{
80110f4: b580 push {r7, lr}
80110f6: b082 sub sp, #8
80110f8: af00 add r7, sp, #0
80110fa: 6078 str r0, [r7, #4]
tcp_abandon(pcb, 1);
80110fc: 2101 movs r1, #1
80110fe: 6878 ldr r0, [r7, #4]
8011100: f7ff ff3a bl 8010f78 <tcp_abandon>
}
8011104: bf00 nop
8011106: 3708 adds r7, #8
8011108: 46bd mov sp, r7
801110a: bd80 pop {r7, pc}
0801110c <tcp_update_rcv_ann_wnd>:
* Returns how much extra window would be advertised if we sent an
* update now.
*/
u32_t
tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb)
{
801110c: b580 push {r7, lr}
801110e: b084 sub sp, #16
8011110: af00 add r7, sp, #0
8011112: 6078 str r0, [r7, #4]
u32_t new_right_edge;
LWIP_ASSERT("tcp_update_rcv_ann_wnd: invalid pcb", pcb != NULL);
8011114: 687b ldr r3, [r7, #4]
8011116: 2b00 cmp r3, #0
8011118: d106 bne.n 8011128 <tcp_update_rcv_ann_wnd+0x1c>
801111a: 4b25 ldr r3, [pc, #148] ; (80111b0 <tcp_update_rcv_ann_wnd+0xa4>)
801111c: f240 32a6 movw r2, #934 ; 0x3a6
8011120: 4924 ldr r1, [pc, #144] ; (80111b4 <tcp_update_rcv_ann_wnd+0xa8>)
8011122: 4825 ldr r0, [pc, #148] ; (80111b8 <tcp_update_rcv_ann_wnd+0xac>)
8011124: f009 ff4e bl 801afc4 <iprintf>
new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd;
8011128: 687b ldr r3, [r7, #4]
801112a: 6a5b ldr r3, [r3, #36] ; 0x24
801112c: 687a ldr r2, [r7, #4]
801112e: 8d12 ldrh r2, [r2, #40] ; 0x28
8011130: 4413 add r3, r2
8011132: 60fb str r3, [r7, #12]
if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) {
8011134: 687b ldr r3, [r7, #4]
8011136: 6adb ldr r3, [r3, #44] ; 0x2c
8011138: 687a ldr r2, [r7, #4]
801113a: 8e52 ldrh r2, [r2, #50] ; 0x32
801113c: f5b2 6f86 cmp.w r2, #1072 ; 0x430
8011140: bf28 it cs
8011142: f44f 6286 movcs.w r2, #1072 ; 0x430
8011146: b292 uxth r2, r2
8011148: 4413 add r3, r2
801114a: 68fa ldr r2, [r7, #12]
801114c: 1ad3 subs r3, r2, r3
801114e: 2b00 cmp r3, #0
8011150: db08 blt.n 8011164 <tcp_update_rcv_ann_wnd+0x58>
/* we can advertise more window */
pcb->rcv_ann_wnd = pcb->rcv_wnd;
8011152: 687b ldr r3, [r7, #4]
8011154: 8d1a ldrh r2, [r3, #40] ; 0x28
8011156: 687b ldr r3, [r7, #4]
8011158: 855a strh r2, [r3, #42] ; 0x2a
return new_right_edge - pcb->rcv_ann_right_edge;
801115a: 687b ldr r3, [r7, #4]
801115c: 6adb ldr r3, [r3, #44] ; 0x2c
801115e: 68fa ldr r2, [r7, #12]
8011160: 1ad3 subs r3, r2, r3
8011162: e020 b.n 80111a6 <tcp_update_rcv_ann_wnd+0x9a>
} else {
if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) {
8011164: 687b ldr r3, [r7, #4]
8011166: 6a5a ldr r2, [r3, #36] ; 0x24
8011168: 687b ldr r3, [r7, #4]
801116a: 6adb ldr r3, [r3, #44] ; 0x2c
801116c: 1ad3 subs r3, r2, r3
801116e: 2b00 cmp r3, #0
8011170: dd03 ble.n 801117a <tcp_update_rcv_ann_wnd+0x6e>
/* Can happen due to other end sending out of advertised window,
* but within actual available (but not yet advertised) window */
pcb->rcv_ann_wnd = 0;
8011172: 687b ldr r3, [r7, #4]
8011174: 2200 movs r2, #0
8011176: 855a strh r2, [r3, #42] ; 0x2a
8011178: e014 b.n 80111a4 <tcp_update_rcv_ann_wnd+0x98>
} else {
/* keep the right edge of window constant */
u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt;
801117a: 687b ldr r3, [r7, #4]
801117c: 6ada ldr r2, [r3, #44] ; 0x2c
801117e: 687b ldr r3, [r7, #4]
8011180: 6a5b ldr r3, [r3, #36] ; 0x24
8011182: 1ad3 subs r3, r2, r3
8011184: 60bb str r3, [r7, #8]
#if !LWIP_WND_SCALE
LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff);
8011186: 68bb ldr r3, [r7, #8]
8011188: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
801118c: d306 bcc.n 801119c <tcp_update_rcv_ann_wnd+0x90>
801118e: 4b08 ldr r3, [pc, #32] ; (80111b0 <tcp_update_rcv_ann_wnd+0xa4>)
8011190: f240 32b6 movw r2, #950 ; 0x3b6
8011194: 4909 ldr r1, [pc, #36] ; (80111bc <tcp_update_rcv_ann_wnd+0xb0>)
8011196: 4808 ldr r0, [pc, #32] ; (80111b8 <tcp_update_rcv_ann_wnd+0xac>)
8011198: f009 ff14 bl 801afc4 <iprintf>
#endif
pcb->rcv_ann_wnd = (tcpwnd_size_t)new_rcv_ann_wnd;
801119c: 68bb ldr r3, [r7, #8]
801119e: b29a uxth r2, r3
80111a0: 687b ldr r3, [r7, #4]
80111a2: 855a strh r2, [r3, #42] ; 0x2a
}
return 0;
80111a4: 2300 movs r3, #0
}
}
80111a6: 4618 mov r0, r3
80111a8: 3710 adds r7, #16
80111aa: 46bd mov sp, r7
80111ac: bd80 pop {r7, pc}
80111ae: bf00 nop
80111b0: 0801cd1c .word 0x0801cd1c
80111b4: 0801cf78 .word 0x0801cf78
80111b8: 0801cd60 .word 0x0801cd60
80111bc: 0801cf9c .word 0x0801cf9c
080111c0 <tcp_recved>:
* @param pcb the tcp_pcb for which data is read
* @param len the amount of bytes that have been read by the application
*/
void
tcp_recved(struct tcp_pcb *pcb, u16_t len)
{
80111c0: b580 push {r7, lr}
80111c2: b084 sub sp, #16
80111c4: af00 add r7, sp, #0
80111c6: 6078 str r0, [r7, #4]
80111c8: 460b mov r3, r1
80111ca: 807b strh r3, [r7, #2]
u32_t wnd_inflation;
tcpwnd_size_t rcv_wnd;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("tcp_recved: invalid pcb", pcb != NULL, return);
80111cc: 687b ldr r3, [r7, #4]
80111ce: 2b00 cmp r3, #0
80111d0: d107 bne.n 80111e2 <tcp_recved+0x22>
80111d2: 4b1f ldr r3, [pc, #124] ; (8011250 <tcp_recved+0x90>)
80111d4: f240 32cf movw r2, #975 ; 0x3cf
80111d8: 491e ldr r1, [pc, #120] ; (8011254 <tcp_recved+0x94>)
80111da: 481f ldr r0, [pc, #124] ; (8011258 <tcp_recved+0x98>)
80111dc: f009 fef2 bl 801afc4 <iprintf>
80111e0: e032 b.n 8011248 <tcp_recved+0x88>
/* pcb->state LISTEN not allowed here */
LWIP_ASSERT("don't call tcp_recved for listen-pcbs",
80111e2: 687b ldr r3, [r7, #4]
80111e4: 7d1b ldrb r3, [r3, #20]
80111e6: 2b01 cmp r3, #1
80111e8: d106 bne.n 80111f8 <tcp_recved+0x38>
80111ea: 4b19 ldr r3, [pc, #100] ; (8011250 <tcp_recved+0x90>)
80111ec: f240 32d2 movw r2, #978 ; 0x3d2
80111f0: 491a ldr r1, [pc, #104] ; (801125c <tcp_recved+0x9c>)
80111f2: 4819 ldr r0, [pc, #100] ; (8011258 <tcp_recved+0x98>)
80111f4: f009 fee6 bl 801afc4 <iprintf>
pcb->state != LISTEN);
rcv_wnd = (tcpwnd_size_t)(pcb->rcv_wnd + len);
80111f8: 687b ldr r3, [r7, #4]
80111fa: 8d1a ldrh r2, [r3, #40] ; 0x28
80111fc: 887b ldrh r3, [r7, #2]
80111fe: 4413 add r3, r2
8011200: 81fb strh r3, [r7, #14]
if ((rcv_wnd > TCP_WND_MAX(pcb)) || (rcv_wnd < pcb->rcv_wnd)) {
8011202: 89fb ldrh r3, [r7, #14]
8011204: f5b3 6f06 cmp.w r3, #2144 ; 0x860
8011208: d804 bhi.n 8011214 <tcp_recved+0x54>
801120a: 687b ldr r3, [r7, #4]
801120c: 8d1b ldrh r3, [r3, #40] ; 0x28
801120e: 89fa ldrh r2, [r7, #14]
8011210: 429a cmp r2, r3
8011212: d204 bcs.n 801121e <tcp_recved+0x5e>
/* window got too big or tcpwnd_size_t overflow */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: window got too big or tcpwnd_size_t overflow\n"));
pcb->rcv_wnd = TCP_WND_MAX(pcb);
8011214: 687b ldr r3, [r7, #4]
8011216: f44f 6206 mov.w r2, #2144 ; 0x860
801121a: 851a strh r2, [r3, #40] ; 0x28
801121c: e002 b.n 8011224 <tcp_recved+0x64>
} else {
pcb->rcv_wnd = rcv_wnd;
801121e: 687b ldr r3, [r7, #4]
8011220: 89fa ldrh r2, [r7, #14]
8011222: 851a strh r2, [r3, #40] ; 0x28
}
wnd_inflation = tcp_update_rcv_ann_wnd(pcb);
8011224: 6878 ldr r0, [r7, #4]
8011226: f7ff ff71 bl 801110c <tcp_update_rcv_ann_wnd>
801122a: 60b8 str r0, [r7, #8]
/* If the change in the right edge of window is significant (default
* watermark is TCP_WND/4), then send an explicit update now.
* Otherwise wait for a packet to be sent in the normal course of
* events (or more window to be available later) */
if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) {
801122c: 68bb ldr r3, [r7, #8]
801122e: f5b3 7f06 cmp.w r3, #536 ; 0x218
8011232: d309 bcc.n 8011248 <tcp_recved+0x88>
tcp_ack_now(pcb);
8011234: 687b ldr r3, [r7, #4]
8011236: 8b5b ldrh r3, [r3, #26]
8011238: f043 0302 orr.w r3, r3, #2
801123c: b29a uxth r2, r3
801123e: 687b ldr r3, [r7, #4]
8011240: 835a strh r2, [r3, #26]
tcp_output(pcb);
8011242: 6878 ldr r0, [r7, #4]
8011244: f003 fe3e bl 8014ec4 <tcp_output>
}
LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: received %"U16_F" bytes, wnd %"TCPWNDSIZE_F" (%"TCPWNDSIZE_F").\n",
len, pcb->rcv_wnd, (u16_t)(TCP_WND_MAX(pcb) - pcb->rcv_wnd)));
}
8011248: 3710 adds r7, #16
801124a: 46bd mov sp, r7
801124c: bd80 pop {r7, pc}
801124e: bf00 nop
8011250: 0801cd1c .word 0x0801cd1c
8011254: 0801cfb8 .word 0x0801cfb8
8011258: 0801cd60 .word 0x0801cd60
801125c: 0801cfd0 .word 0x0801cfd0
08011260 <tcp_slowtmr>:
*
* Automatically called from tcp_tmr().
*/
void
tcp_slowtmr(void)
{
8011260: b5b0 push {r4, r5, r7, lr}
8011262: b090 sub sp, #64 ; 0x40
8011264: af04 add r7, sp, #16
tcpwnd_size_t eff_wnd;
u8_t pcb_remove; /* flag if a PCB should be removed */
u8_t pcb_reset; /* flag if a RST should be sent when removing */
err_t err;
err = ERR_OK;
8011266: 2300 movs r3, #0
8011268: f887 3025 strb.w r3, [r7, #37] ; 0x25
++tcp_ticks;
801126c: 4b94 ldr r3, [pc, #592] ; (80114c0 <tcp_slowtmr+0x260>)
801126e: 681b ldr r3, [r3, #0]
8011270: 3301 adds r3, #1
8011272: 4a93 ldr r2, [pc, #588] ; (80114c0 <tcp_slowtmr+0x260>)
8011274: 6013 str r3, [r2, #0]
++tcp_timer_ctr;
8011276: 4b93 ldr r3, [pc, #588] ; (80114c4 <tcp_slowtmr+0x264>)
8011278: 781b ldrb r3, [r3, #0]
801127a: 3301 adds r3, #1
801127c: b2da uxtb r2, r3
801127e: 4b91 ldr r3, [pc, #580] ; (80114c4 <tcp_slowtmr+0x264>)
8011280: 701a strb r2, [r3, #0]
tcp_slowtmr_start:
/* Steps through all of the active PCBs. */
prev = NULL;
8011282: 2300 movs r3, #0
8011284: 62bb str r3, [r7, #40] ; 0x28
pcb = tcp_active_pcbs;
8011286: 4b90 ldr r3, [pc, #576] ; (80114c8 <tcp_slowtmr+0x268>)
8011288: 681b ldr r3, [r3, #0]
801128a: 62fb str r3, [r7, #44] ; 0x2c
if (pcb == NULL) {
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
}
while (pcb != NULL) {
801128c: e29d b.n 80117ca <tcp_slowtmr+0x56a>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
801128e: 6afb ldr r3, [r7, #44] ; 0x2c
8011290: 7d1b ldrb r3, [r3, #20]
8011292: 2b00 cmp r3, #0
8011294: d106 bne.n 80112a4 <tcp_slowtmr+0x44>
8011296: 4b8d ldr r3, [pc, #564] ; (80114cc <tcp_slowtmr+0x26c>)
8011298: f240 42be movw r2, #1214 ; 0x4be
801129c: 498c ldr r1, [pc, #560] ; (80114d0 <tcp_slowtmr+0x270>)
801129e: 488d ldr r0, [pc, #564] ; (80114d4 <tcp_slowtmr+0x274>)
80112a0: f009 fe90 bl 801afc4 <iprintf>
LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
80112a4: 6afb ldr r3, [r7, #44] ; 0x2c
80112a6: 7d1b ldrb r3, [r3, #20]
80112a8: 2b01 cmp r3, #1
80112aa: d106 bne.n 80112ba <tcp_slowtmr+0x5a>
80112ac: 4b87 ldr r3, [pc, #540] ; (80114cc <tcp_slowtmr+0x26c>)
80112ae: f240 42bf movw r2, #1215 ; 0x4bf
80112b2: 4989 ldr r1, [pc, #548] ; (80114d8 <tcp_slowtmr+0x278>)
80112b4: 4887 ldr r0, [pc, #540] ; (80114d4 <tcp_slowtmr+0x274>)
80112b6: f009 fe85 bl 801afc4 <iprintf>
LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
80112ba: 6afb ldr r3, [r7, #44] ; 0x2c
80112bc: 7d1b ldrb r3, [r3, #20]
80112be: 2b0a cmp r3, #10
80112c0: d106 bne.n 80112d0 <tcp_slowtmr+0x70>
80112c2: 4b82 ldr r3, [pc, #520] ; (80114cc <tcp_slowtmr+0x26c>)
80112c4: f44f 6298 mov.w r2, #1216 ; 0x4c0
80112c8: 4984 ldr r1, [pc, #528] ; (80114dc <tcp_slowtmr+0x27c>)
80112ca: 4882 ldr r0, [pc, #520] ; (80114d4 <tcp_slowtmr+0x274>)
80112cc: f009 fe7a bl 801afc4 <iprintf>
if (pcb->last_timer == tcp_timer_ctr) {
80112d0: 6afb ldr r3, [r7, #44] ; 0x2c
80112d2: 7f9a ldrb r2, [r3, #30]
80112d4: 4b7b ldr r3, [pc, #492] ; (80114c4 <tcp_slowtmr+0x264>)
80112d6: 781b ldrb r3, [r3, #0]
80112d8: 429a cmp r2, r3
80112da: d105 bne.n 80112e8 <tcp_slowtmr+0x88>
/* skip this pcb, we have already processed it */
prev = pcb;
80112dc: 6afb ldr r3, [r7, #44] ; 0x2c
80112de: 62bb str r3, [r7, #40] ; 0x28
pcb = pcb->next;
80112e0: 6afb ldr r3, [r7, #44] ; 0x2c
80112e2: 68db ldr r3, [r3, #12]
80112e4: 62fb str r3, [r7, #44] ; 0x2c
continue;
80112e6: e270 b.n 80117ca <tcp_slowtmr+0x56a>
}
pcb->last_timer = tcp_timer_ctr;
80112e8: 4b76 ldr r3, [pc, #472] ; (80114c4 <tcp_slowtmr+0x264>)
80112ea: 781a ldrb r2, [r3, #0]
80112ec: 6afb ldr r3, [r7, #44] ; 0x2c
80112ee: 779a strb r2, [r3, #30]
pcb_remove = 0;
80112f0: 2300 movs r3, #0
80112f2: f887 3027 strb.w r3, [r7, #39] ; 0x27
pcb_reset = 0;
80112f6: 2300 movs r3, #0
80112f8: f887 3026 strb.w r3, [r7, #38] ; 0x26
if (pcb->state == SYN_SENT && pcb->nrtx >= TCP_SYNMAXRTX) {
80112fc: 6afb ldr r3, [r7, #44] ; 0x2c
80112fe: 7d1b ldrb r3, [r3, #20]
8011300: 2b02 cmp r3, #2
8011302: d10a bne.n 801131a <tcp_slowtmr+0xba>
8011304: 6afb ldr r3, [r7, #44] ; 0x2c
8011306: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
801130a: 2b05 cmp r3, #5
801130c: d905 bls.n 801131a <tcp_slowtmr+0xba>
++pcb_remove;
801130e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011312: 3301 adds r3, #1
8011314: f887 3027 strb.w r3, [r7, #39] ; 0x27
8011318: e11e b.n 8011558 <tcp_slowtmr+0x2f8>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
} else if (pcb->nrtx >= TCP_MAXRTX) {
801131a: 6afb ldr r3, [r7, #44] ; 0x2c
801131c: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
8011320: 2b0b cmp r3, #11
8011322: d905 bls.n 8011330 <tcp_slowtmr+0xd0>
++pcb_remove;
8011324: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011328: 3301 adds r3, #1
801132a: f887 3027 strb.w r3, [r7, #39] ; 0x27
801132e: e113 b.n 8011558 <tcp_slowtmr+0x2f8>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
} else {
if (pcb->persist_backoff > 0) {
8011330: 6afb ldr r3, [r7, #44] ; 0x2c
8011332: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
8011336: 2b00 cmp r3, #0
8011338: d075 beq.n 8011426 <tcp_slowtmr+0x1c6>
LWIP_ASSERT("tcp_slowtimr: persist ticking with in-flight data", pcb->unacked == NULL);
801133a: 6afb ldr r3, [r7, #44] ; 0x2c
801133c: 6f1b ldr r3, [r3, #112] ; 0x70
801133e: 2b00 cmp r3, #0
8011340: d006 beq.n 8011350 <tcp_slowtmr+0xf0>
8011342: 4b62 ldr r3, [pc, #392] ; (80114cc <tcp_slowtmr+0x26c>)
8011344: f240 42d4 movw r2, #1236 ; 0x4d4
8011348: 4965 ldr r1, [pc, #404] ; (80114e0 <tcp_slowtmr+0x280>)
801134a: 4862 ldr r0, [pc, #392] ; (80114d4 <tcp_slowtmr+0x274>)
801134c: f009 fe3a bl 801afc4 <iprintf>
LWIP_ASSERT("tcp_slowtimr: persist ticking with empty send buffer", pcb->unsent != NULL);
8011350: 6afb ldr r3, [r7, #44] ; 0x2c
8011352: 6edb ldr r3, [r3, #108] ; 0x6c
8011354: 2b00 cmp r3, #0
8011356: d106 bne.n 8011366 <tcp_slowtmr+0x106>
8011358: 4b5c ldr r3, [pc, #368] ; (80114cc <tcp_slowtmr+0x26c>)
801135a: f240 42d5 movw r2, #1237 ; 0x4d5
801135e: 4961 ldr r1, [pc, #388] ; (80114e4 <tcp_slowtmr+0x284>)
8011360: 485c ldr r0, [pc, #368] ; (80114d4 <tcp_slowtmr+0x274>)
8011362: f009 fe2f bl 801afc4 <iprintf>
if (pcb->persist_probe >= TCP_MAXRTX) {
8011366: 6afb ldr r3, [r7, #44] ; 0x2c
8011368: f893 309a ldrb.w r3, [r3, #154] ; 0x9a
801136c: 2b0b cmp r3, #11
801136e: d905 bls.n 801137c <tcp_slowtmr+0x11c>
++pcb_remove; /* max probes reached */
8011370: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011374: 3301 adds r3, #1
8011376: f887 3027 strb.w r3, [r7, #39] ; 0x27
801137a: e0ed b.n 8011558 <tcp_slowtmr+0x2f8>
} else {
u8_t backoff_cnt = tcp_persist_backoff[pcb->persist_backoff - 1];
801137c: 6afb ldr r3, [r7, #44] ; 0x2c
801137e: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
8011382: 3b01 subs r3, #1
8011384: 4a58 ldr r2, [pc, #352] ; (80114e8 <tcp_slowtmr+0x288>)
8011386: 5cd3 ldrb r3, [r2, r3]
8011388: 747b strb r3, [r7, #17]
if (pcb->persist_cnt < backoff_cnt) {
801138a: 6afb ldr r3, [r7, #44] ; 0x2c
801138c: f893 3098 ldrb.w r3, [r3, #152] ; 0x98
8011390: 7c7a ldrb r2, [r7, #17]
8011392: 429a cmp r2, r3
8011394: d907 bls.n 80113a6 <tcp_slowtmr+0x146>
pcb->persist_cnt++;
8011396: 6afb ldr r3, [r7, #44] ; 0x2c
8011398: f893 3098 ldrb.w r3, [r3, #152] ; 0x98
801139c: 3301 adds r3, #1
801139e: b2da uxtb r2, r3
80113a0: 6afb ldr r3, [r7, #44] ; 0x2c
80113a2: f883 2098 strb.w r2, [r3, #152] ; 0x98
}
if (pcb->persist_cnt >= backoff_cnt) {
80113a6: 6afb ldr r3, [r7, #44] ; 0x2c
80113a8: f893 3098 ldrb.w r3, [r3, #152] ; 0x98
80113ac: 7c7a ldrb r2, [r7, #17]
80113ae: 429a cmp r2, r3
80113b0: f200 80d2 bhi.w 8011558 <tcp_slowtmr+0x2f8>
int next_slot = 1; /* increment timer to next slot */
80113b4: 2301 movs r3, #1
80113b6: 623b str r3, [r7, #32]
/* If snd_wnd is zero, send 1 byte probes */
if (pcb->snd_wnd == 0) {
80113b8: 6afb ldr r3, [r7, #44] ; 0x2c
80113ba: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
80113be: 2b00 cmp r3, #0
80113c0: d108 bne.n 80113d4 <tcp_slowtmr+0x174>
if (tcp_zero_window_probe(pcb) != ERR_OK) {
80113c2: 6af8 ldr r0, [r7, #44] ; 0x2c
80113c4: f004 fc26 bl 8015c14 <tcp_zero_window_probe>
80113c8: 4603 mov r3, r0
80113ca: 2b00 cmp r3, #0
80113cc: d014 beq.n 80113f8 <tcp_slowtmr+0x198>
next_slot = 0; /* try probe again with current slot */
80113ce: 2300 movs r3, #0
80113d0: 623b str r3, [r7, #32]
80113d2: e011 b.n 80113f8 <tcp_slowtmr+0x198>
}
/* snd_wnd not fully closed, split unsent head and fill window */
} else {
if (tcp_split_unsent_seg(pcb, (u16_t)pcb->snd_wnd) == ERR_OK) {
80113d4: 6afb ldr r3, [r7, #44] ; 0x2c
80113d6: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
80113da: 4619 mov r1, r3
80113dc: 6af8 ldr r0, [r7, #44] ; 0x2c
80113de: f003 faeb bl 80149b8 <tcp_split_unsent_seg>
80113e2: 4603 mov r3, r0
80113e4: 2b00 cmp r3, #0
80113e6: d107 bne.n 80113f8 <tcp_slowtmr+0x198>
if (tcp_output(pcb) == ERR_OK) {
80113e8: 6af8 ldr r0, [r7, #44] ; 0x2c
80113ea: f003 fd6b bl 8014ec4 <tcp_output>
80113ee: 4603 mov r3, r0
80113f0: 2b00 cmp r3, #0
80113f2: d101 bne.n 80113f8 <tcp_slowtmr+0x198>
/* sending will cancel persist timer, else retry with current slot */
next_slot = 0;
80113f4: 2300 movs r3, #0
80113f6: 623b str r3, [r7, #32]
}
}
}
if (next_slot) {
80113f8: 6a3b ldr r3, [r7, #32]
80113fa: 2b00 cmp r3, #0
80113fc: f000 80ac beq.w 8011558 <tcp_slowtmr+0x2f8>
pcb->persist_cnt = 0;
8011400: 6afb ldr r3, [r7, #44] ; 0x2c
8011402: 2200 movs r2, #0
8011404: f883 2098 strb.w r2, [r3, #152] ; 0x98
if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) {
8011408: 6afb ldr r3, [r7, #44] ; 0x2c
801140a: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
801140e: 2b06 cmp r3, #6
8011410: f200 80a2 bhi.w 8011558 <tcp_slowtmr+0x2f8>
pcb->persist_backoff++;
8011414: 6afb ldr r3, [r7, #44] ; 0x2c
8011416: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
801141a: 3301 adds r3, #1
801141c: b2da uxtb r2, r3
801141e: 6afb ldr r3, [r7, #44] ; 0x2c
8011420: f883 2099 strb.w r2, [r3, #153] ; 0x99
8011424: e098 b.n 8011558 <tcp_slowtmr+0x2f8>
}
}
}
} else {
/* Increase the retransmission timer if it is running */
if ((pcb->rtime >= 0) && (pcb->rtime < 0x7FFF)) {
8011426: 6afb ldr r3, [r7, #44] ; 0x2c
8011428: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
801142c: 2b00 cmp r3, #0
801142e: db0f blt.n 8011450 <tcp_slowtmr+0x1f0>
8011430: 6afb ldr r3, [r7, #44] ; 0x2c
8011432: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
8011436: f647 72ff movw r2, #32767 ; 0x7fff
801143a: 4293 cmp r3, r2
801143c: d008 beq.n 8011450 <tcp_slowtmr+0x1f0>
++pcb->rtime;
801143e: 6afb ldr r3, [r7, #44] ; 0x2c
8011440: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
8011444: b29b uxth r3, r3
8011446: 3301 adds r3, #1
8011448: b29b uxth r3, r3
801144a: b21a sxth r2, r3
801144c: 6afb ldr r3, [r7, #44] ; 0x2c
801144e: 861a strh r2, [r3, #48] ; 0x30
}
if (pcb->rtime >= pcb->rto) {
8011450: 6afb ldr r3, [r7, #44] ; 0x2c
8011452: f9b3 2030 ldrsh.w r2, [r3, #48] ; 0x30
8011456: 6afb ldr r3, [r7, #44] ; 0x2c
8011458: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40
801145c: 429a cmp r2, r3
801145e: db7b blt.n 8011558 <tcp_slowtmr+0x2f8>
" pcb->rto %"S16_F"\n",
pcb->rtime, pcb->rto));
/* If prepare phase fails but we have unsent data but no unacked data,
still execute the backoff calculations below, as this means we somehow
failed to send segment. */
if ((tcp_rexmit_rto_prepare(pcb) == ERR_OK) || ((pcb->unacked == NULL) && (pcb->unsent != NULL))) {
8011460: 6af8 ldr r0, [r7, #44] ; 0x2c
8011462: f004 f821 bl 80154a8 <tcp_rexmit_rto_prepare>
8011466: 4603 mov r3, r0
8011468: 2b00 cmp r3, #0
801146a: d007 beq.n 801147c <tcp_slowtmr+0x21c>
801146c: 6afb ldr r3, [r7, #44] ; 0x2c
801146e: 6f1b ldr r3, [r3, #112] ; 0x70
8011470: 2b00 cmp r3, #0
8011472: d171 bne.n 8011558 <tcp_slowtmr+0x2f8>
8011474: 6afb ldr r3, [r7, #44] ; 0x2c
8011476: 6edb ldr r3, [r3, #108] ; 0x6c
8011478: 2b00 cmp r3, #0
801147a: d06d beq.n 8011558 <tcp_slowtmr+0x2f8>
/* Double retransmission time-out unless we are trying to
* connect to somebody (i.e., we are in SYN_SENT). */
if (pcb->state != SYN_SENT) {
801147c: 6afb ldr r3, [r7, #44] ; 0x2c
801147e: 7d1b ldrb r3, [r3, #20]
8011480: 2b02 cmp r3, #2
8011482: d03a beq.n 80114fa <tcp_slowtmr+0x29a>
u8_t backoff_idx = LWIP_MIN(pcb->nrtx, sizeof(tcp_backoff) - 1);
8011484: 6afb ldr r3, [r7, #44] ; 0x2c
8011486: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
801148a: 2b0c cmp r3, #12
801148c: bf28 it cs
801148e: 230c movcs r3, #12
8011490: 76fb strb r3, [r7, #27]
int calc_rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[backoff_idx];
8011492: 6afb ldr r3, [r7, #44] ; 0x2c
8011494: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
8011498: 10db asrs r3, r3, #3
801149a: b21b sxth r3, r3
801149c: 461a mov r2, r3
801149e: 6afb ldr r3, [r7, #44] ; 0x2c
80114a0: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
80114a4: 4413 add r3, r2
80114a6: 7efa ldrb r2, [r7, #27]
80114a8: 4910 ldr r1, [pc, #64] ; (80114ec <tcp_slowtmr+0x28c>)
80114aa: 5c8a ldrb r2, [r1, r2]
80114ac: 4093 lsls r3, r2
80114ae: 617b str r3, [r7, #20]
pcb->rto = (s16_t)LWIP_MIN(calc_rto, 0x7FFF);
80114b0: 697b ldr r3, [r7, #20]
80114b2: f647 72fe movw r2, #32766 ; 0x7ffe
80114b6: 4293 cmp r3, r2
80114b8: dc1a bgt.n 80114f0 <tcp_slowtmr+0x290>
80114ba: 697b ldr r3, [r7, #20]
80114bc: b21a sxth r2, r3
80114be: e019 b.n 80114f4 <tcp_slowtmr+0x294>
80114c0: 2000f840 .word 0x2000f840
80114c4: 2000871e .word 0x2000871e
80114c8: 2000f83c .word 0x2000f83c
80114cc: 0801cd1c .word 0x0801cd1c
80114d0: 0801d060 .word 0x0801d060
80114d4: 0801cd60 .word 0x0801cd60
80114d8: 0801d08c .word 0x0801d08c
80114dc: 0801d0b8 .word 0x0801d0b8
80114e0: 0801d0e8 .word 0x0801d0e8
80114e4: 0801d11c .word 0x0801d11c
80114e8: 08020ffc .word 0x08020ffc
80114ec: 08020fec .word 0x08020fec
80114f0: f647 72ff movw r2, #32767 ; 0x7fff
80114f4: 6afb ldr r3, [r7, #44] ; 0x2c
80114f6: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
}
/* Reset the retransmission timer. */
pcb->rtime = 0;
80114fa: 6afb ldr r3, [r7, #44] ; 0x2c
80114fc: 2200 movs r2, #0
80114fe: 861a strh r2, [r3, #48] ; 0x30
/* Reduce congestion window and ssthresh. */
eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
8011500: 6afb ldr r3, [r7, #44] ; 0x2c
8011502: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8011506: 6afb ldr r3, [r7, #44] ; 0x2c
8011508: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
801150c: 4293 cmp r3, r2
801150e: bf28 it cs
8011510: 4613 movcs r3, r2
8011512: 827b strh r3, [r7, #18]
pcb->ssthresh = eff_wnd >> 1;
8011514: 8a7b ldrh r3, [r7, #18]
8011516: 085b lsrs r3, r3, #1
8011518: b29a uxth r2, r3
801151a: 6afb ldr r3, [r7, #44] ; 0x2c
801151c: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
if (pcb->ssthresh < (tcpwnd_size_t)(pcb->mss << 1)) {
8011520: 6afb ldr r3, [r7, #44] ; 0x2c
8011522: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a
8011526: 6afb ldr r3, [r7, #44] ; 0x2c
8011528: 8e5b ldrh r3, [r3, #50] ; 0x32
801152a: 005b lsls r3, r3, #1
801152c: b29b uxth r3, r3
801152e: 429a cmp r2, r3
8011530: d206 bcs.n 8011540 <tcp_slowtmr+0x2e0>
pcb->ssthresh = (tcpwnd_size_t)(pcb->mss << 1);
8011532: 6afb ldr r3, [r7, #44] ; 0x2c
8011534: 8e5b ldrh r3, [r3, #50] ; 0x32
8011536: 005b lsls r3, r3, #1
8011538: b29a uxth r2, r3
801153a: 6afb ldr r3, [r7, #44] ; 0x2c
801153c: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
}
pcb->cwnd = pcb->mss;
8011540: 6afb ldr r3, [r7, #44] ; 0x2c
8011542: 8e5a ldrh r2, [r3, #50] ; 0x32
8011544: 6afb ldr r3, [r7, #44] ; 0x2c
8011546: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"TCPWNDSIZE_F
" ssthresh %"TCPWNDSIZE_F"\n",
pcb->cwnd, pcb->ssthresh));
pcb->bytes_acked = 0;
801154a: 6afb ldr r3, [r7, #44] ; 0x2c
801154c: 2200 movs r2, #0
801154e: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
/* The following needs to be called AFTER cwnd is set to one
mss - STJ */
tcp_rexmit_rto_commit(pcb);
8011552: 6af8 ldr r0, [r7, #44] ; 0x2c
8011554: f004 f818 bl 8015588 <tcp_rexmit_rto_commit>
}
}
}
}
/* Check if this PCB has stayed too long in FIN-WAIT-2 */
if (pcb->state == FIN_WAIT_2) {
8011558: 6afb ldr r3, [r7, #44] ; 0x2c
801155a: 7d1b ldrb r3, [r3, #20]
801155c: 2b06 cmp r3, #6
801155e: d111 bne.n 8011584 <tcp_slowtmr+0x324>
/* If this PCB is in FIN_WAIT_2 because of SHUT_WR don't let it time out. */
if (pcb->flags & TF_RXCLOSED) {
8011560: 6afb ldr r3, [r7, #44] ; 0x2c
8011562: 8b5b ldrh r3, [r3, #26]
8011564: f003 0310 and.w r3, r3, #16
8011568: 2b00 cmp r3, #0
801156a: d00b beq.n 8011584 <tcp_slowtmr+0x324>
/* PCB was fully closed (either through close() or SHUT_RDWR):
normal FIN-WAIT timeout handling. */
if ((u32_t)(tcp_ticks - pcb->tmr) >
801156c: 4b9c ldr r3, [pc, #624] ; (80117e0 <tcp_slowtmr+0x580>)
801156e: 681a ldr r2, [r3, #0]
8011570: 6afb ldr r3, [r7, #44] ; 0x2c
8011572: 6a1b ldr r3, [r3, #32]
8011574: 1ad3 subs r3, r2, r3
8011576: 2b28 cmp r3, #40 ; 0x28
8011578: d904 bls.n 8011584 <tcp_slowtmr+0x324>
TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
++pcb_remove;
801157a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801157e: 3301 adds r3, #1
8011580: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
}
}
/* Check if KEEPALIVE should be sent */
if (ip_get_option(pcb, SOF_KEEPALIVE) &&
8011584: 6afb ldr r3, [r7, #44] ; 0x2c
8011586: 7a5b ldrb r3, [r3, #9]
8011588: f003 0308 and.w r3, r3, #8
801158c: 2b00 cmp r3, #0
801158e: d04a beq.n 8011626 <tcp_slowtmr+0x3c6>
((pcb->state == ESTABLISHED) ||
8011590: 6afb ldr r3, [r7, #44] ; 0x2c
8011592: 7d1b ldrb r3, [r3, #20]
if (ip_get_option(pcb, SOF_KEEPALIVE) &&
8011594: 2b04 cmp r3, #4
8011596: d003 beq.n 80115a0 <tcp_slowtmr+0x340>
(pcb->state == CLOSE_WAIT))) {
8011598: 6afb ldr r3, [r7, #44] ; 0x2c
801159a: 7d1b ldrb r3, [r3, #20]
((pcb->state == ESTABLISHED) ||
801159c: 2b07 cmp r3, #7
801159e: d142 bne.n 8011626 <tcp_slowtmr+0x3c6>
if ((u32_t)(tcp_ticks - pcb->tmr) >
80115a0: 4b8f ldr r3, [pc, #572] ; (80117e0 <tcp_slowtmr+0x580>)
80115a2: 681a ldr r2, [r3, #0]
80115a4: 6afb ldr r3, [r7, #44] ; 0x2c
80115a6: 6a1b ldr r3, [r3, #32]
80115a8: 1ad2 subs r2, r2, r3
(pcb->keep_idle + TCP_KEEP_DUR(pcb)) / TCP_SLOW_INTERVAL) {
80115aa: 6afb ldr r3, [r7, #44] ; 0x2c
80115ac: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94
80115b0: 4b8c ldr r3, [pc, #560] ; (80117e4 <tcp_slowtmr+0x584>)
80115b2: 440b add r3, r1
80115b4: 498c ldr r1, [pc, #560] ; (80117e8 <tcp_slowtmr+0x588>)
80115b6: fba1 1303 umull r1, r3, r1, r3
80115ba: 095b lsrs r3, r3, #5
if ((u32_t)(tcp_ticks - pcb->tmr) >
80115bc: 429a cmp r2, r3
80115be: d90a bls.n 80115d6 <tcp_slowtmr+0x376>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to "));
ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip);
LWIP_DEBUGF(TCP_DEBUG, ("\n"));
++pcb_remove;
80115c0: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80115c4: 3301 adds r3, #1
80115c6: f887 3027 strb.w r3, [r7, #39] ; 0x27
++pcb_reset;
80115ca: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
80115ce: 3301 adds r3, #1
80115d0: f887 3026 strb.w r3, [r7, #38] ; 0x26
80115d4: e027 b.n 8011626 <tcp_slowtmr+0x3c6>
} else if ((u32_t)(tcp_ticks - pcb->tmr) >
80115d6: 4b82 ldr r3, [pc, #520] ; (80117e0 <tcp_slowtmr+0x580>)
80115d8: 681a ldr r2, [r3, #0]
80115da: 6afb ldr r3, [r7, #44] ; 0x2c
80115dc: 6a1b ldr r3, [r3, #32]
80115de: 1ad2 subs r2, r2, r3
(pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEP_INTVL(pcb))
80115e0: 6afb ldr r3, [r7, #44] ; 0x2c
80115e2: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94
80115e6: 6afb ldr r3, [r7, #44] ; 0x2c
80115e8: f893 309b ldrb.w r3, [r3, #155] ; 0x9b
80115ec: 4618 mov r0, r3
80115ee: 4b7f ldr r3, [pc, #508] ; (80117ec <tcp_slowtmr+0x58c>)
80115f0: fb03 f300 mul.w r3, r3, r0
80115f4: 440b add r3, r1
/ TCP_SLOW_INTERVAL) {
80115f6: 497c ldr r1, [pc, #496] ; (80117e8 <tcp_slowtmr+0x588>)
80115f8: fba1 1303 umull r1, r3, r1, r3
80115fc: 095b lsrs r3, r3, #5
} else if ((u32_t)(tcp_ticks - pcb->tmr) >
80115fe: 429a cmp r2, r3
8011600: d911 bls.n 8011626 <tcp_slowtmr+0x3c6>
err = tcp_keepalive(pcb);
8011602: 6af8 ldr r0, [r7, #44] ; 0x2c
8011604: f004 fac6 bl 8015b94 <tcp_keepalive>
8011608: 4603 mov r3, r0
801160a: f887 3025 strb.w r3, [r7, #37] ; 0x25
if (err == ERR_OK) {
801160e: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25
8011612: 2b00 cmp r3, #0
8011614: d107 bne.n 8011626 <tcp_slowtmr+0x3c6>
pcb->keep_cnt_sent++;
8011616: 6afb ldr r3, [r7, #44] ; 0x2c
8011618: f893 309b ldrb.w r3, [r3, #155] ; 0x9b
801161c: 3301 adds r3, #1
801161e: b2da uxtb r2, r3
8011620: 6afb ldr r3, [r7, #44] ; 0x2c
8011622: f883 209b strb.w r2, [r3, #155] ; 0x9b
/* If this PCB has queued out of sequence data, but has been
inactive for too long, will drop the data (it will eventually
be retransmitted). */
#if TCP_QUEUE_OOSEQ
if (pcb->ooseq != NULL &&
8011626: 6afb ldr r3, [r7, #44] ; 0x2c
8011628: 6f5b ldr r3, [r3, #116] ; 0x74
801162a: 2b00 cmp r3, #0
801162c: d011 beq.n 8011652 <tcp_slowtmr+0x3f2>
(tcp_ticks - pcb->tmr >= (u32_t)pcb->rto * TCP_OOSEQ_TIMEOUT)) {
801162e: 4b6c ldr r3, [pc, #432] ; (80117e0 <tcp_slowtmr+0x580>)
8011630: 681a ldr r2, [r3, #0]
8011632: 6afb ldr r3, [r7, #44] ; 0x2c
8011634: 6a1b ldr r3, [r3, #32]
8011636: 1ad2 subs r2, r2, r3
8011638: 6afb ldr r3, [r7, #44] ; 0x2c
801163a: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40
801163e: 4619 mov r1, r3
8011640: 460b mov r3, r1
8011642: 005b lsls r3, r3, #1
8011644: 440b add r3, r1
8011646: 005b lsls r3, r3, #1
if (pcb->ooseq != NULL &&
8011648: 429a cmp r2, r3
801164a: d302 bcc.n 8011652 <tcp_slowtmr+0x3f2>
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
tcp_free_ooseq(pcb);
801164c: 6af8 ldr r0, [r7, #44] ; 0x2c
801164e: f000 fddd bl 801220c <tcp_free_ooseq>
}
#endif /* TCP_QUEUE_OOSEQ */
/* Check if this PCB has stayed too long in SYN-RCVD */
if (pcb->state == SYN_RCVD) {
8011652: 6afb ldr r3, [r7, #44] ; 0x2c
8011654: 7d1b ldrb r3, [r3, #20]
8011656: 2b03 cmp r3, #3
8011658: d10b bne.n 8011672 <tcp_slowtmr+0x412>
if ((u32_t)(tcp_ticks - pcb->tmr) >
801165a: 4b61 ldr r3, [pc, #388] ; (80117e0 <tcp_slowtmr+0x580>)
801165c: 681a ldr r2, [r3, #0]
801165e: 6afb ldr r3, [r7, #44] ; 0x2c
8011660: 6a1b ldr r3, [r3, #32]
8011662: 1ad3 subs r3, r2, r3
8011664: 2b28 cmp r3, #40 ; 0x28
8011666: d904 bls.n 8011672 <tcp_slowtmr+0x412>
TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
++pcb_remove;
8011668: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801166c: 3301 adds r3, #1
801166e: f887 3027 strb.w r3, [r7, #39] ; 0x27
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
}
}
/* Check if this PCB has stayed too long in LAST-ACK */
if (pcb->state == LAST_ACK) {
8011672: 6afb ldr r3, [r7, #44] ; 0x2c
8011674: 7d1b ldrb r3, [r3, #20]
8011676: 2b09 cmp r3, #9
8011678: d10b bne.n 8011692 <tcp_slowtmr+0x432>
if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
801167a: 4b59 ldr r3, [pc, #356] ; (80117e0 <tcp_slowtmr+0x580>)
801167c: 681a ldr r2, [r3, #0]
801167e: 6afb ldr r3, [r7, #44] ; 0x2c
8011680: 6a1b ldr r3, [r3, #32]
8011682: 1ad3 subs r3, r2, r3
8011684: 2bf0 cmp r3, #240 ; 0xf0
8011686: d904 bls.n 8011692 <tcp_slowtmr+0x432>
++pcb_remove;
8011688: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801168c: 3301 adds r3, #1
801168e: f887 3027 strb.w r3, [r7, #39] ; 0x27
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
}
}
/* If the PCB should be removed, do it. */
if (pcb_remove) {
8011692: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011696: 2b00 cmp r3, #0
8011698: d060 beq.n 801175c <tcp_slowtmr+0x4fc>
struct tcp_pcb *pcb2;
#if LWIP_CALLBACK_API
tcp_err_fn err_fn = pcb->errf;
801169a: 6afb ldr r3, [r7, #44] ; 0x2c
801169c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80116a0: 60fb str r3, [r7, #12]
#endif /* LWIP_CALLBACK_API */
void *err_arg;
enum tcp_state last_state;
tcp_pcb_purge(pcb);
80116a2: 6af8 ldr r0, [r7, #44] ; 0x2c
80116a4: f000 fbfe bl 8011ea4 <tcp_pcb_purge>
/* Remove PCB from tcp_active_pcbs list. */
if (prev != NULL) {
80116a8: 6abb ldr r3, [r7, #40] ; 0x28
80116aa: 2b00 cmp r3, #0
80116ac: d010 beq.n 80116d0 <tcp_slowtmr+0x470>
LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
80116ae: 4b50 ldr r3, [pc, #320] ; (80117f0 <tcp_slowtmr+0x590>)
80116b0: 681b ldr r3, [r3, #0]
80116b2: 6afa ldr r2, [r7, #44] ; 0x2c
80116b4: 429a cmp r2, r3
80116b6: d106 bne.n 80116c6 <tcp_slowtmr+0x466>
80116b8: 4b4e ldr r3, [pc, #312] ; (80117f4 <tcp_slowtmr+0x594>)
80116ba: f240 526d movw r2, #1389 ; 0x56d
80116be: 494e ldr r1, [pc, #312] ; (80117f8 <tcp_slowtmr+0x598>)
80116c0: 484e ldr r0, [pc, #312] ; (80117fc <tcp_slowtmr+0x59c>)
80116c2: f009 fc7f bl 801afc4 <iprintf>
prev->next = pcb->next;
80116c6: 6afb ldr r3, [r7, #44] ; 0x2c
80116c8: 68da ldr r2, [r3, #12]
80116ca: 6abb ldr r3, [r7, #40] ; 0x28
80116cc: 60da str r2, [r3, #12]
80116ce: e00f b.n 80116f0 <tcp_slowtmr+0x490>
} else {
/* This PCB was the first. */
LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
80116d0: 4b47 ldr r3, [pc, #284] ; (80117f0 <tcp_slowtmr+0x590>)
80116d2: 681b ldr r3, [r3, #0]
80116d4: 6afa ldr r2, [r7, #44] ; 0x2c
80116d6: 429a cmp r2, r3
80116d8: d006 beq.n 80116e8 <tcp_slowtmr+0x488>
80116da: 4b46 ldr r3, [pc, #280] ; (80117f4 <tcp_slowtmr+0x594>)
80116dc: f240 5271 movw r2, #1393 ; 0x571
80116e0: 4947 ldr r1, [pc, #284] ; (8011800 <tcp_slowtmr+0x5a0>)
80116e2: 4846 ldr r0, [pc, #280] ; (80117fc <tcp_slowtmr+0x59c>)
80116e4: f009 fc6e bl 801afc4 <iprintf>
tcp_active_pcbs = pcb->next;
80116e8: 6afb ldr r3, [r7, #44] ; 0x2c
80116ea: 68db ldr r3, [r3, #12]
80116ec: 4a40 ldr r2, [pc, #256] ; (80117f0 <tcp_slowtmr+0x590>)
80116ee: 6013 str r3, [r2, #0]
}
if (pcb_reset) {
80116f0: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
80116f4: 2b00 cmp r3, #0
80116f6: d013 beq.n 8011720 <tcp_slowtmr+0x4c0>
tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
80116f8: 6afb ldr r3, [r7, #44] ; 0x2c
80116fa: 6d18 ldr r0, [r3, #80] ; 0x50
80116fc: 6afb ldr r3, [r7, #44] ; 0x2c
80116fe: 6a5c ldr r4, [r3, #36] ; 0x24
8011700: 6afd ldr r5, [r7, #44] ; 0x2c
8011702: 6afb ldr r3, [r7, #44] ; 0x2c
8011704: 3304 adds r3, #4
8011706: 6afa ldr r2, [r7, #44] ; 0x2c
8011708: 8ad2 ldrh r2, [r2, #22]
801170a: 6af9 ldr r1, [r7, #44] ; 0x2c
801170c: 8b09 ldrh r1, [r1, #24]
801170e: 9102 str r1, [sp, #8]
8011710: 9201 str r2, [sp, #4]
8011712: 9300 str r3, [sp, #0]
8011714: 462b mov r3, r5
8011716: 4622 mov r2, r4
8011718: 4601 mov r1, r0
801171a: 6af8 ldr r0, [r7, #44] ; 0x2c
801171c: f004 f986 bl 8015a2c <tcp_rst>
pcb->local_port, pcb->remote_port);
}
err_arg = pcb->callback_arg;
8011720: 6afb ldr r3, [r7, #44] ; 0x2c
8011722: 691b ldr r3, [r3, #16]
8011724: 60bb str r3, [r7, #8]
last_state = pcb->state;
8011726: 6afb ldr r3, [r7, #44] ; 0x2c
8011728: 7d1b ldrb r3, [r3, #20]
801172a: 71fb strb r3, [r7, #7]
pcb2 = pcb;
801172c: 6afb ldr r3, [r7, #44] ; 0x2c
801172e: 603b str r3, [r7, #0]
pcb = pcb->next;
8011730: 6afb ldr r3, [r7, #44] ; 0x2c
8011732: 68db ldr r3, [r3, #12]
8011734: 62fb str r3, [r7, #44] ; 0x2c
tcp_free(pcb2);
8011736: 6838 ldr r0, [r7, #0]
8011738: f7ff f9f4 bl 8010b24 <tcp_free>
tcp_active_pcbs_changed = 0;
801173c: 4b31 ldr r3, [pc, #196] ; (8011804 <tcp_slowtmr+0x5a4>)
801173e: 2200 movs r2, #0
8011740: 701a strb r2, [r3, #0]
TCP_EVENT_ERR(last_state, err_fn, err_arg, ERR_ABRT);
8011742: 68fb ldr r3, [r7, #12]
8011744: 2b00 cmp r3, #0
8011746: d004 beq.n 8011752 <tcp_slowtmr+0x4f2>
8011748: 68fb ldr r3, [r7, #12]
801174a: f06f 010c mvn.w r1, #12
801174e: 68b8 ldr r0, [r7, #8]
8011750: 4798 blx r3
if (tcp_active_pcbs_changed) {
8011752: 4b2c ldr r3, [pc, #176] ; (8011804 <tcp_slowtmr+0x5a4>)
8011754: 781b ldrb r3, [r3, #0]
8011756: 2b00 cmp r3, #0
8011758: d037 beq.n 80117ca <tcp_slowtmr+0x56a>
goto tcp_slowtmr_start;
801175a: e592 b.n 8011282 <tcp_slowtmr+0x22>
}
} else {
/* get the 'next' element now and work with 'prev' below (in case of abort) */
prev = pcb;
801175c: 6afb ldr r3, [r7, #44] ; 0x2c
801175e: 62bb str r3, [r7, #40] ; 0x28
pcb = pcb->next;
8011760: 6afb ldr r3, [r7, #44] ; 0x2c
8011762: 68db ldr r3, [r3, #12]
8011764: 62fb str r3, [r7, #44] ; 0x2c
/* We check if we should poll the connection. */
++prev->polltmr;
8011766: 6abb ldr r3, [r7, #40] ; 0x28
8011768: 7f1b ldrb r3, [r3, #28]
801176a: 3301 adds r3, #1
801176c: b2da uxtb r2, r3
801176e: 6abb ldr r3, [r7, #40] ; 0x28
8011770: 771a strb r2, [r3, #28]
if (prev->polltmr >= prev->pollinterval) {
8011772: 6abb ldr r3, [r7, #40] ; 0x28
8011774: 7f1a ldrb r2, [r3, #28]
8011776: 6abb ldr r3, [r7, #40] ; 0x28
8011778: 7f5b ldrb r3, [r3, #29]
801177a: 429a cmp r2, r3
801177c: d325 bcc.n 80117ca <tcp_slowtmr+0x56a>
prev->polltmr = 0;
801177e: 6abb ldr r3, [r7, #40] ; 0x28
8011780: 2200 movs r2, #0
8011782: 771a strb r2, [r3, #28]
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
tcp_active_pcbs_changed = 0;
8011784: 4b1f ldr r3, [pc, #124] ; (8011804 <tcp_slowtmr+0x5a4>)
8011786: 2200 movs r2, #0
8011788: 701a strb r2, [r3, #0]
TCP_EVENT_POLL(prev, err);
801178a: 6abb ldr r3, [r7, #40] ; 0x28
801178c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8011790: 2b00 cmp r3, #0
8011792: d00b beq.n 80117ac <tcp_slowtmr+0x54c>
8011794: 6abb ldr r3, [r7, #40] ; 0x28
8011796: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
801179a: 6aba ldr r2, [r7, #40] ; 0x28
801179c: 6912 ldr r2, [r2, #16]
801179e: 6ab9 ldr r1, [r7, #40] ; 0x28
80117a0: 4610 mov r0, r2
80117a2: 4798 blx r3
80117a4: 4603 mov r3, r0
80117a6: f887 3025 strb.w r3, [r7, #37] ; 0x25
80117aa: e002 b.n 80117b2 <tcp_slowtmr+0x552>
80117ac: 2300 movs r3, #0
80117ae: f887 3025 strb.w r3, [r7, #37] ; 0x25
if (tcp_active_pcbs_changed) {
80117b2: 4b14 ldr r3, [pc, #80] ; (8011804 <tcp_slowtmr+0x5a4>)
80117b4: 781b ldrb r3, [r3, #0]
80117b6: 2b00 cmp r3, #0
80117b8: d000 beq.n 80117bc <tcp_slowtmr+0x55c>
goto tcp_slowtmr_start;
80117ba: e562 b.n 8011282 <tcp_slowtmr+0x22>
}
/* if err == ERR_ABRT, 'prev' is already deallocated */
if (err == ERR_OK) {
80117bc: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25
80117c0: 2b00 cmp r3, #0
80117c2: d102 bne.n 80117ca <tcp_slowtmr+0x56a>
tcp_output(prev);
80117c4: 6ab8 ldr r0, [r7, #40] ; 0x28
80117c6: f003 fb7d bl 8014ec4 <tcp_output>
while (pcb != NULL) {
80117ca: 6afb ldr r3, [r7, #44] ; 0x2c
80117cc: 2b00 cmp r3, #0
80117ce: f47f ad5e bne.w 801128e <tcp_slowtmr+0x2e>
}
}
/* Steps through all of the TIME-WAIT PCBs. */
prev = NULL;
80117d2: 2300 movs r3, #0
80117d4: 62bb str r3, [r7, #40] ; 0x28
pcb = tcp_tw_pcbs;
80117d6: 4b0c ldr r3, [pc, #48] ; (8011808 <tcp_slowtmr+0x5a8>)
80117d8: 681b ldr r3, [r3, #0]
80117da: 62fb str r3, [r7, #44] ; 0x2c
while (pcb != NULL) {
80117dc: e069 b.n 80118b2 <tcp_slowtmr+0x652>
80117de: bf00 nop
80117e0: 2000f840 .word 0x2000f840
80117e4: 000a4cb8 .word 0x000a4cb8
80117e8: 10624dd3 .word 0x10624dd3
80117ec: 000124f8 .word 0x000124f8
80117f0: 2000f83c .word 0x2000f83c
80117f4: 0801cd1c .word 0x0801cd1c
80117f8: 0801d154 .word 0x0801d154
80117fc: 0801cd60 .word 0x0801cd60
8011800: 0801d180 .word 0x0801d180
8011804: 2000f838 .word 0x2000f838
8011808: 2000f84c .word 0x2000f84c
LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
801180c: 6afb ldr r3, [r7, #44] ; 0x2c
801180e: 7d1b ldrb r3, [r3, #20]
8011810: 2b0a cmp r3, #10
8011812: d006 beq.n 8011822 <tcp_slowtmr+0x5c2>
8011814: 4b2b ldr r3, [pc, #172] ; (80118c4 <tcp_slowtmr+0x664>)
8011816: f240 52a1 movw r2, #1441 ; 0x5a1
801181a: 492b ldr r1, [pc, #172] ; (80118c8 <tcp_slowtmr+0x668>)
801181c: 482b ldr r0, [pc, #172] ; (80118cc <tcp_slowtmr+0x66c>)
801181e: f009 fbd1 bl 801afc4 <iprintf>
pcb_remove = 0;
8011822: 2300 movs r3, #0
8011824: f887 3027 strb.w r3, [r7, #39] ; 0x27
/* Check if this PCB has stayed long enough in TIME-WAIT */
if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
8011828: 4b29 ldr r3, [pc, #164] ; (80118d0 <tcp_slowtmr+0x670>)
801182a: 681a ldr r2, [r3, #0]
801182c: 6afb ldr r3, [r7, #44] ; 0x2c
801182e: 6a1b ldr r3, [r3, #32]
8011830: 1ad3 subs r3, r2, r3
8011832: 2bf0 cmp r3, #240 ; 0xf0
8011834: d904 bls.n 8011840 <tcp_slowtmr+0x5e0>
++pcb_remove;
8011836: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801183a: 3301 adds r3, #1
801183c: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
/* If the PCB should be removed, do it. */
if (pcb_remove) {
8011840: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011844: 2b00 cmp r3, #0
8011846: d02f beq.n 80118a8 <tcp_slowtmr+0x648>
struct tcp_pcb *pcb2;
tcp_pcb_purge(pcb);
8011848: 6af8 ldr r0, [r7, #44] ; 0x2c
801184a: f000 fb2b bl 8011ea4 <tcp_pcb_purge>
/* Remove PCB from tcp_tw_pcbs list. */
if (prev != NULL) {
801184e: 6abb ldr r3, [r7, #40] ; 0x28
8011850: 2b00 cmp r3, #0
8011852: d010 beq.n 8011876 <tcp_slowtmr+0x616>
LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
8011854: 4b1f ldr r3, [pc, #124] ; (80118d4 <tcp_slowtmr+0x674>)
8011856: 681b ldr r3, [r3, #0]
8011858: 6afa ldr r2, [r7, #44] ; 0x2c
801185a: 429a cmp r2, r3
801185c: d106 bne.n 801186c <tcp_slowtmr+0x60c>
801185e: 4b19 ldr r3, [pc, #100] ; (80118c4 <tcp_slowtmr+0x664>)
8011860: f240 52af movw r2, #1455 ; 0x5af
8011864: 491c ldr r1, [pc, #112] ; (80118d8 <tcp_slowtmr+0x678>)
8011866: 4819 ldr r0, [pc, #100] ; (80118cc <tcp_slowtmr+0x66c>)
8011868: f009 fbac bl 801afc4 <iprintf>
prev->next = pcb->next;
801186c: 6afb ldr r3, [r7, #44] ; 0x2c
801186e: 68da ldr r2, [r3, #12]
8011870: 6abb ldr r3, [r7, #40] ; 0x28
8011872: 60da str r2, [r3, #12]
8011874: e00f b.n 8011896 <tcp_slowtmr+0x636>
} else {
/* This PCB was the first. */
LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
8011876: 4b17 ldr r3, [pc, #92] ; (80118d4 <tcp_slowtmr+0x674>)
8011878: 681b ldr r3, [r3, #0]
801187a: 6afa ldr r2, [r7, #44] ; 0x2c
801187c: 429a cmp r2, r3
801187e: d006 beq.n 801188e <tcp_slowtmr+0x62e>
8011880: 4b10 ldr r3, [pc, #64] ; (80118c4 <tcp_slowtmr+0x664>)
8011882: f240 52b3 movw r2, #1459 ; 0x5b3
8011886: 4915 ldr r1, [pc, #84] ; (80118dc <tcp_slowtmr+0x67c>)
8011888: 4810 ldr r0, [pc, #64] ; (80118cc <tcp_slowtmr+0x66c>)
801188a: f009 fb9b bl 801afc4 <iprintf>
tcp_tw_pcbs = pcb->next;
801188e: 6afb ldr r3, [r7, #44] ; 0x2c
8011890: 68db ldr r3, [r3, #12]
8011892: 4a10 ldr r2, [pc, #64] ; (80118d4 <tcp_slowtmr+0x674>)
8011894: 6013 str r3, [r2, #0]
}
pcb2 = pcb;
8011896: 6afb ldr r3, [r7, #44] ; 0x2c
8011898: 61fb str r3, [r7, #28]
pcb = pcb->next;
801189a: 6afb ldr r3, [r7, #44] ; 0x2c
801189c: 68db ldr r3, [r3, #12]
801189e: 62fb str r3, [r7, #44] ; 0x2c
tcp_free(pcb2);
80118a0: 69f8 ldr r0, [r7, #28]
80118a2: f7ff f93f bl 8010b24 <tcp_free>
80118a6: e004 b.n 80118b2 <tcp_slowtmr+0x652>
} else {
prev = pcb;
80118a8: 6afb ldr r3, [r7, #44] ; 0x2c
80118aa: 62bb str r3, [r7, #40] ; 0x28
pcb = pcb->next;
80118ac: 6afb ldr r3, [r7, #44] ; 0x2c
80118ae: 68db ldr r3, [r3, #12]
80118b0: 62fb str r3, [r7, #44] ; 0x2c
while (pcb != NULL) {
80118b2: 6afb ldr r3, [r7, #44] ; 0x2c
80118b4: 2b00 cmp r3, #0
80118b6: d1a9 bne.n 801180c <tcp_slowtmr+0x5ac>
}
}
}
80118b8: bf00 nop
80118ba: bf00 nop
80118bc: 3730 adds r7, #48 ; 0x30
80118be: 46bd mov sp, r7
80118c0: bdb0 pop {r4, r5, r7, pc}
80118c2: bf00 nop
80118c4: 0801cd1c .word 0x0801cd1c
80118c8: 0801d1ac .word 0x0801d1ac
80118cc: 0801cd60 .word 0x0801cd60
80118d0: 2000f840 .word 0x2000f840
80118d4: 2000f84c .word 0x2000f84c
80118d8: 0801d1dc .word 0x0801d1dc
80118dc: 0801d204 .word 0x0801d204
080118e0 <tcp_fasttmr>:
*
* Automatically called from tcp_tmr().
*/
void
tcp_fasttmr(void)
{
80118e0: b580 push {r7, lr}
80118e2: b082 sub sp, #8
80118e4: af00 add r7, sp, #0
struct tcp_pcb *pcb;
++tcp_timer_ctr;
80118e6: 4b2d ldr r3, [pc, #180] ; (801199c <tcp_fasttmr+0xbc>)
80118e8: 781b ldrb r3, [r3, #0]
80118ea: 3301 adds r3, #1
80118ec: b2da uxtb r2, r3
80118ee: 4b2b ldr r3, [pc, #172] ; (801199c <tcp_fasttmr+0xbc>)
80118f0: 701a strb r2, [r3, #0]
tcp_fasttmr_start:
pcb = tcp_active_pcbs;
80118f2: 4b2b ldr r3, [pc, #172] ; (80119a0 <tcp_fasttmr+0xc0>)
80118f4: 681b ldr r3, [r3, #0]
80118f6: 607b str r3, [r7, #4]
while (pcb != NULL) {
80118f8: e048 b.n 801198c <tcp_fasttmr+0xac>
if (pcb->last_timer != tcp_timer_ctr) {
80118fa: 687b ldr r3, [r7, #4]
80118fc: 7f9a ldrb r2, [r3, #30]
80118fe: 4b27 ldr r3, [pc, #156] ; (801199c <tcp_fasttmr+0xbc>)
8011900: 781b ldrb r3, [r3, #0]
8011902: 429a cmp r2, r3
8011904: d03f beq.n 8011986 <tcp_fasttmr+0xa6>
struct tcp_pcb *next;
pcb->last_timer = tcp_timer_ctr;
8011906: 4b25 ldr r3, [pc, #148] ; (801199c <tcp_fasttmr+0xbc>)
8011908: 781a ldrb r2, [r3, #0]
801190a: 687b ldr r3, [r7, #4]
801190c: 779a strb r2, [r3, #30]
/* send delayed ACKs */
if (pcb->flags & TF_ACK_DELAY) {
801190e: 687b ldr r3, [r7, #4]
8011910: 8b5b ldrh r3, [r3, #26]
8011912: f003 0301 and.w r3, r3, #1
8011916: 2b00 cmp r3, #0
8011918: d010 beq.n 801193c <tcp_fasttmr+0x5c>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
tcp_ack_now(pcb);
801191a: 687b ldr r3, [r7, #4]
801191c: 8b5b ldrh r3, [r3, #26]
801191e: f043 0302 orr.w r3, r3, #2
8011922: b29a uxth r2, r3
8011924: 687b ldr r3, [r7, #4]
8011926: 835a strh r2, [r3, #26]
tcp_output(pcb);
8011928: 6878 ldr r0, [r7, #4]
801192a: f003 facb bl 8014ec4 <tcp_output>
tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
801192e: 687b ldr r3, [r7, #4]
8011930: 8b5b ldrh r3, [r3, #26]
8011932: f023 0303 bic.w r3, r3, #3
8011936: b29a uxth r2, r3
8011938: 687b ldr r3, [r7, #4]
801193a: 835a strh r2, [r3, #26]
}
/* send pending FIN */
if (pcb->flags & TF_CLOSEPEND) {
801193c: 687b ldr r3, [r7, #4]
801193e: 8b5b ldrh r3, [r3, #26]
8011940: f003 0308 and.w r3, r3, #8
8011944: 2b00 cmp r3, #0
8011946: d009 beq.n 801195c <tcp_fasttmr+0x7c>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: pending FIN\n"));
tcp_clear_flags(pcb, TF_CLOSEPEND);
8011948: 687b ldr r3, [r7, #4]
801194a: 8b5b ldrh r3, [r3, #26]
801194c: f023 0308 bic.w r3, r3, #8
8011950: b29a uxth r2, r3
8011952: 687b ldr r3, [r7, #4]
8011954: 835a strh r2, [r3, #26]
tcp_close_shutdown_fin(pcb);
8011956: 6878 ldr r0, [r7, #4]
8011958: f7ff fa78 bl 8010e4c <tcp_close_shutdown_fin>
}
next = pcb->next;
801195c: 687b ldr r3, [r7, #4]
801195e: 68db ldr r3, [r3, #12]
8011960: 603b str r3, [r7, #0]
/* If there is data which was previously "refused" by upper layer */
if (pcb->refused_data != NULL) {
8011962: 687b ldr r3, [r7, #4]
8011964: 6f9b ldr r3, [r3, #120] ; 0x78
8011966: 2b00 cmp r3, #0
8011968: d00a beq.n 8011980 <tcp_fasttmr+0xa0>
tcp_active_pcbs_changed = 0;
801196a: 4b0e ldr r3, [pc, #56] ; (80119a4 <tcp_fasttmr+0xc4>)
801196c: 2200 movs r2, #0
801196e: 701a strb r2, [r3, #0]
tcp_process_refused_data(pcb);
8011970: 6878 ldr r0, [r7, #4]
8011972: f000 f819 bl 80119a8 <tcp_process_refused_data>
if (tcp_active_pcbs_changed) {
8011976: 4b0b ldr r3, [pc, #44] ; (80119a4 <tcp_fasttmr+0xc4>)
8011978: 781b ldrb r3, [r3, #0]
801197a: 2b00 cmp r3, #0
801197c: d000 beq.n 8011980 <tcp_fasttmr+0xa0>
/* application callback has changed the pcb list: restart the loop */
goto tcp_fasttmr_start;
801197e: e7b8 b.n 80118f2 <tcp_fasttmr+0x12>
}
}
pcb = next;
8011980: 683b ldr r3, [r7, #0]
8011982: 607b str r3, [r7, #4]
8011984: e002 b.n 801198c <tcp_fasttmr+0xac>
} else {
pcb = pcb->next;
8011986: 687b ldr r3, [r7, #4]
8011988: 68db ldr r3, [r3, #12]
801198a: 607b str r3, [r7, #4]
while (pcb != NULL) {
801198c: 687b ldr r3, [r7, #4]
801198e: 2b00 cmp r3, #0
8011990: d1b3 bne.n 80118fa <tcp_fasttmr+0x1a>
}
}
}
8011992: bf00 nop
8011994: bf00 nop
8011996: 3708 adds r7, #8
8011998: 46bd mov sp, r7
801199a: bd80 pop {r7, pc}
801199c: 2000871e .word 0x2000871e
80119a0: 2000f83c .word 0x2000f83c
80119a4: 2000f838 .word 0x2000f838
080119a8 <tcp_process_refused_data>:
}
/** Pass pcb->refused_data to the recv callback */
err_t
tcp_process_refused_data(struct tcp_pcb *pcb)
{
80119a8: b590 push {r4, r7, lr}
80119aa: b085 sub sp, #20
80119ac: af00 add r7, sp, #0
80119ae: 6078 str r0, [r7, #4]
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
struct pbuf *rest;
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
LWIP_ERROR("tcp_process_refused_data: invalid pcb", pcb != NULL, return ERR_ARG);
80119b0: 687b ldr r3, [r7, #4]
80119b2: 2b00 cmp r3, #0
80119b4: d109 bne.n 80119ca <tcp_process_refused_data+0x22>
80119b6: 4b37 ldr r3, [pc, #220] ; (8011a94 <tcp_process_refused_data+0xec>)
80119b8: f240 6209 movw r2, #1545 ; 0x609
80119bc: 4936 ldr r1, [pc, #216] ; (8011a98 <tcp_process_refused_data+0xf0>)
80119be: 4837 ldr r0, [pc, #220] ; (8011a9c <tcp_process_refused_data+0xf4>)
80119c0: f009 fb00 bl 801afc4 <iprintf>
80119c4: f06f 030f mvn.w r3, #15
80119c8: e060 b.n 8011a8c <tcp_process_refused_data+0xe4>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
while (pcb->refused_data != NULL)
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
{
err_t err;
u8_t refused_flags = pcb->refused_data->flags;
80119ca: 687b ldr r3, [r7, #4]
80119cc: 6f9b ldr r3, [r3, #120] ; 0x78
80119ce: 7b5b ldrb r3, [r3, #13]
80119d0: 73bb strb r3, [r7, #14]
/* set pcb->refused_data to NULL in case the callback frees it and then
closes the pcb */
struct pbuf *refused_data = pcb->refused_data;
80119d2: 687b ldr r3, [r7, #4]
80119d4: 6f9b ldr r3, [r3, #120] ; 0x78
80119d6: 60bb str r3, [r7, #8]
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
pbuf_split_64k(refused_data, &rest);
pcb->refused_data = rest;
#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
pcb->refused_data = NULL;
80119d8: 687b ldr r3, [r7, #4]
80119da: 2200 movs r2, #0
80119dc: 679a str r2, [r3, #120] ; 0x78
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
/* Notify again application with data previously received. */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n"));
TCP_EVENT_RECV(pcb, refused_data, ERR_OK, err);
80119de: 687b ldr r3, [r7, #4]
80119e0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
80119e4: 2b00 cmp r3, #0
80119e6: d00b beq.n 8011a00 <tcp_process_refused_data+0x58>
80119e8: 687b ldr r3, [r7, #4]
80119ea: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
80119ee: 687b ldr r3, [r7, #4]
80119f0: 6918 ldr r0, [r3, #16]
80119f2: 2300 movs r3, #0
80119f4: 68ba ldr r2, [r7, #8]
80119f6: 6879 ldr r1, [r7, #4]
80119f8: 47a0 blx r4
80119fa: 4603 mov r3, r0
80119fc: 73fb strb r3, [r7, #15]
80119fe: e007 b.n 8011a10 <tcp_process_refused_data+0x68>
8011a00: 2300 movs r3, #0
8011a02: 68ba ldr r2, [r7, #8]
8011a04: 6879 ldr r1, [r7, #4]
8011a06: 2000 movs r0, #0
8011a08: f000 f8a4 bl 8011b54 <tcp_recv_null>
8011a0c: 4603 mov r3, r0
8011a0e: 73fb strb r3, [r7, #15]
if (err == ERR_OK) {
8011a10: f997 300f ldrsb.w r3, [r7, #15]
8011a14: 2b00 cmp r3, #0
8011a16: d12a bne.n 8011a6e <tcp_process_refused_data+0xc6>
/* did refused_data include a FIN? */
if ((refused_flags & PBUF_FLAG_TCP_FIN)
8011a18: 7bbb ldrb r3, [r7, #14]
8011a1a: f003 0320 and.w r3, r3, #32
8011a1e: 2b00 cmp r3, #0
8011a20: d033 beq.n 8011a8a <tcp_process_refused_data+0xe2>
&& (rest == NULL)
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
) {
/* correct rcv_wnd as the application won't call tcp_recved()
for the FIN's seqno */
if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
8011a22: 687b ldr r3, [r7, #4]
8011a24: 8d1b ldrh r3, [r3, #40] ; 0x28
8011a26: f5b3 6f06 cmp.w r3, #2144 ; 0x860
8011a2a: d005 beq.n 8011a38 <tcp_process_refused_data+0x90>
pcb->rcv_wnd++;
8011a2c: 687b ldr r3, [r7, #4]
8011a2e: 8d1b ldrh r3, [r3, #40] ; 0x28
8011a30: 3301 adds r3, #1
8011a32: b29a uxth r2, r3
8011a34: 687b ldr r3, [r7, #4]
8011a36: 851a strh r2, [r3, #40] ; 0x28
}
TCP_EVENT_CLOSED(pcb, err);
8011a38: 687b ldr r3, [r7, #4]
8011a3a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8011a3e: 2b00 cmp r3, #0
8011a40: d00b beq.n 8011a5a <tcp_process_refused_data+0xb2>
8011a42: 687b ldr r3, [r7, #4]
8011a44: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
8011a48: 687b ldr r3, [r7, #4]
8011a4a: 6918 ldr r0, [r3, #16]
8011a4c: 2300 movs r3, #0
8011a4e: 2200 movs r2, #0
8011a50: 6879 ldr r1, [r7, #4]
8011a52: 47a0 blx r4
8011a54: 4603 mov r3, r0
8011a56: 73fb strb r3, [r7, #15]
8011a58: e001 b.n 8011a5e <tcp_process_refused_data+0xb6>
8011a5a: 2300 movs r3, #0
8011a5c: 73fb strb r3, [r7, #15]
if (err == ERR_ABRT) {
8011a5e: f997 300f ldrsb.w r3, [r7, #15]
8011a62: f113 0f0d cmn.w r3, #13
8011a66: d110 bne.n 8011a8a <tcp_process_refused_data+0xe2>
return ERR_ABRT;
8011a68: f06f 030c mvn.w r3, #12
8011a6c: e00e b.n 8011a8c <tcp_process_refused_data+0xe4>
}
}
} else if (err == ERR_ABRT) {
8011a6e: f997 300f ldrsb.w r3, [r7, #15]
8011a72: f113 0f0d cmn.w r3, #13
8011a76: d102 bne.n 8011a7e <tcp_process_refused_data+0xd6>
/* if err == ERR_ABRT, 'pcb' is already deallocated */
/* Drop incoming packets because pcb is "full" (only if the incoming
segment contains data). */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n"));
return ERR_ABRT;
8011a78: f06f 030c mvn.w r3, #12
8011a7c: e006 b.n 8011a8c <tcp_process_refused_data+0xe4>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
if (rest != NULL) {
pbuf_cat(refused_data, rest);
}
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
pcb->refused_data = refused_data;
8011a7e: 687b ldr r3, [r7, #4]
8011a80: 68ba ldr r2, [r7, #8]
8011a82: 679a str r2, [r3, #120] ; 0x78
return ERR_INPROGRESS;
8011a84: f06f 0304 mvn.w r3, #4
8011a88: e000 b.n 8011a8c <tcp_process_refused_data+0xe4>
}
}
return ERR_OK;
8011a8a: 2300 movs r3, #0
}
8011a8c: 4618 mov r0, r3
8011a8e: 3714 adds r7, #20
8011a90: 46bd mov sp, r7
8011a92: bd90 pop {r4, r7, pc}
8011a94: 0801cd1c .word 0x0801cd1c
8011a98: 0801d22c .word 0x0801d22c
8011a9c: 0801cd60 .word 0x0801cd60
08011aa0 <tcp_segs_free>:
*
* @param seg tcp_seg list of TCP segments to free
*/
void
tcp_segs_free(struct tcp_seg *seg)
{
8011aa0: b580 push {r7, lr}
8011aa2: b084 sub sp, #16
8011aa4: af00 add r7, sp, #0
8011aa6: 6078 str r0, [r7, #4]
while (seg != NULL) {
8011aa8: e007 b.n 8011aba <tcp_segs_free+0x1a>
struct tcp_seg *next = seg->next;
8011aaa: 687b ldr r3, [r7, #4]
8011aac: 681b ldr r3, [r3, #0]
8011aae: 60fb str r3, [r7, #12]
tcp_seg_free(seg);
8011ab0: 6878 ldr r0, [r7, #4]
8011ab2: f000 f80a bl 8011aca <tcp_seg_free>
seg = next;
8011ab6: 68fb ldr r3, [r7, #12]
8011ab8: 607b str r3, [r7, #4]
while (seg != NULL) {
8011aba: 687b ldr r3, [r7, #4]
8011abc: 2b00 cmp r3, #0
8011abe: d1f4 bne.n 8011aaa <tcp_segs_free+0xa>
}
}
8011ac0: bf00 nop
8011ac2: bf00 nop
8011ac4: 3710 adds r7, #16
8011ac6: 46bd mov sp, r7
8011ac8: bd80 pop {r7, pc}
08011aca <tcp_seg_free>:
*
* @param seg single tcp_seg to free
*/
void
tcp_seg_free(struct tcp_seg *seg)
{
8011aca: b580 push {r7, lr}
8011acc: b082 sub sp, #8
8011ace: af00 add r7, sp, #0
8011ad0: 6078 str r0, [r7, #4]
if (seg != NULL) {
8011ad2: 687b ldr r3, [r7, #4]
8011ad4: 2b00 cmp r3, #0
8011ad6: d00c beq.n 8011af2 <tcp_seg_free+0x28>
if (seg->p != NULL) {
8011ad8: 687b ldr r3, [r7, #4]
8011ada: 685b ldr r3, [r3, #4]
8011adc: 2b00 cmp r3, #0
8011ade: d004 beq.n 8011aea <tcp_seg_free+0x20>
pbuf_free(seg->p);
8011ae0: 687b ldr r3, [r7, #4]
8011ae2: 685b ldr r3, [r3, #4]
8011ae4: 4618 mov r0, r3
8011ae6: f7fe fd61 bl 80105ac <pbuf_free>
#if TCP_DEBUG
seg->p = NULL;
#endif /* TCP_DEBUG */
}
memp_free(MEMP_TCP_SEG, seg);
8011aea: 6879 ldr r1, [r7, #4]
8011aec: 2003 movs r0, #3
8011aee: f7fd fead bl 800f84c <memp_free>
}
}
8011af2: bf00 nop
8011af4: 3708 adds r7, #8
8011af6: 46bd mov sp, r7
8011af8: bd80 pop {r7, pc}
...
08011afc <tcp_seg_copy>:
* @param seg the old tcp_seg
* @return a copy of seg
*/
struct tcp_seg *
tcp_seg_copy(struct tcp_seg *seg)
{
8011afc: b580 push {r7, lr}
8011afe: b084 sub sp, #16
8011b00: af00 add r7, sp, #0
8011b02: 6078 str r0, [r7, #4]
struct tcp_seg *cseg;
LWIP_ASSERT("tcp_seg_copy: invalid seg", seg != NULL);
8011b04: 687b ldr r3, [r7, #4]
8011b06: 2b00 cmp r3, #0
8011b08: d106 bne.n 8011b18 <tcp_seg_copy+0x1c>
8011b0a: 4b0f ldr r3, [pc, #60] ; (8011b48 <tcp_seg_copy+0x4c>)
8011b0c: f240 6282 movw r2, #1666 ; 0x682
8011b10: 490e ldr r1, [pc, #56] ; (8011b4c <tcp_seg_copy+0x50>)
8011b12: 480f ldr r0, [pc, #60] ; (8011b50 <tcp_seg_copy+0x54>)
8011b14: f009 fa56 bl 801afc4 <iprintf>
cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG);
8011b18: 2003 movs r0, #3
8011b1a: f7fd fe45 bl 800f7a8 <memp_malloc>
8011b1e: 60f8 str r0, [r7, #12]
if (cseg == NULL) {
8011b20: 68fb ldr r3, [r7, #12]
8011b22: 2b00 cmp r3, #0
8011b24: d101 bne.n 8011b2a <tcp_seg_copy+0x2e>
return NULL;
8011b26: 2300 movs r3, #0
8011b28: e00a b.n 8011b40 <tcp_seg_copy+0x44>
}
SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg));
8011b2a: 2210 movs r2, #16
8011b2c: 6879 ldr r1, [r7, #4]
8011b2e: 68f8 ldr r0, [r7, #12]
8011b30: f009 fa32 bl 801af98 <memcpy>
pbuf_ref(cseg->p);
8011b34: 68fb ldr r3, [r7, #12]
8011b36: 685b ldr r3, [r3, #4]
8011b38: 4618 mov r0, r3
8011b3a: f7fe fddd bl 80106f8 <pbuf_ref>
return cseg;
8011b3e: 68fb ldr r3, [r7, #12]
}
8011b40: 4618 mov r0, r3
8011b42: 3710 adds r7, #16
8011b44: 46bd mov sp, r7
8011b46: bd80 pop {r7, pc}
8011b48: 0801cd1c .word 0x0801cd1c
8011b4c: 0801d270 .word 0x0801d270
8011b50: 0801cd60 .word 0x0801cd60
08011b54 <tcp_recv_null>:
* Default receive callback that is called if the user didn't register
* a recv callback for the pcb.
*/
err_t
tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
{
8011b54: b580 push {r7, lr}
8011b56: b084 sub sp, #16
8011b58: af00 add r7, sp, #0
8011b5a: 60f8 str r0, [r7, #12]
8011b5c: 60b9 str r1, [r7, #8]
8011b5e: 607a str r2, [r7, #4]
8011b60: 70fb strb r3, [r7, #3]
LWIP_UNUSED_ARG(arg);
LWIP_ERROR("tcp_recv_null: invalid pcb", pcb != NULL, return ERR_ARG);
8011b62: 68bb ldr r3, [r7, #8]
8011b64: 2b00 cmp r3, #0
8011b66: d109 bne.n 8011b7c <tcp_recv_null+0x28>
8011b68: 4b12 ldr r3, [pc, #72] ; (8011bb4 <tcp_recv_null+0x60>)
8011b6a: f44f 62d3 mov.w r2, #1688 ; 0x698
8011b6e: 4912 ldr r1, [pc, #72] ; (8011bb8 <tcp_recv_null+0x64>)
8011b70: 4812 ldr r0, [pc, #72] ; (8011bbc <tcp_recv_null+0x68>)
8011b72: f009 fa27 bl 801afc4 <iprintf>
8011b76: f06f 030f mvn.w r3, #15
8011b7a: e016 b.n 8011baa <tcp_recv_null+0x56>
if (p != NULL) {
8011b7c: 687b ldr r3, [r7, #4]
8011b7e: 2b00 cmp r3, #0
8011b80: d009 beq.n 8011b96 <tcp_recv_null+0x42>
tcp_recved(pcb, p->tot_len);
8011b82: 687b ldr r3, [r7, #4]
8011b84: 891b ldrh r3, [r3, #8]
8011b86: 4619 mov r1, r3
8011b88: 68b8 ldr r0, [r7, #8]
8011b8a: f7ff fb19 bl 80111c0 <tcp_recved>
pbuf_free(p);
8011b8e: 6878 ldr r0, [r7, #4]
8011b90: f7fe fd0c bl 80105ac <pbuf_free>
8011b94: e008 b.n 8011ba8 <tcp_recv_null+0x54>
} else if (err == ERR_OK) {
8011b96: f997 3003 ldrsb.w r3, [r7, #3]
8011b9a: 2b00 cmp r3, #0
8011b9c: d104 bne.n 8011ba8 <tcp_recv_null+0x54>
return tcp_close(pcb);
8011b9e: 68b8 ldr r0, [r7, #8]
8011ba0: f7ff f9be bl 8010f20 <tcp_close>
8011ba4: 4603 mov r3, r0
8011ba6: e000 b.n 8011baa <tcp_recv_null+0x56>
}
return ERR_OK;
8011ba8: 2300 movs r3, #0
}
8011baa: 4618 mov r0, r3
8011bac: 3710 adds r7, #16
8011bae: 46bd mov sp, r7
8011bb0: bd80 pop {r7, pc}
8011bb2: bf00 nop
8011bb4: 0801cd1c .word 0x0801cd1c
8011bb8: 0801d28c .word 0x0801d28c
8011bbc: 0801cd60 .word 0x0801cd60
08011bc0 <tcp_kill_prio>:
*
* @param prio minimum priority
*/
static void
tcp_kill_prio(u8_t prio)
{
8011bc0: b580 push {r7, lr}
8011bc2: b086 sub sp, #24
8011bc4: af00 add r7, sp, #0
8011bc6: 4603 mov r3, r0
8011bc8: 71fb strb r3, [r7, #7]
struct tcp_pcb *pcb, *inactive;
u32_t inactivity;
u8_t mprio;
mprio = LWIP_MIN(TCP_PRIO_MAX, prio);
8011bca: f997 3007 ldrsb.w r3, [r7, #7]
8011bce: 2b00 cmp r3, #0
8011bd0: db01 blt.n 8011bd6 <tcp_kill_prio+0x16>
8011bd2: 79fb ldrb r3, [r7, #7]
8011bd4: e000 b.n 8011bd8 <tcp_kill_prio+0x18>
8011bd6: 237f movs r3, #127 ; 0x7f
8011bd8: 72fb strb r3, [r7, #11]
/* We want to kill connections with a lower prio, so bail out if
* supplied prio is 0 - there can never be a lower prio
*/
if (mprio == 0) {
8011bda: 7afb ldrb r3, [r7, #11]
8011bdc: 2b00 cmp r3, #0
8011bde: d034 beq.n 8011c4a <tcp_kill_prio+0x8a>
/* We only want kill connections with a lower prio, so decrement prio by one
* and start searching for oldest connection with same or lower priority than mprio.
* We want to find the connections with the lowest possible prio, and among
* these the one with the longest inactivity time.
*/
mprio--;
8011be0: 7afb ldrb r3, [r7, #11]
8011be2: 3b01 subs r3, #1
8011be4: 72fb strb r3, [r7, #11]
inactivity = 0;
8011be6: 2300 movs r3, #0
8011be8: 60fb str r3, [r7, #12]
inactive = NULL;
8011bea: 2300 movs r3, #0
8011bec: 613b str r3, [r7, #16]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8011bee: 4b19 ldr r3, [pc, #100] ; (8011c54 <tcp_kill_prio+0x94>)
8011bf0: 681b ldr r3, [r3, #0]
8011bf2: 617b str r3, [r7, #20]
8011bf4: e01f b.n 8011c36 <tcp_kill_prio+0x76>
/* lower prio is always a kill candidate */
if ((pcb->prio < mprio) ||
8011bf6: 697b ldr r3, [r7, #20]
8011bf8: 7d5b ldrb r3, [r3, #21]
8011bfa: 7afa ldrb r2, [r7, #11]
8011bfc: 429a cmp r2, r3
8011bfe: d80c bhi.n 8011c1a <tcp_kill_prio+0x5a>
/* longer inactivity is also a kill candidate */
((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
8011c00: 697b ldr r3, [r7, #20]
8011c02: 7d5b ldrb r3, [r3, #21]
if ((pcb->prio < mprio) ||
8011c04: 7afa ldrb r2, [r7, #11]
8011c06: 429a cmp r2, r3
8011c08: d112 bne.n 8011c30 <tcp_kill_prio+0x70>
((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
8011c0a: 4b13 ldr r3, [pc, #76] ; (8011c58 <tcp_kill_prio+0x98>)
8011c0c: 681a ldr r2, [r3, #0]
8011c0e: 697b ldr r3, [r7, #20]
8011c10: 6a1b ldr r3, [r3, #32]
8011c12: 1ad3 subs r3, r2, r3
8011c14: 68fa ldr r2, [r7, #12]
8011c16: 429a cmp r2, r3
8011c18: d80a bhi.n 8011c30 <tcp_kill_prio+0x70>
inactivity = tcp_ticks - pcb->tmr;
8011c1a: 4b0f ldr r3, [pc, #60] ; (8011c58 <tcp_kill_prio+0x98>)
8011c1c: 681a ldr r2, [r3, #0]
8011c1e: 697b ldr r3, [r7, #20]
8011c20: 6a1b ldr r3, [r3, #32]
8011c22: 1ad3 subs r3, r2, r3
8011c24: 60fb str r3, [r7, #12]
inactive = pcb;
8011c26: 697b ldr r3, [r7, #20]
8011c28: 613b str r3, [r7, #16]
mprio = pcb->prio;
8011c2a: 697b ldr r3, [r7, #20]
8011c2c: 7d5b ldrb r3, [r3, #21]
8011c2e: 72fb strb r3, [r7, #11]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8011c30: 697b ldr r3, [r7, #20]
8011c32: 68db ldr r3, [r3, #12]
8011c34: 617b str r3, [r7, #20]
8011c36: 697b ldr r3, [r7, #20]
8011c38: 2b00 cmp r3, #0
8011c3a: d1dc bne.n 8011bf6 <tcp_kill_prio+0x36>
}
}
if (inactive != NULL) {
8011c3c: 693b ldr r3, [r7, #16]
8011c3e: 2b00 cmp r3, #0
8011c40: d004 beq.n 8011c4c <tcp_kill_prio+0x8c>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
(void *)inactive, inactivity));
tcp_abort(inactive);
8011c42: 6938 ldr r0, [r7, #16]
8011c44: f7ff fa56 bl 80110f4 <tcp_abort>
8011c48: e000 b.n 8011c4c <tcp_kill_prio+0x8c>
return;
8011c4a: bf00 nop
}
}
8011c4c: 3718 adds r7, #24
8011c4e: 46bd mov sp, r7
8011c50: bd80 pop {r7, pc}
8011c52: bf00 nop
8011c54: 2000f83c .word 0x2000f83c
8011c58: 2000f840 .word 0x2000f840
08011c5c <tcp_kill_state>:
* Kills the oldest connection that is in specific state.
* Called from tcp_alloc() for LAST_ACK and CLOSING if no more connections are available.
*/
static void
tcp_kill_state(enum tcp_state state)
{
8011c5c: b580 push {r7, lr}
8011c5e: b086 sub sp, #24
8011c60: af00 add r7, sp, #0
8011c62: 4603 mov r3, r0
8011c64: 71fb strb r3, [r7, #7]
struct tcp_pcb *pcb, *inactive;
u32_t inactivity;
LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK));
8011c66: 79fb ldrb r3, [r7, #7]
8011c68: 2b08 cmp r3, #8
8011c6a: d009 beq.n 8011c80 <tcp_kill_state+0x24>
8011c6c: 79fb ldrb r3, [r7, #7]
8011c6e: 2b09 cmp r3, #9
8011c70: d006 beq.n 8011c80 <tcp_kill_state+0x24>
8011c72: 4b1a ldr r3, [pc, #104] ; (8011cdc <tcp_kill_state+0x80>)
8011c74: f240 62dd movw r2, #1757 ; 0x6dd
8011c78: 4919 ldr r1, [pc, #100] ; (8011ce0 <tcp_kill_state+0x84>)
8011c7a: 481a ldr r0, [pc, #104] ; (8011ce4 <tcp_kill_state+0x88>)
8011c7c: f009 f9a2 bl 801afc4 <iprintf>
inactivity = 0;
8011c80: 2300 movs r3, #0
8011c82: 60fb str r3, [r7, #12]
inactive = NULL;
8011c84: 2300 movs r3, #0
8011c86: 613b str r3, [r7, #16]
/* Go through the list of active pcbs and get the oldest pcb that is in state
CLOSING/LAST_ACK. */
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8011c88: 4b17 ldr r3, [pc, #92] ; (8011ce8 <tcp_kill_state+0x8c>)
8011c8a: 681b ldr r3, [r3, #0]
8011c8c: 617b str r3, [r7, #20]
8011c8e: e017 b.n 8011cc0 <tcp_kill_state+0x64>
if (pcb->state == state) {
8011c90: 697b ldr r3, [r7, #20]
8011c92: 7d1b ldrb r3, [r3, #20]
8011c94: 79fa ldrb r2, [r7, #7]
8011c96: 429a cmp r2, r3
8011c98: d10f bne.n 8011cba <tcp_kill_state+0x5e>
if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
8011c9a: 4b14 ldr r3, [pc, #80] ; (8011cec <tcp_kill_state+0x90>)
8011c9c: 681a ldr r2, [r3, #0]
8011c9e: 697b ldr r3, [r7, #20]
8011ca0: 6a1b ldr r3, [r3, #32]
8011ca2: 1ad3 subs r3, r2, r3
8011ca4: 68fa ldr r2, [r7, #12]
8011ca6: 429a cmp r2, r3
8011ca8: d807 bhi.n 8011cba <tcp_kill_state+0x5e>
inactivity = tcp_ticks - pcb->tmr;
8011caa: 4b10 ldr r3, [pc, #64] ; (8011cec <tcp_kill_state+0x90>)
8011cac: 681a ldr r2, [r3, #0]
8011cae: 697b ldr r3, [r7, #20]
8011cb0: 6a1b ldr r3, [r3, #32]
8011cb2: 1ad3 subs r3, r2, r3
8011cb4: 60fb str r3, [r7, #12]
inactive = pcb;
8011cb6: 697b ldr r3, [r7, #20]
8011cb8: 613b str r3, [r7, #16]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8011cba: 697b ldr r3, [r7, #20]
8011cbc: 68db ldr r3, [r3, #12]
8011cbe: 617b str r3, [r7, #20]
8011cc0: 697b ldr r3, [r7, #20]
8011cc2: 2b00 cmp r3, #0
8011cc4: d1e4 bne.n 8011c90 <tcp_kill_state+0x34>
}
}
}
if (inactive != NULL) {
8011cc6: 693b ldr r3, [r7, #16]
8011cc8: 2b00 cmp r3, #0
8011cca: d003 beq.n 8011cd4 <tcp_kill_state+0x78>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_closing: killing oldest %s PCB %p (%"S32_F")\n",
tcp_state_str[state], (void *)inactive, inactivity));
/* Don't send a RST, since no data is lost. */
tcp_abandon(inactive, 0);
8011ccc: 2100 movs r1, #0
8011cce: 6938 ldr r0, [r7, #16]
8011cd0: f7ff f952 bl 8010f78 <tcp_abandon>
}
}
8011cd4: bf00 nop
8011cd6: 3718 adds r7, #24
8011cd8: 46bd mov sp, r7
8011cda: bd80 pop {r7, pc}
8011cdc: 0801cd1c .word 0x0801cd1c
8011ce0: 0801d2a8 .word 0x0801d2a8
8011ce4: 0801cd60 .word 0x0801cd60
8011ce8: 2000f83c .word 0x2000f83c
8011cec: 2000f840 .word 0x2000f840
08011cf0 <tcp_kill_timewait>:
* Kills the oldest connection that is in TIME_WAIT state.
* Called from tcp_alloc() if no more connections are available.
*/
static void
tcp_kill_timewait(void)
{
8011cf0: b580 push {r7, lr}
8011cf2: b084 sub sp, #16
8011cf4: af00 add r7, sp, #0
struct tcp_pcb *pcb, *inactive;
u32_t inactivity;
inactivity = 0;
8011cf6: 2300 movs r3, #0
8011cf8: 607b str r3, [r7, #4]
inactive = NULL;
8011cfa: 2300 movs r3, #0
8011cfc: 60bb str r3, [r7, #8]
/* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
8011cfe: 4b12 ldr r3, [pc, #72] ; (8011d48 <tcp_kill_timewait+0x58>)
8011d00: 681b ldr r3, [r3, #0]
8011d02: 60fb str r3, [r7, #12]
8011d04: e012 b.n 8011d2c <tcp_kill_timewait+0x3c>
if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
8011d06: 4b11 ldr r3, [pc, #68] ; (8011d4c <tcp_kill_timewait+0x5c>)
8011d08: 681a ldr r2, [r3, #0]
8011d0a: 68fb ldr r3, [r7, #12]
8011d0c: 6a1b ldr r3, [r3, #32]
8011d0e: 1ad3 subs r3, r2, r3
8011d10: 687a ldr r2, [r7, #4]
8011d12: 429a cmp r2, r3
8011d14: d807 bhi.n 8011d26 <tcp_kill_timewait+0x36>
inactivity = tcp_ticks - pcb->tmr;
8011d16: 4b0d ldr r3, [pc, #52] ; (8011d4c <tcp_kill_timewait+0x5c>)
8011d18: 681a ldr r2, [r3, #0]
8011d1a: 68fb ldr r3, [r7, #12]
8011d1c: 6a1b ldr r3, [r3, #32]
8011d1e: 1ad3 subs r3, r2, r3
8011d20: 607b str r3, [r7, #4]
inactive = pcb;
8011d22: 68fb ldr r3, [r7, #12]
8011d24: 60bb str r3, [r7, #8]
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
8011d26: 68fb ldr r3, [r7, #12]
8011d28: 68db ldr r3, [r3, #12]
8011d2a: 60fb str r3, [r7, #12]
8011d2c: 68fb ldr r3, [r7, #12]
8011d2e: 2b00 cmp r3, #0
8011d30: d1e9 bne.n 8011d06 <tcp_kill_timewait+0x16>
}
}
if (inactive != NULL) {
8011d32: 68bb ldr r3, [r7, #8]
8011d34: 2b00 cmp r3, #0
8011d36: d002 beq.n 8011d3e <tcp_kill_timewait+0x4e>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
(void *)inactive, inactivity));
tcp_abort(inactive);
8011d38: 68b8 ldr r0, [r7, #8]
8011d3a: f7ff f9db bl 80110f4 <tcp_abort>
}
}
8011d3e: bf00 nop
8011d40: 3710 adds r7, #16
8011d42: 46bd mov sp, r7
8011d44: bd80 pop {r7, pc}
8011d46: bf00 nop
8011d48: 2000f84c .word 0x2000f84c
8011d4c: 2000f840 .word 0x2000f840
08011d50 <tcp_handle_closepend>:
* now send the FIN (which failed before), the pcb might be in a state that is
* OK for us to now free it.
*/
static void
tcp_handle_closepend(void)
{
8011d50: b580 push {r7, lr}
8011d52: b082 sub sp, #8
8011d54: af00 add r7, sp, #0
struct tcp_pcb *pcb = tcp_active_pcbs;
8011d56: 4b10 ldr r3, [pc, #64] ; (8011d98 <tcp_handle_closepend+0x48>)
8011d58: 681b ldr r3, [r3, #0]
8011d5a: 607b str r3, [r7, #4]
while (pcb != NULL) {
8011d5c: e014 b.n 8011d88 <tcp_handle_closepend+0x38>
struct tcp_pcb *next = pcb->next;
8011d5e: 687b ldr r3, [r7, #4]
8011d60: 68db ldr r3, [r3, #12]
8011d62: 603b str r3, [r7, #0]
/* send pending FIN */
if (pcb->flags & TF_CLOSEPEND) {
8011d64: 687b ldr r3, [r7, #4]
8011d66: 8b5b ldrh r3, [r3, #26]
8011d68: f003 0308 and.w r3, r3, #8
8011d6c: 2b00 cmp r3, #0
8011d6e: d009 beq.n 8011d84 <tcp_handle_closepend+0x34>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_handle_closepend: pending FIN\n"));
tcp_clear_flags(pcb, TF_CLOSEPEND);
8011d70: 687b ldr r3, [r7, #4]
8011d72: 8b5b ldrh r3, [r3, #26]
8011d74: f023 0308 bic.w r3, r3, #8
8011d78: b29a uxth r2, r3
8011d7a: 687b ldr r3, [r7, #4]
8011d7c: 835a strh r2, [r3, #26]
tcp_close_shutdown_fin(pcb);
8011d7e: 6878 ldr r0, [r7, #4]
8011d80: f7ff f864 bl 8010e4c <tcp_close_shutdown_fin>
}
pcb = next;
8011d84: 683b ldr r3, [r7, #0]
8011d86: 607b str r3, [r7, #4]
while (pcb != NULL) {
8011d88: 687b ldr r3, [r7, #4]
8011d8a: 2b00 cmp r3, #0
8011d8c: d1e7 bne.n 8011d5e <tcp_handle_closepend+0xe>
}
}
8011d8e: bf00 nop
8011d90: bf00 nop
8011d92: 3708 adds r7, #8
8011d94: 46bd mov sp, r7
8011d96: bd80 pop {r7, pc}
8011d98: 2000f83c .word 0x2000f83c
08011d9c <tcp_alloc>:
* @param prio priority for the new pcb
* @return a new tcp_pcb that initially is in state CLOSED
*/
struct tcp_pcb *
tcp_alloc(u8_t prio)
{
8011d9c: b580 push {r7, lr}
8011d9e: b084 sub sp, #16
8011da0: af00 add r7, sp, #0
8011da2: 4603 mov r3, r0
8011da4: 71fb strb r3, [r7, #7]
struct tcp_pcb *pcb;
LWIP_ASSERT_CORE_LOCKED();
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011da6: 2001 movs r0, #1
8011da8: f7fd fcfe bl 800f7a8 <memp_malloc>
8011dac: 60f8 str r0, [r7, #12]
if (pcb == NULL) {
8011dae: 68fb ldr r3, [r7, #12]
8011db0: 2b00 cmp r3, #0
8011db2: d126 bne.n 8011e02 <tcp_alloc+0x66>
/* Try to send FIN for all pcbs stuck in TF_CLOSEPEND first */
tcp_handle_closepend();
8011db4: f7ff ffcc bl 8011d50 <tcp_handle_closepend>
/* Try killing oldest connection in TIME-WAIT. */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
tcp_kill_timewait();
8011db8: f7ff ff9a bl 8011cf0 <tcp_kill_timewait>
/* Try to allocate a tcp_pcb again. */
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011dbc: 2001 movs r0, #1
8011dbe: f7fd fcf3 bl 800f7a8 <memp_malloc>
8011dc2: 60f8 str r0, [r7, #12]
if (pcb == NULL) {
8011dc4: 68fb ldr r3, [r7, #12]
8011dc6: 2b00 cmp r3, #0
8011dc8: d11b bne.n 8011e02 <tcp_alloc+0x66>
/* Try killing oldest connection in LAST-ACK (these wouldn't go to TIME-WAIT). */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest LAST-ACK connection\n"));
tcp_kill_state(LAST_ACK);
8011dca: 2009 movs r0, #9
8011dcc: f7ff ff46 bl 8011c5c <tcp_kill_state>
/* Try to allocate a tcp_pcb again. */
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011dd0: 2001 movs r0, #1
8011dd2: f7fd fce9 bl 800f7a8 <memp_malloc>
8011dd6: 60f8 str r0, [r7, #12]
if (pcb == NULL) {
8011dd8: 68fb ldr r3, [r7, #12]
8011dda: 2b00 cmp r3, #0
8011ddc: d111 bne.n 8011e02 <tcp_alloc+0x66>
/* Try killing oldest connection in CLOSING. */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest CLOSING connection\n"));
tcp_kill_state(CLOSING);
8011dde: 2008 movs r0, #8
8011de0: f7ff ff3c bl 8011c5c <tcp_kill_state>
/* Try to allocate a tcp_pcb again. */
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011de4: 2001 movs r0, #1
8011de6: f7fd fcdf bl 800f7a8 <memp_malloc>
8011dea: 60f8 str r0, [r7, #12]
if (pcb == NULL) {
8011dec: 68fb ldr r3, [r7, #12]
8011dee: 2b00 cmp r3, #0
8011df0: d107 bne.n 8011e02 <tcp_alloc+0x66>
/* Try killing oldest active connection with lower priority than the new one. */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio));
tcp_kill_prio(prio);
8011df2: 79fb ldrb r3, [r7, #7]
8011df4: 4618 mov r0, r3
8011df6: f7ff fee3 bl 8011bc0 <tcp_kill_prio>
/* Try to allocate a tcp_pcb again. */
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011dfa: 2001 movs r0, #1
8011dfc: f7fd fcd4 bl 800f7a8 <memp_malloc>
8011e00: 60f8 str r0, [r7, #12]
if (pcb != NULL) {
/* adjust err stats: memp_malloc failed above */
MEMP_STATS_DEC(err, MEMP_TCP_PCB);
}
}
if (pcb != NULL) {
8011e02: 68fb ldr r3, [r7, #12]
8011e04: 2b00 cmp r3, #0
8011e06: d03f beq.n 8011e88 <tcp_alloc+0xec>
/* zero out the whole pcb, so there is no need to initialize members to zero */
memset(pcb, 0, sizeof(struct tcp_pcb));
8011e08: 229c movs r2, #156 ; 0x9c
8011e0a: 2100 movs r1, #0
8011e0c: 68f8 ldr r0, [r7, #12]
8011e0e: f009 f8d1 bl 801afb4 <memset>
pcb->prio = prio;
8011e12: 68fb ldr r3, [r7, #12]
8011e14: 79fa ldrb r2, [r7, #7]
8011e16: 755a strb r2, [r3, #21]
pcb->snd_buf = TCP_SND_BUF;
8011e18: 68fb ldr r3, [r7, #12]
8011e1a: f44f 6286 mov.w r2, #1072 ; 0x430
8011e1e: f8a3 2064 strh.w r2, [r3, #100] ; 0x64
/* Start with a window that does not need scaling. When window scaling is
enabled and used, the window is enlarged when both sides agree on scaling. */
pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND);
8011e22: 68fb ldr r3, [r7, #12]
8011e24: f44f 6206 mov.w r2, #2144 ; 0x860
8011e28: 855a strh r2, [r3, #42] ; 0x2a
8011e2a: 68fb ldr r3, [r7, #12]
8011e2c: 8d5a ldrh r2, [r3, #42] ; 0x2a
8011e2e: 68fb ldr r3, [r7, #12]
8011e30: 851a strh r2, [r3, #40] ; 0x28
pcb->ttl = TCP_TTL;
8011e32: 68fb ldr r3, [r7, #12]
8011e34: 22ff movs r2, #255 ; 0xff
8011e36: 72da strb r2, [r3, #11]
/* As initial send MSS, we use TCP_MSS but limit it to 536.
The send MSS is updated when an MSS option is received. */
pcb->mss = INITIAL_MSS;
8011e38: 68fb ldr r3, [r7, #12]
8011e3a: f44f 7206 mov.w r2, #536 ; 0x218
8011e3e: 865a strh r2, [r3, #50] ; 0x32
pcb->rto = 3000 / TCP_SLOW_INTERVAL;
8011e40: 68fb ldr r3, [r7, #12]
8011e42: 2206 movs r2, #6
8011e44: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
pcb->sv = 3000 / TCP_SLOW_INTERVAL;
8011e48: 68fb ldr r3, [r7, #12]
8011e4a: 2206 movs r2, #6
8011e4c: 87da strh r2, [r3, #62] ; 0x3e
pcb->rtime = -1;
8011e4e: 68fb ldr r3, [r7, #12]
8011e50: f64f 72ff movw r2, #65535 ; 0xffff
8011e54: 861a strh r2, [r3, #48] ; 0x30
pcb->cwnd = 1;
8011e56: 68fb ldr r3, [r7, #12]
8011e58: 2201 movs r2, #1
8011e5a: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
pcb->tmr = tcp_ticks;
8011e5e: 4b0d ldr r3, [pc, #52] ; (8011e94 <tcp_alloc+0xf8>)
8011e60: 681a ldr r2, [r3, #0]
8011e62: 68fb ldr r3, [r7, #12]
8011e64: 621a str r2, [r3, #32]
pcb->last_timer = tcp_timer_ctr;
8011e66: 4b0c ldr r3, [pc, #48] ; (8011e98 <tcp_alloc+0xfc>)
8011e68: 781a ldrb r2, [r3, #0]
8011e6a: 68fb ldr r3, [r7, #12]
8011e6c: 779a strb r2, [r3, #30]
of using the largest advertised receive window. We've seen complications with
receiving TCPs that use window scaling and/or window auto-tuning where the
initial advertised window is very small and then grows rapidly once the
connection is established. To avoid these complications, we set ssthresh to the
largest effective cwnd (amount of in-flight data) that the sender can have. */
pcb->ssthresh = TCP_SND_BUF;
8011e6e: 68fb ldr r3, [r7, #12]
8011e70: f44f 6286 mov.w r2, #1072 ; 0x430
8011e74: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
#if LWIP_CALLBACK_API
pcb->recv = tcp_recv_null;
8011e78: 68fb ldr r3, [r7, #12]
8011e7a: 4a08 ldr r2, [pc, #32] ; (8011e9c <tcp_alloc+0x100>)
8011e7c: f8c3 2084 str.w r2, [r3, #132] ; 0x84
#endif /* LWIP_CALLBACK_API */
/* Init KEEPALIVE timer */
pcb->keep_idle = TCP_KEEPIDLE_DEFAULT;
8011e80: 68fb ldr r3, [r7, #12]
8011e82: 4a07 ldr r2, [pc, #28] ; (8011ea0 <tcp_alloc+0x104>)
8011e84: f8c3 2094 str.w r2, [r3, #148] ; 0x94
#if LWIP_TCP_KEEPALIVE
pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT;
pcb->keep_cnt = TCP_KEEPCNT_DEFAULT;
#endif /* LWIP_TCP_KEEPALIVE */
}
return pcb;
8011e88: 68fb ldr r3, [r7, #12]
}
8011e8a: 4618 mov r0, r3
8011e8c: 3710 adds r7, #16
8011e8e: 46bd mov sp, r7
8011e90: bd80 pop {r7, pc}
8011e92: bf00 nop
8011e94: 2000f840 .word 0x2000f840
8011e98: 2000871e .word 0x2000871e
8011e9c: 08011b55 .word 0x08011b55
8011ea0: 006ddd00 .word 0x006ddd00
08011ea4 <tcp_pcb_purge>:
*
* @param pcb tcp_pcb to purge. The pcb itself is not deallocated!
*/
void
tcp_pcb_purge(struct tcp_pcb *pcb)
{
8011ea4: b580 push {r7, lr}
8011ea6: b082 sub sp, #8
8011ea8: af00 add r7, sp, #0
8011eaa: 6078 str r0, [r7, #4]
LWIP_ERROR("tcp_pcb_purge: invalid pcb", pcb != NULL, return);
8011eac: 687b ldr r3, [r7, #4]
8011eae: 2b00 cmp r3, #0
8011eb0: d107 bne.n 8011ec2 <tcp_pcb_purge+0x1e>
8011eb2: 4b21 ldr r3, [pc, #132] ; (8011f38 <tcp_pcb_purge+0x94>)
8011eb4: f640 0251 movw r2, #2129 ; 0x851
8011eb8: 4920 ldr r1, [pc, #128] ; (8011f3c <tcp_pcb_purge+0x98>)
8011eba: 4821 ldr r0, [pc, #132] ; (8011f40 <tcp_pcb_purge+0x9c>)
8011ebc: f009 f882 bl 801afc4 <iprintf>
8011ec0: e037 b.n 8011f32 <tcp_pcb_purge+0x8e>
if (pcb->state != CLOSED &&
8011ec2: 687b ldr r3, [r7, #4]
8011ec4: 7d1b ldrb r3, [r3, #20]
8011ec6: 2b00 cmp r3, #0
8011ec8: d033 beq.n 8011f32 <tcp_pcb_purge+0x8e>
pcb->state != TIME_WAIT &&
8011eca: 687b ldr r3, [r7, #4]
8011ecc: 7d1b ldrb r3, [r3, #20]
if (pcb->state != CLOSED &&
8011ece: 2b0a cmp r3, #10
8011ed0: d02f beq.n 8011f32 <tcp_pcb_purge+0x8e>
pcb->state != LISTEN) {
8011ed2: 687b ldr r3, [r7, #4]
8011ed4: 7d1b ldrb r3, [r3, #20]
pcb->state != TIME_WAIT &&
8011ed6: 2b01 cmp r3, #1
8011ed8: d02b beq.n 8011f32 <tcp_pcb_purge+0x8e>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
tcp_backlog_accepted(pcb);
if (pcb->refused_data != NULL) {
8011eda: 687b ldr r3, [r7, #4]
8011edc: 6f9b ldr r3, [r3, #120] ; 0x78
8011ede: 2b00 cmp r3, #0
8011ee0: d007 beq.n 8011ef2 <tcp_pcb_purge+0x4e>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n"));
pbuf_free(pcb->refused_data);
8011ee2: 687b ldr r3, [r7, #4]
8011ee4: 6f9b ldr r3, [r3, #120] ; 0x78
8011ee6: 4618 mov r0, r3
8011ee8: f7fe fb60 bl 80105ac <pbuf_free>
pcb->refused_data = NULL;
8011eec: 687b ldr r3, [r7, #4]
8011eee: 2200 movs r2, #0
8011ef0: 679a str r2, [r3, #120] ; 0x78
}
if (pcb->unacked != NULL) {
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
}
#if TCP_QUEUE_OOSEQ
if (pcb->ooseq != NULL) {
8011ef2: 687b ldr r3, [r7, #4]
8011ef4: 6f5b ldr r3, [r3, #116] ; 0x74
8011ef6: 2b00 cmp r3, #0
8011ef8: d002 beq.n 8011f00 <tcp_pcb_purge+0x5c>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
tcp_free_ooseq(pcb);
8011efa: 6878 ldr r0, [r7, #4]
8011efc: f000 f986 bl 801220c <tcp_free_ooseq>
}
#endif /* TCP_QUEUE_OOSEQ */
/* Stop the retransmission timer as it will expect data on unacked
queue if it fires */
pcb->rtime = -1;
8011f00: 687b ldr r3, [r7, #4]
8011f02: f64f 72ff movw r2, #65535 ; 0xffff
8011f06: 861a strh r2, [r3, #48] ; 0x30
tcp_segs_free(pcb->unsent);
8011f08: 687b ldr r3, [r7, #4]
8011f0a: 6edb ldr r3, [r3, #108] ; 0x6c
8011f0c: 4618 mov r0, r3
8011f0e: f7ff fdc7 bl 8011aa0 <tcp_segs_free>
tcp_segs_free(pcb->unacked);
8011f12: 687b ldr r3, [r7, #4]
8011f14: 6f1b ldr r3, [r3, #112] ; 0x70
8011f16: 4618 mov r0, r3
8011f18: f7ff fdc2 bl 8011aa0 <tcp_segs_free>
pcb->unacked = pcb->unsent = NULL;
8011f1c: 687b ldr r3, [r7, #4]
8011f1e: 2200 movs r2, #0
8011f20: 66da str r2, [r3, #108] ; 0x6c
8011f22: 687b ldr r3, [r7, #4]
8011f24: 6eda ldr r2, [r3, #108] ; 0x6c
8011f26: 687b ldr r3, [r7, #4]
8011f28: 671a str r2, [r3, #112] ; 0x70
#if TCP_OVERSIZE
pcb->unsent_oversize = 0;
8011f2a: 687b ldr r3, [r7, #4]
8011f2c: 2200 movs r2, #0
8011f2e: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
#endif /* TCP_OVERSIZE */
}
}
8011f32: 3708 adds r7, #8
8011f34: 46bd mov sp, r7
8011f36: bd80 pop {r7, pc}
8011f38: 0801cd1c .word 0x0801cd1c
8011f3c: 0801d368 .word 0x0801d368
8011f40: 0801cd60 .word 0x0801cd60
08011f44 <tcp_pcb_remove>:
* @param pcblist PCB list to purge.
* @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated!
*/
void
tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
{
8011f44: b580 push {r7, lr}
8011f46: b084 sub sp, #16
8011f48: af00 add r7, sp, #0
8011f4a: 6078 str r0, [r7, #4]
8011f4c: 6039 str r1, [r7, #0]
LWIP_ASSERT("tcp_pcb_remove: invalid pcb", pcb != NULL);
8011f4e: 683b ldr r3, [r7, #0]
8011f50: 2b00 cmp r3, #0
8011f52: d106 bne.n 8011f62 <tcp_pcb_remove+0x1e>
8011f54: 4b3e ldr r3, [pc, #248] ; (8012050 <tcp_pcb_remove+0x10c>)
8011f56: f640 0283 movw r2, #2179 ; 0x883
8011f5a: 493e ldr r1, [pc, #248] ; (8012054 <tcp_pcb_remove+0x110>)
8011f5c: 483e ldr r0, [pc, #248] ; (8012058 <tcp_pcb_remove+0x114>)
8011f5e: f009 f831 bl 801afc4 <iprintf>
LWIP_ASSERT("tcp_pcb_remove: invalid pcblist", pcblist != NULL);
8011f62: 687b ldr r3, [r7, #4]
8011f64: 2b00 cmp r3, #0
8011f66: d106 bne.n 8011f76 <tcp_pcb_remove+0x32>
8011f68: 4b39 ldr r3, [pc, #228] ; (8012050 <tcp_pcb_remove+0x10c>)
8011f6a: f640 0284 movw r2, #2180 ; 0x884
8011f6e: 493b ldr r1, [pc, #236] ; (801205c <tcp_pcb_remove+0x118>)
8011f70: 4839 ldr r0, [pc, #228] ; (8012058 <tcp_pcb_remove+0x114>)
8011f72: f009 f827 bl 801afc4 <iprintf>
TCP_RMV(pcblist, pcb);
8011f76: 687b ldr r3, [r7, #4]
8011f78: 681b ldr r3, [r3, #0]
8011f7a: 683a ldr r2, [r7, #0]
8011f7c: 429a cmp r2, r3
8011f7e: d105 bne.n 8011f8c <tcp_pcb_remove+0x48>
8011f80: 687b ldr r3, [r7, #4]
8011f82: 681b ldr r3, [r3, #0]
8011f84: 68da ldr r2, [r3, #12]
8011f86: 687b ldr r3, [r7, #4]
8011f88: 601a str r2, [r3, #0]
8011f8a: e013 b.n 8011fb4 <tcp_pcb_remove+0x70>
8011f8c: 687b ldr r3, [r7, #4]
8011f8e: 681b ldr r3, [r3, #0]
8011f90: 60fb str r3, [r7, #12]
8011f92: e00c b.n 8011fae <tcp_pcb_remove+0x6a>
8011f94: 68fb ldr r3, [r7, #12]
8011f96: 68db ldr r3, [r3, #12]
8011f98: 683a ldr r2, [r7, #0]
8011f9a: 429a cmp r2, r3
8011f9c: d104 bne.n 8011fa8 <tcp_pcb_remove+0x64>
8011f9e: 683b ldr r3, [r7, #0]
8011fa0: 68da ldr r2, [r3, #12]
8011fa2: 68fb ldr r3, [r7, #12]
8011fa4: 60da str r2, [r3, #12]
8011fa6: e005 b.n 8011fb4 <tcp_pcb_remove+0x70>
8011fa8: 68fb ldr r3, [r7, #12]
8011faa: 68db ldr r3, [r3, #12]
8011fac: 60fb str r3, [r7, #12]
8011fae: 68fb ldr r3, [r7, #12]
8011fb0: 2b00 cmp r3, #0
8011fb2: d1ef bne.n 8011f94 <tcp_pcb_remove+0x50>
8011fb4: 683b ldr r3, [r7, #0]
8011fb6: 2200 movs r2, #0
8011fb8: 60da str r2, [r3, #12]
tcp_pcb_purge(pcb);
8011fba: 6838 ldr r0, [r7, #0]
8011fbc: f7ff ff72 bl 8011ea4 <tcp_pcb_purge>
/* if there is an outstanding delayed ACKs, send it */
if ((pcb->state != TIME_WAIT) &&
8011fc0: 683b ldr r3, [r7, #0]
8011fc2: 7d1b ldrb r3, [r3, #20]
8011fc4: 2b0a cmp r3, #10
8011fc6: d013 beq.n 8011ff0 <tcp_pcb_remove+0xac>
(pcb->state != LISTEN) &&
8011fc8: 683b ldr r3, [r7, #0]
8011fca: 7d1b ldrb r3, [r3, #20]
if ((pcb->state != TIME_WAIT) &&
8011fcc: 2b01 cmp r3, #1
8011fce: d00f beq.n 8011ff0 <tcp_pcb_remove+0xac>
(pcb->flags & TF_ACK_DELAY)) {
8011fd0: 683b ldr r3, [r7, #0]
8011fd2: 8b5b ldrh r3, [r3, #26]
8011fd4: f003 0301 and.w r3, r3, #1
(pcb->state != LISTEN) &&
8011fd8: 2b00 cmp r3, #0
8011fda: d009 beq.n 8011ff0 <tcp_pcb_remove+0xac>
tcp_ack_now(pcb);
8011fdc: 683b ldr r3, [r7, #0]
8011fde: 8b5b ldrh r3, [r3, #26]
8011fe0: f043 0302 orr.w r3, r3, #2
8011fe4: b29a uxth r2, r3
8011fe6: 683b ldr r3, [r7, #0]
8011fe8: 835a strh r2, [r3, #26]
tcp_output(pcb);
8011fea: 6838 ldr r0, [r7, #0]
8011fec: f002 ff6a bl 8014ec4 <tcp_output>
}
if (pcb->state != LISTEN) {
8011ff0: 683b ldr r3, [r7, #0]
8011ff2: 7d1b ldrb r3, [r3, #20]
8011ff4: 2b01 cmp r3, #1
8011ff6: d020 beq.n 801203a <tcp_pcb_remove+0xf6>
LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL);
8011ff8: 683b ldr r3, [r7, #0]
8011ffa: 6edb ldr r3, [r3, #108] ; 0x6c
8011ffc: 2b00 cmp r3, #0
8011ffe: d006 beq.n 801200e <tcp_pcb_remove+0xca>
8012000: 4b13 ldr r3, [pc, #76] ; (8012050 <tcp_pcb_remove+0x10c>)
8012002: f640 0293 movw r2, #2195 ; 0x893
8012006: 4916 ldr r1, [pc, #88] ; (8012060 <tcp_pcb_remove+0x11c>)
8012008: 4813 ldr r0, [pc, #76] ; (8012058 <tcp_pcb_remove+0x114>)
801200a: f008 ffdb bl 801afc4 <iprintf>
LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL);
801200e: 683b ldr r3, [r7, #0]
8012010: 6f1b ldr r3, [r3, #112] ; 0x70
8012012: 2b00 cmp r3, #0
8012014: d006 beq.n 8012024 <tcp_pcb_remove+0xe0>
8012016: 4b0e ldr r3, [pc, #56] ; (8012050 <tcp_pcb_remove+0x10c>)
8012018: f640 0294 movw r2, #2196 ; 0x894
801201c: 4911 ldr r1, [pc, #68] ; (8012064 <tcp_pcb_remove+0x120>)
801201e: 480e ldr r0, [pc, #56] ; (8012058 <tcp_pcb_remove+0x114>)
8012020: f008 ffd0 bl 801afc4 <iprintf>
#if TCP_QUEUE_OOSEQ
LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL);
8012024: 683b ldr r3, [r7, #0]
8012026: 6f5b ldr r3, [r3, #116] ; 0x74
8012028: 2b00 cmp r3, #0
801202a: d006 beq.n 801203a <tcp_pcb_remove+0xf6>
801202c: 4b08 ldr r3, [pc, #32] ; (8012050 <tcp_pcb_remove+0x10c>)
801202e: f640 0296 movw r2, #2198 ; 0x896
8012032: 490d ldr r1, [pc, #52] ; (8012068 <tcp_pcb_remove+0x124>)
8012034: 4808 ldr r0, [pc, #32] ; (8012058 <tcp_pcb_remove+0x114>)
8012036: f008 ffc5 bl 801afc4 <iprintf>
#endif /* TCP_QUEUE_OOSEQ */
}
pcb->state = CLOSED;
801203a: 683b ldr r3, [r7, #0]
801203c: 2200 movs r2, #0
801203e: 751a strb r2, [r3, #20]
/* reset the local port to prevent the pcb from being 'bound' */
pcb->local_port = 0;
8012040: 683b ldr r3, [r7, #0]
8012042: 2200 movs r2, #0
8012044: 82da strh r2, [r3, #22]
LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
}
8012046: bf00 nop
8012048: 3710 adds r7, #16
801204a: 46bd mov sp, r7
801204c: bd80 pop {r7, pc}
801204e: bf00 nop
8012050: 0801cd1c .word 0x0801cd1c
8012054: 0801d384 .word 0x0801d384
8012058: 0801cd60 .word 0x0801cd60
801205c: 0801d3a0 .word 0x0801d3a0
8012060: 0801d3c0 .word 0x0801d3c0
8012064: 0801d3d8 .word 0x0801d3d8
8012068: 0801d3f4 .word 0x0801d3f4
0801206c <tcp_next_iss>:
*
* @return u32_t pseudo random sequence number
*/
u32_t
tcp_next_iss(struct tcp_pcb *pcb)
{
801206c: b580 push {r7, lr}
801206e: b082 sub sp, #8
8012070: af00 add r7, sp, #0
8012072: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
return LWIP_HOOK_TCP_ISN(&pcb->local_ip, pcb->local_port, &pcb->remote_ip, pcb->remote_port);
#else /* LWIP_HOOK_TCP_ISN */
static u32_t iss = 6510;
LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
8012074: 687b ldr r3, [r7, #4]
8012076: 2b00 cmp r3, #0
8012078: d106 bne.n 8012088 <tcp_next_iss+0x1c>
801207a: 4b0a ldr r3, [pc, #40] ; (80120a4 <tcp_next_iss+0x38>)
801207c: f640 02af movw r2, #2223 ; 0x8af
8012080: 4909 ldr r1, [pc, #36] ; (80120a8 <tcp_next_iss+0x3c>)
8012082: 480a ldr r0, [pc, #40] ; (80120ac <tcp_next_iss+0x40>)
8012084: f008 ff9e bl 801afc4 <iprintf>
LWIP_UNUSED_ARG(pcb);
iss += tcp_ticks; /* XXX */
8012088: 4b09 ldr r3, [pc, #36] ; (80120b0 <tcp_next_iss+0x44>)
801208a: 681a ldr r2, [r3, #0]
801208c: 4b09 ldr r3, [pc, #36] ; (80120b4 <tcp_next_iss+0x48>)
801208e: 681b ldr r3, [r3, #0]
8012090: 4413 add r3, r2
8012092: 4a07 ldr r2, [pc, #28] ; (80120b0 <tcp_next_iss+0x44>)
8012094: 6013 str r3, [r2, #0]
return iss;
8012096: 4b06 ldr r3, [pc, #24] ; (80120b0 <tcp_next_iss+0x44>)
8012098: 681b ldr r3, [r3, #0]
#endif /* LWIP_HOOK_TCP_ISN */
}
801209a: 4618 mov r0, r3
801209c: 3708 adds r7, #8
801209e: 46bd mov sp, r7
80120a0: bd80 pop {r7, pc}
80120a2: bf00 nop
80120a4: 0801cd1c .word 0x0801cd1c
80120a8: 0801d40c .word 0x0801d40c
80120ac: 0801cd60 .word 0x0801cd60
80120b0: 2000006c .word 0x2000006c
80120b4: 2000f840 .word 0x2000f840
080120b8 <tcp_eff_send_mss_netif>:
* by calculating the minimum of TCP_MSS and the mtu (if set) of the target
* netif (if not NULL).
*/
u16_t
tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif, const ip_addr_t *dest)
{
80120b8: b580 push {r7, lr}
80120ba: b086 sub sp, #24
80120bc: af00 add r7, sp, #0
80120be: 4603 mov r3, r0
80120c0: 60b9 str r1, [r7, #8]
80120c2: 607a str r2, [r7, #4]
80120c4: 81fb strh r3, [r7, #14]
u16_t mss_s;
u16_t mtu;
LWIP_UNUSED_ARG(dest); /* in case IPv6 is disabled */
LWIP_ASSERT("tcp_eff_send_mss_netif: invalid dst_ip", dest != NULL);
80120c6: 687b ldr r3, [r7, #4]
80120c8: 2b00 cmp r3, #0
80120ca: d106 bne.n 80120da <tcp_eff_send_mss_netif+0x22>
80120cc: 4b14 ldr r3, [pc, #80] ; (8012120 <tcp_eff_send_mss_netif+0x68>)
80120ce: f640 02c5 movw r2, #2245 ; 0x8c5
80120d2: 4914 ldr r1, [pc, #80] ; (8012124 <tcp_eff_send_mss_netif+0x6c>)
80120d4: 4814 ldr r0, [pc, #80] ; (8012128 <tcp_eff_send_mss_netif+0x70>)
80120d6: f008 ff75 bl 801afc4 <iprintf>
else
#endif /* LWIP_IPV4 */
#endif /* LWIP_IPV6 */
#if LWIP_IPV4
{
if (outif == NULL) {
80120da: 68bb ldr r3, [r7, #8]
80120dc: 2b00 cmp r3, #0
80120de: d101 bne.n 80120e4 <tcp_eff_send_mss_netif+0x2c>
return sendmss;
80120e0: 89fb ldrh r3, [r7, #14]
80120e2: e019 b.n 8012118 <tcp_eff_send_mss_netif+0x60>
}
mtu = outif->mtu;
80120e4: 68bb ldr r3, [r7, #8]
80120e6: 8d1b ldrh r3, [r3, #40] ; 0x28
80120e8: 82fb strh r3, [r7, #22]
}
#endif /* LWIP_IPV4 */
if (mtu != 0) {
80120ea: 8afb ldrh r3, [r7, #22]
80120ec: 2b00 cmp r3, #0
80120ee: d012 beq.n 8012116 <tcp_eff_send_mss_netif+0x5e>
else
#endif /* LWIP_IPV4 */
#endif /* LWIP_IPV6 */
#if LWIP_IPV4
{
offset = IP_HLEN + TCP_HLEN;
80120f0: 2328 movs r3, #40 ; 0x28
80120f2: 82bb strh r3, [r7, #20]
}
#endif /* LWIP_IPV4 */
mss_s = (mtu > offset) ? (u16_t)(mtu - offset) : 0;
80120f4: 8afa ldrh r2, [r7, #22]
80120f6: 8abb ldrh r3, [r7, #20]
80120f8: 429a cmp r2, r3
80120fa: d904 bls.n 8012106 <tcp_eff_send_mss_netif+0x4e>
80120fc: 8afa ldrh r2, [r7, #22]
80120fe: 8abb ldrh r3, [r7, #20]
8012100: 1ad3 subs r3, r2, r3
8012102: b29b uxth r3, r3
8012104: e000 b.n 8012108 <tcp_eff_send_mss_netif+0x50>
8012106: 2300 movs r3, #0
8012108: 827b strh r3, [r7, #18]
/* RFC 1122, chap 4.2.2.6:
* Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize
* We correct for TCP options in tcp_write(), and don't support IP options.
*/
sendmss = LWIP_MIN(sendmss, mss_s);
801210a: 8a7a ldrh r2, [r7, #18]
801210c: 89fb ldrh r3, [r7, #14]
801210e: 4293 cmp r3, r2
8012110: bf28 it cs
8012112: 4613 movcs r3, r2
8012114: 81fb strh r3, [r7, #14]
}
return sendmss;
8012116: 89fb ldrh r3, [r7, #14]
}
8012118: 4618 mov r0, r3
801211a: 3718 adds r7, #24
801211c: 46bd mov sp, r7
801211e: bd80 pop {r7, pc}
8012120: 0801cd1c .word 0x0801cd1c
8012124: 0801d428 .word 0x0801d428
8012128: 0801cd60 .word 0x0801cd60
0801212c <tcp_netif_ip_addr_changed_pcblist>:
#endif /* TCP_CALCULATE_EFF_SEND_MSS */
/** Helper function for tcp_netif_ip_addr_changed() that iterates a pcb list */
static void
tcp_netif_ip_addr_changed_pcblist(const ip_addr_t *old_addr, struct tcp_pcb *pcb_list)
{
801212c: b580 push {r7, lr}
801212e: b084 sub sp, #16
8012130: af00 add r7, sp, #0
8012132: 6078 str r0, [r7, #4]
8012134: 6039 str r1, [r7, #0]
struct tcp_pcb *pcb;
pcb = pcb_list;
8012136: 683b ldr r3, [r7, #0]
8012138: 60fb str r3, [r7, #12]
LWIP_ASSERT("tcp_netif_ip_addr_changed_pcblist: invalid old_addr", old_addr != NULL);
801213a: 687b ldr r3, [r7, #4]
801213c: 2b00 cmp r3, #0
801213e: d119 bne.n 8012174 <tcp_netif_ip_addr_changed_pcblist+0x48>
8012140: 4b10 ldr r3, [pc, #64] ; (8012184 <tcp_netif_ip_addr_changed_pcblist+0x58>)
8012142: f44f 6210 mov.w r2, #2304 ; 0x900
8012146: 4910 ldr r1, [pc, #64] ; (8012188 <tcp_netif_ip_addr_changed_pcblist+0x5c>)
8012148: 4810 ldr r0, [pc, #64] ; (801218c <tcp_netif_ip_addr_changed_pcblist+0x60>)
801214a: f008 ff3b bl 801afc4 <iprintf>
while (pcb != NULL) {
801214e: e011 b.n 8012174 <tcp_netif_ip_addr_changed_pcblist+0x48>
/* PCB bound to current local interface address? */
if (ip_addr_cmp(&pcb->local_ip, old_addr)
8012150: 68fb ldr r3, [r7, #12]
8012152: 681a ldr r2, [r3, #0]
8012154: 687b ldr r3, [r7, #4]
8012156: 681b ldr r3, [r3, #0]
8012158: 429a cmp r2, r3
801215a: d108 bne.n 801216e <tcp_netif_ip_addr_changed_pcblist+0x42>
/* connections to link-local addresses must persist (RFC3927 ch. 1.9) */
&& (!IP_IS_V4_VAL(pcb->local_ip) || !ip4_addr_islinklocal(ip_2_ip4(&pcb->local_ip)))
#endif /* LWIP_AUTOIP */
) {
/* this connection must be aborted */
struct tcp_pcb *next = pcb->next;
801215c: 68fb ldr r3, [r7, #12]
801215e: 68db ldr r3, [r3, #12]
8012160: 60bb str r3, [r7, #8]
LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
tcp_abort(pcb);
8012162: 68f8 ldr r0, [r7, #12]
8012164: f7fe ffc6 bl 80110f4 <tcp_abort>
pcb = next;
8012168: 68bb ldr r3, [r7, #8]
801216a: 60fb str r3, [r7, #12]
801216c: e002 b.n 8012174 <tcp_netif_ip_addr_changed_pcblist+0x48>
} else {
pcb = pcb->next;
801216e: 68fb ldr r3, [r7, #12]
8012170: 68db ldr r3, [r3, #12]
8012172: 60fb str r3, [r7, #12]
while (pcb != NULL) {
8012174: 68fb ldr r3, [r7, #12]
8012176: 2b00 cmp r3, #0
8012178: d1ea bne.n 8012150 <tcp_netif_ip_addr_changed_pcblist+0x24>
}
}
}
801217a: bf00 nop
801217c: bf00 nop
801217e: 3710 adds r7, #16
8012180: 46bd mov sp, r7
8012182: bd80 pop {r7, pc}
8012184: 0801cd1c .word 0x0801cd1c
8012188: 0801d450 .word 0x0801d450
801218c: 0801cd60 .word 0x0801cd60
08012190 <tcp_netif_ip_addr_changed>:
* @param old_addr IP address of the netif before change
* @param new_addr IP address of the netif after change or NULL if netif has been removed
*/
void
tcp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
{
8012190: b580 push {r7, lr}
8012192: b084 sub sp, #16
8012194: af00 add r7, sp, #0
8012196: 6078 str r0, [r7, #4]
8012198: 6039 str r1, [r7, #0]
struct tcp_pcb_listen *lpcb;
if (!ip_addr_isany(old_addr)) {
801219a: 687b ldr r3, [r7, #4]
801219c: 2b00 cmp r3, #0
801219e: d02a beq.n 80121f6 <tcp_netif_ip_addr_changed+0x66>
80121a0: 687b ldr r3, [r7, #4]
80121a2: 681b ldr r3, [r3, #0]
80121a4: 2b00 cmp r3, #0
80121a6: d026 beq.n 80121f6 <tcp_netif_ip_addr_changed+0x66>
tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_active_pcbs);
80121a8: 4b15 ldr r3, [pc, #84] ; (8012200 <tcp_netif_ip_addr_changed+0x70>)
80121aa: 681b ldr r3, [r3, #0]
80121ac: 4619 mov r1, r3
80121ae: 6878 ldr r0, [r7, #4]
80121b0: f7ff ffbc bl 801212c <tcp_netif_ip_addr_changed_pcblist>
tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_bound_pcbs);
80121b4: 4b13 ldr r3, [pc, #76] ; (8012204 <tcp_netif_ip_addr_changed+0x74>)
80121b6: 681b ldr r3, [r3, #0]
80121b8: 4619 mov r1, r3
80121ba: 6878 ldr r0, [r7, #4]
80121bc: f7ff ffb6 bl 801212c <tcp_netif_ip_addr_changed_pcblist>
if (!ip_addr_isany(new_addr)) {
80121c0: 683b ldr r3, [r7, #0]
80121c2: 2b00 cmp r3, #0
80121c4: d017 beq.n 80121f6 <tcp_netif_ip_addr_changed+0x66>
80121c6: 683b ldr r3, [r7, #0]
80121c8: 681b ldr r3, [r3, #0]
80121ca: 2b00 cmp r3, #0
80121cc: d013 beq.n 80121f6 <tcp_netif_ip_addr_changed+0x66>
/* PCB bound to current local interface address? */
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
80121ce: 4b0e ldr r3, [pc, #56] ; (8012208 <tcp_netif_ip_addr_changed+0x78>)
80121d0: 681b ldr r3, [r3, #0]
80121d2: 60fb str r3, [r7, #12]
80121d4: e00c b.n 80121f0 <tcp_netif_ip_addr_changed+0x60>
/* PCB bound to current local interface address? */
if (ip_addr_cmp(&lpcb->local_ip, old_addr)) {
80121d6: 68fb ldr r3, [r7, #12]
80121d8: 681a ldr r2, [r3, #0]
80121da: 687b ldr r3, [r7, #4]
80121dc: 681b ldr r3, [r3, #0]
80121de: 429a cmp r2, r3
80121e0: d103 bne.n 80121ea <tcp_netif_ip_addr_changed+0x5a>
/* The PCB is listening to the old ipaddr and
* is set to listen to the new one instead */
ip_addr_copy(lpcb->local_ip, *new_addr);
80121e2: 683b ldr r3, [r7, #0]
80121e4: 681a ldr r2, [r3, #0]
80121e6: 68fb ldr r3, [r7, #12]
80121e8: 601a str r2, [r3, #0]
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
80121ea: 68fb ldr r3, [r7, #12]
80121ec: 68db ldr r3, [r3, #12]
80121ee: 60fb str r3, [r7, #12]
80121f0: 68fb ldr r3, [r7, #12]
80121f2: 2b00 cmp r3, #0
80121f4: d1ef bne.n 80121d6 <tcp_netif_ip_addr_changed+0x46>
}
}
}
}
}
80121f6: bf00 nop
80121f8: 3710 adds r7, #16
80121fa: 46bd mov sp, r7
80121fc: bd80 pop {r7, pc}
80121fe: bf00 nop
8012200: 2000f83c .word 0x2000f83c
8012204: 2000f848 .word 0x2000f848
8012208: 2000f844 .word 0x2000f844
0801220c <tcp_free_ooseq>:
#if TCP_QUEUE_OOSEQ
/* Free all ooseq pbufs (and possibly reset SACK state) */
void
tcp_free_ooseq(struct tcp_pcb *pcb)
{
801220c: b580 push {r7, lr}
801220e: b082 sub sp, #8
8012210: af00 add r7, sp, #0
8012212: 6078 str r0, [r7, #4]
if (pcb->ooseq) {
8012214: 687b ldr r3, [r7, #4]
8012216: 6f5b ldr r3, [r3, #116] ; 0x74
8012218: 2b00 cmp r3, #0
801221a: d007 beq.n 801222c <tcp_free_ooseq+0x20>
tcp_segs_free(pcb->ooseq);
801221c: 687b ldr r3, [r7, #4]
801221e: 6f5b ldr r3, [r3, #116] ; 0x74
8012220: 4618 mov r0, r3
8012222: f7ff fc3d bl 8011aa0 <tcp_segs_free>
pcb->ooseq = NULL;
8012226: 687b ldr r3, [r7, #4]
8012228: 2200 movs r2, #0
801222a: 675a str r2, [r3, #116] ; 0x74
#if LWIP_TCP_SACK_OUT
memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks));
#endif /* LWIP_TCP_SACK_OUT */
}
}
801222c: bf00 nop
801222e: 3708 adds r7, #8
8012230: 46bd mov sp, r7
8012232: bd80 pop {r7, pc}
08012234 <tcp_input>:
* @param p received TCP segment to process (p->payload pointing to the TCP header)
* @param inp network interface on which this segment was received
*/
void
tcp_input(struct pbuf *p, struct netif *inp)
{
8012234: b590 push {r4, r7, lr}
8012236: b08d sub sp, #52 ; 0x34
8012238: af04 add r7, sp, #16
801223a: 6078 str r0, [r7, #4]
801223c: 6039 str r1, [r7, #0]
u8_t hdrlen_bytes;
err_t err;
LWIP_UNUSED_ARG(inp);
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("tcp_input: invalid pbuf", p != NULL);
801223e: 687b ldr r3, [r7, #4]
8012240: 2b00 cmp r3, #0
8012242: d105 bne.n 8012250 <tcp_input+0x1c>
8012244: 4b9b ldr r3, [pc, #620] ; (80124b4 <tcp_input+0x280>)
8012246: 2283 movs r2, #131 ; 0x83
8012248: 499b ldr r1, [pc, #620] ; (80124b8 <tcp_input+0x284>)
801224a: 489c ldr r0, [pc, #624] ; (80124bc <tcp_input+0x288>)
801224c: f008 feba bl 801afc4 <iprintf>
PERF_START;
TCP_STATS_INC(tcp.recv);
MIB2_STATS_INC(mib2.tcpinsegs);
tcphdr = (struct tcp_hdr *)p->payload;
8012250: 687b ldr r3, [r7, #4]
8012252: 685b ldr r3, [r3, #4]
8012254: 4a9a ldr r2, [pc, #616] ; (80124c0 <tcp_input+0x28c>)
8012256: 6013 str r3, [r2, #0]
#if TCP_INPUT_DEBUG
tcp_debug_print(tcphdr);
#endif
/* Check that TCP header fits in payload */
if (p->len < TCP_HLEN) {
8012258: 687b ldr r3, [r7, #4]
801225a: 895b ldrh r3, [r3, #10]
801225c: 2b13 cmp r3, #19
801225e: f240 83c4 bls.w 80129ea <tcp_input+0x7b6>
TCP_STATS_INC(tcp.lenerr);
goto dropped;
}
/* Don't even process incoming broadcasts/multicasts. */
if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
8012262: 4b98 ldr r3, [pc, #608] ; (80124c4 <tcp_input+0x290>)
8012264: 695b ldr r3, [r3, #20]
8012266: 4a97 ldr r2, [pc, #604] ; (80124c4 <tcp_input+0x290>)
8012268: 6812 ldr r2, [r2, #0]
801226a: 4611 mov r1, r2
801226c: 4618 mov r0, r3
801226e: f007 fdfb bl 8019e68 <ip4_addr_isbroadcast_u32>
8012272: 4603 mov r3, r0
8012274: 2b00 cmp r3, #0
8012276: f040 83ba bne.w 80129ee <tcp_input+0x7ba>
ip_addr_ismulticast(ip_current_dest_addr())) {
801227a: 4b92 ldr r3, [pc, #584] ; (80124c4 <tcp_input+0x290>)
801227c: 695b ldr r3, [r3, #20]
801227e: f003 03f0 and.w r3, r3, #240 ; 0xf0
if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
8012282: 2be0 cmp r3, #224 ; 0xe0
8012284: f000 83b3 beq.w 80129ee <tcp_input+0x7ba>
}
}
#endif /* CHECKSUM_CHECK_TCP */
/* sanity-check header length */
hdrlen_bytes = TCPH_HDRLEN_BYTES(tcphdr);
8012288: 4b8d ldr r3, [pc, #564] ; (80124c0 <tcp_input+0x28c>)
801228a: 681b ldr r3, [r3, #0]
801228c: 899b ldrh r3, [r3, #12]
801228e: b29b uxth r3, r3
8012290: 4618 mov r0, r3
8012292: f7fc fdd3 bl 800ee3c <lwip_htons>
8012296: 4603 mov r3, r0
8012298: 0b1b lsrs r3, r3, #12
801229a: b29b uxth r3, r3
801229c: b2db uxtb r3, r3
801229e: 009b lsls r3, r3, #2
80122a0: 74bb strb r3, [r7, #18]
if ((hdrlen_bytes < TCP_HLEN) || (hdrlen_bytes > p->tot_len)) {
80122a2: 7cbb ldrb r3, [r7, #18]
80122a4: 2b13 cmp r3, #19
80122a6: f240 83a4 bls.w 80129f2 <tcp_input+0x7be>
80122aa: 7cbb ldrb r3, [r7, #18]
80122ac: b29a uxth r2, r3
80122ae: 687b ldr r3, [r7, #4]
80122b0: 891b ldrh r3, [r3, #8]
80122b2: 429a cmp r2, r3
80122b4: f200 839d bhi.w 80129f2 <tcp_input+0x7be>
goto dropped;
}
/* Move the payload pointer in the pbuf so that it points to the
TCP data instead of the TCP header. */
tcphdr_optlen = (u16_t)(hdrlen_bytes - TCP_HLEN);
80122b8: 7cbb ldrb r3, [r7, #18]
80122ba: b29b uxth r3, r3
80122bc: 3b14 subs r3, #20
80122be: b29a uxth r2, r3
80122c0: 4b81 ldr r3, [pc, #516] ; (80124c8 <tcp_input+0x294>)
80122c2: 801a strh r2, [r3, #0]
tcphdr_opt2 = NULL;
80122c4: 4b81 ldr r3, [pc, #516] ; (80124cc <tcp_input+0x298>)
80122c6: 2200 movs r2, #0
80122c8: 601a str r2, [r3, #0]
if (p->len >= hdrlen_bytes) {
80122ca: 687b ldr r3, [r7, #4]
80122cc: 895a ldrh r2, [r3, #10]
80122ce: 7cbb ldrb r3, [r7, #18]
80122d0: b29b uxth r3, r3
80122d2: 429a cmp r2, r3
80122d4: d309 bcc.n 80122ea <tcp_input+0xb6>
/* all options are in the first pbuf */
tcphdr_opt1len = tcphdr_optlen;
80122d6: 4b7c ldr r3, [pc, #496] ; (80124c8 <tcp_input+0x294>)
80122d8: 881a ldrh r2, [r3, #0]
80122da: 4b7d ldr r3, [pc, #500] ; (80124d0 <tcp_input+0x29c>)
80122dc: 801a strh r2, [r3, #0]
pbuf_remove_header(p, hdrlen_bytes); /* cannot fail */
80122de: 7cbb ldrb r3, [r7, #18]
80122e0: 4619 mov r1, r3
80122e2: 6878 ldr r0, [r7, #4]
80122e4: f7fe f8dc bl 80104a0 <pbuf_remove_header>
80122e8: e04e b.n 8012388 <tcp_input+0x154>
} else {
u16_t opt2len;
/* TCP header fits into first pbuf, options don't - data is in the next pbuf */
/* there must be a next pbuf, due to hdrlen_bytes sanity check above */
LWIP_ASSERT("p->next != NULL", p->next != NULL);
80122ea: 687b ldr r3, [r7, #4]
80122ec: 681b ldr r3, [r3, #0]
80122ee: 2b00 cmp r3, #0
80122f0: d105 bne.n 80122fe <tcp_input+0xca>
80122f2: 4b70 ldr r3, [pc, #448] ; (80124b4 <tcp_input+0x280>)
80122f4: 22c2 movs r2, #194 ; 0xc2
80122f6: 4977 ldr r1, [pc, #476] ; (80124d4 <tcp_input+0x2a0>)
80122f8: 4870 ldr r0, [pc, #448] ; (80124bc <tcp_input+0x288>)
80122fa: f008 fe63 bl 801afc4 <iprintf>
/* advance over the TCP header (cannot fail) */
pbuf_remove_header(p, TCP_HLEN);
80122fe: 2114 movs r1, #20
8012300: 6878 ldr r0, [r7, #4]
8012302: f7fe f8cd bl 80104a0 <pbuf_remove_header>
/* determine how long the first and second parts of the options are */
tcphdr_opt1len = p->len;
8012306: 687b ldr r3, [r7, #4]
8012308: 895a ldrh r2, [r3, #10]
801230a: 4b71 ldr r3, [pc, #452] ; (80124d0 <tcp_input+0x29c>)
801230c: 801a strh r2, [r3, #0]
opt2len = (u16_t)(tcphdr_optlen - tcphdr_opt1len);
801230e: 4b6e ldr r3, [pc, #440] ; (80124c8 <tcp_input+0x294>)
8012310: 881a ldrh r2, [r3, #0]
8012312: 4b6f ldr r3, [pc, #444] ; (80124d0 <tcp_input+0x29c>)
8012314: 881b ldrh r3, [r3, #0]
8012316: 1ad3 subs r3, r2, r3
8012318: 823b strh r3, [r7, #16]
/* options continue in the next pbuf: set p to zero length and hide the
options in the next pbuf (adjusting p->tot_len) */
pbuf_remove_header(p, tcphdr_opt1len);
801231a: 4b6d ldr r3, [pc, #436] ; (80124d0 <tcp_input+0x29c>)
801231c: 881b ldrh r3, [r3, #0]
801231e: 4619 mov r1, r3
8012320: 6878 ldr r0, [r7, #4]
8012322: f7fe f8bd bl 80104a0 <pbuf_remove_header>
/* check that the options fit in the second pbuf */
if (opt2len > p->next->len) {
8012326: 687b ldr r3, [r7, #4]
8012328: 681b ldr r3, [r3, #0]
801232a: 895b ldrh r3, [r3, #10]
801232c: 8a3a ldrh r2, [r7, #16]
801232e: 429a cmp r2, r3
8012330: f200 8361 bhi.w 80129f6 <tcp_input+0x7c2>
TCP_STATS_INC(tcp.lenerr);
goto dropped;
}
/* remember the pointer to the second part of the options */
tcphdr_opt2 = (u8_t *)p->next->payload;
8012334: 687b ldr r3, [r7, #4]
8012336: 681b ldr r3, [r3, #0]
8012338: 685b ldr r3, [r3, #4]
801233a: 4a64 ldr r2, [pc, #400] ; (80124cc <tcp_input+0x298>)
801233c: 6013 str r3, [r2, #0]
/* advance p->next to point after the options, and manually
adjust p->tot_len to keep it consistent with the changed p->next */
pbuf_remove_header(p->next, opt2len);
801233e: 687b ldr r3, [r7, #4]
8012340: 681b ldr r3, [r3, #0]
8012342: 8a3a ldrh r2, [r7, #16]
8012344: 4611 mov r1, r2
8012346: 4618 mov r0, r3
8012348: f7fe f8aa bl 80104a0 <pbuf_remove_header>
p->tot_len = (u16_t)(p->tot_len - opt2len);
801234c: 687b ldr r3, [r7, #4]
801234e: 891a ldrh r2, [r3, #8]
8012350: 8a3b ldrh r3, [r7, #16]
8012352: 1ad3 subs r3, r2, r3
8012354: b29a uxth r2, r3
8012356: 687b ldr r3, [r7, #4]
8012358: 811a strh r2, [r3, #8]
LWIP_ASSERT("p->len == 0", p->len == 0);
801235a: 687b ldr r3, [r7, #4]
801235c: 895b ldrh r3, [r3, #10]
801235e: 2b00 cmp r3, #0
8012360: d005 beq.n 801236e <tcp_input+0x13a>
8012362: 4b54 ldr r3, [pc, #336] ; (80124b4 <tcp_input+0x280>)
8012364: 22df movs r2, #223 ; 0xdf
8012366: 495c ldr r1, [pc, #368] ; (80124d8 <tcp_input+0x2a4>)
8012368: 4854 ldr r0, [pc, #336] ; (80124bc <tcp_input+0x288>)
801236a: f008 fe2b bl 801afc4 <iprintf>
LWIP_ASSERT("p->tot_len == p->next->tot_len", p->tot_len == p->next->tot_len);
801236e: 687b ldr r3, [r7, #4]
8012370: 891a ldrh r2, [r3, #8]
8012372: 687b ldr r3, [r7, #4]
8012374: 681b ldr r3, [r3, #0]
8012376: 891b ldrh r3, [r3, #8]
8012378: 429a cmp r2, r3
801237a: d005 beq.n 8012388 <tcp_input+0x154>
801237c: 4b4d ldr r3, [pc, #308] ; (80124b4 <tcp_input+0x280>)
801237e: 22e0 movs r2, #224 ; 0xe0
8012380: 4956 ldr r1, [pc, #344] ; (80124dc <tcp_input+0x2a8>)
8012382: 484e ldr r0, [pc, #312] ; (80124bc <tcp_input+0x288>)
8012384: f008 fe1e bl 801afc4 <iprintf>
}
/* Convert fields in TCP header to host byte order. */
tcphdr->src = lwip_ntohs(tcphdr->src);
8012388: 4b4d ldr r3, [pc, #308] ; (80124c0 <tcp_input+0x28c>)
801238a: 681b ldr r3, [r3, #0]
801238c: 881b ldrh r3, [r3, #0]
801238e: b29b uxth r3, r3
8012390: 4a4b ldr r2, [pc, #300] ; (80124c0 <tcp_input+0x28c>)
8012392: 6814 ldr r4, [r2, #0]
8012394: 4618 mov r0, r3
8012396: f7fc fd51 bl 800ee3c <lwip_htons>
801239a: 4603 mov r3, r0
801239c: 8023 strh r3, [r4, #0]
tcphdr->dest = lwip_ntohs(tcphdr->dest);
801239e: 4b48 ldr r3, [pc, #288] ; (80124c0 <tcp_input+0x28c>)
80123a0: 681b ldr r3, [r3, #0]
80123a2: 885b ldrh r3, [r3, #2]
80123a4: b29b uxth r3, r3
80123a6: 4a46 ldr r2, [pc, #280] ; (80124c0 <tcp_input+0x28c>)
80123a8: 6814 ldr r4, [r2, #0]
80123aa: 4618 mov r0, r3
80123ac: f7fc fd46 bl 800ee3c <lwip_htons>
80123b0: 4603 mov r3, r0
80123b2: 8063 strh r3, [r4, #2]
seqno = tcphdr->seqno = lwip_ntohl(tcphdr->seqno);
80123b4: 4b42 ldr r3, [pc, #264] ; (80124c0 <tcp_input+0x28c>)
80123b6: 681b ldr r3, [r3, #0]
80123b8: 685b ldr r3, [r3, #4]
80123ba: 4a41 ldr r2, [pc, #260] ; (80124c0 <tcp_input+0x28c>)
80123bc: 6814 ldr r4, [r2, #0]
80123be: 4618 mov r0, r3
80123c0: f7fc fd51 bl 800ee66 <lwip_htonl>
80123c4: 4603 mov r3, r0
80123c6: 6063 str r3, [r4, #4]
80123c8: 6863 ldr r3, [r4, #4]
80123ca: 4a45 ldr r2, [pc, #276] ; (80124e0 <tcp_input+0x2ac>)
80123cc: 6013 str r3, [r2, #0]
ackno = tcphdr->ackno = lwip_ntohl(tcphdr->ackno);
80123ce: 4b3c ldr r3, [pc, #240] ; (80124c0 <tcp_input+0x28c>)
80123d0: 681b ldr r3, [r3, #0]
80123d2: 689b ldr r3, [r3, #8]
80123d4: 4a3a ldr r2, [pc, #232] ; (80124c0 <tcp_input+0x28c>)
80123d6: 6814 ldr r4, [r2, #0]
80123d8: 4618 mov r0, r3
80123da: f7fc fd44 bl 800ee66 <lwip_htonl>
80123de: 4603 mov r3, r0
80123e0: 60a3 str r3, [r4, #8]
80123e2: 68a3 ldr r3, [r4, #8]
80123e4: 4a3f ldr r2, [pc, #252] ; (80124e4 <tcp_input+0x2b0>)
80123e6: 6013 str r3, [r2, #0]
tcphdr->wnd = lwip_ntohs(tcphdr->wnd);
80123e8: 4b35 ldr r3, [pc, #212] ; (80124c0 <tcp_input+0x28c>)
80123ea: 681b ldr r3, [r3, #0]
80123ec: 89db ldrh r3, [r3, #14]
80123ee: b29b uxth r3, r3
80123f0: 4a33 ldr r2, [pc, #204] ; (80124c0 <tcp_input+0x28c>)
80123f2: 6814 ldr r4, [r2, #0]
80123f4: 4618 mov r0, r3
80123f6: f7fc fd21 bl 800ee3c <lwip_htons>
80123fa: 4603 mov r3, r0
80123fc: 81e3 strh r3, [r4, #14]
flags = TCPH_FLAGS(tcphdr);
80123fe: 4b30 ldr r3, [pc, #192] ; (80124c0 <tcp_input+0x28c>)
8012400: 681b ldr r3, [r3, #0]
8012402: 899b ldrh r3, [r3, #12]
8012404: b29b uxth r3, r3
8012406: 4618 mov r0, r3
8012408: f7fc fd18 bl 800ee3c <lwip_htons>
801240c: 4603 mov r3, r0
801240e: b2db uxtb r3, r3
8012410: f003 033f and.w r3, r3, #63 ; 0x3f
8012414: b2da uxtb r2, r3
8012416: 4b34 ldr r3, [pc, #208] ; (80124e8 <tcp_input+0x2b4>)
8012418: 701a strb r2, [r3, #0]
tcplen = p->tot_len;
801241a: 687b ldr r3, [r7, #4]
801241c: 891a ldrh r2, [r3, #8]
801241e: 4b33 ldr r3, [pc, #204] ; (80124ec <tcp_input+0x2b8>)
8012420: 801a strh r2, [r3, #0]
if (flags & (TCP_FIN | TCP_SYN)) {
8012422: 4b31 ldr r3, [pc, #196] ; (80124e8 <tcp_input+0x2b4>)
8012424: 781b ldrb r3, [r3, #0]
8012426: f003 0303 and.w r3, r3, #3
801242a: 2b00 cmp r3, #0
801242c: d00c beq.n 8012448 <tcp_input+0x214>
tcplen++;
801242e: 4b2f ldr r3, [pc, #188] ; (80124ec <tcp_input+0x2b8>)
8012430: 881b ldrh r3, [r3, #0]
8012432: 3301 adds r3, #1
8012434: b29a uxth r2, r3
8012436: 4b2d ldr r3, [pc, #180] ; (80124ec <tcp_input+0x2b8>)
8012438: 801a strh r2, [r3, #0]
if (tcplen < p->tot_len) {
801243a: 687b ldr r3, [r7, #4]
801243c: 891a ldrh r2, [r3, #8]
801243e: 4b2b ldr r3, [pc, #172] ; (80124ec <tcp_input+0x2b8>)
8012440: 881b ldrh r3, [r3, #0]
8012442: 429a cmp r2, r3
8012444: f200 82d9 bhi.w 80129fa <tcp_input+0x7c6>
}
}
/* Demultiplex an incoming segment. First, we check if it is destined
for an active connection. */
prev = NULL;
8012448: 2300 movs r3, #0
801244a: 61bb str r3, [r7, #24]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
801244c: 4b28 ldr r3, [pc, #160] ; (80124f0 <tcp_input+0x2bc>)
801244e: 681b ldr r3, [r3, #0]
8012450: 61fb str r3, [r7, #28]
8012452: e09d b.n 8012590 <tcp_input+0x35c>
LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
8012454: 69fb ldr r3, [r7, #28]
8012456: 7d1b ldrb r3, [r3, #20]
8012458: 2b00 cmp r3, #0
801245a: d105 bne.n 8012468 <tcp_input+0x234>
801245c: 4b15 ldr r3, [pc, #84] ; (80124b4 <tcp_input+0x280>)
801245e: 22fb movs r2, #251 ; 0xfb
8012460: 4924 ldr r1, [pc, #144] ; (80124f4 <tcp_input+0x2c0>)
8012462: 4816 ldr r0, [pc, #88] ; (80124bc <tcp_input+0x288>)
8012464: f008 fdae bl 801afc4 <iprintf>
LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
8012468: 69fb ldr r3, [r7, #28]
801246a: 7d1b ldrb r3, [r3, #20]
801246c: 2b0a cmp r3, #10
801246e: d105 bne.n 801247c <tcp_input+0x248>
8012470: 4b10 ldr r3, [pc, #64] ; (80124b4 <tcp_input+0x280>)
8012472: 22fc movs r2, #252 ; 0xfc
8012474: 4920 ldr r1, [pc, #128] ; (80124f8 <tcp_input+0x2c4>)
8012476: 4811 ldr r0, [pc, #68] ; (80124bc <tcp_input+0x288>)
8012478: f008 fda4 bl 801afc4 <iprintf>
LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
801247c: 69fb ldr r3, [r7, #28]
801247e: 7d1b ldrb r3, [r3, #20]
8012480: 2b01 cmp r3, #1
8012482: d105 bne.n 8012490 <tcp_input+0x25c>
8012484: 4b0b ldr r3, [pc, #44] ; (80124b4 <tcp_input+0x280>)
8012486: 22fd movs r2, #253 ; 0xfd
8012488: 491c ldr r1, [pc, #112] ; (80124fc <tcp_input+0x2c8>)
801248a: 480c ldr r0, [pc, #48] ; (80124bc <tcp_input+0x288>)
801248c: f008 fd9a bl 801afc4 <iprintf>
/* check if PCB is bound to specific netif */
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
8012490: 69fb ldr r3, [r7, #28]
8012492: 7a1b ldrb r3, [r3, #8]
8012494: 2b00 cmp r3, #0
8012496: d033 beq.n 8012500 <tcp_input+0x2cc>
(pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
8012498: 69fb ldr r3, [r7, #28]
801249a: 7a1a ldrb r2, [r3, #8]
801249c: 4b09 ldr r3, [pc, #36] ; (80124c4 <tcp_input+0x290>)
801249e: 685b ldr r3, [r3, #4]
80124a0: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
80124a4: 3301 adds r3, #1
80124a6: b2db uxtb r3, r3
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80124a8: 429a cmp r2, r3
80124aa: d029 beq.n 8012500 <tcp_input+0x2cc>
prev = pcb;
80124ac: 69fb ldr r3, [r7, #28]
80124ae: 61bb str r3, [r7, #24]
continue;
80124b0: e06b b.n 801258a <tcp_input+0x356>
80124b2: bf00 nop
80124b4: 0801d484 .word 0x0801d484
80124b8: 0801d4b8 .word 0x0801d4b8
80124bc: 0801d4d0 .word 0x0801d4d0
80124c0: 20008730 .word 0x20008730
80124c4: 2000c108 .word 0x2000c108
80124c8: 20008734 .word 0x20008734
80124cc: 20008738 .word 0x20008738
80124d0: 20008736 .word 0x20008736
80124d4: 0801d4f8 .word 0x0801d4f8
80124d8: 0801d508 .word 0x0801d508
80124dc: 0801d514 .word 0x0801d514
80124e0: 20008740 .word 0x20008740
80124e4: 20008744 .word 0x20008744
80124e8: 2000874c .word 0x2000874c
80124ec: 2000874a .word 0x2000874a
80124f0: 2000f83c .word 0x2000f83c
80124f4: 0801d534 .word 0x0801d534
80124f8: 0801d55c .word 0x0801d55c
80124fc: 0801d588 .word 0x0801d588
}
if (pcb->remote_port == tcphdr->src &&
8012500: 69fb ldr r3, [r7, #28]
8012502: 8b1a ldrh r2, [r3, #24]
8012504: 4b94 ldr r3, [pc, #592] ; (8012758 <tcp_input+0x524>)
8012506: 681b ldr r3, [r3, #0]
8012508: 881b ldrh r3, [r3, #0]
801250a: b29b uxth r3, r3
801250c: 429a cmp r2, r3
801250e: d13a bne.n 8012586 <tcp_input+0x352>
pcb->local_port == tcphdr->dest &&
8012510: 69fb ldr r3, [r7, #28]
8012512: 8ada ldrh r2, [r3, #22]
8012514: 4b90 ldr r3, [pc, #576] ; (8012758 <tcp_input+0x524>)
8012516: 681b ldr r3, [r3, #0]
8012518: 885b ldrh r3, [r3, #2]
801251a: b29b uxth r3, r3
if (pcb->remote_port == tcphdr->src &&
801251c: 429a cmp r2, r3
801251e: d132 bne.n 8012586 <tcp_input+0x352>
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
8012520: 69fb ldr r3, [r7, #28]
8012522: 685a ldr r2, [r3, #4]
8012524: 4b8d ldr r3, [pc, #564] ; (801275c <tcp_input+0x528>)
8012526: 691b ldr r3, [r3, #16]
pcb->local_port == tcphdr->dest &&
8012528: 429a cmp r2, r3
801252a: d12c bne.n 8012586 <tcp_input+0x352>
ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
801252c: 69fb ldr r3, [r7, #28]
801252e: 681a ldr r2, [r3, #0]
8012530: 4b8a ldr r3, [pc, #552] ; (801275c <tcp_input+0x528>)
8012532: 695b ldr r3, [r3, #20]
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
8012534: 429a cmp r2, r3
8012536: d126 bne.n 8012586 <tcp_input+0x352>
/* Move this PCB to the front of the list so that subsequent
lookups will be faster (we exploit locality in TCP segment
arrivals). */
LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
8012538: 69fb ldr r3, [r7, #28]
801253a: 68db ldr r3, [r3, #12]
801253c: 69fa ldr r2, [r7, #28]
801253e: 429a cmp r2, r3
8012540: d106 bne.n 8012550 <tcp_input+0x31c>
8012542: 4b87 ldr r3, [pc, #540] ; (8012760 <tcp_input+0x52c>)
8012544: f240 120d movw r2, #269 ; 0x10d
8012548: 4986 ldr r1, [pc, #536] ; (8012764 <tcp_input+0x530>)
801254a: 4887 ldr r0, [pc, #540] ; (8012768 <tcp_input+0x534>)
801254c: f008 fd3a bl 801afc4 <iprintf>
if (prev != NULL) {
8012550: 69bb ldr r3, [r7, #24]
8012552: 2b00 cmp r3, #0
8012554: d00a beq.n 801256c <tcp_input+0x338>
prev->next = pcb->next;
8012556: 69fb ldr r3, [r7, #28]
8012558: 68da ldr r2, [r3, #12]
801255a: 69bb ldr r3, [r7, #24]
801255c: 60da str r2, [r3, #12]
pcb->next = tcp_active_pcbs;
801255e: 4b83 ldr r3, [pc, #524] ; (801276c <tcp_input+0x538>)
8012560: 681a ldr r2, [r3, #0]
8012562: 69fb ldr r3, [r7, #28]
8012564: 60da str r2, [r3, #12]
tcp_active_pcbs = pcb;
8012566: 4a81 ldr r2, [pc, #516] ; (801276c <tcp_input+0x538>)
8012568: 69fb ldr r3, [r7, #28]
801256a: 6013 str r3, [r2, #0]
} else {
TCP_STATS_INC(tcp.cachehit);
}
LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
801256c: 69fb ldr r3, [r7, #28]
801256e: 68db ldr r3, [r3, #12]
8012570: 69fa ldr r2, [r7, #28]
8012572: 429a cmp r2, r3
8012574: d111 bne.n 801259a <tcp_input+0x366>
8012576: 4b7a ldr r3, [pc, #488] ; (8012760 <tcp_input+0x52c>)
8012578: f240 1215 movw r2, #277 ; 0x115
801257c: 497c ldr r1, [pc, #496] ; (8012770 <tcp_input+0x53c>)
801257e: 487a ldr r0, [pc, #488] ; (8012768 <tcp_input+0x534>)
8012580: f008 fd20 bl 801afc4 <iprintf>
break;
8012584: e009 b.n 801259a <tcp_input+0x366>
}
prev = pcb;
8012586: 69fb ldr r3, [r7, #28]
8012588: 61bb str r3, [r7, #24]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
801258a: 69fb ldr r3, [r7, #28]
801258c: 68db ldr r3, [r3, #12]
801258e: 61fb str r3, [r7, #28]
8012590: 69fb ldr r3, [r7, #28]
8012592: 2b00 cmp r3, #0
8012594: f47f af5e bne.w 8012454 <tcp_input+0x220>
8012598: e000 b.n 801259c <tcp_input+0x368>
break;
801259a: bf00 nop
}
if (pcb == NULL) {
801259c: 69fb ldr r3, [r7, #28]
801259e: 2b00 cmp r3, #0
80125a0: f040 8095 bne.w 80126ce <tcp_input+0x49a>
/* If it did not go to an active connection, we check the connections
in the TIME-WAIT state. */
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
80125a4: 4b73 ldr r3, [pc, #460] ; (8012774 <tcp_input+0x540>)
80125a6: 681b ldr r3, [r3, #0]
80125a8: 61fb str r3, [r7, #28]
80125aa: e03f b.n 801262c <tcp_input+0x3f8>
LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
80125ac: 69fb ldr r3, [r7, #28]
80125ae: 7d1b ldrb r3, [r3, #20]
80125b0: 2b0a cmp r3, #10
80125b2: d006 beq.n 80125c2 <tcp_input+0x38e>
80125b4: 4b6a ldr r3, [pc, #424] ; (8012760 <tcp_input+0x52c>)
80125b6: f240 121f movw r2, #287 ; 0x11f
80125ba: 496f ldr r1, [pc, #444] ; (8012778 <tcp_input+0x544>)
80125bc: 486a ldr r0, [pc, #424] ; (8012768 <tcp_input+0x534>)
80125be: f008 fd01 bl 801afc4 <iprintf>
/* check if PCB is bound to specific netif */
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80125c2: 69fb ldr r3, [r7, #28]
80125c4: 7a1b ldrb r3, [r3, #8]
80125c6: 2b00 cmp r3, #0
80125c8: d009 beq.n 80125de <tcp_input+0x3aa>
(pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
80125ca: 69fb ldr r3, [r7, #28]
80125cc: 7a1a ldrb r2, [r3, #8]
80125ce: 4b63 ldr r3, [pc, #396] ; (801275c <tcp_input+0x528>)
80125d0: 685b ldr r3, [r3, #4]
80125d2: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
80125d6: 3301 adds r3, #1
80125d8: b2db uxtb r3, r3
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80125da: 429a cmp r2, r3
80125dc: d122 bne.n 8012624 <tcp_input+0x3f0>
continue;
}
if (pcb->remote_port == tcphdr->src &&
80125de: 69fb ldr r3, [r7, #28]
80125e0: 8b1a ldrh r2, [r3, #24]
80125e2: 4b5d ldr r3, [pc, #372] ; (8012758 <tcp_input+0x524>)
80125e4: 681b ldr r3, [r3, #0]
80125e6: 881b ldrh r3, [r3, #0]
80125e8: b29b uxth r3, r3
80125ea: 429a cmp r2, r3
80125ec: d11b bne.n 8012626 <tcp_input+0x3f2>
pcb->local_port == tcphdr->dest &&
80125ee: 69fb ldr r3, [r7, #28]
80125f0: 8ada ldrh r2, [r3, #22]
80125f2: 4b59 ldr r3, [pc, #356] ; (8012758 <tcp_input+0x524>)
80125f4: 681b ldr r3, [r3, #0]
80125f6: 885b ldrh r3, [r3, #2]
80125f8: b29b uxth r3, r3
if (pcb->remote_port == tcphdr->src &&
80125fa: 429a cmp r2, r3
80125fc: d113 bne.n 8012626 <tcp_input+0x3f2>
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
80125fe: 69fb ldr r3, [r7, #28]
8012600: 685a ldr r2, [r3, #4]
8012602: 4b56 ldr r3, [pc, #344] ; (801275c <tcp_input+0x528>)
8012604: 691b ldr r3, [r3, #16]
pcb->local_port == tcphdr->dest &&
8012606: 429a cmp r2, r3
8012608: d10d bne.n 8012626 <tcp_input+0x3f2>
ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
801260a: 69fb ldr r3, [r7, #28]
801260c: 681a ldr r2, [r3, #0]
801260e: 4b53 ldr r3, [pc, #332] ; (801275c <tcp_input+0x528>)
8012610: 695b ldr r3, [r3, #20]
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
8012612: 429a cmp r2, r3
8012614: d107 bne.n 8012626 <tcp_input+0x3f2>
#ifdef LWIP_HOOK_TCP_INPACKET_PCB
if (LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen, tcphdr_opt1len,
tcphdr_opt2, p) == ERR_OK)
#endif
{
tcp_timewait_input(pcb);
8012616: 69f8 ldr r0, [r7, #28]
8012618: f000 fb54 bl 8012cc4 <tcp_timewait_input>
}
pbuf_free(p);
801261c: 6878 ldr r0, [r7, #4]
801261e: f7fd ffc5 bl 80105ac <pbuf_free>
return;
8012622: e1f0 b.n 8012a06 <tcp_input+0x7d2>
continue;
8012624: bf00 nop
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
8012626: 69fb ldr r3, [r7, #28]
8012628: 68db ldr r3, [r3, #12]
801262a: 61fb str r3, [r7, #28]
801262c: 69fb ldr r3, [r7, #28]
801262e: 2b00 cmp r3, #0
8012630: d1bc bne.n 80125ac <tcp_input+0x378>
}
}
/* Finally, if we still did not get a match, we check all PCBs that
are LISTENing for incoming connections. */
prev = NULL;
8012632: 2300 movs r3, #0
8012634: 61bb str r3, [r7, #24]
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
8012636: 4b51 ldr r3, [pc, #324] ; (801277c <tcp_input+0x548>)
8012638: 681b ldr r3, [r3, #0]
801263a: 617b str r3, [r7, #20]
801263c: e02a b.n 8012694 <tcp_input+0x460>
/* check if PCB is bound to specific netif */
if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
801263e: 697b ldr r3, [r7, #20]
8012640: 7a1b ldrb r3, [r3, #8]
8012642: 2b00 cmp r3, #0
8012644: d00c beq.n 8012660 <tcp_input+0x42c>
(lpcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
8012646: 697b ldr r3, [r7, #20]
8012648: 7a1a ldrb r2, [r3, #8]
801264a: 4b44 ldr r3, [pc, #272] ; (801275c <tcp_input+0x528>)
801264c: 685b ldr r3, [r3, #4]
801264e: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
8012652: 3301 adds r3, #1
8012654: b2db uxtb r3, r3
if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
8012656: 429a cmp r2, r3
8012658: d002 beq.n 8012660 <tcp_input+0x42c>
prev = (struct tcp_pcb *)lpcb;
801265a: 697b ldr r3, [r7, #20]
801265c: 61bb str r3, [r7, #24]
continue;
801265e: e016 b.n 801268e <tcp_input+0x45a>
}
if (lpcb->local_port == tcphdr->dest) {
8012660: 697b ldr r3, [r7, #20]
8012662: 8ada ldrh r2, [r3, #22]
8012664: 4b3c ldr r3, [pc, #240] ; (8012758 <tcp_input+0x524>)
8012666: 681b ldr r3, [r3, #0]
8012668: 885b ldrh r3, [r3, #2]
801266a: b29b uxth r3, r3
801266c: 429a cmp r2, r3
801266e: d10c bne.n 801268a <tcp_input+0x456>
lpcb_prev = prev;
#else /* SO_REUSE */
break;
#endif /* SO_REUSE */
} else if (IP_ADDR_PCB_VERSION_MATCH_EXACT(lpcb, ip_current_dest_addr())) {
if (ip_addr_cmp(&lpcb->local_ip, ip_current_dest_addr())) {
8012670: 697b ldr r3, [r7, #20]
8012672: 681a ldr r2, [r3, #0]
8012674: 4b39 ldr r3, [pc, #228] ; (801275c <tcp_input+0x528>)
8012676: 695b ldr r3, [r3, #20]
8012678: 429a cmp r2, r3
801267a: d00f beq.n 801269c <tcp_input+0x468>
/* found an exact match */
break;
} else if (ip_addr_isany(&lpcb->local_ip)) {
801267c: 697b ldr r3, [r7, #20]
801267e: 2b00 cmp r3, #0
8012680: d00d beq.n 801269e <tcp_input+0x46a>
8012682: 697b ldr r3, [r7, #20]
8012684: 681b ldr r3, [r3, #0]
8012686: 2b00 cmp r3, #0
8012688: d009 beq.n 801269e <tcp_input+0x46a>
break;
#endif /* SO_REUSE */
}
}
}
prev = (struct tcp_pcb *)lpcb;
801268a: 697b ldr r3, [r7, #20]
801268c: 61bb str r3, [r7, #24]
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
801268e: 697b ldr r3, [r7, #20]
8012690: 68db ldr r3, [r3, #12]
8012692: 617b str r3, [r7, #20]
8012694: 697b ldr r3, [r7, #20]
8012696: 2b00 cmp r3, #0
8012698: d1d1 bne.n 801263e <tcp_input+0x40a>
801269a: e000 b.n 801269e <tcp_input+0x46a>
break;
801269c: bf00 nop
/* only pass to ANY if no specific local IP has been found */
lpcb = lpcb_any;
prev = lpcb_prev;
}
#endif /* SO_REUSE */
if (lpcb != NULL) {
801269e: 697b ldr r3, [r7, #20]
80126a0: 2b00 cmp r3, #0
80126a2: d014 beq.n 80126ce <tcp_input+0x49a>
/* Move this PCB to the front of the list so that subsequent
lookups will be faster (we exploit locality in TCP segment
arrivals). */
if (prev != NULL) {
80126a4: 69bb ldr r3, [r7, #24]
80126a6: 2b00 cmp r3, #0
80126a8: d00a beq.n 80126c0 <tcp_input+0x48c>
((struct tcp_pcb_listen *)prev)->next = lpcb->next;
80126aa: 697b ldr r3, [r7, #20]
80126ac: 68da ldr r2, [r3, #12]
80126ae: 69bb ldr r3, [r7, #24]
80126b0: 60da str r2, [r3, #12]
/* our successor is the remainder of the listening list */
lpcb->next = tcp_listen_pcbs.listen_pcbs;
80126b2: 4b32 ldr r3, [pc, #200] ; (801277c <tcp_input+0x548>)
80126b4: 681a ldr r2, [r3, #0]
80126b6: 697b ldr r3, [r7, #20]
80126b8: 60da str r2, [r3, #12]
/* put this listening pcb at the head of the listening list */
tcp_listen_pcbs.listen_pcbs = lpcb;
80126ba: 4a30 ldr r2, [pc, #192] ; (801277c <tcp_input+0x548>)
80126bc: 697b ldr r3, [r7, #20]
80126be: 6013 str r3, [r2, #0]
#ifdef LWIP_HOOK_TCP_INPACKET_PCB
if (LWIP_HOOK_TCP_INPACKET_PCB((struct tcp_pcb *)lpcb, tcphdr, tcphdr_optlen,
tcphdr_opt1len, tcphdr_opt2, p) == ERR_OK)
#endif
{
tcp_listen_input(lpcb);
80126c0: 6978 ldr r0, [r7, #20]
80126c2: f000 fa01 bl 8012ac8 <tcp_listen_input>
}
pbuf_free(p);
80126c6: 6878 ldr r0, [r7, #4]
80126c8: f7fd ff70 bl 80105ac <pbuf_free>
return;
80126cc: e19b b.n 8012a06 <tcp_input+0x7d2>
tcphdr_opt1len, tcphdr_opt2, p) != ERR_OK) {
pbuf_free(p);
return;
}
#endif
if (pcb != NULL) {
80126ce: 69fb ldr r3, [r7, #28]
80126d0: 2b00 cmp r3, #0
80126d2: f000 8160 beq.w 8012996 <tcp_input+0x762>
#if TCP_INPUT_DEBUG
tcp_debug_print_state(pcb->state);
#endif /* TCP_INPUT_DEBUG */
/* Set up a tcp_seg structure. */
inseg.next = NULL;
80126d6: 4b2a ldr r3, [pc, #168] ; (8012780 <tcp_input+0x54c>)
80126d8: 2200 movs r2, #0
80126da: 601a str r2, [r3, #0]
inseg.len = p->tot_len;
80126dc: 687b ldr r3, [r7, #4]
80126de: 891a ldrh r2, [r3, #8]
80126e0: 4b27 ldr r3, [pc, #156] ; (8012780 <tcp_input+0x54c>)
80126e2: 811a strh r2, [r3, #8]
inseg.p = p;
80126e4: 4a26 ldr r2, [pc, #152] ; (8012780 <tcp_input+0x54c>)
80126e6: 687b ldr r3, [r7, #4]
80126e8: 6053 str r3, [r2, #4]
inseg.tcphdr = tcphdr;
80126ea: 4b1b ldr r3, [pc, #108] ; (8012758 <tcp_input+0x524>)
80126ec: 681b ldr r3, [r3, #0]
80126ee: 4a24 ldr r2, [pc, #144] ; (8012780 <tcp_input+0x54c>)
80126f0: 60d3 str r3, [r2, #12]
recv_data = NULL;
80126f2: 4b24 ldr r3, [pc, #144] ; (8012784 <tcp_input+0x550>)
80126f4: 2200 movs r2, #0
80126f6: 601a str r2, [r3, #0]
recv_flags = 0;
80126f8: 4b23 ldr r3, [pc, #140] ; (8012788 <tcp_input+0x554>)
80126fa: 2200 movs r2, #0
80126fc: 701a strb r2, [r3, #0]
recv_acked = 0;
80126fe: 4b23 ldr r3, [pc, #140] ; (801278c <tcp_input+0x558>)
8012700: 2200 movs r2, #0
8012702: 801a strh r2, [r3, #0]
if (flags & TCP_PSH) {
8012704: 4b22 ldr r3, [pc, #136] ; (8012790 <tcp_input+0x55c>)
8012706: 781b ldrb r3, [r3, #0]
8012708: f003 0308 and.w r3, r3, #8
801270c: 2b00 cmp r3, #0
801270e: d006 beq.n 801271e <tcp_input+0x4ea>
p->flags |= PBUF_FLAG_PUSH;
8012710: 687b ldr r3, [r7, #4]
8012712: 7b5b ldrb r3, [r3, #13]
8012714: f043 0301 orr.w r3, r3, #1
8012718: b2da uxtb r2, r3
801271a: 687b ldr r3, [r7, #4]
801271c: 735a strb r2, [r3, #13]
}
/* If there is data which was previously "refused" by upper layer */
if (pcb->refused_data != NULL) {
801271e: 69fb ldr r3, [r7, #28]
8012720: 6f9b ldr r3, [r3, #120] ; 0x78
8012722: 2b00 cmp r3, #0
8012724: d038 beq.n 8012798 <tcp_input+0x564>
if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
8012726: 69f8 ldr r0, [r7, #28]
8012728: f7ff f93e bl 80119a8 <tcp_process_refused_data>
801272c: 4603 mov r3, r0
801272e: f113 0f0d cmn.w r3, #13
8012732: d007 beq.n 8012744 <tcp_input+0x510>
((pcb->refused_data != NULL) && (tcplen > 0))) {
8012734: 69fb ldr r3, [r7, #28]
8012736: 6f9b ldr r3, [r3, #120] ; 0x78
if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
8012738: 2b00 cmp r3, #0
801273a: d02d beq.n 8012798 <tcp_input+0x564>
((pcb->refused_data != NULL) && (tcplen > 0))) {
801273c: 4b15 ldr r3, [pc, #84] ; (8012794 <tcp_input+0x560>)
801273e: 881b ldrh r3, [r3, #0]
8012740: 2b00 cmp r3, #0
8012742: d029 beq.n 8012798 <tcp_input+0x564>
/* pcb has been aborted or refused data is still refused and the new
segment contains data */
if (pcb->rcv_ann_wnd == 0) {
8012744: 69fb ldr r3, [r7, #28]
8012746: 8d5b ldrh r3, [r3, #42] ; 0x2a
8012748: 2b00 cmp r3, #0
801274a: f040 8104 bne.w 8012956 <tcp_input+0x722>
/* this is a zero-window probe, we respond to it with current RCV.NXT
and drop the data segment */
tcp_send_empty_ack(pcb);
801274e: 69f8 ldr r0, [r7, #28]
8012750: f003 f9be bl 8015ad0 <tcp_send_empty_ack>
}
TCP_STATS_INC(tcp.drop);
MIB2_STATS_INC(mib2.tcpinerrs);
goto aborted;
8012754: e0ff b.n 8012956 <tcp_input+0x722>
8012756: bf00 nop
8012758: 20008730 .word 0x20008730
801275c: 2000c108 .word 0x2000c108
8012760: 0801d484 .word 0x0801d484
8012764: 0801d5b0 .word 0x0801d5b0
8012768: 0801d4d0 .word 0x0801d4d0
801276c: 2000f83c .word 0x2000f83c
8012770: 0801d5dc .word 0x0801d5dc
8012774: 2000f84c .word 0x2000f84c
8012778: 0801d608 .word 0x0801d608
801277c: 2000f844 .word 0x2000f844
8012780: 20008720 .word 0x20008720
8012784: 20008750 .word 0x20008750
8012788: 2000874d .word 0x2000874d
801278c: 20008748 .word 0x20008748
8012790: 2000874c .word 0x2000874c
8012794: 2000874a .word 0x2000874a
}
}
tcp_input_pcb = pcb;
8012798: 4a9c ldr r2, [pc, #624] ; (8012a0c <tcp_input+0x7d8>)
801279a: 69fb ldr r3, [r7, #28]
801279c: 6013 str r3, [r2, #0]
err = tcp_process(pcb);
801279e: 69f8 ldr r0, [r7, #28]
80127a0: f000 fb0a bl 8012db8 <tcp_process>
80127a4: 4603 mov r3, r0
80127a6: 74fb strb r3, [r7, #19]
/* A return value of ERR_ABRT means that tcp_abort() was called
and that the pcb has been freed. If so, we don't do anything. */
if (err != ERR_ABRT) {
80127a8: f997 3013 ldrsb.w r3, [r7, #19]
80127ac: f113 0f0d cmn.w r3, #13
80127b0: f000 80d3 beq.w 801295a <tcp_input+0x726>
if (recv_flags & TF_RESET) {
80127b4: 4b96 ldr r3, [pc, #600] ; (8012a10 <tcp_input+0x7dc>)
80127b6: 781b ldrb r3, [r3, #0]
80127b8: f003 0308 and.w r3, r3, #8
80127bc: 2b00 cmp r3, #0
80127be: d015 beq.n 80127ec <tcp_input+0x5b8>
/* TF_RESET means that the connection was reset by the other
end. We then call the error callback to inform the
application that the connection is dead before we
deallocate the PCB. */
TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_RST);
80127c0: 69fb ldr r3, [r7, #28]
80127c2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80127c6: 2b00 cmp r3, #0
80127c8: d008 beq.n 80127dc <tcp_input+0x5a8>
80127ca: 69fb ldr r3, [r7, #28]
80127cc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80127d0: 69fa ldr r2, [r7, #28]
80127d2: 6912 ldr r2, [r2, #16]
80127d4: f06f 010d mvn.w r1, #13
80127d8: 4610 mov r0, r2
80127da: 4798 blx r3
tcp_pcb_remove(&tcp_active_pcbs, pcb);
80127dc: 69f9 ldr r1, [r7, #28]
80127de: 488d ldr r0, [pc, #564] ; (8012a14 <tcp_input+0x7e0>)
80127e0: f7ff fbb0 bl 8011f44 <tcp_pcb_remove>
tcp_free(pcb);
80127e4: 69f8 ldr r0, [r7, #28]
80127e6: f7fe f99d bl 8010b24 <tcp_free>
80127ea: e0c1 b.n 8012970 <tcp_input+0x73c>
} else {
err = ERR_OK;
80127ec: 2300 movs r3, #0
80127ee: 74fb strb r3, [r7, #19]
/* If the application has registered a "sent" function to be
called when new send buffer space is available, we call it
now. */
if (recv_acked > 0) {
80127f0: 4b89 ldr r3, [pc, #548] ; (8012a18 <tcp_input+0x7e4>)
80127f2: 881b ldrh r3, [r3, #0]
80127f4: 2b00 cmp r3, #0
80127f6: d01d beq.n 8012834 <tcp_input+0x600>
while (acked > 0) {
acked16 = (u16_t)LWIP_MIN(acked, 0xffffu);
acked -= acked16;
#else
{
acked16 = recv_acked;
80127f8: 4b87 ldr r3, [pc, #540] ; (8012a18 <tcp_input+0x7e4>)
80127fa: 881b ldrh r3, [r3, #0]
80127fc: 81fb strh r3, [r7, #14]
#endif
TCP_EVENT_SENT(pcb, (u16_t)acked16, err);
80127fe: 69fb ldr r3, [r7, #28]
8012800: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8012804: 2b00 cmp r3, #0
8012806: d00a beq.n 801281e <tcp_input+0x5ea>
8012808: 69fb ldr r3, [r7, #28]
801280a: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
801280e: 69fa ldr r2, [r7, #28]
8012810: 6910 ldr r0, [r2, #16]
8012812: 89fa ldrh r2, [r7, #14]
8012814: 69f9 ldr r1, [r7, #28]
8012816: 4798 blx r3
8012818: 4603 mov r3, r0
801281a: 74fb strb r3, [r7, #19]
801281c: e001 b.n 8012822 <tcp_input+0x5ee>
801281e: 2300 movs r3, #0
8012820: 74fb strb r3, [r7, #19]
if (err == ERR_ABRT) {
8012822: f997 3013 ldrsb.w r3, [r7, #19]
8012826: f113 0f0d cmn.w r3, #13
801282a: f000 8098 beq.w 801295e <tcp_input+0x72a>
goto aborted;
}
}
recv_acked = 0;
801282e: 4b7a ldr r3, [pc, #488] ; (8012a18 <tcp_input+0x7e4>)
8012830: 2200 movs r2, #0
8012832: 801a strh r2, [r3, #0]
}
if (tcp_input_delayed_close(pcb)) {
8012834: 69f8 ldr r0, [r7, #28]
8012836: f000 f907 bl 8012a48 <tcp_input_delayed_close>
801283a: 4603 mov r3, r0
801283c: 2b00 cmp r3, #0
801283e: f040 8090 bne.w 8012962 <tcp_input+0x72e>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
while (recv_data != NULL) {
struct pbuf *rest = NULL;
pbuf_split_64k(recv_data, &rest);
#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
if (recv_data != NULL) {
8012842: 4b76 ldr r3, [pc, #472] ; (8012a1c <tcp_input+0x7e8>)
8012844: 681b ldr r3, [r3, #0]
8012846: 2b00 cmp r3, #0
8012848: d041 beq.n 80128ce <tcp_input+0x69a>
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL);
801284a: 69fb ldr r3, [r7, #28]
801284c: 6f9b ldr r3, [r3, #120] ; 0x78
801284e: 2b00 cmp r3, #0
8012850: d006 beq.n 8012860 <tcp_input+0x62c>
8012852: 4b73 ldr r3, [pc, #460] ; (8012a20 <tcp_input+0x7ec>)
8012854: f44f 72f3 mov.w r2, #486 ; 0x1e6
8012858: 4972 ldr r1, [pc, #456] ; (8012a24 <tcp_input+0x7f0>)
801285a: 4873 ldr r0, [pc, #460] ; (8012a28 <tcp_input+0x7f4>)
801285c: f008 fbb2 bl 801afc4 <iprintf>
if (pcb->flags & TF_RXCLOSED) {
8012860: 69fb ldr r3, [r7, #28]
8012862: 8b5b ldrh r3, [r3, #26]
8012864: f003 0310 and.w r3, r3, #16
8012868: 2b00 cmp r3, #0
801286a: d008 beq.n 801287e <tcp_input+0x64a>
/* received data although already closed -> abort (send RST) to
notify the remote host that not all data has been processed */
pbuf_free(recv_data);
801286c: 4b6b ldr r3, [pc, #428] ; (8012a1c <tcp_input+0x7e8>)
801286e: 681b ldr r3, [r3, #0]
8012870: 4618 mov r0, r3
8012872: f7fd fe9b bl 80105ac <pbuf_free>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
if (rest != NULL) {
pbuf_free(rest);
}
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
tcp_abort(pcb);
8012876: 69f8 ldr r0, [r7, #28]
8012878: f7fe fc3c bl 80110f4 <tcp_abort>
goto aborted;
801287c: e078 b.n 8012970 <tcp_input+0x73c>
}
/* Notify application that data has been received. */
TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
801287e: 69fb ldr r3, [r7, #28]
8012880: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8012884: 2b00 cmp r3, #0
8012886: d00c beq.n 80128a2 <tcp_input+0x66e>
8012888: 69fb ldr r3, [r7, #28]
801288a: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
801288e: 69fb ldr r3, [r7, #28]
8012890: 6918 ldr r0, [r3, #16]
8012892: 4b62 ldr r3, [pc, #392] ; (8012a1c <tcp_input+0x7e8>)
8012894: 681a ldr r2, [r3, #0]
8012896: 2300 movs r3, #0
8012898: 69f9 ldr r1, [r7, #28]
801289a: 47a0 blx r4
801289c: 4603 mov r3, r0
801289e: 74fb strb r3, [r7, #19]
80128a0: e008 b.n 80128b4 <tcp_input+0x680>
80128a2: 4b5e ldr r3, [pc, #376] ; (8012a1c <tcp_input+0x7e8>)
80128a4: 681a ldr r2, [r3, #0]
80128a6: 2300 movs r3, #0
80128a8: 69f9 ldr r1, [r7, #28]
80128aa: 2000 movs r0, #0
80128ac: f7ff f952 bl 8011b54 <tcp_recv_null>
80128b0: 4603 mov r3, r0
80128b2: 74fb strb r3, [r7, #19]
if (err == ERR_ABRT) {
80128b4: f997 3013 ldrsb.w r3, [r7, #19]
80128b8: f113 0f0d cmn.w r3, #13
80128bc: d053 beq.n 8012966 <tcp_input+0x732>
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
goto aborted;
}
/* If the upper layer can't receive this data, store it */
if (err != ERR_OK) {
80128be: f997 3013 ldrsb.w r3, [r7, #19]
80128c2: 2b00 cmp r3, #0
80128c4: d003 beq.n 80128ce <tcp_input+0x69a>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
if (rest != NULL) {
pbuf_cat(recv_data, rest);
}
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
pcb->refused_data = recv_data;
80128c6: 4b55 ldr r3, [pc, #340] ; (8012a1c <tcp_input+0x7e8>)
80128c8: 681a ldr r2, [r3, #0]
80128ca: 69fb ldr r3, [r7, #28]
80128cc: 679a str r2, [r3, #120] ; 0x78
}
}
/* If a FIN segment was received, we call the callback
function with a NULL buffer to indicate EOF. */
if (recv_flags & TF_GOT_FIN) {
80128ce: 4b50 ldr r3, [pc, #320] ; (8012a10 <tcp_input+0x7dc>)
80128d0: 781b ldrb r3, [r3, #0]
80128d2: f003 0320 and.w r3, r3, #32
80128d6: 2b00 cmp r3, #0
80128d8: d030 beq.n 801293c <tcp_input+0x708>
if (pcb->refused_data != NULL) {
80128da: 69fb ldr r3, [r7, #28]
80128dc: 6f9b ldr r3, [r3, #120] ; 0x78
80128de: 2b00 cmp r3, #0
80128e0: d009 beq.n 80128f6 <tcp_input+0x6c2>
/* Delay this if we have refused data. */
pcb->refused_data->flags |= PBUF_FLAG_TCP_FIN;
80128e2: 69fb ldr r3, [r7, #28]
80128e4: 6f9b ldr r3, [r3, #120] ; 0x78
80128e6: 7b5a ldrb r2, [r3, #13]
80128e8: 69fb ldr r3, [r7, #28]
80128ea: 6f9b ldr r3, [r3, #120] ; 0x78
80128ec: f042 0220 orr.w r2, r2, #32
80128f0: b2d2 uxtb r2, r2
80128f2: 735a strb r2, [r3, #13]
80128f4: e022 b.n 801293c <tcp_input+0x708>
} else {
/* correct rcv_wnd as the application won't call tcp_recved()
for the FIN's seqno */
if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
80128f6: 69fb ldr r3, [r7, #28]
80128f8: 8d1b ldrh r3, [r3, #40] ; 0x28
80128fa: f5b3 6f06 cmp.w r3, #2144 ; 0x860
80128fe: d005 beq.n 801290c <tcp_input+0x6d8>
pcb->rcv_wnd++;
8012900: 69fb ldr r3, [r7, #28]
8012902: 8d1b ldrh r3, [r3, #40] ; 0x28
8012904: 3301 adds r3, #1
8012906: b29a uxth r2, r3
8012908: 69fb ldr r3, [r7, #28]
801290a: 851a strh r2, [r3, #40] ; 0x28
}
TCP_EVENT_CLOSED(pcb, err);
801290c: 69fb ldr r3, [r7, #28]
801290e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8012912: 2b00 cmp r3, #0
8012914: d00b beq.n 801292e <tcp_input+0x6fa>
8012916: 69fb ldr r3, [r7, #28]
8012918: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
801291c: 69fb ldr r3, [r7, #28]
801291e: 6918 ldr r0, [r3, #16]
8012920: 2300 movs r3, #0
8012922: 2200 movs r2, #0
8012924: 69f9 ldr r1, [r7, #28]
8012926: 47a0 blx r4
8012928: 4603 mov r3, r0
801292a: 74fb strb r3, [r7, #19]
801292c: e001 b.n 8012932 <tcp_input+0x6fe>
801292e: 2300 movs r3, #0
8012930: 74fb strb r3, [r7, #19]
if (err == ERR_ABRT) {
8012932: f997 3013 ldrsb.w r3, [r7, #19]
8012936: f113 0f0d cmn.w r3, #13
801293a: d016 beq.n 801296a <tcp_input+0x736>
goto aborted;
}
}
}
tcp_input_pcb = NULL;
801293c: 4b33 ldr r3, [pc, #204] ; (8012a0c <tcp_input+0x7d8>)
801293e: 2200 movs r2, #0
8012940: 601a str r2, [r3, #0]
if (tcp_input_delayed_close(pcb)) {
8012942: 69f8 ldr r0, [r7, #28]
8012944: f000 f880 bl 8012a48 <tcp_input_delayed_close>
8012948: 4603 mov r3, r0
801294a: 2b00 cmp r3, #0
801294c: d10f bne.n 801296e <tcp_input+0x73a>
goto aborted;
}
/* Try to send something out. */
tcp_output(pcb);
801294e: 69f8 ldr r0, [r7, #28]
8012950: f002 fab8 bl 8014ec4 <tcp_output>
8012954: e00c b.n 8012970 <tcp_input+0x73c>
goto aborted;
8012956: bf00 nop
8012958: e00a b.n 8012970 <tcp_input+0x73c>
#endif /* TCP_INPUT_DEBUG */
}
}
/* Jump target if pcb has been aborted in a callback (by calling tcp_abort()).
Below this line, 'pcb' may not be dereferenced! */
aborted:
801295a: bf00 nop
801295c: e008 b.n 8012970 <tcp_input+0x73c>
goto aborted;
801295e: bf00 nop
8012960: e006 b.n 8012970 <tcp_input+0x73c>
goto aborted;
8012962: bf00 nop
8012964: e004 b.n 8012970 <tcp_input+0x73c>
goto aborted;
8012966: bf00 nop
8012968: e002 b.n 8012970 <tcp_input+0x73c>
goto aborted;
801296a: bf00 nop
801296c: e000 b.n 8012970 <tcp_input+0x73c>
goto aborted;
801296e: bf00 nop
tcp_input_pcb = NULL;
8012970: 4b26 ldr r3, [pc, #152] ; (8012a0c <tcp_input+0x7d8>)
8012972: 2200 movs r2, #0
8012974: 601a str r2, [r3, #0]
recv_data = NULL;
8012976: 4b29 ldr r3, [pc, #164] ; (8012a1c <tcp_input+0x7e8>)
8012978: 2200 movs r2, #0
801297a: 601a str r2, [r3, #0]
/* give up our reference to inseg.p */
if (inseg.p != NULL) {
801297c: 4b2b ldr r3, [pc, #172] ; (8012a2c <tcp_input+0x7f8>)
801297e: 685b ldr r3, [r3, #4]
8012980: 2b00 cmp r3, #0
8012982: d03f beq.n 8012a04 <tcp_input+0x7d0>
pbuf_free(inseg.p);
8012984: 4b29 ldr r3, [pc, #164] ; (8012a2c <tcp_input+0x7f8>)
8012986: 685b ldr r3, [r3, #4]
8012988: 4618 mov r0, r3
801298a: f7fd fe0f bl 80105ac <pbuf_free>
inseg.p = NULL;
801298e: 4b27 ldr r3, [pc, #156] ; (8012a2c <tcp_input+0x7f8>)
8012990: 2200 movs r2, #0
8012992: 605a str r2, [r3, #4]
pbuf_free(p);
}
LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
PERF_STOP("tcp_input");
return;
8012994: e036 b.n 8012a04 <tcp_input+0x7d0>
if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
8012996: 4b26 ldr r3, [pc, #152] ; (8012a30 <tcp_input+0x7fc>)
8012998: 681b ldr r3, [r3, #0]
801299a: 899b ldrh r3, [r3, #12]
801299c: b29b uxth r3, r3
801299e: 4618 mov r0, r3
80129a0: f7fc fa4c bl 800ee3c <lwip_htons>
80129a4: 4603 mov r3, r0
80129a6: b2db uxtb r3, r3
80129a8: f003 0304 and.w r3, r3, #4
80129ac: 2b00 cmp r3, #0
80129ae: d118 bne.n 80129e2 <tcp_input+0x7ae>
tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
80129b0: 4b20 ldr r3, [pc, #128] ; (8012a34 <tcp_input+0x800>)
80129b2: 6819 ldr r1, [r3, #0]
80129b4: 4b20 ldr r3, [pc, #128] ; (8012a38 <tcp_input+0x804>)
80129b6: 881b ldrh r3, [r3, #0]
80129b8: 461a mov r2, r3
80129ba: 4b20 ldr r3, [pc, #128] ; (8012a3c <tcp_input+0x808>)
80129bc: 681b ldr r3, [r3, #0]
80129be: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
80129c0: 4b1b ldr r3, [pc, #108] ; (8012a30 <tcp_input+0x7fc>)
80129c2: 681b ldr r3, [r3, #0]
tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
80129c4: 885b ldrh r3, [r3, #2]
80129c6: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
80129c8: 4a19 ldr r2, [pc, #100] ; (8012a30 <tcp_input+0x7fc>)
80129ca: 6812 ldr r2, [r2, #0]
tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
80129cc: 8812 ldrh r2, [r2, #0]
80129ce: b292 uxth r2, r2
80129d0: 9202 str r2, [sp, #8]
80129d2: 9301 str r3, [sp, #4]
80129d4: 4b1a ldr r3, [pc, #104] ; (8012a40 <tcp_input+0x80c>)
80129d6: 9300 str r3, [sp, #0]
80129d8: 4b1a ldr r3, [pc, #104] ; (8012a44 <tcp_input+0x810>)
80129da: 4602 mov r2, r0
80129dc: 2000 movs r0, #0
80129de: f003 f825 bl 8015a2c <tcp_rst>
pbuf_free(p);
80129e2: 6878 ldr r0, [r7, #4]
80129e4: f7fd fde2 bl 80105ac <pbuf_free>
return;
80129e8: e00c b.n 8012a04 <tcp_input+0x7d0>
goto dropped;
80129ea: bf00 nop
80129ec: e006 b.n 80129fc <tcp_input+0x7c8>
goto dropped;
80129ee: bf00 nop
80129f0: e004 b.n 80129fc <tcp_input+0x7c8>
goto dropped;
80129f2: bf00 nop
80129f4: e002 b.n 80129fc <tcp_input+0x7c8>
goto dropped;
80129f6: bf00 nop
80129f8: e000 b.n 80129fc <tcp_input+0x7c8>
goto dropped;
80129fa: bf00 nop
dropped:
TCP_STATS_INC(tcp.drop);
MIB2_STATS_INC(mib2.tcpinerrs);
pbuf_free(p);
80129fc: 6878 ldr r0, [r7, #4]
80129fe: f7fd fdd5 bl 80105ac <pbuf_free>
8012a02: e000 b.n 8012a06 <tcp_input+0x7d2>
return;
8012a04: bf00 nop
}
8012a06: 3724 adds r7, #36 ; 0x24
8012a08: 46bd mov sp, r7
8012a0a: bd90 pop {r4, r7, pc}
8012a0c: 2000f850 .word 0x2000f850
8012a10: 2000874d .word 0x2000874d
8012a14: 2000f83c .word 0x2000f83c
8012a18: 20008748 .word 0x20008748
8012a1c: 20008750 .word 0x20008750
8012a20: 0801d484 .word 0x0801d484
8012a24: 0801d638 .word 0x0801d638
8012a28: 0801d4d0 .word 0x0801d4d0
8012a2c: 20008720 .word 0x20008720
8012a30: 20008730 .word 0x20008730
8012a34: 20008744 .word 0x20008744
8012a38: 2000874a .word 0x2000874a
8012a3c: 20008740 .word 0x20008740
8012a40: 2000c118 .word 0x2000c118
8012a44: 2000c11c .word 0x2000c11c
08012a48 <tcp_input_delayed_close>:
* any more.
* @returns 1 if the pcb has been closed and deallocated, 0 otherwise
*/
static int
tcp_input_delayed_close(struct tcp_pcb *pcb)
{
8012a48: b580 push {r7, lr}
8012a4a: b082 sub sp, #8
8012a4c: af00 add r7, sp, #0
8012a4e: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_input_delayed_close: invalid pcb", pcb != NULL);
8012a50: 687b ldr r3, [r7, #4]
8012a52: 2b00 cmp r3, #0
8012a54: d106 bne.n 8012a64 <tcp_input_delayed_close+0x1c>
8012a56: 4b17 ldr r3, [pc, #92] ; (8012ab4 <tcp_input_delayed_close+0x6c>)
8012a58: f240 225a movw r2, #602 ; 0x25a
8012a5c: 4916 ldr r1, [pc, #88] ; (8012ab8 <tcp_input_delayed_close+0x70>)
8012a5e: 4817 ldr r0, [pc, #92] ; (8012abc <tcp_input_delayed_close+0x74>)
8012a60: f008 fab0 bl 801afc4 <iprintf>
if (recv_flags & TF_CLOSED) {
8012a64: 4b16 ldr r3, [pc, #88] ; (8012ac0 <tcp_input_delayed_close+0x78>)
8012a66: 781b ldrb r3, [r3, #0]
8012a68: f003 0310 and.w r3, r3, #16
8012a6c: 2b00 cmp r3, #0
8012a6e: d01c beq.n 8012aaa <tcp_input_delayed_close+0x62>
/* The connection has been closed and we will deallocate the
PCB. */
if (!(pcb->flags & TF_RXCLOSED)) {
8012a70: 687b ldr r3, [r7, #4]
8012a72: 8b5b ldrh r3, [r3, #26]
8012a74: f003 0310 and.w r3, r3, #16
8012a78: 2b00 cmp r3, #0
8012a7a: d10d bne.n 8012a98 <tcp_input_delayed_close+0x50>
/* Connection closed although the application has only shut down the
tx side: call the PCB's err callback and indicate the closure to
ensure the application doesn't continue using the PCB. */
TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_CLSD);
8012a7c: 687b ldr r3, [r7, #4]
8012a7e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8012a82: 2b00 cmp r3, #0
8012a84: d008 beq.n 8012a98 <tcp_input_delayed_close+0x50>
8012a86: 687b ldr r3, [r7, #4]
8012a88: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8012a8c: 687a ldr r2, [r7, #4]
8012a8e: 6912 ldr r2, [r2, #16]
8012a90: f06f 010e mvn.w r1, #14
8012a94: 4610 mov r0, r2
8012a96: 4798 blx r3
}
tcp_pcb_remove(&tcp_active_pcbs, pcb);
8012a98: 6879 ldr r1, [r7, #4]
8012a9a: 480a ldr r0, [pc, #40] ; (8012ac4 <tcp_input_delayed_close+0x7c>)
8012a9c: f7ff fa52 bl 8011f44 <tcp_pcb_remove>
tcp_free(pcb);
8012aa0: 6878 ldr r0, [r7, #4]
8012aa2: f7fe f83f bl 8010b24 <tcp_free>
return 1;
8012aa6: 2301 movs r3, #1
8012aa8: e000 b.n 8012aac <tcp_input_delayed_close+0x64>
}
return 0;
8012aaa: 2300 movs r3, #0
}
8012aac: 4618 mov r0, r3
8012aae: 3708 adds r7, #8
8012ab0: 46bd mov sp, r7
8012ab2: bd80 pop {r7, pc}
8012ab4: 0801d484 .word 0x0801d484
8012ab8: 0801d654 .word 0x0801d654
8012abc: 0801d4d0 .word 0x0801d4d0
8012ac0: 2000874d .word 0x2000874d
8012ac4: 2000f83c .word 0x2000f83c
08012ac8 <tcp_listen_input>:
* @note the segment which arrived is saved in global variables, therefore only the pcb
* involved is passed as a parameter to this function
*/
static void
tcp_listen_input(struct tcp_pcb_listen *pcb)
{
8012ac8: b590 push {r4, r7, lr}
8012aca: b08b sub sp, #44 ; 0x2c
8012acc: af04 add r7, sp, #16
8012ace: 6078 str r0, [r7, #4]
struct tcp_pcb *npcb;
u32_t iss;
err_t rc;
if (flags & TCP_RST) {
8012ad0: 4b6f ldr r3, [pc, #444] ; (8012c90 <tcp_listen_input+0x1c8>)
8012ad2: 781b ldrb r3, [r3, #0]
8012ad4: f003 0304 and.w r3, r3, #4
8012ad8: 2b00 cmp r3, #0
8012ada: f040 80d2 bne.w 8012c82 <tcp_listen_input+0x1ba>
/* An incoming RST should be ignored. Return. */
return;
}
LWIP_ASSERT("tcp_listen_input: invalid pcb", pcb != NULL);
8012ade: 687b ldr r3, [r7, #4]
8012ae0: 2b00 cmp r3, #0
8012ae2: d106 bne.n 8012af2 <tcp_listen_input+0x2a>
8012ae4: 4b6b ldr r3, [pc, #428] ; (8012c94 <tcp_listen_input+0x1cc>)
8012ae6: f240 2281 movw r2, #641 ; 0x281
8012aea: 496b ldr r1, [pc, #428] ; (8012c98 <tcp_listen_input+0x1d0>)
8012aec: 486b ldr r0, [pc, #428] ; (8012c9c <tcp_listen_input+0x1d4>)
8012aee: f008 fa69 bl 801afc4 <iprintf>
/* In the LISTEN state, we check for incoming SYN segments,
creates a new PCB, and responds with a SYN|ACK. */
if (flags & TCP_ACK) {
8012af2: 4b67 ldr r3, [pc, #412] ; (8012c90 <tcp_listen_input+0x1c8>)
8012af4: 781b ldrb r3, [r3, #0]
8012af6: f003 0310 and.w r3, r3, #16
8012afa: 2b00 cmp r3, #0
8012afc: d019 beq.n 8012b32 <tcp_listen_input+0x6a>
/* For incoming segments with the ACK flag set, respond with a
RST. */
LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012afe: 4b68 ldr r3, [pc, #416] ; (8012ca0 <tcp_listen_input+0x1d8>)
8012b00: 6819 ldr r1, [r3, #0]
8012b02: 4b68 ldr r3, [pc, #416] ; (8012ca4 <tcp_listen_input+0x1dc>)
8012b04: 881b ldrh r3, [r3, #0]
8012b06: 461a mov r2, r3
8012b08: 4b67 ldr r3, [pc, #412] ; (8012ca8 <tcp_listen_input+0x1e0>)
8012b0a: 681b ldr r3, [r3, #0]
8012b0c: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8012b0e: 4b67 ldr r3, [pc, #412] ; (8012cac <tcp_listen_input+0x1e4>)
8012b10: 681b ldr r3, [r3, #0]
tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012b12: 885b ldrh r3, [r3, #2]
8012b14: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8012b16: 4a65 ldr r2, [pc, #404] ; (8012cac <tcp_listen_input+0x1e4>)
8012b18: 6812 ldr r2, [r2, #0]
tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012b1a: 8812 ldrh r2, [r2, #0]
8012b1c: b292 uxth r2, r2
8012b1e: 9202 str r2, [sp, #8]
8012b20: 9301 str r3, [sp, #4]
8012b22: 4b63 ldr r3, [pc, #396] ; (8012cb0 <tcp_listen_input+0x1e8>)
8012b24: 9300 str r3, [sp, #0]
8012b26: 4b63 ldr r3, [pc, #396] ; (8012cb4 <tcp_listen_input+0x1ec>)
8012b28: 4602 mov r2, r0
8012b2a: 6878 ldr r0, [r7, #4]
8012b2c: f002 ff7e bl 8015a2c <tcp_rst>
tcp_abandon(npcb, 0);
return;
}
tcp_output(npcb);
}
return;
8012b30: e0a9 b.n 8012c86 <tcp_listen_input+0x1be>
} else if (flags & TCP_SYN) {
8012b32: 4b57 ldr r3, [pc, #348] ; (8012c90 <tcp_listen_input+0x1c8>)
8012b34: 781b ldrb r3, [r3, #0]
8012b36: f003 0302 and.w r3, r3, #2
8012b3a: 2b00 cmp r3, #0
8012b3c: f000 80a3 beq.w 8012c86 <tcp_listen_input+0x1be>
npcb = tcp_alloc(pcb->prio);
8012b40: 687b ldr r3, [r7, #4]
8012b42: 7d5b ldrb r3, [r3, #21]
8012b44: 4618 mov r0, r3
8012b46: f7ff f929 bl 8011d9c <tcp_alloc>
8012b4a: 6178 str r0, [r7, #20]
if (npcb == NULL) {
8012b4c: 697b ldr r3, [r7, #20]
8012b4e: 2b00 cmp r3, #0
8012b50: d111 bne.n 8012b76 <tcp_listen_input+0xae>
TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
8012b52: 687b ldr r3, [r7, #4]
8012b54: 699b ldr r3, [r3, #24]
8012b56: 2b00 cmp r3, #0
8012b58: d00a beq.n 8012b70 <tcp_listen_input+0xa8>
8012b5a: 687b ldr r3, [r7, #4]
8012b5c: 699b ldr r3, [r3, #24]
8012b5e: 687a ldr r2, [r7, #4]
8012b60: 6910 ldr r0, [r2, #16]
8012b62: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
8012b66: 2100 movs r1, #0
8012b68: 4798 blx r3
8012b6a: 4603 mov r3, r0
8012b6c: 73bb strb r3, [r7, #14]
return;
8012b6e: e08b b.n 8012c88 <tcp_listen_input+0x1c0>
TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
8012b70: 23f0 movs r3, #240 ; 0xf0
8012b72: 73bb strb r3, [r7, #14]
return;
8012b74: e088 b.n 8012c88 <tcp_listen_input+0x1c0>
ip_addr_copy(npcb->local_ip, *ip_current_dest_addr());
8012b76: 4b50 ldr r3, [pc, #320] ; (8012cb8 <tcp_listen_input+0x1f0>)
8012b78: 695a ldr r2, [r3, #20]
8012b7a: 697b ldr r3, [r7, #20]
8012b7c: 601a str r2, [r3, #0]
ip_addr_copy(npcb->remote_ip, *ip_current_src_addr());
8012b7e: 4b4e ldr r3, [pc, #312] ; (8012cb8 <tcp_listen_input+0x1f0>)
8012b80: 691a ldr r2, [r3, #16]
8012b82: 697b ldr r3, [r7, #20]
8012b84: 605a str r2, [r3, #4]
npcb->local_port = pcb->local_port;
8012b86: 687b ldr r3, [r7, #4]
8012b88: 8ada ldrh r2, [r3, #22]
8012b8a: 697b ldr r3, [r7, #20]
8012b8c: 82da strh r2, [r3, #22]
npcb->remote_port = tcphdr->src;
8012b8e: 4b47 ldr r3, [pc, #284] ; (8012cac <tcp_listen_input+0x1e4>)
8012b90: 681b ldr r3, [r3, #0]
8012b92: 881b ldrh r3, [r3, #0]
8012b94: b29a uxth r2, r3
8012b96: 697b ldr r3, [r7, #20]
8012b98: 831a strh r2, [r3, #24]
npcb->state = SYN_RCVD;
8012b9a: 697b ldr r3, [r7, #20]
8012b9c: 2203 movs r2, #3
8012b9e: 751a strb r2, [r3, #20]
npcb->rcv_nxt = seqno + 1;
8012ba0: 4b41 ldr r3, [pc, #260] ; (8012ca8 <tcp_listen_input+0x1e0>)
8012ba2: 681b ldr r3, [r3, #0]
8012ba4: 1c5a adds r2, r3, #1
8012ba6: 697b ldr r3, [r7, #20]
8012ba8: 625a str r2, [r3, #36] ; 0x24
npcb->rcv_ann_right_edge = npcb->rcv_nxt;
8012baa: 697b ldr r3, [r7, #20]
8012bac: 6a5a ldr r2, [r3, #36] ; 0x24
8012bae: 697b ldr r3, [r7, #20]
8012bb0: 62da str r2, [r3, #44] ; 0x2c
iss = tcp_next_iss(npcb);
8012bb2: 6978 ldr r0, [r7, #20]
8012bb4: f7ff fa5a bl 801206c <tcp_next_iss>
8012bb8: 6138 str r0, [r7, #16]
npcb->snd_wl2 = iss;
8012bba: 697b ldr r3, [r7, #20]
8012bbc: 693a ldr r2, [r7, #16]
8012bbe: 659a str r2, [r3, #88] ; 0x58
npcb->snd_nxt = iss;
8012bc0: 697b ldr r3, [r7, #20]
8012bc2: 693a ldr r2, [r7, #16]
8012bc4: 651a str r2, [r3, #80] ; 0x50
npcb->lastack = iss;
8012bc6: 697b ldr r3, [r7, #20]
8012bc8: 693a ldr r2, [r7, #16]
8012bca: 645a str r2, [r3, #68] ; 0x44
npcb->snd_lbb = iss;
8012bcc: 697b ldr r3, [r7, #20]
8012bce: 693a ldr r2, [r7, #16]
8012bd0: 65da str r2, [r3, #92] ; 0x5c
npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
8012bd2: 4b35 ldr r3, [pc, #212] ; (8012ca8 <tcp_listen_input+0x1e0>)
8012bd4: 681b ldr r3, [r3, #0]
8012bd6: 1e5a subs r2, r3, #1
8012bd8: 697b ldr r3, [r7, #20]
8012bda: 655a str r2, [r3, #84] ; 0x54
npcb->callback_arg = pcb->callback_arg;
8012bdc: 687b ldr r3, [r7, #4]
8012bde: 691a ldr r2, [r3, #16]
8012be0: 697b ldr r3, [r7, #20]
8012be2: 611a str r2, [r3, #16]
npcb->listener = pcb;
8012be4: 697b ldr r3, [r7, #20]
8012be6: 687a ldr r2, [r7, #4]
8012be8: 67da str r2, [r3, #124] ; 0x7c
npcb->so_options = pcb->so_options & SOF_INHERITED;
8012bea: 687b ldr r3, [r7, #4]
8012bec: 7a5b ldrb r3, [r3, #9]
8012bee: f003 030c and.w r3, r3, #12
8012bf2: b2da uxtb r2, r3
8012bf4: 697b ldr r3, [r7, #20]
8012bf6: 725a strb r2, [r3, #9]
npcb->netif_idx = pcb->netif_idx;
8012bf8: 687b ldr r3, [r7, #4]
8012bfa: 7a1a ldrb r2, [r3, #8]
8012bfc: 697b ldr r3, [r7, #20]
8012bfe: 721a strb r2, [r3, #8]
TCP_REG_ACTIVE(npcb);
8012c00: 4b2e ldr r3, [pc, #184] ; (8012cbc <tcp_listen_input+0x1f4>)
8012c02: 681a ldr r2, [r3, #0]
8012c04: 697b ldr r3, [r7, #20]
8012c06: 60da str r2, [r3, #12]
8012c08: 4a2c ldr r2, [pc, #176] ; (8012cbc <tcp_listen_input+0x1f4>)
8012c0a: 697b ldr r3, [r7, #20]
8012c0c: 6013 str r3, [r2, #0]
8012c0e: f003 f8cf bl 8015db0 <tcp_timer_needed>
8012c12: 4b2b ldr r3, [pc, #172] ; (8012cc0 <tcp_listen_input+0x1f8>)
8012c14: 2201 movs r2, #1
8012c16: 701a strb r2, [r3, #0]
tcp_parseopt(npcb);
8012c18: 6978 ldr r0, [r7, #20]
8012c1a: f001 fd8d bl 8014738 <tcp_parseopt>
npcb->snd_wnd = tcphdr->wnd;
8012c1e: 4b23 ldr r3, [pc, #140] ; (8012cac <tcp_listen_input+0x1e4>)
8012c20: 681b ldr r3, [r3, #0]
8012c22: 89db ldrh r3, [r3, #14]
8012c24: b29a uxth r2, r3
8012c26: 697b ldr r3, [r7, #20]
8012c28: f8a3 2060 strh.w r2, [r3, #96] ; 0x60
npcb->snd_wnd_max = npcb->snd_wnd;
8012c2c: 697b ldr r3, [r7, #20]
8012c2e: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8012c32: 697b ldr r3, [r7, #20]
8012c34: f8a3 2062 strh.w r2, [r3, #98] ; 0x62
npcb->mss = tcp_eff_send_mss(npcb->mss, &npcb->local_ip, &npcb->remote_ip);
8012c38: 697b ldr r3, [r7, #20]
8012c3a: 8e5c ldrh r4, [r3, #50] ; 0x32
8012c3c: 697b ldr r3, [r7, #20]
8012c3e: 3304 adds r3, #4
8012c40: 4618 mov r0, r3
8012c42: f006 fe5d bl 8019900 <ip4_route>
8012c46: 4601 mov r1, r0
8012c48: 697b ldr r3, [r7, #20]
8012c4a: 3304 adds r3, #4
8012c4c: 461a mov r2, r3
8012c4e: 4620 mov r0, r4
8012c50: f7ff fa32 bl 80120b8 <tcp_eff_send_mss_netif>
8012c54: 4603 mov r3, r0
8012c56: 461a mov r2, r3
8012c58: 697b ldr r3, [r7, #20]
8012c5a: 865a strh r2, [r3, #50] ; 0x32
rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK);
8012c5c: 2112 movs r1, #18
8012c5e: 6978 ldr r0, [r7, #20]
8012c60: f002 f842 bl 8014ce8 <tcp_enqueue_flags>
8012c64: 4603 mov r3, r0
8012c66: 73fb strb r3, [r7, #15]
if (rc != ERR_OK) {
8012c68: f997 300f ldrsb.w r3, [r7, #15]
8012c6c: 2b00 cmp r3, #0
8012c6e: d004 beq.n 8012c7a <tcp_listen_input+0x1b2>
tcp_abandon(npcb, 0);
8012c70: 2100 movs r1, #0
8012c72: 6978 ldr r0, [r7, #20]
8012c74: f7fe f980 bl 8010f78 <tcp_abandon>
return;
8012c78: e006 b.n 8012c88 <tcp_listen_input+0x1c0>
tcp_output(npcb);
8012c7a: 6978 ldr r0, [r7, #20]
8012c7c: f002 f922 bl 8014ec4 <tcp_output>
return;
8012c80: e001 b.n 8012c86 <tcp_listen_input+0x1be>
return;
8012c82: bf00 nop
8012c84: e000 b.n 8012c88 <tcp_listen_input+0x1c0>
return;
8012c86: bf00 nop
}
8012c88: 371c adds r7, #28
8012c8a: 46bd mov sp, r7
8012c8c: bd90 pop {r4, r7, pc}
8012c8e: bf00 nop
8012c90: 2000874c .word 0x2000874c
8012c94: 0801d484 .word 0x0801d484
8012c98: 0801d67c .word 0x0801d67c
8012c9c: 0801d4d0 .word 0x0801d4d0
8012ca0: 20008744 .word 0x20008744
8012ca4: 2000874a .word 0x2000874a
8012ca8: 20008740 .word 0x20008740
8012cac: 20008730 .word 0x20008730
8012cb0: 2000c118 .word 0x2000c118
8012cb4: 2000c11c .word 0x2000c11c
8012cb8: 2000c108 .word 0x2000c108
8012cbc: 2000f83c .word 0x2000f83c
8012cc0: 2000f838 .word 0x2000f838
08012cc4 <tcp_timewait_input>:
* @note the segment which arrived is saved in global variables, therefore only the pcb
* involved is passed as a parameter to this function
*/
static void
tcp_timewait_input(struct tcp_pcb *pcb)
{
8012cc4: b580 push {r7, lr}
8012cc6: b086 sub sp, #24
8012cc8: af04 add r7, sp, #16
8012cca: 6078 str r0, [r7, #4]
/* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */
/* RFC 793 3.9 Event Processing - Segment Arrives:
* - first check sequence number - we skip that one in TIME_WAIT (always
* acceptable since we only send ACKs)
* - second check the RST bit (... return) */
if (flags & TCP_RST) {
8012ccc: 4b2f ldr r3, [pc, #188] ; (8012d8c <tcp_timewait_input+0xc8>)
8012cce: 781b ldrb r3, [r3, #0]
8012cd0: f003 0304 and.w r3, r3, #4
8012cd4: 2b00 cmp r3, #0
8012cd6: d153 bne.n 8012d80 <tcp_timewait_input+0xbc>
return;
}
LWIP_ASSERT("tcp_timewait_input: invalid pcb", pcb != NULL);
8012cd8: 687b ldr r3, [r7, #4]
8012cda: 2b00 cmp r3, #0
8012cdc: d106 bne.n 8012cec <tcp_timewait_input+0x28>
8012cde: 4b2c ldr r3, [pc, #176] ; (8012d90 <tcp_timewait_input+0xcc>)
8012ce0: f240 22ee movw r2, #750 ; 0x2ee
8012ce4: 492b ldr r1, [pc, #172] ; (8012d94 <tcp_timewait_input+0xd0>)
8012ce6: 482c ldr r0, [pc, #176] ; (8012d98 <tcp_timewait_input+0xd4>)
8012ce8: f008 f96c bl 801afc4 <iprintf>
/* - fourth, check the SYN bit, */
if (flags & TCP_SYN) {
8012cec: 4b27 ldr r3, [pc, #156] ; (8012d8c <tcp_timewait_input+0xc8>)
8012cee: 781b ldrb r3, [r3, #0]
8012cf0: f003 0302 and.w r3, r3, #2
8012cf4: 2b00 cmp r3, #0
8012cf6: d02a beq.n 8012d4e <tcp_timewait_input+0x8a>
/* If an incoming segment is not acceptable, an acknowledgment
should be sent in reply */
if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd)) {
8012cf8: 4b28 ldr r3, [pc, #160] ; (8012d9c <tcp_timewait_input+0xd8>)
8012cfa: 681a ldr r2, [r3, #0]
8012cfc: 687b ldr r3, [r7, #4]
8012cfe: 6a5b ldr r3, [r3, #36] ; 0x24
8012d00: 1ad3 subs r3, r2, r3
8012d02: 2b00 cmp r3, #0
8012d04: db2d blt.n 8012d62 <tcp_timewait_input+0x9e>
8012d06: 4b25 ldr r3, [pc, #148] ; (8012d9c <tcp_timewait_input+0xd8>)
8012d08: 681a ldr r2, [r3, #0]
8012d0a: 687b ldr r3, [r7, #4]
8012d0c: 6a5b ldr r3, [r3, #36] ; 0x24
8012d0e: 6879 ldr r1, [r7, #4]
8012d10: 8d09 ldrh r1, [r1, #40] ; 0x28
8012d12: 440b add r3, r1
8012d14: 1ad3 subs r3, r2, r3
8012d16: 2b00 cmp r3, #0
8012d18: dc23 bgt.n 8012d62 <tcp_timewait_input+0x9e>
/* If the SYN is in the window it is an error, send a reset */
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012d1a: 4b21 ldr r3, [pc, #132] ; (8012da0 <tcp_timewait_input+0xdc>)
8012d1c: 6819 ldr r1, [r3, #0]
8012d1e: 4b21 ldr r3, [pc, #132] ; (8012da4 <tcp_timewait_input+0xe0>)
8012d20: 881b ldrh r3, [r3, #0]
8012d22: 461a mov r2, r3
8012d24: 4b1d ldr r3, [pc, #116] ; (8012d9c <tcp_timewait_input+0xd8>)
8012d26: 681b ldr r3, [r3, #0]
8012d28: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8012d2a: 4b1f ldr r3, [pc, #124] ; (8012da8 <tcp_timewait_input+0xe4>)
8012d2c: 681b ldr r3, [r3, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012d2e: 885b ldrh r3, [r3, #2]
8012d30: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8012d32: 4a1d ldr r2, [pc, #116] ; (8012da8 <tcp_timewait_input+0xe4>)
8012d34: 6812 ldr r2, [r2, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012d36: 8812 ldrh r2, [r2, #0]
8012d38: b292 uxth r2, r2
8012d3a: 9202 str r2, [sp, #8]
8012d3c: 9301 str r3, [sp, #4]
8012d3e: 4b1b ldr r3, [pc, #108] ; (8012dac <tcp_timewait_input+0xe8>)
8012d40: 9300 str r3, [sp, #0]
8012d42: 4b1b ldr r3, [pc, #108] ; (8012db0 <tcp_timewait_input+0xec>)
8012d44: 4602 mov r2, r0
8012d46: 6878 ldr r0, [r7, #4]
8012d48: f002 fe70 bl 8015a2c <tcp_rst>
return;
8012d4c: e01b b.n 8012d86 <tcp_timewait_input+0xc2>
}
} else if (flags & TCP_FIN) {
8012d4e: 4b0f ldr r3, [pc, #60] ; (8012d8c <tcp_timewait_input+0xc8>)
8012d50: 781b ldrb r3, [r3, #0]
8012d52: f003 0301 and.w r3, r3, #1
8012d56: 2b00 cmp r3, #0
8012d58: d003 beq.n 8012d62 <tcp_timewait_input+0x9e>
/* - eighth, check the FIN bit: Remain in the TIME-WAIT state.
Restart the 2 MSL time-wait timeout.*/
pcb->tmr = tcp_ticks;
8012d5a: 4b16 ldr r3, [pc, #88] ; (8012db4 <tcp_timewait_input+0xf0>)
8012d5c: 681a ldr r2, [r3, #0]
8012d5e: 687b ldr r3, [r7, #4]
8012d60: 621a str r2, [r3, #32]
}
if ((tcplen > 0)) {
8012d62: 4b10 ldr r3, [pc, #64] ; (8012da4 <tcp_timewait_input+0xe0>)
8012d64: 881b ldrh r3, [r3, #0]
8012d66: 2b00 cmp r3, #0
8012d68: d00c beq.n 8012d84 <tcp_timewait_input+0xc0>
/* Acknowledge data, FIN or out-of-window SYN */
tcp_ack_now(pcb);
8012d6a: 687b ldr r3, [r7, #4]
8012d6c: 8b5b ldrh r3, [r3, #26]
8012d6e: f043 0302 orr.w r3, r3, #2
8012d72: b29a uxth r2, r3
8012d74: 687b ldr r3, [r7, #4]
8012d76: 835a strh r2, [r3, #26]
tcp_output(pcb);
8012d78: 6878 ldr r0, [r7, #4]
8012d7a: f002 f8a3 bl 8014ec4 <tcp_output>
}
return;
8012d7e: e001 b.n 8012d84 <tcp_timewait_input+0xc0>
return;
8012d80: bf00 nop
8012d82: e000 b.n 8012d86 <tcp_timewait_input+0xc2>
return;
8012d84: bf00 nop
}
8012d86: 3708 adds r7, #8
8012d88: 46bd mov sp, r7
8012d8a: bd80 pop {r7, pc}
8012d8c: 2000874c .word 0x2000874c
8012d90: 0801d484 .word 0x0801d484
8012d94: 0801d69c .word 0x0801d69c
8012d98: 0801d4d0 .word 0x0801d4d0
8012d9c: 20008740 .word 0x20008740
8012da0: 20008744 .word 0x20008744
8012da4: 2000874a .word 0x2000874a
8012da8: 20008730 .word 0x20008730
8012dac: 2000c118 .word 0x2000c118
8012db0: 2000c11c .word 0x2000c11c
8012db4: 2000f840 .word 0x2000f840
08012db8 <tcp_process>:
* @note the segment which arrived is saved in global variables, therefore only the pcb
* involved is passed as a parameter to this function
*/
static err_t
tcp_process(struct tcp_pcb *pcb)
{
8012db8: b590 push {r4, r7, lr}
8012dba: b08d sub sp, #52 ; 0x34
8012dbc: af04 add r7, sp, #16
8012dbe: 6078 str r0, [r7, #4]
struct tcp_seg *rseg;
u8_t acceptable = 0;
8012dc0: 2300 movs r3, #0
8012dc2: 76fb strb r3, [r7, #27]
err_t err;
err = ERR_OK;
8012dc4: 2300 movs r3, #0
8012dc6: 76bb strb r3, [r7, #26]
LWIP_ASSERT("tcp_process: invalid pcb", pcb != NULL);
8012dc8: 687b ldr r3, [r7, #4]
8012dca: 2b00 cmp r3, #0
8012dcc: d106 bne.n 8012ddc <tcp_process+0x24>
8012dce: 4ba5 ldr r3, [pc, #660] ; (8013064 <tcp_process+0x2ac>)
8012dd0: f44f 7247 mov.w r2, #796 ; 0x31c
8012dd4: 49a4 ldr r1, [pc, #656] ; (8013068 <tcp_process+0x2b0>)
8012dd6: 48a5 ldr r0, [pc, #660] ; (801306c <tcp_process+0x2b4>)
8012dd8: f008 f8f4 bl 801afc4 <iprintf>
/* Process incoming RST segments. */
if (flags & TCP_RST) {
8012ddc: 4ba4 ldr r3, [pc, #656] ; (8013070 <tcp_process+0x2b8>)
8012dde: 781b ldrb r3, [r3, #0]
8012de0: f003 0304 and.w r3, r3, #4
8012de4: 2b00 cmp r3, #0
8012de6: d04e beq.n 8012e86 <tcp_process+0xce>
/* First, determine if the reset is acceptable. */
if (pcb->state == SYN_SENT) {
8012de8: 687b ldr r3, [r7, #4]
8012dea: 7d1b ldrb r3, [r3, #20]
8012dec: 2b02 cmp r3, #2
8012dee: d108 bne.n 8012e02 <tcp_process+0x4a>
/* "In the SYN-SENT state (a RST received in response to an initial SYN),
the RST is acceptable if the ACK field acknowledges the SYN." */
if (ackno == pcb->snd_nxt) {
8012df0: 687b ldr r3, [r7, #4]
8012df2: 6d1a ldr r2, [r3, #80] ; 0x50
8012df4: 4b9f ldr r3, [pc, #636] ; (8013074 <tcp_process+0x2bc>)
8012df6: 681b ldr r3, [r3, #0]
8012df8: 429a cmp r2, r3
8012dfa: d123 bne.n 8012e44 <tcp_process+0x8c>
acceptable = 1;
8012dfc: 2301 movs r3, #1
8012dfe: 76fb strb r3, [r7, #27]
8012e00: e020 b.n 8012e44 <tcp_process+0x8c>
}
} else {
/* "In all states except SYN-SENT, all reset (RST) segments are validated
by checking their SEQ-fields." */
if (seqno == pcb->rcv_nxt) {
8012e02: 687b ldr r3, [r7, #4]
8012e04: 6a5a ldr r2, [r3, #36] ; 0x24
8012e06: 4b9c ldr r3, [pc, #624] ; (8013078 <tcp_process+0x2c0>)
8012e08: 681b ldr r3, [r3, #0]
8012e0a: 429a cmp r2, r3
8012e0c: d102 bne.n 8012e14 <tcp_process+0x5c>
acceptable = 1;
8012e0e: 2301 movs r3, #1
8012e10: 76fb strb r3, [r7, #27]
8012e12: e017 b.n 8012e44 <tcp_process+0x8c>
} else if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
8012e14: 4b98 ldr r3, [pc, #608] ; (8013078 <tcp_process+0x2c0>)
8012e16: 681a ldr r2, [r3, #0]
8012e18: 687b ldr r3, [r7, #4]
8012e1a: 6a5b ldr r3, [r3, #36] ; 0x24
8012e1c: 1ad3 subs r3, r2, r3
8012e1e: 2b00 cmp r3, #0
8012e20: db10 blt.n 8012e44 <tcp_process+0x8c>
8012e22: 4b95 ldr r3, [pc, #596] ; (8013078 <tcp_process+0x2c0>)
8012e24: 681a ldr r2, [r3, #0]
8012e26: 687b ldr r3, [r7, #4]
8012e28: 6a5b ldr r3, [r3, #36] ; 0x24
8012e2a: 6879 ldr r1, [r7, #4]
8012e2c: 8d09 ldrh r1, [r1, #40] ; 0x28
8012e2e: 440b add r3, r1
8012e30: 1ad3 subs r3, r2, r3
8012e32: 2b00 cmp r3, #0
8012e34: dc06 bgt.n 8012e44 <tcp_process+0x8c>
pcb->rcv_nxt + pcb->rcv_wnd)) {
/* If the sequence number is inside the window, we send a challenge ACK
and wait for a re-send with matching sequence number.
This follows RFC 5961 section 3.2 and addresses CVE-2004-0230
(RST spoofing attack), which is present in RFC 793 RST handling. */
tcp_ack_now(pcb);
8012e36: 687b ldr r3, [r7, #4]
8012e38: 8b5b ldrh r3, [r3, #26]
8012e3a: f043 0302 orr.w r3, r3, #2
8012e3e: b29a uxth r2, r3
8012e40: 687b ldr r3, [r7, #4]
8012e42: 835a strh r2, [r3, #26]
}
}
if (acceptable) {
8012e44: 7efb ldrb r3, [r7, #27]
8012e46: 2b00 cmp r3, #0
8012e48: d01b beq.n 8012e82 <tcp_process+0xca>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
8012e4a: 687b ldr r3, [r7, #4]
8012e4c: 7d1b ldrb r3, [r3, #20]
8012e4e: 2b00 cmp r3, #0
8012e50: d106 bne.n 8012e60 <tcp_process+0xa8>
8012e52: 4b84 ldr r3, [pc, #528] ; (8013064 <tcp_process+0x2ac>)
8012e54: f44f 724e mov.w r2, #824 ; 0x338
8012e58: 4988 ldr r1, [pc, #544] ; (801307c <tcp_process+0x2c4>)
8012e5a: 4884 ldr r0, [pc, #528] ; (801306c <tcp_process+0x2b4>)
8012e5c: f008 f8b2 bl 801afc4 <iprintf>
recv_flags |= TF_RESET;
8012e60: 4b87 ldr r3, [pc, #540] ; (8013080 <tcp_process+0x2c8>)
8012e62: 781b ldrb r3, [r3, #0]
8012e64: f043 0308 orr.w r3, r3, #8
8012e68: b2da uxtb r2, r3
8012e6a: 4b85 ldr r3, [pc, #532] ; (8013080 <tcp_process+0x2c8>)
8012e6c: 701a strb r2, [r3, #0]
tcp_clear_flags(pcb, TF_ACK_DELAY);
8012e6e: 687b ldr r3, [r7, #4]
8012e70: 8b5b ldrh r3, [r3, #26]
8012e72: f023 0301 bic.w r3, r3, #1
8012e76: b29a uxth r2, r3
8012e78: 687b ldr r3, [r7, #4]
8012e7a: 835a strh r2, [r3, #26]
return ERR_RST;
8012e7c: f06f 030d mvn.w r3, #13
8012e80: e37a b.n 8013578 <tcp_process+0x7c0>
} else {
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
seqno, pcb->rcv_nxt));
LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
seqno, pcb->rcv_nxt));
return ERR_OK;
8012e82: 2300 movs r3, #0
8012e84: e378 b.n 8013578 <tcp_process+0x7c0>
}
}
if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) {
8012e86: 4b7a ldr r3, [pc, #488] ; (8013070 <tcp_process+0x2b8>)
8012e88: 781b ldrb r3, [r3, #0]
8012e8a: f003 0302 and.w r3, r3, #2
8012e8e: 2b00 cmp r3, #0
8012e90: d010 beq.n 8012eb4 <tcp_process+0xfc>
8012e92: 687b ldr r3, [r7, #4]
8012e94: 7d1b ldrb r3, [r3, #20]
8012e96: 2b02 cmp r3, #2
8012e98: d00c beq.n 8012eb4 <tcp_process+0xfc>
8012e9a: 687b ldr r3, [r7, #4]
8012e9c: 7d1b ldrb r3, [r3, #20]
8012e9e: 2b03 cmp r3, #3
8012ea0: d008 beq.n 8012eb4 <tcp_process+0xfc>
/* Cope with new connection attempt after remote end crashed */
tcp_ack_now(pcb);
8012ea2: 687b ldr r3, [r7, #4]
8012ea4: 8b5b ldrh r3, [r3, #26]
8012ea6: f043 0302 orr.w r3, r3, #2
8012eaa: b29a uxth r2, r3
8012eac: 687b ldr r3, [r7, #4]
8012eae: 835a strh r2, [r3, #26]
return ERR_OK;
8012eb0: 2300 movs r3, #0
8012eb2: e361 b.n 8013578 <tcp_process+0x7c0>
}
if ((pcb->flags & TF_RXCLOSED) == 0) {
8012eb4: 687b ldr r3, [r7, #4]
8012eb6: 8b5b ldrh r3, [r3, #26]
8012eb8: f003 0310 and.w r3, r3, #16
8012ebc: 2b00 cmp r3, #0
8012ebe: d103 bne.n 8012ec8 <tcp_process+0x110>
/* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */
pcb->tmr = tcp_ticks;
8012ec0: 4b70 ldr r3, [pc, #448] ; (8013084 <tcp_process+0x2cc>)
8012ec2: 681a ldr r2, [r3, #0]
8012ec4: 687b ldr r3, [r7, #4]
8012ec6: 621a str r2, [r3, #32]
}
pcb->keep_cnt_sent = 0;
8012ec8: 687b ldr r3, [r7, #4]
8012eca: 2200 movs r2, #0
8012ecc: f883 209b strb.w r2, [r3, #155] ; 0x9b
pcb->persist_probe = 0;
8012ed0: 687b ldr r3, [r7, #4]
8012ed2: 2200 movs r2, #0
8012ed4: f883 209a strb.w r2, [r3, #154] ; 0x9a
tcp_parseopt(pcb);
8012ed8: 6878 ldr r0, [r7, #4]
8012eda: f001 fc2d bl 8014738 <tcp_parseopt>
/* Do different things depending on the TCP state. */
switch (pcb->state) {
8012ede: 687b ldr r3, [r7, #4]
8012ee0: 7d1b ldrb r3, [r3, #20]
8012ee2: 3b02 subs r3, #2
8012ee4: 2b07 cmp r3, #7
8012ee6: f200 8337 bhi.w 8013558 <tcp_process+0x7a0>
8012eea: a201 add r2, pc, #4 ; (adr r2, 8012ef0 <tcp_process+0x138>)
8012eec: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8012ef0: 08012f11 .word 0x08012f11
8012ef4: 08013141 .word 0x08013141
8012ef8: 080132b9 .word 0x080132b9
8012efc: 080132e3 .word 0x080132e3
8012f00: 08013407 .word 0x08013407
8012f04: 080132b9 .word 0x080132b9
8012f08: 08013493 .word 0x08013493
8012f0c: 08013523 .word 0x08013523
case SYN_SENT:
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
pcb->snd_nxt, lwip_ntohl(pcb->unacked->tcphdr->seqno)));
/* received SYN ACK with expected sequence number? */
if ((flags & TCP_ACK) && (flags & TCP_SYN)
8012f10: 4b57 ldr r3, [pc, #348] ; (8013070 <tcp_process+0x2b8>)
8012f12: 781b ldrb r3, [r3, #0]
8012f14: f003 0310 and.w r3, r3, #16
8012f18: 2b00 cmp r3, #0
8012f1a: f000 80e4 beq.w 80130e6 <tcp_process+0x32e>
8012f1e: 4b54 ldr r3, [pc, #336] ; (8013070 <tcp_process+0x2b8>)
8012f20: 781b ldrb r3, [r3, #0]
8012f22: f003 0302 and.w r3, r3, #2
8012f26: 2b00 cmp r3, #0
8012f28: f000 80dd beq.w 80130e6 <tcp_process+0x32e>
&& (ackno == pcb->lastack + 1)) {
8012f2c: 687b ldr r3, [r7, #4]
8012f2e: 6c5b ldr r3, [r3, #68] ; 0x44
8012f30: 1c5a adds r2, r3, #1
8012f32: 4b50 ldr r3, [pc, #320] ; (8013074 <tcp_process+0x2bc>)
8012f34: 681b ldr r3, [r3, #0]
8012f36: 429a cmp r2, r3
8012f38: f040 80d5 bne.w 80130e6 <tcp_process+0x32e>
pcb->rcv_nxt = seqno + 1;
8012f3c: 4b4e ldr r3, [pc, #312] ; (8013078 <tcp_process+0x2c0>)
8012f3e: 681b ldr r3, [r3, #0]
8012f40: 1c5a adds r2, r3, #1
8012f42: 687b ldr r3, [r7, #4]
8012f44: 625a str r2, [r3, #36] ; 0x24
pcb->rcv_ann_right_edge = pcb->rcv_nxt;
8012f46: 687b ldr r3, [r7, #4]
8012f48: 6a5a ldr r2, [r3, #36] ; 0x24
8012f4a: 687b ldr r3, [r7, #4]
8012f4c: 62da str r2, [r3, #44] ; 0x2c
pcb->lastack = ackno;
8012f4e: 4b49 ldr r3, [pc, #292] ; (8013074 <tcp_process+0x2bc>)
8012f50: 681a ldr r2, [r3, #0]
8012f52: 687b ldr r3, [r7, #4]
8012f54: 645a str r2, [r3, #68] ; 0x44
pcb->snd_wnd = tcphdr->wnd;
8012f56: 4b4c ldr r3, [pc, #304] ; (8013088 <tcp_process+0x2d0>)
8012f58: 681b ldr r3, [r3, #0]
8012f5a: 89db ldrh r3, [r3, #14]
8012f5c: b29a uxth r2, r3
8012f5e: 687b ldr r3, [r7, #4]
8012f60: f8a3 2060 strh.w r2, [r3, #96] ; 0x60
pcb->snd_wnd_max = pcb->snd_wnd;
8012f64: 687b ldr r3, [r7, #4]
8012f66: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8012f6a: 687b ldr r3, [r7, #4]
8012f6c: f8a3 2062 strh.w r2, [r3, #98] ; 0x62
pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
8012f70: 4b41 ldr r3, [pc, #260] ; (8013078 <tcp_process+0x2c0>)
8012f72: 681b ldr r3, [r3, #0]
8012f74: 1e5a subs r2, r3, #1
8012f76: 687b ldr r3, [r7, #4]
8012f78: 655a str r2, [r3, #84] ; 0x54
pcb->state = ESTABLISHED;
8012f7a: 687b ldr r3, [r7, #4]
8012f7c: 2204 movs r2, #4
8012f7e: 751a strb r2, [r3, #20]
#if TCP_CALCULATE_EFF_SEND_MSS
pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip);
8012f80: 687b ldr r3, [r7, #4]
8012f82: 8e5c ldrh r4, [r3, #50] ; 0x32
8012f84: 687b ldr r3, [r7, #4]
8012f86: 3304 adds r3, #4
8012f88: 4618 mov r0, r3
8012f8a: f006 fcb9 bl 8019900 <ip4_route>
8012f8e: 4601 mov r1, r0
8012f90: 687b ldr r3, [r7, #4]
8012f92: 3304 adds r3, #4
8012f94: 461a mov r2, r3
8012f96: 4620 mov r0, r4
8012f98: f7ff f88e bl 80120b8 <tcp_eff_send_mss_netif>
8012f9c: 4603 mov r3, r0
8012f9e: 461a mov r2, r3
8012fa0: 687b ldr r3, [r7, #4]
8012fa2: 865a strh r2, [r3, #50] ; 0x32
#endif /* TCP_CALCULATE_EFF_SEND_MSS */
pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
8012fa4: 687b ldr r3, [r7, #4]
8012fa6: 8e5b ldrh r3, [r3, #50] ; 0x32
8012fa8: 009a lsls r2, r3, #2
8012faa: 687b ldr r3, [r7, #4]
8012fac: 8e5b ldrh r3, [r3, #50] ; 0x32
8012fae: 005b lsls r3, r3, #1
8012fb0: f241 111c movw r1, #4380 ; 0x111c
8012fb4: 428b cmp r3, r1
8012fb6: bf38 it cc
8012fb8: 460b movcc r3, r1
8012fba: 429a cmp r2, r3
8012fbc: d204 bcs.n 8012fc8 <tcp_process+0x210>
8012fbe: 687b ldr r3, [r7, #4]
8012fc0: 8e5b ldrh r3, [r3, #50] ; 0x32
8012fc2: 009b lsls r3, r3, #2
8012fc4: b29b uxth r3, r3
8012fc6: e00d b.n 8012fe4 <tcp_process+0x22c>
8012fc8: 687b ldr r3, [r7, #4]
8012fca: 8e5b ldrh r3, [r3, #50] ; 0x32
8012fcc: 005b lsls r3, r3, #1
8012fce: f241 121c movw r2, #4380 ; 0x111c
8012fd2: 4293 cmp r3, r2
8012fd4: d904 bls.n 8012fe0 <tcp_process+0x228>
8012fd6: 687b ldr r3, [r7, #4]
8012fd8: 8e5b ldrh r3, [r3, #50] ; 0x32
8012fda: 005b lsls r3, r3, #1
8012fdc: b29b uxth r3, r3
8012fde: e001 b.n 8012fe4 <tcp_process+0x22c>
8012fe0: f241 131c movw r3, #4380 ; 0x111c
8012fe4: 687a ldr r2, [r7, #4]
8012fe6: f8a2 3048 strh.w r3, [r2, #72] ; 0x48
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SENT): cwnd %"TCPWNDSIZE_F
" ssthresh %"TCPWNDSIZE_F"\n",
pcb->cwnd, pcb->ssthresh));
LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0));
8012fea: 687b ldr r3, [r7, #4]
8012fec: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8012ff0: 2b00 cmp r3, #0
8012ff2: d106 bne.n 8013002 <tcp_process+0x24a>
8012ff4: 4b1b ldr r3, [pc, #108] ; (8013064 <tcp_process+0x2ac>)
8012ff6: f44f 725b mov.w r2, #876 ; 0x36c
8012ffa: 4924 ldr r1, [pc, #144] ; (801308c <tcp_process+0x2d4>)
8012ffc: 481b ldr r0, [pc, #108] ; (801306c <tcp_process+0x2b4>)
8012ffe: f007 ffe1 bl 801afc4 <iprintf>
--pcb->snd_queuelen;
8013002: 687b ldr r3, [r7, #4]
8013004: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8013008: 3b01 subs r3, #1
801300a: b29a uxth r2, r3
801300c: 687b ldr r3, [r7, #4]
801300e: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen));
rseg = pcb->unacked;
8013012: 687b ldr r3, [r7, #4]
8013014: 6f1b ldr r3, [r3, #112] ; 0x70
8013016: 61fb str r3, [r7, #28]
if (rseg == NULL) {
8013018: 69fb ldr r3, [r7, #28]
801301a: 2b00 cmp r3, #0
801301c: d111 bne.n 8013042 <tcp_process+0x28a>
/* might happen if tcp_output fails in tcp_rexmit_rto()
in which case the segment is on the unsent list */
rseg = pcb->unsent;
801301e: 687b ldr r3, [r7, #4]
8013020: 6edb ldr r3, [r3, #108] ; 0x6c
8013022: 61fb str r3, [r7, #28]
LWIP_ASSERT("no segment to free", rseg != NULL);
8013024: 69fb ldr r3, [r7, #28]
8013026: 2b00 cmp r3, #0
8013028: d106 bne.n 8013038 <tcp_process+0x280>
801302a: 4b0e ldr r3, [pc, #56] ; (8013064 <tcp_process+0x2ac>)
801302c: f44f 725d mov.w r2, #884 ; 0x374
8013030: 4917 ldr r1, [pc, #92] ; (8013090 <tcp_process+0x2d8>)
8013032: 480e ldr r0, [pc, #56] ; (801306c <tcp_process+0x2b4>)
8013034: f007 ffc6 bl 801afc4 <iprintf>
pcb->unsent = rseg->next;
8013038: 69fb ldr r3, [r7, #28]
801303a: 681a ldr r2, [r3, #0]
801303c: 687b ldr r3, [r7, #4]
801303e: 66da str r2, [r3, #108] ; 0x6c
8013040: e003 b.n 801304a <tcp_process+0x292>
} else {
pcb->unacked = rseg->next;
8013042: 69fb ldr r3, [r7, #28]
8013044: 681a ldr r2, [r3, #0]
8013046: 687b ldr r3, [r7, #4]
8013048: 671a str r2, [r3, #112] ; 0x70
}
tcp_seg_free(rseg);
801304a: 69f8 ldr r0, [r7, #28]
801304c: f7fe fd3d bl 8011aca <tcp_seg_free>
/* If there's nothing left to acknowledge, stop the retransmit
timer, otherwise reset it to start again */
if (pcb->unacked == NULL) {
8013050: 687b ldr r3, [r7, #4]
8013052: 6f1b ldr r3, [r3, #112] ; 0x70
8013054: 2b00 cmp r3, #0
8013056: d11d bne.n 8013094 <tcp_process+0x2dc>
pcb->rtime = -1;
8013058: 687b ldr r3, [r7, #4]
801305a: f64f 72ff movw r2, #65535 ; 0xffff
801305e: 861a strh r2, [r3, #48] ; 0x30
8013060: e01f b.n 80130a2 <tcp_process+0x2ea>
8013062: bf00 nop
8013064: 0801d484 .word 0x0801d484
8013068: 0801d6bc .word 0x0801d6bc
801306c: 0801d4d0 .word 0x0801d4d0
8013070: 2000874c .word 0x2000874c
8013074: 20008744 .word 0x20008744
8013078: 20008740 .word 0x20008740
801307c: 0801d6d8 .word 0x0801d6d8
8013080: 2000874d .word 0x2000874d
8013084: 2000f840 .word 0x2000f840
8013088: 20008730 .word 0x20008730
801308c: 0801d6f8 .word 0x0801d6f8
8013090: 0801d710 .word 0x0801d710
} else {
pcb->rtime = 0;
8013094: 687b ldr r3, [r7, #4]
8013096: 2200 movs r2, #0
8013098: 861a strh r2, [r3, #48] ; 0x30
pcb->nrtx = 0;
801309a: 687b ldr r3, [r7, #4]
801309c: 2200 movs r2, #0
801309e: f883 2042 strb.w r2, [r3, #66] ; 0x42
}
/* Call the user specified function to call when successfully
* connected. */
TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
80130a2: 687b ldr r3, [r7, #4]
80130a4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80130a8: 2b00 cmp r3, #0
80130aa: d00a beq.n 80130c2 <tcp_process+0x30a>
80130ac: 687b ldr r3, [r7, #4]
80130ae: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80130b2: 687a ldr r2, [r7, #4]
80130b4: 6910 ldr r0, [r2, #16]
80130b6: 2200 movs r2, #0
80130b8: 6879 ldr r1, [r7, #4]
80130ba: 4798 blx r3
80130bc: 4603 mov r3, r0
80130be: 76bb strb r3, [r7, #26]
80130c0: e001 b.n 80130c6 <tcp_process+0x30e>
80130c2: 2300 movs r3, #0
80130c4: 76bb strb r3, [r7, #26]
if (err == ERR_ABRT) {
80130c6: f997 301a ldrsb.w r3, [r7, #26]
80130ca: f113 0f0d cmn.w r3, #13
80130ce: d102 bne.n 80130d6 <tcp_process+0x31e>
return ERR_ABRT;
80130d0: f06f 030c mvn.w r3, #12
80130d4: e250 b.n 8013578 <tcp_process+0x7c0>
}
tcp_ack_now(pcb);
80130d6: 687b ldr r3, [r7, #4]
80130d8: 8b5b ldrh r3, [r3, #26]
80130da: f043 0302 orr.w r3, r3, #2
80130de: b29a uxth r2, r3
80130e0: 687b ldr r3, [r7, #4]
80130e2: 835a strh r2, [r3, #26]
if (pcb->nrtx < TCP_SYNMAXRTX) {
pcb->rtime = 0;
tcp_rexmit_rto(pcb);
}
}
break;
80130e4: e23a b.n 801355c <tcp_process+0x7a4>
else if (flags & TCP_ACK) {
80130e6: 4b9d ldr r3, [pc, #628] ; (801335c <tcp_process+0x5a4>)
80130e8: 781b ldrb r3, [r3, #0]
80130ea: f003 0310 and.w r3, r3, #16
80130ee: 2b00 cmp r3, #0
80130f0: f000 8234 beq.w 801355c <tcp_process+0x7a4>
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
80130f4: 4b9a ldr r3, [pc, #616] ; (8013360 <tcp_process+0x5a8>)
80130f6: 6819 ldr r1, [r3, #0]
80130f8: 4b9a ldr r3, [pc, #616] ; (8013364 <tcp_process+0x5ac>)
80130fa: 881b ldrh r3, [r3, #0]
80130fc: 461a mov r2, r3
80130fe: 4b9a ldr r3, [pc, #616] ; (8013368 <tcp_process+0x5b0>)
8013100: 681b ldr r3, [r3, #0]
8013102: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8013104: 4b99 ldr r3, [pc, #612] ; (801336c <tcp_process+0x5b4>)
8013106: 681b ldr r3, [r3, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8013108: 885b ldrh r3, [r3, #2]
801310a: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
801310c: 4a97 ldr r2, [pc, #604] ; (801336c <tcp_process+0x5b4>)
801310e: 6812 ldr r2, [r2, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8013110: 8812 ldrh r2, [r2, #0]
8013112: b292 uxth r2, r2
8013114: 9202 str r2, [sp, #8]
8013116: 9301 str r3, [sp, #4]
8013118: 4b95 ldr r3, [pc, #596] ; (8013370 <tcp_process+0x5b8>)
801311a: 9300 str r3, [sp, #0]
801311c: 4b95 ldr r3, [pc, #596] ; (8013374 <tcp_process+0x5bc>)
801311e: 4602 mov r2, r0
8013120: 6878 ldr r0, [r7, #4]
8013122: f002 fc83 bl 8015a2c <tcp_rst>
if (pcb->nrtx < TCP_SYNMAXRTX) {
8013126: 687b ldr r3, [r7, #4]
8013128: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
801312c: 2b05 cmp r3, #5
801312e: f200 8215 bhi.w 801355c <tcp_process+0x7a4>
pcb->rtime = 0;
8013132: 687b ldr r3, [r7, #4]
8013134: 2200 movs r2, #0
8013136: 861a strh r2, [r3, #48] ; 0x30
tcp_rexmit_rto(pcb);
8013138: 6878 ldr r0, [r7, #4]
801313a: f002 fa4d bl 80155d8 <tcp_rexmit_rto>
break;
801313e: e20d b.n 801355c <tcp_process+0x7a4>
case SYN_RCVD:
if (flags & TCP_ACK) {
8013140: 4b86 ldr r3, [pc, #536] ; (801335c <tcp_process+0x5a4>)
8013142: 781b ldrb r3, [r3, #0]
8013144: f003 0310 and.w r3, r3, #16
8013148: 2b00 cmp r3, #0
801314a: f000 80a1 beq.w 8013290 <tcp_process+0x4d8>
/* expected ACK number? */
if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
801314e: 4b84 ldr r3, [pc, #528] ; (8013360 <tcp_process+0x5a8>)
8013150: 681a ldr r2, [r3, #0]
8013152: 687b ldr r3, [r7, #4]
8013154: 6c5b ldr r3, [r3, #68] ; 0x44
8013156: 1ad3 subs r3, r2, r3
8013158: 3b01 subs r3, #1
801315a: 2b00 cmp r3, #0
801315c: db7e blt.n 801325c <tcp_process+0x4a4>
801315e: 4b80 ldr r3, [pc, #512] ; (8013360 <tcp_process+0x5a8>)
8013160: 681a ldr r2, [r3, #0]
8013162: 687b ldr r3, [r7, #4]
8013164: 6d1b ldr r3, [r3, #80] ; 0x50
8013166: 1ad3 subs r3, r2, r3
8013168: 2b00 cmp r3, #0
801316a: dc77 bgt.n 801325c <tcp_process+0x4a4>
pcb->state = ESTABLISHED;
801316c: 687b ldr r3, [r7, #4]
801316e: 2204 movs r2, #4
8013170: 751a strb r2, [r3, #20]
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
if (pcb->listener == NULL) {
8013172: 687b ldr r3, [r7, #4]
8013174: 6fdb ldr r3, [r3, #124] ; 0x7c
8013176: 2b00 cmp r3, #0
8013178: d102 bne.n 8013180 <tcp_process+0x3c8>
/* listen pcb might be closed by now */
err = ERR_VAL;
801317a: 23fa movs r3, #250 ; 0xfa
801317c: 76bb strb r3, [r7, #26]
801317e: e01d b.n 80131bc <tcp_process+0x404>
} else
#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */
{
#if LWIP_CALLBACK_API
LWIP_ASSERT("pcb->listener->accept != NULL", pcb->listener->accept != NULL);
8013180: 687b ldr r3, [r7, #4]
8013182: 6fdb ldr r3, [r3, #124] ; 0x7c
8013184: 699b ldr r3, [r3, #24]
8013186: 2b00 cmp r3, #0
8013188: d106 bne.n 8013198 <tcp_process+0x3e0>
801318a: 4b7b ldr r3, [pc, #492] ; (8013378 <tcp_process+0x5c0>)
801318c: f44f 726a mov.w r2, #936 ; 0x3a8
8013190: 497a ldr r1, [pc, #488] ; (801337c <tcp_process+0x5c4>)
8013192: 487b ldr r0, [pc, #492] ; (8013380 <tcp_process+0x5c8>)
8013194: f007 ff16 bl 801afc4 <iprintf>
#endif
tcp_backlog_accepted(pcb);
/* Call the accept function. */
TCP_EVENT_ACCEPT(pcb->listener, pcb, pcb->callback_arg, ERR_OK, err);
8013198: 687b ldr r3, [r7, #4]
801319a: 6fdb ldr r3, [r3, #124] ; 0x7c
801319c: 699b ldr r3, [r3, #24]
801319e: 2b00 cmp r3, #0
80131a0: d00a beq.n 80131b8 <tcp_process+0x400>
80131a2: 687b ldr r3, [r7, #4]
80131a4: 6fdb ldr r3, [r3, #124] ; 0x7c
80131a6: 699b ldr r3, [r3, #24]
80131a8: 687a ldr r2, [r7, #4]
80131aa: 6910 ldr r0, [r2, #16]
80131ac: 2200 movs r2, #0
80131ae: 6879 ldr r1, [r7, #4]
80131b0: 4798 blx r3
80131b2: 4603 mov r3, r0
80131b4: 76bb strb r3, [r7, #26]
80131b6: e001 b.n 80131bc <tcp_process+0x404>
80131b8: 23f0 movs r3, #240 ; 0xf0
80131ba: 76bb strb r3, [r7, #26]
}
if (err != ERR_OK) {
80131bc: f997 301a ldrsb.w r3, [r7, #26]
80131c0: 2b00 cmp r3, #0
80131c2: d00a beq.n 80131da <tcp_process+0x422>
/* If the accept function returns with an error, we abort
* the connection. */
/* Already aborted? */
if (err != ERR_ABRT) {
80131c4: f997 301a ldrsb.w r3, [r7, #26]
80131c8: f113 0f0d cmn.w r3, #13
80131cc: d002 beq.n 80131d4 <tcp_process+0x41c>
tcp_abort(pcb);
80131ce: 6878 ldr r0, [r7, #4]
80131d0: f7fd ff90 bl 80110f4 <tcp_abort>
}
return ERR_ABRT;
80131d4: f06f 030c mvn.w r3, #12
80131d8: e1ce b.n 8013578 <tcp_process+0x7c0>
}
/* If there was any data contained within this ACK,
* we'd better pass it on to the application as well. */
tcp_receive(pcb);
80131da: 6878 ldr r0, [r7, #4]
80131dc: f000 fae0 bl 80137a0 <tcp_receive>
/* Prevent ACK for SYN to generate a sent event */
if (recv_acked != 0) {
80131e0: 4b68 ldr r3, [pc, #416] ; (8013384 <tcp_process+0x5cc>)
80131e2: 881b ldrh r3, [r3, #0]
80131e4: 2b00 cmp r3, #0
80131e6: d005 beq.n 80131f4 <tcp_process+0x43c>
recv_acked--;
80131e8: 4b66 ldr r3, [pc, #408] ; (8013384 <tcp_process+0x5cc>)
80131ea: 881b ldrh r3, [r3, #0]
80131ec: 3b01 subs r3, #1
80131ee: b29a uxth r2, r3
80131f0: 4b64 ldr r3, [pc, #400] ; (8013384 <tcp_process+0x5cc>)
80131f2: 801a strh r2, [r3, #0]
}
pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
80131f4: 687b ldr r3, [r7, #4]
80131f6: 8e5b ldrh r3, [r3, #50] ; 0x32
80131f8: 009a lsls r2, r3, #2
80131fa: 687b ldr r3, [r7, #4]
80131fc: 8e5b ldrh r3, [r3, #50] ; 0x32
80131fe: 005b lsls r3, r3, #1
8013200: f241 111c movw r1, #4380 ; 0x111c
8013204: 428b cmp r3, r1
8013206: bf38 it cc
8013208: 460b movcc r3, r1
801320a: 429a cmp r2, r3
801320c: d204 bcs.n 8013218 <tcp_process+0x460>
801320e: 687b ldr r3, [r7, #4]
8013210: 8e5b ldrh r3, [r3, #50] ; 0x32
8013212: 009b lsls r3, r3, #2
8013214: b29b uxth r3, r3
8013216: e00d b.n 8013234 <tcp_process+0x47c>
8013218: 687b ldr r3, [r7, #4]
801321a: 8e5b ldrh r3, [r3, #50] ; 0x32
801321c: 005b lsls r3, r3, #1
801321e: f241 121c movw r2, #4380 ; 0x111c
8013222: 4293 cmp r3, r2
8013224: d904 bls.n 8013230 <tcp_process+0x478>
8013226: 687b ldr r3, [r7, #4]
8013228: 8e5b ldrh r3, [r3, #50] ; 0x32
801322a: 005b lsls r3, r3, #1
801322c: b29b uxth r3, r3
801322e: e001 b.n 8013234 <tcp_process+0x47c>
8013230: f241 131c movw r3, #4380 ; 0x111c
8013234: 687a ldr r2, [r7, #4]
8013236: f8a2 3048 strh.w r3, [r2, #72] ; 0x48
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SYN_RCVD): cwnd %"TCPWNDSIZE_F
" ssthresh %"TCPWNDSIZE_F"\n",
pcb->cwnd, pcb->ssthresh));
if (recv_flags & TF_GOT_FIN) {
801323a: 4b53 ldr r3, [pc, #332] ; (8013388 <tcp_process+0x5d0>)
801323c: 781b ldrb r3, [r3, #0]
801323e: f003 0320 and.w r3, r3, #32
8013242: 2b00 cmp r3, #0
8013244: d037 beq.n 80132b6 <tcp_process+0x4fe>
tcp_ack_now(pcb);
8013246: 687b ldr r3, [r7, #4]
8013248: 8b5b ldrh r3, [r3, #26]
801324a: f043 0302 orr.w r3, r3, #2
801324e: b29a uxth r2, r3
8013250: 687b ldr r3, [r7, #4]
8013252: 835a strh r2, [r3, #26]
pcb->state = CLOSE_WAIT;
8013254: 687b ldr r3, [r7, #4]
8013256: 2207 movs r2, #7
8013258: 751a strb r2, [r3, #20]
if (recv_flags & TF_GOT_FIN) {
801325a: e02c b.n 80132b6 <tcp_process+0x4fe>
}
} else {
/* incorrect ACK number, send RST */
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
801325c: 4b40 ldr r3, [pc, #256] ; (8013360 <tcp_process+0x5a8>)
801325e: 6819 ldr r1, [r3, #0]
8013260: 4b40 ldr r3, [pc, #256] ; (8013364 <tcp_process+0x5ac>)
8013262: 881b ldrh r3, [r3, #0]
8013264: 461a mov r2, r3
8013266: 4b40 ldr r3, [pc, #256] ; (8013368 <tcp_process+0x5b0>)
8013268: 681b ldr r3, [r3, #0]
801326a: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
801326c: 4b3f ldr r3, [pc, #252] ; (801336c <tcp_process+0x5b4>)
801326e: 681b ldr r3, [r3, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8013270: 885b ldrh r3, [r3, #2]
8013272: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8013274: 4a3d ldr r2, [pc, #244] ; (801336c <tcp_process+0x5b4>)
8013276: 6812 ldr r2, [r2, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8013278: 8812 ldrh r2, [r2, #0]
801327a: b292 uxth r2, r2
801327c: 9202 str r2, [sp, #8]
801327e: 9301 str r3, [sp, #4]
8013280: 4b3b ldr r3, [pc, #236] ; (8013370 <tcp_process+0x5b8>)
8013282: 9300 str r3, [sp, #0]
8013284: 4b3b ldr r3, [pc, #236] ; (8013374 <tcp_process+0x5bc>)
8013286: 4602 mov r2, r0
8013288: 6878 ldr r0, [r7, #4]
801328a: f002 fbcf bl 8015a2c <tcp_rst>
}
} else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
/* Looks like another copy of the SYN - retransmit our SYN-ACK */
tcp_rexmit(pcb);
}
break;
801328e: e167 b.n 8013560 <tcp_process+0x7a8>
} else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
8013290: 4b32 ldr r3, [pc, #200] ; (801335c <tcp_process+0x5a4>)
8013292: 781b ldrb r3, [r3, #0]
8013294: f003 0302 and.w r3, r3, #2
8013298: 2b00 cmp r3, #0
801329a: f000 8161 beq.w 8013560 <tcp_process+0x7a8>
801329e: 687b ldr r3, [r7, #4]
80132a0: 6a5b ldr r3, [r3, #36] ; 0x24
80132a2: 1e5a subs r2, r3, #1
80132a4: 4b30 ldr r3, [pc, #192] ; (8013368 <tcp_process+0x5b0>)
80132a6: 681b ldr r3, [r3, #0]
80132a8: 429a cmp r2, r3
80132aa: f040 8159 bne.w 8013560 <tcp_process+0x7a8>
tcp_rexmit(pcb);
80132ae: 6878 ldr r0, [r7, #4]
80132b0: f002 f9b4 bl 801561c <tcp_rexmit>
break;
80132b4: e154 b.n 8013560 <tcp_process+0x7a8>
80132b6: e153 b.n 8013560 <tcp_process+0x7a8>
case CLOSE_WAIT:
/* FALLTHROUGH */
case ESTABLISHED:
tcp_receive(pcb);
80132b8: 6878 ldr r0, [r7, #4]
80132ba: f000 fa71 bl 80137a0 <tcp_receive>
if (recv_flags & TF_GOT_FIN) { /* passive close */
80132be: 4b32 ldr r3, [pc, #200] ; (8013388 <tcp_process+0x5d0>)
80132c0: 781b ldrb r3, [r3, #0]
80132c2: f003 0320 and.w r3, r3, #32
80132c6: 2b00 cmp r3, #0
80132c8: f000 814c beq.w 8013564 <tcp_process+0x7ac>
tcp_ack_now(pcb);
80132cc: 687b ldr r3, [r7, #4]
80132ce: 8b5b ldrh r3, [r3, #26]
80132d0: f043 0302 orr.w r3, r3, #2
80132d4: b29a uxth r2, r3
80132d6: 687b ldr r3, [r7, #4]
80132d8: 835a strh r2, [r3, #26]
pcb->state = CLOSE_WAIT;
80132da: 687b ldr r3, [r7, #4]
80132dc: 2207 movs r2, #7
80132de: 751a strb r2, [r3, #20]
}
break;
80132e0: e140 b.n 8013564 <tcp_process+0x7ac>
case FIN_WAIT_1:
tcp_receive(pcb);
80132e2: 6878 ldr r0, [r7, #4]
80132e4: f000 fa5c bl 80137a0 <tcp_receive>
if (recv_flags & TF_GOT_FIN) {
80132e8: 4b27 ldr r3, [pc, #156] ; (8013388 <tcp_process+0x5d0>)
80132ea: 781b ldrb r3, [r3, #0]
80132ec: f003 0320 and.w r3, r3, #32
80132f0: 2b00 cmp r3, #0
80132f2: d071 beq.n 80133d8 <tcp_process+0x620>
if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
80132f4: 4b19 ldr r3, [pc, #100] ; (801335c <tcp_process+0x5a4>)
80132f6: 781b ldrb r3, [r3, #0]
80132f8: f003 0310 and.w r3, r3, #16
80132fc: 2b00 cmp r3, #0
80132fe: d060 beq.n 80133c2 <tcp_process+0x60a>
8013300: 687b ldr r3, [r7, #4]
8013302: 6d1a ldr r2, [r3, #80] ; 0x50
8013304: 4b16 ldr r3, [pc, #88] ; (8013360 <tcp_process+0x5a8>)
8013306: 681b ldr r3, [r3, #0]
8013308: 429a cmp r2, r3
801330a: d15a bne.n 80133c2 <tcp_process+0x60a>
pcb->unsent == NULL) {
801330c: 687b ldr r3, [r7, #4]
801330e: 6edb ldr r3, [r3, #108] ; 0x6c
if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
8013310: 2b00 cmp r3, #0
8013312: d156 bne.n 80133c2 <tcp_process+0x60a>
LWIP_DEBUGF(TCP_DEBUG,
("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
tcp_ack_now(pcb);
8013314: 687b ldr r3, [r7, #4]
8013316: 8b5b ldrh r3, [r3, #26]
8013318: f043 0302 orr.w r3, r3, #2
801331c: b29a uxth r2, r3
801331e: 687b ldr r3, [r7, #4]
8013320: 835a strh r2, [r3, #26]
tcp_pcb_purge(pcb);
8013322: 6878 ldr r0, [r7, #4]
8013324: f7fe fdbe bl 8011ea4 <tcp_pcb_purge>
TCP_RMV_ACTIVE(pcb);
8013328: 4b18 ldr r3, [pc, #96] ; (801338c <tcp_process+0x5d4>)
801332a: 681b ldr r3, [r3, #0]
801332c: 687a ldr r2, [r7, #4]
801332e: 429a cmp r2, r3
8013330: d105 bne.n 801333e <tcp_process+0x586>
8013332: 4b16 ldr r3, [pc, #88] ; (801338c <tcp_process+0x5d4>)
8013334: 681b ldr r3, [r3, #0]
8013336: 68db ldr r3, [r3, #12]
8013338: 4a14 ldr r2, [pc, #80] ; (801338c <tcp_process+0x5d4>)
801333a: 6013 str r3, [r2, #0]
801333c: e02e b.n 801339c <tcp_process+0x5e4>
801333e: 4b13 ldr r3, [pc, #76] ; (801338c <tcp_process+0x5d4>)
8013340: 681b ldr r3, [r3, #0]
8013342: 617b str r3, [r7, #20]
8013344: e027 b.n 8013396 <tcp_process+0x5de>
8013346: 697b ldr r3, [r7, #20]
8013348: 68db ldr r3, [r3, #12]
801334a: 687a ldr r2, [r7, #4]
801334c: 429a cmp r2, r3
801334e: d11f bne.n 8013390 <tcp_process+0x5d8>
8013350: 687b ldr r3, [r7, #4]
8013352: 68da ldr r2, [r3, #12]
8013354: 697b ldr r3, [r7, #20]
8013356: 60da str r2, [r3, #12]
8013358: e020 b.n 801339c <tcp_process+0x5e4>
801335a: bf00 nop
801335c: 2000874c .word 0x2000874c
8013360: 20008744 .word 0x20008744
8013364: 2000874a .word 0x2000874a
8013368: 20008740 .word 0x20008740
801336c: 20008730 .word 0x20008730
8013370: 2000c118 .word 0x2000c118
8013374: 2000c11c .word 0x2000c11c
8013378: 0801d484 .word 0x0801d484
801337c: 0801d724 .word 0x0801d724
8013380: 0801d4d0 .word 0x0801d4d0
8013384: 20008748 .word 0x20008748
8013388: 2000874d .word 0x2000874d
801338c: 2000f83c .word 0x2000f83c
8013390: 697b ldr r3, [r7, #20]
8013392: 68db ldr r3, [r3, #12]
8013394: 617b str r3, [r7, #20]
8013396: 697b ldr r3, [r7, #20]
8013398: 2b00 cmp r3, #0
801339a: d1d4 bne.n 8013346 <tcp_process+0x58e>
801339c: 687b ldr r3, [r7, #4]
801339e: 2200 movs r2, #0
80133a0: 60da str r2, [r3, #12]
80133a2: 4b77 ldr r3, [pc, #476] ; (8013580 <tcp_process+0x7c8>)
80133a4: 2201 movs r2, #1
80133a6: 701a strb r2, [r3, #0]
pcb->state = TIME_WAIT;
80133a8: 687b ldr r3, [r7, #4]
80133aa: 220a movs r2, #10
80133ac: 751a strb r2, [r3, #20]
TCP_REG(&tcp_tw_pcbs, pcb);
80133ae: 4b75 ldr r3, [pc, #468] ; (8013584 <tcp_process+0x7cc>)
80133b0: 681a ldr r2, [r3, #0]
80133b2: 687b ldr r3, [r7, #4]
80133b4: 60da str r2, [r3, #12]
80133b6: 4a73 ldr r2, [pc, #460] ; (8013584 <tcp_process+0x7cc>)
80133b8: 687b ldr r3, [r7, #4]
80133ba: 6013 str r3, [r2, #0]
80133bc: f002 fcf8 bl 8015db0 <tcp_timer_needed>
}
} else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
pcb->unsent == NULL) {
pcb->state = FIN_WAIT_2;
}
break;
80133c0: e0d2 b.n 8013568 <tcp_process+0x7b0>
tcp_ack_now(pcb);
80133c2: 687b ldr r3, [r7, #4]
80133c4: 8b5b ldrh r3, [r3, #26]
80133c6: f043 0302 orr.w r3, r3, #2
80133ca: b29a uxth r2, r3
80133cc: 687b ldr r3, [r7, #4]
80133ce: 835a strh r2, [r3, #26]
pcb->state = CLOSING;
80133d0: 687b ldr r3, [r7, #4]
80133d2: 2208 movs r2, #8
80133d4: 751a strb r2, [r3, #20]
break;
80133d6: e0c7 b.n 8013568 <tcp_process+0x7b0>
} else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
80133d8: 4b6b ldr r3, [pc, #428] ; (8013588 <tcp_process+0x7d0>)
80133da: 781b ldrb r3, [r3, #0]
80133dc: f003 0310 and.w r3, r3, #16
80133e0: 2b00 cmp r3, #0
80133e2: f000 80c1 beq.w 8013568 <tcp_process+0x7b0>
80133e6: 687b ldr r3, [r7, #4]
80133e8: 6d1a ldr r2, [r3, #80] ; 0x50
80133ea: 4b68 ldr r3, [pc, #416] ; (801358c <tcp_process+0x7d4>)
80133ec: 681b ldr r3, [r3, #0]
80133ee: 429a cmp r2, r3
80133f0: f040 80ba bne.w 8013568 <tcp_process+0x7b0>
pcb->unsent == NULL) {
80133f4: 687b ldr r3, [r7, #4]
80133f6: 6edb ldr r3, [r3, #108] ; 0x6c
} else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
80133f8: 2b00 cmp r3, #0
80133fa: f040 80b5 bne.w 8013568 <tcp_process+0x7b0>
pcb->state = FIN_WAIT_2;
80133fe: 687b ldr r3, [r7, #4]
8013400: 2206 movs r2, #6
8013402: 751a strb r2, [r3, #20]
break;
8013404: e0b0 b.n 8013568 <tcp_process+0x7b0>
case FIN_WAIT_2:
tcp_receive(pcb);
8013406: 6878 ldr r0, [r7, #4]
8013408: f000 f9ca bl 80137a0 <tcp_receive>
if (recv_flags & TF_GOT_FIN) {
801340c: 4b60 ldr r3, [pc, #384] ; (8013590 <tcp_process+0x7d8>)
801340e: 781b ldrb r3, [r3, #0]
8013410: f003 0320 and.w r3, r3, #32
8013414: 2b00 cmp r3, #0
8013416: f000 80a9 beq.w 801356c <tcp_process+0x7b4>
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
tcp_ack_now(pcb);
801341a: 687b ldr r3, [r7, #4]
801341c: 8b5b ldrh r3, [r3, #26]
801341e: f043 0302 orr.w r3, r3, #2
8013422: b29a uxth r2, r3
8013424: 687b ldr r3, [r7, #4]
8013426: 835a strh r2, [r3, #26]
tcp_pcb_purge(pcb);
8013428: 6878 ldr r0, [r7, #4]
801342a: f7fe fd3b bl 8011ea4 <tcp_pcb_purge>
TCP_RMV_ACTIVE(pcb);
801342e: 4b59 ldr r3, [pc, #356] ; (8013594 <tcp_process+0x7dc>)
8013430: 681b ldr r3, [r3, #0]
8013432: 687a ldr r2, [r7, #4]
8013434: 429a cmp r2, r3
8013436: d105 bne.n 8013444 <tcp_process+0x68c>
8013438: 4b56 ldr r3, [pc, #344] ; (8013594 <tcp_process+0x7dc>)
801343a: 681b ldr r3, [r3, #0]
801343c: 68db ldr r3, [r3, #12]
801343e: 4a55 ldr r2, [pc, #340] ; (8013594 <tcp_process+0x7dc>)
8013440: 6013 str r3, [r2, #0]
8013442: e013 b.n 801346c <tcp_process+0x6b4>
8013444: 4b53 ldr r3, [pc, #332] ; (8013594 <tcp_process+0x7dc>)
8013446: 681b ldr r3, [r3, #0]
8013448: 613b str r3, [r7, #16]
801344a: e00c b.n 8013466 <tcp_process+0x6ae>
801344c: 693b ldr r3, [r7, #16]
801344e: 68db ldr r3, [r3, #12]
8013450: 687a ldr r2, [r7, #4]
8013452: 429a cmp r2, r3
8013454: d104 bne.n 8013460 <tcp_process+0x6a8>
8013456: 687b ldr r3, [r7, #4]
8013458: 68da ldr r2, [r3, #12]
801345a: 693b ldr r3, [r7, #16]
801345c: 60da str r2, [r3, #12]
801345e: e005 b.n 801346c <tcp_process+0x6b4>
8013460: 693b ldr r3, [r7, #16]
8013462: 68db ldr r3, [r3, #12]
8013464: 613b str r3, [r7, #16]
8013466: 693b ldr r3, [r7, #16]
8013468: 2b00 cmp r3, #0
801346a: d1ef bne.n 801344c <tcp_process+0x694>
801346c: 687b ldr r3, [r7, #4]
801346e: 2200 movs r2, #0
8013470: 60da str r2, [r3, #12]
8013472: 4b43 ldr r3, [pc, #268] ; (8013580 <tcp_process+0x7c8>)
8013474: 2201 movs r2, #1
8013476: 701a strb r2, [r3, #0]
pcb->state = TIME_WAIT;
8013478: 687b ldr r3, [r7, #4]
801347a: 220a movs r2, #10
801347c: 751a strb r2, [r3, #20]
TCP_REG(&tcp_tw_pcbs, pcb);
801347e: 4b41 ldr r3, [pc, #260] ; (8013584 <tcp_process+0x7cc>)
8013480: 681a ldr r2, [r3, #0]
8013482: 687b ldr r3, [r7, #4]
8013484: 60da str r2, [r3, #12]
8013486: 4a3f ldr r2, [pc, #252] ; (8013584 <tcp_process+0x7cc>)
8013488: 687b ldr r3, [r7, #4]
801348a: 6013 str r3, [r2, #0]
801348c: f002 fc90 bl 8015db0 <tcp_timer_needed>
}
break;
8013490: e06c b.n 801356c <tcp_process+0x7b4>
case CLOSING:
tcp_receive(pcb);
8013492: 6878 ldr r0, [r7, #4]
8013494: f000 f984 bl 80137a0 <tcp_receive>
if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
8013498: 4b3b ldr r3, [pc, #236] ; (8013588 <tcp_process+0x7d0>)
801349a: 781b ldrb r3, [r3, #0]
801349c: f003 0310 and.w r3, r3, #16
80134a0: 2b00 cmp r3, #0
80134a2: d065 beq.n 8013570 <tcp_process+0x7b8>
80134a4: 687b ldr r3, [r7, #4]
80134a6: 6d1a ldr r2, [r3, #80] ; 0x50
80134a8: 4b38 ldr r3, [pc, #224] ; (801358c <tcp_process+0x7d4>)
80134aa: 681b ldr r3, [r3, #0]
80134ac: 429a cmp r2, r3
80134ae: d15f bne.n 8013570 <tcp_process+0x7b8>
80134b0: 687b ldr r3, [r7, #4]
80134b2: 6edb ldr r3, [r3, #108] ; 0x6c
80134b4: 2b00 cmp r3, #0
80134b6: d15b bne.n 8013570 <tcp_process+0x7b8>
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
tcp_pcb_purge(pcb);
80134b8: 6878 ldr r0, [r7, #4]
80134ba: f7fe fcf3 bl 8011ea4 <tcp_pcb_purge>
TCP_RMV_ACTIVE(pcb);
80134be: 4b35 ldr r3, [pc, #212] ; (8013594 <tcp_process+0x7dc>)
80134c0: 681b ldr r3, [r3, #0]
80134c2: 687a ldr r2, [r7, #4]
80134c4: 429a cmp r2, r3
80134c6: d105 bne.n 80134d4 <tcp_process+0x71c>
80134c8: 4b32 ldr r3, [pc, #200] ; (8013594 <tcp_process+0x7dc>)
80134ca: 681b ldr r3, [r3, #0]
80134cc: 68db ldr r3, [r3, #12]
80134ce: 4a31 ldr r2, [pc, #196] ; (8013594 <tcp_process+0x7dc>)
80134d0: 6013 str r3, [r2, #0]
80134d2: e013 b.n 80134fc <tcp_process+0x744>
80134d4: 4b2f ldr r3, [pc, #188] ; (8013594 <tcp_process+0x7dc>)
80134d6: 681b ldr r3, [r3, #0]
80134d8: 60fb str r3, [r7, #12]
80134da: e00c b.n 80134f6 <tcp_process+0x73e>
80134dc: 68fb ldr r3, [r7, #12]
80134de: 68db ldr r3, [r3, #12]
80134e0: 687a ldr r2, [r7, #4]
80134e2: 429a cmp r2, r3
80134e4: d104 bne.n 80134f0 <tcp_process+0x738>
80134e6: 687b ldr r3, [r7, #4]
80134e8: 68da ldr r2, [r3, #12]
80134ea: 68fb ldr r3, [r7, #12]
80134ec: 60da str r2, [r3, #12]
80134ee: e005 b.n 80134fc <tcp_process+0x744>
80134f0: 68fb ldr r3, [r7, #12]
80134f2: 68db ldr r3, [r3, #12]
80134f4: 60fb str r3, [r7, #12]
80134f6: 68fb ldr r3, [r7, #12]
80134f8: 2b00 cmp r3, #0
80134fa: d1ef bne.n 80134dc <tcp_process+0x724>
80134fc: 687b ldr r3, [r7, #4]
80134fe: 2200 movs r2, #0
8013500: 60da str r2, [r3, #12]
8013502: 4b1f ldr r3, [pc, #124] ; (8013580 <tcp_process+0x7c8>)
8013504: 2201 movs r2, #1
8013506: 701a strb r2, [r3, #0]
pcb->state = TIME_WAIT;
8013508: 687b ldr r3, [r7, #4]
801350a: 220a movs r2, #10
801350c: 751a strb r2, [r3, #20]
TCP_REG(&tcp_tw_pcbs, pcb);
801350e: 4b1d ldr r3, [pc, #116] ; (8013584 <tcp_process+0x7cc>)
8013510: 681a ldr r2, [r3, #0]
8013512: 687b ldr r3, [r7, #4]
8013514: 60da str r2, [r3, #12]
8013516: 4a1b ldr r2, [pc, #108] ; (8013584 <tcp_process+0x7cc>)
8013518: 687b ldr r3, [r7, #4]
801351a: 6013 str r3, [r2, #0]
801351c: f002 fc48 bl 8015db0 <tcp_timer_needed>
}
break;
8013520: e026 b.n 8013570 <tcp_process+0x7b8>
case LAST_ACK:
tcp_receive(pcb);
8013522: 6878 ldr r0, [r7, #4]
8013524: f000 f93c bl 80137a0 <tcp_receive>
if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
8013528: 4b17 ldr r3, [pc, #92] ; (8013588 <tcp_process+0x7d0>)
801352a: 781b ldrb r3, [r3, #0]
801352c: f003 0310 and.w r3, r3, #16
8013530: 2b00 cmp r3, #0
8013532: d01f beq.n 8013574 <tcp_process+0x7bc>
8013534: 687b ldr r3, [r7, #4]
8013536: 6d1a ldr r2, [r3, #80] ; 0x50
8013538: 4b14 ldr r3, [pc, #80] ; (801358c <tcp_process+0x7d4>)
801353a: 681b ldr r3, [r3, #0]
801353c: 429a cmp r2, r3
801353e: d119 bne.n 8013574 <tcp_process+0x7bc>
8013540: 687b ldr r3, [r7, #4]
8013542: 6edb ldr r3, [r3, #108] ; 0x6c
8013544: 2b00 cmp r3, #0
8013546: d115 bne.n 8013574 <tcp_process+0x7bc>
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
/* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */
recv_flags |= TF_CLOSED;
8013548: 4b11 ldr r3, [pc, #68] ; (8013590 <tcp_process+0x7d8>)
801354a: 781b ldrb r3, [r3, #0]
801354c: f043 0310 orr.w r3, r3, #16
8013550: b2da uxtb r2, r3
8013552: 4b0f ldr r3, [pc, #60] ; (8013590 <tcp_process+0x7d8>)
8013554: 701a strb r2, [r3, #0]
}
break;
8013556: e00d b.n 8013574 <tcp_process+0x7bc>
default:
break;
8013558: bf00 nop
801355a: e00c b.n 8013576 <tcp_process+0x7be>
break;
801355c: bf00 nop
801355e: e00a b.n 8013576 <tcp_process+0x7be>
break;
8013560: bf00 nop
8013562: e008 b.n 8013576 <tcp_process+0x7be>
break;
8013564: bf00 nop
8013566: e006 b.n 8013576 <tcp_process+0x7be>
break;
8013568: bf00 nop
801356a: e004 b.n 8013576 <tcp_process+0x7be>
break;
801356c: bf00 nop
801356e: e002 b.n 8013576 <tcp_process+0x7be>
break;
8013570: bf00 nop
8013572: e000 b.n 8013576 <tcp_process+0x7be>
break;
8013574: bf00 nop
}
return ERR_OK;
8013576: 2300 movs r3, #0
}
8013578: 4618 mov r0, r3
801357a: 3724 adds r7, #36 ; 0x24
801357c: 46bd mov sp, r7
801357e: bd90 pop {r4, r7, pc}
8013580: 2000f838 .word 0x2000f838
8013584: 2000f84c .word 0x2000f84c
8013588: 2000874c .word 0x2000874c
801358c: 20008744 .word 0x20008744
8013590: 2000874d .word 0x2000874d
8013594: 2000f83c .word 0x2000f83c
08013598 <tcp_oos_insert_segment>:
*
* Called from tcp_receive()
*/
static void
tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next)
{
8013598: b590 push {r4, r7, lr}
801359a: b085 sub sp, #20
801359c: af00 add r7, sp, #0
801359e: 6078 str r0, [r7, #4]
80135a0: 6039 str r1, [r7, #0]
struct tcp_seg *old_seg;
LWIP_ASSERT("tcp_oos_insert_segment: invalid cseg", cseg != NULL);
80135a2: 687b ldr r3, [r7, #4]
80135a4: 2b00 cmp r3, #0
80135a6: d106 bne.n 80135b6 <tcp_oos_insert_segment+0x1e>
80135a8: 4b3b ldr r3, [pc, #236] ; (8013698 <tcp_oos_insert_segment+0x100>)
80135aa: f240 421f movw r2, #1055 ; 0x41f
80135ae: 493b ldr r1, [pc, #236] ; (801369c <tcp_oos_insert_segment+0x104>)
80135b0: 483b ldr r0, [pc, #236] ; (80136a0 <tcp_oos_insert_segment+0x108>)
80135b2: f007 fd07 bl 801afc4 <iprintf>
if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
80135b6: 687b ldr r3, [r7, #4]
80135b8: 68db ldr r3, [r3, #12]
80135ba: 899b ldrh r3, [r3, #12]
80135bc: b29b uxth r3, r3
80135be: 4618 mov r0, r3
80135c0: f7fb fc3c bl 800ee3c <lwip_htons>
80135c4: 4603 mov r3, r0
80135c6: b2db uxtb r3, r3
80135c8: f003 0301 and.w r3, r3, #1
80135cc: 2b00 cmp r3, #0
80135ce: d028 beq.n 8013622 <tcp_oos_insert_segment+0x8a>
/* received segment overlaps all following segments */
tcp_segs_free(next);
80135d0: 6838 ldr r0, [r7, #0]
80135d2: f7fe fa65 bl 8011aa0 <tcp_segs_free>
next = NULL;
80135d6: 2300 movs r3, #0
80135d8: 603b str r3, [r7, #0]
80135da: e056 b.n 801368a <tcp_oos_insert_segment+0xf2>
oos queue may have segments with FIN flag */
while (next &&
TCP_SEQ_GEQ((seqno + cseg->len),
(next->tcphdr->seqno + next->len))) {
/* cseg with FIN already processed */
if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
80135dc: 683b ldr r3, [r7, #0]
80135de: 68db ldr r3, [r3, #12]
80135e0: 899b ldrh r3, [r3, #12]
80135e2: b29b uxth r3, r3
80135e4: 4618 mov r0, r3
80135e6: f7fb fc29 bl 800ee3c <lwip_htons>
80135ea: 4603 mov r3, r0
80135ec: b2db uxtb r3, r3
80135ee: f003 0301 and.w r3, r3, #1
80135f2: 2b00 cmp r3, #0
80135f4: d00d beq.n 8013612 <tcp_oos_insert_segment+0x7a>
TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN);
80135f6: 687b ldr r3, [r7, #4]
80135f8: 68db ldr r3, [r3, #12]
80135fa: 899b ldrh r3, [r3, #12]
80135fc: b29c uxth r4, r3
80135fe: 2001 movs r0, #1
8013600: f7fb fc1c bl 800ee3c <lwip_htons>
8013604: 4603 mov r3, r0
8013606: 461a mov r2, r3
8013608: 687b ldr r3, [r7, #4]
801360a: 68db ldr r3, [r3, #12]
801360c: 4322 orrs r2, r4
801360e: b292 uxth r2, r2
8013610: 819a strh r2, [r3, #12]
}
old_seg = next;
8013612: 683b ldr r3, [r7, #0]
8013614: 60fb str r3, [r7, #12]
next = next->next;
8013616: 683b ldr r3, [r7, #0]
8013618: 681b ldr r3, [r3, #0]
801361a: 603b str r3, [r7, #0]
tcp_seg_free(old_seg);
801361c: 68f8 ldr r0, [r7, #12]
801361e: f7fe fa54 bl 8011aca <tcp_seg_free>
while (next &&
8013622: 683b ldr r3, [r7, #0]
8013624: 2b00 cmp r3, #0
8013626: d00e beq.n 8013646 <tcp_oos_insert_segment+0xae>
TCP_SEQ_GEQ((seqno + cseg->len),
8013628: 687b ldr r3, [r7, #4]
801362a: 891b ldrh r3, [r3, #8]
801362c: 461a mov r2, r3
801362e: 4b1d ldr r3, [pc, #116] ; (80136a4 <tcp_oos_insert_segment+0x10c>)
8013630: 681b ldr r3, [r3, #0]
8013632: 441a add r2, r3
8013634: 683b ldr r3, [r7, #0]
8013636: 68db ldr r3, [r3, #12]
8013638: 685b ldr r3, [r3, #4]
801363a: 6839 ldr r1, [r7, #0]
801363c: 8909 ldrh r1, [r1, #8]
801363e: 440b add r3, r1
8013640: 1ad3 subs r3, r2, r3
while (next &&
8013642: 2b00 cmp r3, #0
8013644: daca bge.n 80135dc <tcp_oos_insert_segment+0x44>
}
if (next &&
8013646: 683b ldr r3, [r7, #0]
8013648: 2b00 cmp r3, #0
801364a: d01e beq.n 801368a <tcp_oos_insert_segment+0xf2>
TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) {
801364c: 687b ldr r3, [r7, #4]
801364e: 891b ldrh r3, [r3, #8]
8013650: 461a mov r2, r3
8013652: 4b14 ldr r3, [pc, #80] ; (80136a4 <tcp_oos_insert_segment+0x10c>)
8013654: 681b ldr r3, [r3, #0]
8013656: 441a add r2, r3
8013658: 683b ldr r3, [r7, #0]
801365a: 68db ldr r3, [r3, #12]
801365c: 685b ldr r3, [r3, #4]
801365e: 1ad3 subs r3, r2, r3
if (next &&
8013660: 2b00 cmp r3, #0
8013662: dd12 ble.n 801368a <tcp_oos_insert_segment+0xf2>
/* We need to trim the incoming segment. */
cseg->len = (u16_t)(next->tcphdr->seqno - seqno);
8013664: 683b ldr r3, [r7, #0]
8013666: 68db ldr r3, [r3, #12]
8013668: 685b ldr r3, [r3, #4]
801366a: b29a uxth r2, r3
801366c: 4b0d ldr r3, [pc, #52] ; (80136a4 <tcp_oos_insert_segment+0x10c>)
801366e: 681b ldr r3, [r3, #0]
8013670: b29b uxth r3, r3
8013672: 1ad3 subs r3, r2, r3
8013674: b29a uxth r2, r3
8013676: 687b ldr r3, [r7, #4]
8013678: 811a strh r2, [r3, #8]
pbuf_realloc(cseg->p, cseg->len);
801367a: 687b ldr r3, [r7, #4]
801367c: 685a ldr r2, [r3, #4]
801367e: 687b ldr r3, [r7, #4]
8013680: 891b ldrh r3, [r3, #8]
8013682: 4619 mov r1, r3
8013684: 4610 mov r0, r2
8013686: f7fc fe0b bl 80102a0 <pbuf_realloc>
}
}
cseg->next = next;
801368a: 687b ldr r3, [r7, #4]
801368c: 683a ldr r2, [r7, #0]
801368e: 601a str r2, [r3, #0]
}
8013690: bf00 nop
8013692: 3714 adds r7, #20
8013694: 46bd mov sp, r7
8013696: bd90 pop {r4, r7, pc}
8013698: 0801d484 .word 0x0801d484
801369c: 0801d744 .word 0x0801d744
80136a0: 0801d4d0 .word 0x0801d4d0
80136a4: 20008740 .word 0x20008740
080136a8 <tcp_free_acked_segments>:
/** Remove segments from a list if the incoming ACK acknowledges them */
static struct tcp_seg *
tcp_free_acked_segments(struct tcp_pcb *pcb, struct tcp_seg *seg_list, const char *dbg_list_name,
struct tcp_seg *dbg_other_seg_list)
{
80136a8: b5b0 push {r4, r5, r7, lr}
80136aa: b086 sub sp, #24
80136ac: af00 add r7, sp, #0
80136ae: 60f8 str r0, [r7, #12]
80136b0: 60b9 str r1, [r7, #8]
80136b2: 607a str r2, [r7, #4]
80136b4: 603b str r3, [r7, #0]
u16_t clen;
LWIP_UNUSED_ARG(dbg_list_name);
LWIP_UNUSED_ARG(dbg_other_seg_list);
while (seg_list != NULL &&
80136b6: e03e b.n 8013736 <tcp_free_acked_segments+0x8e>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->%s\n",
lwip_ntohl(seg_list->tcphdr->seqno),
lwip_ntohl(seg_list->tcphdr->seqno) + TCP_TCPLEN(seg_list),
dbg_list_name));
next = seg_list;
80136b8: 68bb ldr r3, [r7, #8]
80136ba: 617b str r3, [r7, #20]
seg_list = seg_list->next;
80136bc: 68bb ldr r3, [r7, #8]
80136be: 681b ldr r3, [r3, #0]
80136c0: 60bb str r3, [r7, #8]
clen = pbuf_clen(next->p);
80136c2: 697b ldr r3, [r7, #20]
80136c4: 685b ldr r3, [r3, #4]
80136c6: 4618 mov r0, r3
80136c8: f7fc fffe bl 80106c8 <pbuf_clen>
80136cc: 4603 mov r3, r0
80136ce: 827b strh r3, [r7, #18]
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ",
(tcpwnd_size_t)pcb->snd_queuelen));
LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= clen));
80136d0: 68fb ldr r3, [r7, #12]
80136d2: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
80136d6: 8a7a ldrh r2, [r7, #18]
80136d8: 429a cmp r2, r3
80136da: d906 bls.n 80136ea <tcp_free_acked_segments+0x42>
80136dc: 4b2a ldr r3, [pc, #168] ; (8013788 <tcp_free_acked_segments+0xe0>)
80136de: f240 4257 movw r2, #1111 ; 0x457
80136e2: 492a ldr r1, [pc, #168] ; (801378c <tcp_free_acked_segments+0xe4>)
80136e4: 482a ldr r0, [pc, #168] ; (8013790 <tcp_free_acked_segments+0xe8>)
80136e6: f007 fc6d bl 801afc4 <iprintf>
pcb->snd_queuelen = (u16_t)(pcb->snd_queuelen - clen);
80136ea: 68fb ldr r3, [r7, #12]
80136ec: f8b3 2066 ldrh.w r2, [r3, #102] ; 0x66
80136f0: 8a7b ldrh r3, [r7, #18]
80136f2: 1ad3 subs r3, r2, r3
80136f4: b29a uxth r2, r3
80136f6: 68fb ldr r3, [r7, #12]
80136f8: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
recv_acked = (tcpwnd_size_t)(recv_acked + next->len);
80136fc: 697b ldr r3, [r7, #20]
80136fe: 891a ldrh r2, [r3, #8]
8013700: 4b24 ldr r3, [pc, #144] ; (8013794 <tcp_free_acked_segments+0xec>)
8013702: 881b ldrh r3, [r3, #0]
8013704: 4413 add r3, r2
8013706: b29a uxth r2, r3
8013708: 4b22 ldr r3, [pc, #136] ; (8013794 <tcp_free_acked_segments+0xec>)
801370a: 801a strh r2, [r3, #0]
tcp_seg_free(next);
801370c: 6978 ldr r0, [r7, #20]
801370e: f7fe f9dc bl 8011aca <tcp_seg_free>
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing %s)\n",
(tcpwnd_size_t)pcb->snd_queuelen,
dbg_list_name));
if (pcb->snd_queuelen != 0) {
8013712: 68fb ldr r3, [r7, #12]
8013714: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8013718: 2b00 cmp r3, #0
801371a: d00c beq.n 8013736 <tcp_free_acked_segments+0x8e>
LWIP_ASSERT("tcp_receive: valid queue length",
801371c: 68bb ldr r3, [r7, #8]
801371e: 2b00 cmp r3, #0
8013720: d109 bne.n 8013736 <tcp_free_acked_segments+0x8e>
8013722: 683b ldr r3, [r7, #0]
8013724: 2b00 cmp r3, #0
8013726: d106 bne.n 8013736 <tcp_free_acked_segments+0x8e>
8013728: 4b17 ldr r3, [pc, #92] ; (8013788 <tcp_free_acked_segments+0xe0>)
801372a: f240 4261 movw r2, #1121 ; 0x461
801372e: 491a ldr r1, [pc, #104] ; (8013798 <tcp_free_acked_segments+0xf0>)
8013730: 4817 ldr r0, [pc, #92] ; (8013790 <tcp_free_acked_segments+0xe8>)
8013732: f007 fc47 bl 801afc4 <iprintf>
while (seg_list != NULL &&
8013736: 68bb ldr r3, [r7, #8]
8013738: 2b00 cmp r3, #0
801373a: d020 beq.n 801377e <tcp_free_acked_segments+0xd6>
TCP_SEQ_LEQ(lwip_ntohl(seg_list->tcphdr->seqno) +
801373c: 68bb ldr r3, [r7, #8]
801373e: 68db ldr r3, [r3, #12]
8013740: 685b ldr r3, [r3, #4]
8013742: 4618 mov r0, r3
8013744: f7fb fb8f bl 800ee66 <lwip_htonl>
8013748: 4604 mov r4, r0
801374a: 68bb ldr r3, [r7, #8]
801374c: 891b ldrh r3, [r3, #8]
801374e: 461d mov r5, r3
8013750: 68bb ldr r3, [r7, #8]
8013752: 68db ldr r3, [r3, #12]
8013754: 899b ldrh r3, [r3, #12]
8013756: b29b uxth r3, r3
8013758: 4618 mov r0, r3
801375a: f7fb fb6f bl 800ee3c <lwip_htons>
801375e: 4603 mov r3, r0
8013760: b2db uxtb r3, r3
8013762: f003 0303 and.w r3, r3, #3
8013766: 2b00 cmp r3, #0
8013768: d001 beq.n 801376e <tcp_free_acked_segments+0xc6>
801376a: 2301 movs r3, #1
801376c: e000 b.n 8013770 <tcp_free_acked_segments+0xc8>
801376e: 2300 movs r3, #0
8013770: 442b add r3, r5
8013772: 18e2 adds r2, r4, r3
8013774: 4b09 ldr r3, [pc, #36] ; (801379c <tcp_free_acked_segments+0xf4>)
8013776: 681b ldr r3, [r3, #0]
8013778: 1ad3 subs r3, r2, r3
while (seg_list != NULL &&
801377a: 2b00 cmp r3, #0
801377c: dd9c ble.n 80136b8 <tcp_free_acked_segments+0x10>
seg_list != NULL || dbg_other_seg_list != NULL);
}
}
return seg_list;
801377e: 68bb ldr r3, [r7, #8]
}
8013780: 4618 mov r0, r3
8013782: 3718 adds r7, #24
8013784: 46bd mov sp, r7
8013786: bdb0 pop {r4, r5, r7, pc}
8013788: 0801d484 .word 0x0801d484
801378c: 0801d76c .word 0x0801d76c
8013790: 0801d4d0 .word 0x0801d4d0
8013794: 20008748 .word 0x20008748
8013798: 0801d794 .word 0x0801d794
801379c: 20008744 .word 0x20008744
080137a0 <tcp_receive>:
*
* Called from tcp_process().
*/
static void
tcp_receive(struct tcp_pcb *pcb)
{
80137a0: b5b0 push {r4, r5, r7, lr}
80137a2: b094 sub sp, #80 ; 0x50
80137a4: af00 add r7, sp, #0
80137a6: 6078 str r0, [r7, #4]
s16_t m;
u32_t right_wnd_edge;
int found_dupack = 0;
80137a8: 2300 movs r3, #0
80137aa: 64bb str r3, [r7, #72] ; 0x48
LWIP_ASSERT("tcp_receive: invalid pcb", pcb != NULL);
80137ac: 687b ldr r3, [r7, #4]
80137ae: 2b00 cmp r3, #0
80137b0: d106 bne.n 80137c0 <tcp_receive+0x20>
80137b2: 4ba6 ldr r3, [pc, #664] ; (8013a4c <tcp_receive+0x2ac>)
80137b4: f240 427b movw r2, #1147 ; 0x47b
80137b8: 49a5 ldr r1, [pc, #660] ; (8013a50 <tcp_receive+0x2b0>)
80137ba: 48a6 ldr r0, [pc, #664] ; (8013a54 <tcp_receive+0x2b4>)
80137bc: f007 fc02 bl 801afc4 <iprintf>
LWIP_ASSERT("tcp_receive: wrong state", pcb->state >= ESTABLISHED);
80137c0: 687b ldr r3, [r7, #4]
80137c2: 7d1b ldrb r3, [r3, #20]
80137c4: 2b03 cmp r3, #3
80137c6: d806 bhi.n 80137d6 <tcp_receive+0x36>
80137c8: 4ba0 ldr r3, [pc, #640] ; (8013a4c <tcp_receive+0x2ac>)
80137ca: f240 427c movw r2, #1148 ; 0x47c
80137ce: 49a2 ldr r1, [pc, #648] ; (8013a58 <tcp_receive+0x2b8>)
80137d0: 48a0 ldr r0, [pc, #640] ; (8013a54 <tcp_receive+0x2b4>)
80137d2: f007 fbf7 bl 801afc4 <iprintf>
if (flags & TCP_ACK) {
80137d6: 4ba1 ldr r3, [pc, #644] ; (8013a5c <tcp_receive+0x2bc>)
80137d8: 781b ldrb r3, [r3, #0]
80137da: f003 0310 and.w r3, r3, #16
80137de: 2b00 cmp r3, #0
80137e0: f000 8263 beq.w 8013caa <tcp_receive+0x50a>
right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2;
80137e4: 687b ldr r3, [r7, #4]
80137e6: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
80137ea: 461a mov r2, r3
80137ec: 687b ldr r3, [r7, #4]
80137ee: 6d9b ldr r3, [r3, #88] ; 0x58
80137f0: 4413 add r3, r2
80137f2: 633b str r3, [r7, #48] ; 0x30
/* Update window. */
if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
80137f4: 687b ldr r3, [r7, #4]
80137f6: 6d5a ldr r2, [r3, #84] ; 0x54
80137f8: 4b99 ldr r3, [pc, #612] ; (8013a60 <tcp_receive+0x2c0>)
80137fa: 681b ldr r3, [r3, #0]
80137fc: 1ad3 subs r3, r2, r3
80137fe: 2b00 cmp r3, #0
8013800: db1b blt.n 801383a <tcp_receive+0x9a>
(pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
8013802: 687b ldr r3, [r7, #4]
8013804: 6d5a ldr r2, [r3, #84] ; 0x54
8013806: 4b96 ldr r3, [pc, #600] ; (8013a60 <tcp_receive+0x2c0>)
8013808: 681b ldr r3, [r3, #0]
if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
801380a: 429a cmp r2, r3
801380c: d106 bne.n 801381c <tcp_receive+0x7c>
(pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
801380e: 687b ldr r3, [r7, #4]
8013810: 6d9a ldr r2, [r3, #88] ; 0x58
8013812: 4b94 ldr r3, [pc, #592] ; (8013a64 <tcp_receive+0x2c4>)
8013814: 681b ldr r3, [r3, #0]
8013816: 1ad3 subs r3, r2, r3
8013818: 2b00 cmp r3, #0
801381a: db0e blt.n 801383a <tcp_receive+0x9a>
(pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
801381c: 687b ldr r3, [r7, #4]
801381e: 6d9a ldr r2, [r3, #88] ; 0x58
8013820: 4b90 ldr r3, [pc, #576] ; (8013a64 <tcp_receive+0x2c4>)
8013822: 681b ldr r3, [r3, #0]
(pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
8013824: 429a cmp r2, r3
8013826: d125 bne.n 8013874 <tcp_receive+0xd4>
(pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
8013828: 4b8f ldr r3, [pc, #572] ; (8013a68 <tcp_receive+0x2c8>)
801382a: 681b ldr r3, [r3, #0]
801382c: 89db ldrh r3, [r3, #14]
801382e: b29a uxth r2, r3
8013830: 687b ldr r3, [r7, #4]
8013832: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8013836: 429a cmp r2, r3
8013838: d91c bls.n 8013874 <tcp_receive+0xd4>
pcb->snd_wnd = SND_WND_SCALE(pcb, tcphdr->wnd);
801383a: 4b8b ldr r3, [pc, #556] ; (8013a68 <tcp_receive+0x2c8>)
801383c: 681b ldr r3, [r3, #0]
801383e: 89db ldrh r3, [r3, #14]
8013840: b29a uxth r2, r3
8013842: 687b ldr r3, [r7, #4]
8013844: f8a3 2060 strh.w r2, [r3, #96] ; 0x60
/* keep track of the biggest window announced by the remote host to calculate
the maximum segment size */
if (pcb->snd_wnd_max < pcb->snd_wnd) {
8013848: 687b ldr r3, [r7, #4]
801384a: f8b3 2062 ldrh.w r2, [r3, #98] ; 0x62
801384e: 687b ldr r3, [r7, #4]
8013850: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8013854: 429a cmp r2, r3
8013856: d205 bcs.n 8013864 <tcp_receive+0xc4>
pcb->snd_wnd_max = pcb->snd_wnd;
8013858: 687b ldr r3, [r7, #4]
801385a: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
801385e: 687b ldr r3, [r7, #4]
8013860: f8a3 2062 strh.w r2, [r3, #98] ; 0x62
}
pcb->snd_wl1 = seqno;
8013864: 4b7e ldr r3, [pc, #504] ; (8013a60 <tcp_receive+0x2c0>)
8013866: 681a ldr r2, [r3, #0]
8013868: 687b ldr r3, [r7, #4]
801386a: 655a str r2, [r3, #84] ; 0x54
pcb->snd_wl2 = ackno;
801386c: 4b7d ldr r3, [pc, #500] ; (8013a64 <tcp_receive+0x2c4>)
801386e: 681a ldr r2, [r3, #0]
8013870: 687b ldr r3, [r7, #4]
8013872: 659a str r2, [r3, #88] ; 0x58
* If it only passes 1, should reset dupack counter
*
*/
/* Clause 1 */
if (TCP_SEQ_LEQ(ackno, pcb->lastack)) {
8013874: 4b7b ldr r3, [pc, #492] ; (8013a64 <tcp_receive+0x2c4>)
8013876: 681a ldr r2, [r3, #0]
8013878: 687b ldr r3, [r7, #4]
801387a: 6c5b ldr r3, [r3, #68] ; 0x44
801387c: 1ad3 subs r3, r2, r3
801387e: 2b00 cmp r3, #0
8013880: dc58 bgt.n 8013934 <tcp_receive+0x194>
/* Clause 2 */
if (tcplen == 0) {
8013882: 4b7a ldr r3, [pc, #488] ; (8013a6c <tcp_receive+0x2cc>)
8013884: 881b ldrh r3, [r3, #0]
8013886: 2b00 cmp r3, #0
8013888: d14b bne.n 8013922 <tcp_receive+0x182>
/* Clause 3 */
if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge) {
801388a: 687b ldr r3, [r7, #4]
801388c: 6d9b ldr r3, [r3, #88] ; 0x58
801388e: 687a ldr r2, [r7, #4]
8013890: f8b2 2060 ldrh.w r2, [r2, #96] ; 0x60
8013894: 4413 add r3, r2
8013896: 6b3a ldr r2, [r7, #48] ; 0x30
8013898: 429a cmp r2, r3
801389a: d142 bne.n 8013922 <tcp_receive+0x182>
/* Clause 4 */
if (pcb->rtime >= 0) {
801389c: 687b ldr r3, [r7, #4]
801389e: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
80138a2: 2b00 cmp r3, #0
80138a4: db3d blt.n 8013922 <tcp_receive+0x182>
/* Clause 5 */
if (pcb->lastack == ackno) {
80138a6: 687b ldr r3, [r7, #4]
80138a8: 6c5a ldr r2, [r3, #68] ; 0x44
80138aa: 4b6e ldr r3, [pc, #440] ; (8013a64 <tcp_receive+0x2c4>)
80138ac: 681b ldr r3, [r3, #0]
80138ae: 429a cmp r2, r3
80138b0: d137 bne.n 8013922 <tcp_receive+0x182>
found_dupack = 1;
80138b2: 2301 movs r3, #1
80138b4: 64bb str r3, [r7, #72] ; 0x48
if ((u8_t)(pcb->dupacks + 1) > pcb->dupacks) {
80138b6: 687b ldr r3, [r7, #4]
80138b8: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
80138bc: 2bff cmp r3, #255 ; 0xff
80138be: d007 beq.n 80138d0 <tcp_receive+0x130>
++pcb->dupacks;
80138c0: 687b ldr r3, [r7, #4]
80138c2: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
80138c6: 3301 adds r3, #1
80138c8: b2da uxtb r2, r3
80138ca: 687b ldr r3, [r7, #4]
80138cc: f883 2043 strb.w r2, [r3, #67] ; 0x43
}
if (pcb->dupacks > 3) {
80138d0: 687b ldr r3, [r7, #4]
80138d2: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
80138d6: 2b03 cmp r3, #3
80138d8: d91b bls.n 8013912 <tcp_receive+0x172>
/* Inflate the congestion window */
TCP_WND_INC(pcb->cwnd, pcb->mss);
80138da: 687b ldr r3, [r7, #4]
80138dc: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
80138e0: 687b ldr r3, [r7, #4]
80138e2: 8e5b ldrh r3, [r3, #50] ; 0x32
80138e4: 4413 add r3, r2
80138e6: b29a uxth r2, r3
80138e8: 687b ldr r3, [r7, #4]
80138ea: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
80138ee: 429a cmp r2, r3
80138f0: d30a bcc.n 8013908 <tcp_receive+0x168>
80138f2: 687b ldr r3, [r7, #4]
80138f4: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
80138f8: 687b ldr r3, [r7, #4]
80138fa: 8e5b ldrh r3, [r3, #50] ; 0x32
80138fc: 4413 add r3, r2
80138fe: b29a uxth r2, r3
8013900: 687b ldr r3, [r7, #4]
8013902: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
8013906: e004 b.n 8013912 <tcp_receive+0x172>
8013908: 687b ldr r3, [r7, #4]
801390a: f64f 72ff movw r2, #65535 ; 0xffff
801390e: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
}
if (pcb->dupacks >= 3) {
8013912: 687b ldr r3, [r7, #4]
8013914: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
8013918: 2b02 cmp r3, #2
801391a: d902 bls.n 8013922 <tcp_receive+0x182>
/* Do fast retransmit (checked via TF_INFR, not via dupacks count) */
tcp_rexmit_fast(pcb);
801391c: 6878 ldr r0, [r7, #4]
801391e: f001 fee9 bl 80156f4 <tcp_rexmit_fast>
}
}
}
/* If Clause (1) or more is true, but not a duplicate ack, reset
* count of consecutive duplicate acks */
if (!found_dupack) {
8013922: 6cbb ldr r3, [r7, #72] ; 0x48
8013924: 2b00 cmp r3, #0
8013926: f040 8160 bne.w 8013bea <tcp_receive+0x44a>
pcb->dupacks = 0;
801392a: 687b ldr r3, [r7, #4]
801392c: 2200 movs r2, #0
801392e: f883 2043 strb.w r2, [r3, #67] ; 0x43
8013932: e15a b.n 8013bea <tcp_receive+0x44a>
}
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013934: 4b4b ldr r3, [pc, #300] ; (8013a64 <tcp_receive+0x2c4>)
8013936: 681a ldr r2, [r3, #0]
8013938: 687b ldr r3, [r7, #4]
801393a: 6c5b ldr r3, [r3, #68] ; 0x44
801393c: 1ad3 subs r3, r2, r3
801393e: 3b01 subs r3, #1
8013940: 2b00 cmp r3, #0
8013942: f2c0 814d blt.w 8013be0 <tcp_receive+0x440>
8013946: 4b47 ldr r3, [pc, #284] ; (8013a64 <tcp_receive+0x2c4>)
8013948: 681a ldr r2, [r3, #0]
801394a: 687b ldr r3, [r7, #4]
801394c: 6d1b ldr r3, [r3, #80] ; 0x50
801394e: 1ad3 subs r3, r2, r3
8013950: 2b00 cmp r3, #0
8013952: f300 8145 bgt.w 8013be0 <tcp_receive+0x440>
tcpwnd_size_t acked;
/* Reset the "IN Fast Retransmit" flag, since we are no longer
in fast retransmit. Also reset the congestion window to the
slow start threshold. */
if (pcb->flags & TF_INFR) {
8013956: 687b ldr r3, [r7, #4]
8013958: 8b5b ldrh r3, [r3, #26]
801395a: f003 0304 and.w r3, r3, #4
801395e: 2b00 cmp r3, #0
8013960: d010 beq.n 8013984 <tcp_receive+0x1e4>
tcp_clear_flags(pcb, TF_INFR);
8013962: 687b ldr r3, [r7, #4]
8013964: 8b5b ldrh r3, [r3, #26]
8013966: f023 0304 bic.w r3, r3, #4
801396a: b29a uxth r2, r3
801396c: 687b ldr r3, [r7, #4]
801396e: 835a strh r2, [r3, #26]
pcb->cwnd = pcb->ssthresh;
8013970: 687b ldr r3, [r7, #4]
8013972: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a
8013976: 687b ldr r3, [r7, #4]
8013978: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
pcb->bytes_acked = 0;
801397c: 687b ldr r3, [r7, #4]
801397e: 2200 movs r2, #0
8013980: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
}
/* Reset the number of retransmissions. */
pcb->nrtx = 0;
8013984: 687b ldr r3, [r7, #4]
8013986: 2200 movs r2, #0
8013988: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Reset the retransmission time-out. */
pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
801398c: 687b ldr r3, [r7, #4]
801398e: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
8013992: 10db asrs r3, r3, #3
8013994: b21b sxth r3, r3
8013996: b29a uxth r2, r3
8013998: 687b ldr r3, [r7, #4]
801399a: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
801399e: b29b uxth r3, r3
80139a0: 4413 add r3, r2
80139a2: b29b uxth r3, r3
80139a4: b21a sxth r2, r3
80139a6: 687b ldr r3, [r7, #4]
80139a8: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
/* Record how much data this ACK acks */
acked = (tcpwnd_size_t)(ackno - pcb->lastack);
80139ac: 4b2d ldr r3, [pc, #180] ; (8013a64 <tcp_receive+0x2c4>)
80139ae: 681b ldr r3, [r3, #0]
80139b0: b29a uxth r2, r3
80139b2: 687b ldr r3, [r7, #4]
80139b4: 6c5b ldr r3, [r3, #68] ; 0x44
80139b6: b29b uxth r3, r3
80139b8: 1ad3 subs r3, r2, r3
80139ba: 85fb strh r3, [r7, #46] ; 0x2e
/* Reset the fast retransmit variables. */
pcb->dupacks = 0;
80139bc: 687b ldr r3, [r7, #4]
80139be: 2200 movs r2, #0
80139c0: f883 2043 strb.w r2, [r3, #67] ; 0x43
pcb->lastack = ackno;
80139c4: 4b27 ldr r3, [pc, #156] ; (8013a64 <tcp_receive+0x2c4>)
80139c6: 681a ldr r2, [r3, #0]
80139c8: 687b ldr r3, [r7, #4]
80139ca: 645a str r2, [r3, #68] ; 0x44
/* Update the congestion control variables (cwnd and
ssthresh). */
if (pcb->state >= ESTABLISHED) {
80139cc: 687b ldr r3, [r7, #4]
80139ce: 7d1b ldrb r3, [r3, #20]
80139d0: 2b03 cmp r3, #3
80139d2: f240 8096 bls.w 8013b02 <tcp_receive+0x362>
if (pcb->cwnd < pcb->ssthresh) {
80139d6: 687b ldr r3, [r7, #4]
80139d8: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
80139dc: 687b ldr r3, [r7, #4]
80139de: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a
80139e2: 429a cmp r2, r3
80139e4: d244 bcs.n 8013a70 <tcp_receive+0x2d0>
tcpwnd_size_t increase;
/* limit to 1 SMSS segment during period following RTO */
u8_t num_seg = (pcb->flags & TF_RTO) ? 1 : 2;
80139e6: 687b ldr r3, [r7, #4]
80139e8: 8b5b ldrh r3, [r3, #26]
80139ea: f403 6300 and.w r3, r3, #2048 ; 0x800
80139ee: 2b00 cmp r3, #0
80139f0: d001 beq.n 80139f6 <tcp_receive+0x256>
80139f2: 2301 movs r3, #1
80139f4: e000 b.n 80139f8 <tcp_receive+0x258>
80139f6: 2302 movs r3, #2
80139f8: f887 302d strb.w r3, [r7, #45] ; 0x2d
/* RFC 3465, section 2.2 Slow Start */
increase = LWIP_MIN(acked, (tcpwnd_size_t)(num_seg * pcb->mss));
80139fc: f897 302d ldrb.w r3, [r7, #45] ; 0x2d
8013a00: b29a uxth r2, r3
8013a02: 687b ldr r3, [r7, #4]
8013a04: 8e5b ldrh r3, [r3, #50] ; 0x32
8013a06: fb12 f303 smulbb r3, r2, r3
8013a0a: b29b uxth r3, r3
8013a0c: 8dfa ldrh r2, [r7, #46] ; 0x2e
8013a0e: 4293 cmp r3, r2
8013a10: bf28 it cs
8013a12: 4613 movcs r3, r2
8013a14: 857b strh r3, [r7, #42] ; 0x2a
TCP_WND_INC(pcb->cwnd, increase);
8013a16: 687b ldr r3, [r7, #4]
8013a18: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013a1c: 8d7b ldrh r3, [r7, #42] ; 0x2a
8013a1e: 4413 add r3, r2
8013a20: b29a uxth r2, r3
8013a22: 687b ldr r3, [r7, #4]
8013a24: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013a28: 429a cmp r2, r3
8013a2a: d309 bcc.n 8013a40 <tcp_receive+0x2a0>
8013a2c: 687b ldr r3, [r7, #4]
8013a2e: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013a32: 8d7b ldrh r3, [r7, #42] ; 0x2a
8013a34: 4413 add r3, r2
8013a36: b29a uxth r2, r3
8013a38: 687b ldr r3, [r7, #4]
8013a3a: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
8013a3e: e060 b.n 8013b02 <tcp_receive+0x362>
8013a40: 687b ldr r3, [r7, #4]
8013a42: f64f 72ff movw r2, #65535 ; 0xffff
8013a46: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
8013a4a: e05a b.n 8013b02 <tcp_receive+0x362>
8013a4c: 0801d484 .word 0x0801d484
8013a50: 0801d7b4 .word 0x0801d7b4
8013a54: 0801d4d0 .word 0x0801d4d0
8013a58: 0801d7d0 .word 0x0801d7d0
8013a5c: 2000874c .word 0x2000874c
8013a60: 20008740 .word 0x20008740
8013a64: 20008744 .word 0x20008744
8013a68: 20008730 .word 0x20008730
8013a6c: 2000874a .word 0x2000874a
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd));
} else {
/* RFC 3465, section 2.1 Congestion Avoidance */
TCP_WND_INC(pcb->bytes_acked, acked);
8013a70: 687b ldr r3, [r7, #4]
8013a72: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
8013a76: 8dfb ldrh r3, [r7, #46] ; 0x2e
8013a78: 4413 add r3, r2
8013a7a: b29a uxth r2, r3
8013a7c: 687b ldr r3, [r7, #4]
8013a7e: f8b3 306a ldrh.w r3, [r3, #106] ; 0x6a
8013a82: 429a cmp r2, r3
8013a84: d309 bcc.n 8013a9a <tcp_receive+0x2fa>
8013a86: 687b ldr r3, [r7, #4]
8013a88: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
8013a8c: 8dfb ldrh r3, [r7, #46] ; 0x2e
8013a8e: 4413 add r3, r2
8013a90: b29a uxth r2, r3
8013a92: 687b ldr r3, [r7, #4]
8013a94: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
8013a98: e004 b.n 8013aa4 <tcp_receive+0x304>
8013a9a: 687b ldr r3, [r7, #4]
8013a9c: f64f 72ff movw r2, #65535 ; 0xffff
8013aa0: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
if (pcb->bytes_acked >= pcb->cwnd) {
8013aa4: 687b ldr r3, [r7, #4]
8013aa6: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
8013aaa: 687b ldr r3, [r7, #4]
8013aac: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013ab0: 429a cmp r2, r3
8013ab2: d326 bcc.n 8013b02 <tcp_receive+0x362>
pcb->bytes_acked = (tcpwnd_size_t)(pcb->bytes_acked - pcb->cwnd);
8013ab4: 687b ldr r3, [r7, #4]
8013ab6: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
8013aba: 687b ldr r3, [r7, #4]
8013abc: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013ac0: 1ad3 subs r3, r2, r3
8013ac2: b29a uxth r2, r3
8013ac4: 687b ldr r3, [r7, #4]
8013ac6: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
TCP_WND_INC(pcb->cwnd, pcb->mss);
8013aca: 687b ldr r3, [r7, #4]
8013acc: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013ad0: 687b ldr r3, [r7, #4]
8013ad2: 8e5b ldrh r3, [r3, #50] ; 0x32
8013ad4: 4413 add r3, r2
8013ad6: b29a uxth r2, r3
8013ad8: 687b ldr r3, [r7, #4]
8013ada: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013ade: 429a cmp r2, r3
8013ae0: d30a bcc.n 8013af8 <tcp_receive+0x358>
8013ae2: 687b ldr r3, [r7, #4]
8013ae4: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013ae8: 687b ldr r3, [r7, #4]
8013aea: 8e5b ldrh r3, [r3, #50] ; 0x32
8013aec: 4413 add r3, r2
8013aee: b29a uxth r2, r3
8013af0: 687b ldr r3, [r7, #4]
8013af2: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
8013af6: e004 b.n 8013b02 <tcp_receive+0x362>
8013af8: 687b ldr r3, [r7, #4]
8013afa: f64f 72ff movw r2, #65535 ; 0xffff
8013afe: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
pcb->unacked != NULL ?
lwip_ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked) : 0));
/* Remove segment from the unacknowledged list if the incoming
ACK acknowledges them. */
pcb->unacked = tcp_free_acked_segments(pcb, pcb->unacked, "unacked", pcb->unsent);
8013b02: 687b ldr r3, [r7, #4]
8013b04: 6f19 ldr r1, [r3, #112] ; 0x70
8013b06: 687b ldr r3, [r7, #4]
8013b08: 6edb ldr r3, [r3, #108] ; 0x6c
8013b0a: 4a98 ldr r2, [pc, #608] ; (8013d6c <tcp_receive+0x5cc>)
8013b0c: 6878 ldr r0, [r7, #4]
8013b0e: f7ff fdcb bl 80136a8 <tcp_free_acked_segments>
8013b12: 4602 mov r2, r0
8013b14: 687b ldr r3, [r7, #4]
8013b16: 671a str r2, [r3, #112] ; 0x70
on the list are acknowledged by the ACK. This may seem
strange since an "unsent" segment shouldn't be acked. The
rationale is that lwIP puts all outstanding segments on the
->unsent list after a retransmission, so these segments may
in fact have been sent once. */
pcb->unsent = tcp_free_acked_segments(pcb, pcb->unsent, "unsent", pcb->unacked);
8013b18: 687b ldr r3, [r7, #4]
8013b1a: 6ed9 ldr r1, [r3, #108] ; 0x6c
8013b1c: 687b ldr r3, [r7, #4]
8013b1e: 6f1b ldr r3, [r3, #112] ; 0x70
8013b20: 4a93 ldr r2, [pc, #588] ; (8013d70 <tcp_receive+0x5d0>)
8013b22: 6878 ldr r0, [r7, #4]
8013b24: f7ff fdc0 bl 80136a8 <tcp_free_acked_segments>
8013b28: 4602 mov r2, r0
8013b2a: 687b ldr r3, [r7, #4]
8013b2c: 66da str r2, [r3, #108] ; 0x6c
/* If there's nothing left to acknowledge, stop the retransmit
timer, otherwise reset it to start again */
if (pcb->unacked == NULL) {
8013b2e: 687b ldr r3, [r7, #4]
8013b30: 6f1b ldr r3, [r3, #112] ; 0x70
8013b32: 2b00 cmp r3, #0
8013b34: d104 bne.n 8013b40 <tcp_receive+0x3a0>
pcb->rtime = -1;
8013b36: 687b ldr r3, [r7, #4]
8013b38: f64f 72ff movw r2, #65535 ; 0xffff
8013b3c: 861a strh r2, [r3, #48] ; 0x30
8013b3e: e002 b.n 8013b46 <tcp_receive+0x3a6>
} else {
pcb->rtime = 0;
8013b40: 687b ldr r3, [r7, #4]
8013b42: 2200 movs r2, #0
8013b44: 861a strh r2, [r3, #48] ; 0x30
}
pcb->polltmr = 0;
8013b46: 687b ldr r3, [r7, #4]
8013b48: 2200 movs r2, #0
8013b4a: 771a strb r2, [r3, #28]
#if TCP_OVERSIZE
if (pcb->unsent == NULL) {
8013b4c: 687b ldr r3, [r7, #4]
8013b4e: 6edb ldr r3, [r3, #108] ; 0x6c
8013b50: 2b00 cmp r3, #0
8013b52: d103 bne.n 8013b5c <tcp_receive+0x3bc>
pcb->unsent_oversize = 0;
8013b54: 687b ldr r3, [r7, #4]
8013b56: 2200 movs r2, #0
8013b58: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
/* Inform neighbor reachability of forward progress. */
nd6_reachability_hint(ip6_current_src_addr());
}
#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/
pcb->snd_buf = (tcpwnd_size_t)(pcb->snd_buf + recv_acked);
8013b5c: 687b ldr r3, [r7, #4]
8013b5e: f8b3 2064 ldrh.w r2, [r3, #100] ; 0x64
8013b62: 4b84 ldr r3, [pc, #528] ; (8013d74 <tcp_receive+0x5d4>)
8013b64: 881b ldrh r3, [r3, #0]
8013b66: 4413 add r3, r2
8013b68: b29a uxth r2, r3
8013b6a: 687b ldr r3, [r7, #4]
8013b6c: f8a3 2064 strh.w r2, [r3, #100] ; 0x64
/* check if this ACK ends our retransmission of in-flight data */
if (pcb->flags & TF_RTO) {
8013b70: 687b ldr r3, [r7, #4]
8013b72: 8b5b ldrh r3, [r3, #26]
8013b74: f403 6300 and.w r3, r3, #2048 ; 0x800
8013b78: 2b00 cmp r3, #0
8013b7a: d035 beq.n 8013be8 <tcp_receive+0x448>
/* RTO is done if
1) both queues are empty or
2) unacked is empty and unsent head contains data not part of RTO or
3) unacked head contains data not part of RTO */
if (pcb->unacked == NULL) {
8013b7c: 687b ldr r3, [r7, #4]
8013b7e: 6f1b ldr r3, [r3, #112] ; 0x70
8013b80: 2b00 cmp r3, #0
8013b82: d118 bne.n 8013bb6 <tcp_receive+0x416>
if ((pcb->unsent == NULL) ||
8013b84: 687b ldr r3, [r7, #4]
8013b86: 6edb ldr r3, [r3, #108] ; 0x6c
8013b88: 2b00 cmp r3, #0
8013b8a: d00c beq.n 8013ba6 <tcp_receive+0x406>
(TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unsent->tcphdr->seqno)))) {
8013b8c: 687b ldr r3, [r7, #4]
8013b8e: 6cdc ldr r4, [r3, #76] ; 0x4c
8013b90: 687b ldr r3, [r7, #4]
8013b92: 6edb ldr r3, [r3, #108] ; 0x6c
8013b94: 68db ldr r3, [r3, #12]
8013b96: 685b ldr r3, [r3, #4]
8013b98: 4618 mov r0, r3
8013b9a: f7fb f964 bl 800ee66 <lwip_htonl>
8013b9e: 4603 mov r3, r0
8013ba0: 1ae3 subs r3, r4, r3
if ((pcb->unsent == NULL) ||
8013ba2: 2b00 cmp r3, #0
8013ba4: dc20 bgt.n 8013be8 <tcp_receive+0x448>
tcp_clear_flags(pcb, TF_RTO);
8013ba6: 687b ldr r3, [r7, #4]
8013ba8: 8b5b ldrh r3, [r3, #26]
8013baa: f423 6300 bic.w r3, r3, #2048 ; 0x800
8013bae: b29a uxth r2, r3
8013bb0: 687b ldr r3, [r7, #4]
8013bb2: 835a strh r2, [r3, #26]
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013bb4: e018 b.n 8013be8 <tcp_receive+0x448>
}
} else if (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unacked->tcphdr->seqno))) {
8013bb6: 687b ldr r3, [r7, #4]
8013bb8: 6cdc ldr r4, [r3, #76] ; 0x4c
8013bba: 687b ldr r3, [r7, #4]
8013bbc: 6f1b ldr r3, [r3, #112] ; 0x70
8013bbe: 68db ldr r3, [r3, #12]
8013bc0: 685b ldr r3, [r3, #4]
8013bc2: 4618 mov r0, r3
8013bc4: f7fb f94f bl 800ee66 <lwip_htonl>
8013bc8: 4603 mov r3, r0
8013bca: 1ae3 subs r3, r4, r3
8013bcc: 2b00 cmp r3, #0
8013bce: dc0b bgt.n 8013be8 <tcp_receive+0x448>
tcp_clear_flags(pcb, TF_RTO);
8013bd0: 687b ldr r3, [r7, #4]
8013bd2: 8b5b ldrh r3, [r3, #26]
8013bd4: f423 6300 bic.w r3, r3, #2048 ; 0x800
8013bd8: b29a uxth r2, r3
8013bda: 687b ldr r3, [r7, #4]
8013bdc: 835a strh r2, [r3, #26]
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013bde: e003 b.n 8013be8 <tcp_receive+0x448>
}
}
/* End of ACK for new data processing. */
} else {
/* Out of sequence ACK, didn't really ack anything */
tcp_send_empty_ack(pcb);
8013be0: 6878 ldr r0, [r7, #4]
8013be2: f001 ff75 bl 8015ad0 <tcp_send_empty_ack>
8013be6: e000 b.n 8013bea <tcp_receive+0x44a>
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013be8: bf00 nop
pcb->rttest, pcb->rtseq, ackno));
/* RTT estimation calculations. This is done by checking if the
incoming segment acknowledges the segment we use to take a
round-trip time measurement. */
if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
8013bea: 687b ldr r3, [r7, #4]
8013bec: 6b5b ldr r3, [r3, #52] ; 0x34
8013bee: 2b00 cmp r3, #0
8013bf0: d05b beq.n 8013caa <tcp_receive+0x50a>
8013bf2: 687b ldr r3, [r7, #4]
8013bf4: 6b9a ldr r2, [r3, #56] ; 0x38
8013bf6: 4b60 ldr r3, [pc, #384] ; (8013d78 <tcp_receive+0x5d8>)
8013bf8: 681b ldr r3, [r3, #0]
8013bfa: 1ad3 subs r3, r2, r3
8013bfc: 2b00 cmp r3, #0
8013bfe: da54 bge.n 8013caa <tcp_receive+0x50a>
/* diff between this shouldn't exceed 32K since this are tcp timer ticks
and a round-trip shouldn't be that long... */
m = (s16_t)(tcp_ticks - pcb->rttest);
8013c00: 4b5e ldr r3, [pc, #376] ; (8013d7c <tcp_receive+0x5dc>)
8013c02: 681b ldr r3, [r3, #0]
8013c04: b29a uxth r2, r3
8013c06: 687b ldr r3, [r7, #4]
8013c08: 6b5b ldr r3, [r3, #52] ; 0x34
8013c0a: b29b uxth r3, r3
8013c0c: 1ad3 subs r3, r2, r3
8013c0e: b29b uxth r3, r3
8013c10: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
m, (u16_t)(m * TCP_SLOW_INTERVAL)));
/* This is taken directly from VJs original code in his paper */
m = (s16_t)(m - (pcb->sa >> 3));
8013c14: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e
8013c18: 687b ldr r3, [r7, #4]
8013c1a: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
8013c1e: 10db asrs r3, r3, #3
8013c20: b21b sxth r3, r3
8013c22: b29b uxth r3, r3
8013c24: 1ad3 subs r3, r2, r3
8013c26: b29b uxth r3, r3
8013c28: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
pcb->sa = (s16_t)(pcb->sa + m);
8013c2c: 687b ldr r3, [r7, #4]
8013c2e: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
8013c32: b29a uxth r2, r3
8013c34: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e
8013c38: 4413 add r3, r2
8013c3a: b29b uxth r3, r3
8013c3c: b21a sxth r2, r3
8013c3e: 687b ldr r3, [r7, #4]
8013c40: 879a strh r2, [r3, #60] ; 0x3c
if (m < 0) {
8013c42: f9b7 304e ldrsh.w r3, [r7, #78] ; 0x4e
8013c46: 2b00 cmp r3, #0
8013c48: da05 bge.n 8013c56 <tcp_receive+0x4b6>
m = (s16_t) - m;
8013c4a: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e
8013c4e: 425b negs r3, r3
8013c50: b29b uxth r3, r3
8013c52: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
}
m = (s16_t)(m - (pcb->sv >> 2));
8013c56: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e
8013c5a: 687b ldr r3, [r7, #4]
8013c5c: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
8013c60: 109b asrs r3, r3, #2
8013c62: b21b sxth r3, r3
8013c64: b29b uxth r3, r3
8013c66: 1ad3 subs r3, r2, r3
8013c68: b29b uxth r3, r3
8013c6a: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
pcb->sv = (s16_t)(pcb->sv + m);
8013c6e: 687b ldr r3, [r7, #4]
8013c70: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
8013c74: b29a uxth r2, r3
8013c76: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e
8013c7a: 4413 add r3, r2
8013c7c: b29b uxth r3, r3
8013c7e: b21a sxth r2, r3
8013c80: 687b ldr r3, [r7, #4]
8013c82: 87da strh r2, [r3, #62] ; 0x3e
pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
8013c84: 687b ldr r3, [r7, #4]
8013c86: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
8013c8a: 10db asrs r3, r3, #3
8013c8c: b21b sxth r3, r3
8013c8e: b29a uxth r2, r3
8013c90: 687b ldr r3, [r7, #4]
8013c92: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
8013c96: b29b uxth r3, r3
8013c98: 4413 add r3, r2
8013c9a: b29b uxth r3, r3
8013c9c: b21a sxth r2, r3
8013c9e: 687b ldr r3, [r7, #4]
8013ca0: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n",
pcb->rto, (u16_t)(pcb->rto * TCP_SLOW_INTERVAL)));
pcb->rttest = 0;
8013ca4: 687b ldr r3, [r7, #4]
8013ca6: 2200 movs r2, #0
8013ca8: 635a str r2, [r3, #52] ; 0x34
/* If the incoming segment contains data, we must process it
further unless the pcb already received a FIN.
(RFC 793, chapter 3.9, "SEGMENT ARRIVES" in states CLOSE-WAIT, CLOSING,
LAST-ACK and TIME-WAIT: "Ignore the segment text.") */
if ((tcplen > 0) && (pcb->state < CLOSE_WAIT)) {
8013caa: 4b35 ldr r3, [pc, #212] ; (8013d80 <tcp_receive+0x5e0>)
8013cac: 881b ldrh r3, [r3, #0]
8013cae: 2b00 cmp r3, #0
8013cb0: f000 84e1 beq.w 8014676 <tcp_receive+0xed6>
8013cb4: 687b ldr r3, [r7, #4]
8013cb6: 7d1b ldrb r3, [r3, #20]
8013cb8: 2b06 cmp r3, #6
8013cba: f200 84dc bhi.w 8014676 <tcp_receive+0xed6>
this if the sequence number of the incoming segment is less
than rcv_nxt, and the sequence number plus the length of the
segment is larger than rcv_nxt. */
/* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
8013cbe: 687b ldr r3, [r7, #4]
8013cc0: 6a5a ldr r2, [r3, #36] ; 0x24
8013cc2: 4b30 ldr r3, [pc, #192] ; (8013d84 <tcp_receive+0x5e4>)
8013cc4: 681b ldr r3, [r3, #0]
8013cc6: 1ad3 subs r3, r2, r3
8013cc8: 3b01 subs r3, #1
8013cca: 2b00 cmp r3, #0
8013ccc: f2c0 808e blt.w 8013dec <tcp_receive+0x64c>
8013cd0: 687b ldr r3, [r7, #4]
8013cd2: 6a5a ldr r2, [r3, #36] ; 0x24
8013cd4: 4b2a ldr r3, [pc, #168] ; (8013d80 <tcp_receive+0x5e0>)
8013cd6: 881b ldrh r3, [r3, #0]
8013cd8: 4619 mov r1, r3
8013cda: 4b2a ldr r3, [pc, #168] ; (8013d84 <tcp_receive+0x5e4>)
8013cdc: 681b ldr r3, [r3, #0]
8013cde: 440b add r3, r1
8013ce0: 1ad3 subs r3, r2, r3
8013ce2: 3301 adds r3, #1
8013ce4: 2b00 cmp r3, #0
8013ce6: f300 8081 bgt.w 8013dec <tcp_receive+0x64c>
After we are done with adjusting the pbuf pointers we must
adjust the ->data pointer in the seg and the segment
length.*/
struct pbuf *p = inseg.p;
8013cea: 4b27 ldr r3, [pc, #156] ; (8013d88 <tcp_receive+0x5e8>)
8013cec: 685b ldr r3, [r3, #4]
8013cee: 647b str r3, [r7, #68] ; 0x44
u32_t off32 = pcb->rcv_nxt - seqno;
8013cf0: 687b ldr r3, [r7, #4]
8013cf2: 6a5a ldr r2, [r3, #36] ; 0x24
8013cf4: 4b23 ldr r3, [pc, #140] ; (8013d84 <tcp_receive+0x5e4>)
8013cf6: 681b ldr r3, [r3, #0]
8013cf8: 1ad3 subs r3, r2, r3
8013cfa: 627b str r3, [r7, #36] ; 0x24
u16_t new_tot_len, off;
LWIP_ASSERT("inseg.p != NULL", inseg.p);
8013cfc: 4b22 ldr r3, [pc, #136] ; (8013d88 <tcp_receive+0x5e8>)
8013cfe: 685b ldr r3, [r3, #4]
8013d00: 2b00 cmp r3, #0
8013d02: d106 bne.n 8013d12 <tcp_receive+0x572>
8013d04: 4b21 ldr r3, [pc, #132] ; (8013d8c <tcp_receive+0x5ec>)
8013d06: f240 5294 movw r2, #1428 ; 0x594
8013d0a: 4921 ldr r1, [pc, #132] ; (8013d90 <tcp_receive+0x5f0>)
8013d0c: 4821 ldr r0, [pc, #132] ; (8013d94 <tcp_receive+0x5f4>)
8013d0e: f007 f959 bl 801afc4 <iprintf>
LWIP_ASSERT("insane offset!", (off32 < 0xffff));
8013d12: 6a7b ldr r3, [r7, #36] ; 0x24
8013d14: f64f 72fe movw r2, #65534 ; 0xfffe
8013d18: 4293 cmp r3, r2
8013d1a: d906 bls.n 8013d2a <tcp_receive+0x58a>
8013d1c: 4b1b ldr r3, [pc, #108] ; (8013d8c <tcp_receive+0x5ec>)
8013d1e: f240 5295 movw r2, #1429 ; 0x595
8013d22: 491d ldr r1, [pc, #116] ; (8013d98 <tcp_receive+0x5f8>)
8013d24: 481b ldr r0, [pc, #108] ; (8013d94 <tcp_receive+0x5f4>)
8013d26: f007 f94d bl 801afc4 <iprintf>
off = (u16_t)off32;
8013d2a: 6a7b ldr r3, [r7, #36] ; 0x24
8013d2c: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off));
8013d30: 4b15 ldr r3, [pc, #84] ; (8013d88 <tcp_receive+0x5e8>)
8013d32: 685b ldr r3, [r3, #4]
8013d34: 891b ldrh r3, [r3, #8]
8013d36: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
8013d3a: 429a cmp r2, r3
8013d3c: d906 bls.n 8013d4c <tcp_receive+0x5ac>
8013d3e: 4b13 ldr r3, [pc, #76] ; (8013d8c <tcp_receive+0x5ec>)
8013d40: f240 5297 movw r2, #1431 ; 0x597
8013d44: 4915 ldr r1, [pc, #84] ; (8013d9c <tcp_receive+0x5fc>)
8013d46: 4813 ldr r0, [pc, #76] ; (8013d94 <tcp_receive+0x5f4>)
8013d48: f007 f93c bl 801afc4 <iprintf>
inseg.len -= off;
8013d4c: 4b0e ldr r3, [pc, #56] ; (8013d88 <tcp_receive+0x5e8>)
8013d4e: 891a ldrh r2, [r3, #8]
8013d50: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
8013d54: 1ad3 subs r3, r2, r3
8013d56: b29a uxth r2, r3
8013d58: 4b0b ldr r3, [pc, #44] ; (8013d88 <tcp_receive+0x5e8>)
8013d5a: 811a strh r2, [r3, #8]
new_tot_len = (u16_t)(inseg.p->tot_len - off);
8013d5c: 4b0a ldr r3, [pc, #40] ; (8013d88 <tcp_receive+0x5e8>)
8013d5e: 685b ldr r3, [r3, #4]
8013d60: 891a ldrh r2, [r3, #8]
8013d62: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
8013d66: 1ad3 subs r3, r2, r3
8013d68: 847b strh r3, [r7, #34] ; 0x22
while (p->len < off) {
8013d6a: e029 b.n 8013dc0 <tcp_receive+0x620>
8013d6c: 0801d7ec .word 0x0801d7ec
8013d70: 0801d7f4 .word 0x0801d7f4
8013d74: 20008748 .word 0x20008748
8013d78: 20008744 .word 0x20008744
8013d7c: 2000f840 .word 0x2000f840
8013d80: 2000874a .word 0x2000874a
8013d84: 20008740 .word 0x20008740
8013d88: 20008720 .word 0x20008720
8013d8c: 0801d484 .word 0x0801d484
8013d90: 0801d7fc .word 0x0801d7fc
8013d94: 0801d4d0 .word 0x0801d4d0
8013d98: 0801d80c .word 0x0801d80c
8013d9c: 0801d81c .word 0x0801d81c
off -= p->len;
8013da0: 6c7b ldr r3, [r7, #68] ; 0x44
8013da2: 895b ldrh r3, [r3, #10]
8013da4: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
8013da8: 1ad3 subs r3, r2, r3
8013daa: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
/* all pbufs up to and including this one have len==0, so tot_len is equal */
p->tot_len = new_tot_len;
8013dae: 6c7b ldr r3, [r7, #68] ; 0x44
8013db0: 8c7a ldrh r2, [r7, #34] ; 0x22
8013db2: 811a strh r2, [r3, #8]
p->len = 0;
8013db4: 6c7b ldr r3, [r7, #68] ; 0x44
8013db6: 2200 movs r2, #0
8013db8: 815a strh r2, [r3, #10]
p = p->next;
8013dba: 6c7b ldr r3, [r7, #68] ; 0x44
8013dbc: 681b ldr r3, [r3, #0]
8013dbe: 647b str r3, [r7, #68] ; 0x44
while (p->len < off) {
8013dc0: 6c7b ldr r3, [r7, #68] ; 0x44
8013dc2: 895b ldrh r3, [r3, #10]
8013dc4: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
8013dc8: 429a cmp r2, r3
8013dca: d8e9 bhi.n 8013da0 <tcp_receive+0x600>
}
/* cannot fail... */
pbuf_remove_header(p, off);
8013dcc: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
8013dd0: 4619 mov r1, r3
8013dd2: 6c78 ldr r0, [r7, #68] ; 0x44
8013dd4: f7fc fb64 bl 80104a0 <pbuf_remove_header>
inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
8013dd8: 687b ldr r3, [r7, #4]
8013dda: 6a5b ldr r3, [r3, #36] ; 0x24
8013ddc: 4a91 ldr r2, [pc, #580] ; (8014024 <tcp_receive+0x884>)
8013dde: 6013 str r3, [r2, #0]
8013de0: 4b91 ldr r3, [pc, #580] ; (8014028 <tcp_receive+0x888>)
8013de2: 68db ldr r3, [r3, #12]
8013de4: 4a8f ldr r2, [pc, #572] ; (8014024 <tcp_receive+0x884>)
8013de6: 6812 ldr r2, [r2, #0]
8013de8: 605a str r2, [r3, #4]
if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
8013dea: e00d b.n 8013e08 <tcp_receive+0x668>
} else {
if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
8013dec: 4b8d ldr r3, [pc, #564] ; (8014024 <tcp_receive+0x884>)
8013dee: 681a ldr r2, [r3, #0]
8013df0: 687b ldr r3, [r7, #4]
8013df2: 6a5b ldr r3, [r3, #36] ; 0x24
8013df4: 1ad3 subs r3, r2, r3
8013df6: 2b00 cmp r3, #0
8013df8: da06 bge.n 8013e08 <tcp_receive+0x668>
/* the whole segment is < rcv_nxt */
/* must be a duplicate of a packet that has already been correctly handled */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
tcp_ack_now(pcb);
8013dfa: 687b ldr r3, [r7, #4]
8013dfc: 8b5b ldrh r3, [r3, #26]
8013dfe: f043 0302 orr.w r3, r3, #2
8013e02: b29a uxth r2, r3
8013e04: 687b ldr r3, [r7, #4]
8013e06: 835a strh r2, [r3, #26]
}
/* The sequence number must be within the window (above rcv_nxt
and below rcv_nxt + rcv_wnd) in order to be further
processed. */
if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
8013e08: 4b86 ldr r3, [pc, #536] ; (8014024 <tcp_receive+0x884>)
8013e0a: 681a ldr r2, [r3, #0]
8013e0c: 687b ldr r3, [r7, #4]
8013e0e: 6a5b ldr r3, [r3, #36] ; 0x24
8013e10: 1ad3 subs r3, r2, r3
8013e12: 2b00 cmp r3, #0
8013e14: f2c0 842a blt.w 801466c <tcp_receive+0xecc>
8013e18: 4b82 ldr r3, [pc, #520] ; (8014024 <tcp_receive+0x884>)
8013e1a: 681a ldr r2, [r3, #0]
8013e1c: 687b ldr r3, [r7, #4]
8013e1e: 6a5b ldr r3, [r3, #36] ; 0x24
8013e20: 6879 ldr r1, [r7, #4]
8013e22: 8d09 ldrh r1, [r1, #40] ; 0x28
8013e24: 440b add r3, r1
8013e26: 1ad3 subs r3, r2, r3
8013e28: 3301 adds r3, #1
8013e2a: 2b00 cmp r3, #0
8013e2c: f300 841e bgt.w 801466c <tcp_receive+0xecc>
pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
if (pcb->rcv_nxt == seqno) {
8013e30: 687b ldr r3, [r7, #4]
8013e32: 6a5a ldr r2, [r3, #36] ; 0x24
8013e34: 4b7b ldr r3, [pc, #492] ; (8014024 <tcp_receive+0x884>)
8013e36: 681b ldr r3, [r3, #0]
8013e38: 429a cmp r2, r3
8013e3a: f040 829a bne.w 8014372 <tcp_receive+0xbd2>
/* The incoming segment is the next in sequence. We check if
we have to trim the end of the segment and update rcv_nxt
and pass the data to the application. */
tcplen = TCP_TCPLEN(&inseg);
8013e3e: 4b7a ldr r3, [pc, #488] ; (8014028 <tcp_receive+0x888>)
8013e40: 891c ldrh r4, [r3, #8]
8013e42: 4b79 ldr r3, [pc, #484] ; (8014028 <tcp_receive+0x888>)
8013e44: 68db ldr r3, [r3, #12]
8013e46: 899b ldrh r3, [r3, #12]
8013e48: b29b uxth r3, r3
8013e4a: 4618 mov r0, r3
8013e4c: f7fa fff6 bl 800ee3c <lwip_htons>
8013e50: 4603 mov r3, r0
8013e52: b2db uxtb r3, r3
8013e54: f003 0303 and.w r3, r3, #3
8013e58: 2b00 cmp r3, #0
8013e5a: d001 beq.n 8013e60 <tcp_receive+0x6c0>
8013e5c: 2301 movs r3, #1
8013e5e: e000 b.n 8013e62 <tcp_receive+0x6c2>
8013e60: 2300 movs r3, #0
8013e62: 4423 add r3, r4
8013e64: b29a uxth r2, r3
8013e66: 4b71 ldr r3, [pc, #452] ; (801402c <tcp_receive+0x88c>)
8013e68: 801a strh r2, [r3, #0]
if (tcplen > pcb->rcv_wnd) {
8013e6a: 687b ldr r3, [r7, #4]
8013e6c: 8d1a ldrh r2, [r3, #40] ; 0x28
8013e6e: 4b6f ldr r3, [pc, #444] ; (801402c <tcp_receive+0x88c>)
8013e70: 881b ldrh r3, [r3, #0]
8013e72: 429a cmp r2, r3
8013e74: d275 bcs.n 8013f62 <tcp_receive+0x7c2>
LWIP_DEBUGF(TCP_INPUT_DEBUG,
("tcp_receive: other end overran receive window"
"seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
8013e76: 4b6c ldr r3, [pc, #432] ; (8014028 <tcp_receive+0x888>)
8013e78: 68db ldr r3, [r3, #12]
8013e7a: 899b ldrh r3, [r3, #12]
8013e7c: b29b uxth r3, r3
8013e7e: 4618 mov r0, r3
8013e80: f7fa ffdc bl 800ee3c <lwip_htons>
8013e84: 4603 mov r3, r0
8013e86: b2db uxtb r3, r3
8013e88: f003 0301 and.w r3, r3, #1
8013e8c: 2b00 cmp r3, #0
8013e8e: d01f beq.n 8013ed0 <tcp_receive+0x730>
/* Must remove the FIN from the header as we're trimming
* that byte of sequence-space from the packet */
TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) & ~(unsigned int)TCP_FIN);
8013e90: 4b65 ldr r3, [pc, #404] ; (8014028 <tcp_receive+0x888>)
8013e92: 68db ldr r3, [r3, #12]
8013e94: 899b ldrh r3, [r3, #12]
8013e96: b29b uxth r3, r3
8013e98: b21b sxth r3, r3
8013e9a: f423 537c bic.w r3, r3, #16128 ; 0x3f00
8013e9e: b21c sxth r4, r3
8013ea0: 4b61 ldr r3, [pc, #388] ; (8014028 <tcp_receive+0x888>)
8013ea2: 68db ldr r3, [r3, #12]
8013ea4: 899b ldrh r3, [r3, #12]
8013ea6: b29b uxth r3, r3
8013ea8: 4618 mov r0, r3
8013eaa: f7fa ffc7 bl 800ee3c <lwip_htons>
8013eae: 4603 mov r3, r0
8013eb0: b2db uxtb r3, r3
8013eb2: b29b uxth r3, r3
8013eb4: f003 033e and.w r3, r3, #62 ; 0x3e
8013eb8: b29b uxth r3, r3
8013eba: 4618 mov r0, r3
8013ebc: f7fa ffbe bl 800ee3c <lwip_htons>
8013ec0: 4603 mov r3, r0
8013ec2: b21b sxth r3, r3
8013ec4: 4323 orrs r3, r4
8013ec6: b21a sxth r2, r3
8013ec8: 4b57 ldr r3, [pc, #348] ; (8014028 <tcp_receive+0x888>)
8013eca: 68db ldr r3, [r3, #12]
8013ecc: b292 uxth r2, r2
8013ece: 819a strh r2, [r3, #12]
}
/* Adjust length of segment to fit in the window. */
TCPWND_CHECK16(pcb->rcv_wnd);
inseg.len = (u16_t)pcb->rcv_wnd;
8013ed0: 687b ldr r3, [r7, #4]
8013ed2: 8d1a ldrh r2, [r3, #40] ; 0x28
8013ed4: 4b54 ldr r3, [pc, #336] ; (8014028 <tcp_receive+0x888>)
8013ed6: 811a strh r2, [r3, #8]
if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
8013ed8: 4b53 ldr r3, [pc, #332] ; (8014028 <tcp_receive+0x888>)
8013eda: 68db ldr r3, [r3, #12]
8013edc: 899b ldrh r3, [r3, #12]
8013ede: b29b uxth r3, r3
8013ee0: 4618 mov r0, r3
8013ee2: f7fa ffab bl 800ee3c <lwip_htons>
8013ee6: 4603 mov r3, r0
8013ee8: b2db uxtb r3, r3
8013eea: f003 0302 and.w r3, r3, #2
8013eee: 2b00 cmp r3, #0
8013ef0: d005 beq.n 8013efe <tcp_receive+0x75e>
inseg.len -= 1;
8013ef2: 4b4d ldr r3, [pc, #308] ; (8014028 <tcp_receive+0x888>)
8013ef4: 891b ldrh r3, [r3, #8]
8013ef6: 3b01 subs r3, #1
8013ef8: b29a uxth r2, r3
8013efa: 4b4b ldr r3, [pc, #300] ; (8014028 <tcp_receive+0x888>)
8013efc: 811a strh r2, [r3, #8]
}
pbuf_realloc(inseg.p, inseg.len);
8013efe: 4b4a ldr r3, [pc, #296] ; (8014028 <tcp_receive+0x888>)
8013f00: 685b ldr r3, [r3, #4]
8013f02: 4a49 ldr r2, [pc, #292] ; (8014028 <tcp_receive+0x888>)
8013f04: 8912 ldrh r2, [r2, #8]
8013f06: 4611 mov r1, r2
8013f08: 4618 mov r0, r3
8013f0a: f7fc f9c9 bl 80102a0 <pbuf_realloc>
tcplen = TCP_TCPLEN(&inseg);
8013f0e: 4b46 ldr r3, [pc, #280] ; (8014028 <tcp_receive+0x888>)
8013f10: 891c ldrh r4, [r3, #8]
8013f12: 4b45 ldr r3, [pc, #276] ; (8014028 <tcp_receive+0x888>)
8013f14: 68db ldr r3, [r3, #12]
8013f16: 899b ldrh r3, [r3, #12]
8013f18: b29b uxth r3, r3
8013f1a: 4618 mov r0, r3
8013f1c: f7fa ff8e bl 800ee3c <lwip_htons>
8013f20: 4603 mov r3, r0
8013f22: b2db uxtb r3, r3
8013f24: f003 0303 and.w r3, r3, #3
8013f28: 2b00 cmp r3, #0
8013f2a: d001 beq.n 8013f30 <tcp_receive+0x790>
8013f2c: 2301 movs r3, #1
8013f2e: e000 b.n 8013f32 <tcp_receive+0x792>
8013f30: 2300 movs r3, #0
8013f32: 4423 add r3, r4
8013f34: b29a uxth r2, r3
8013f36: 4b3d ldr r3, [pc, #244] ; (801402c <tcp_receive+0x88c>)
8013f38: 801a strh r2, [r3, #0]
LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
8013f3a: 4b3c ldr r3, [pc, #240] ; (801402c <tcp_receive+0x88c>)
8013f3c: 881b ldrh r3, [r3, #0]
8013f3e: 461a mov r2, r3
8013f40: 4b38 ldr r3, [pc, #224] ; (8014024 <tcp_receive+0x884>)
8013f42: 681b ldr r3, [r3, #0]
8013f44: 441a add r2, r3
8013f46: 687b ldr r3, [r7, #4]
8013f48: 6a5b ldr r3, [r3, #36] ; 0x24
8013f4a: 6879 ldr r1, [r7, #4]
8013f4c: 8d09 ldrh r1, [r1, #40] ; 0x28
8013f4e: 440b add r3, r1
8013f50: 429a cmp r2, r3
8013f52: d006 beq.n 8013f62 <tcp_receive+0x7c2>
8013f54: 4b36 ldr r3, [pc, #216] ; (8014030 <tcp_receive+0x890>)
8013f56: f240 52cb movw r2, #1483 ; 0x5cb
8013f5a: 4936 ldr r1, [pc, #216] ; (8014034 <tcp_receive+0x894>)
8013f5c: 4836 ldr r0, [pc, #216] ; (8014038 <tcp_receive+0x898>)
8013f5e: f007 f831 bl 801afc4 <iprintf>
}
#if TCP_QUEUE_OOSEQ
/* Received in-sequence data, adjust ooseq data if:
- FIN has been received or
- inseq overlaps with ooseq */
if (pcb->ooseq != NULL) {
8013f62: 687b ldr r3, [r7, #4]
8013f64: 6f5b ldr r3, [r3, #116] ; 0x74
8013f66: 2b00 cmp r3, #0
8013f68: f000 80e7 beq.w 801413a <tcp_receive+0x99a>
if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
8013f6c: 4b2e ldr r3, [pc, #184] ; (8014028 <tcp_receive+0x888>)
8013f6e: 68db ldr r3, [r3, #12]
8013f70: 899b ldrh r3, [r3, #12]
8013f72: b29b uxth r3, r3
8013f74: 4618 mov r0, r3
8013f76: f7fa ff61 bl 800ee3c <lwip_htons>
8013f7a: 4603 mov r3, r0
8013f7c: b2db uxtb r3, r3
8013f7e: f003 0301 and.w r3, r3, #1
8013f82: 2b00 cmp r3, #0
8013f84: d010 beq.n 8013fa8 <tcp_receive+0x808>
LWIP_DEBUGF(TCP_INPUT_DEBUG,
("tcp_receive: received in-order FIN, binning ooseq queue\n"));
/* Received in-order FIN means anything that was received
* out of order must now have been received in-order, so
* bin the ooseq queue */
while (pcb->ooseq != NULL) {
8013f86: e00a b.n 8013f9e <tcp_receive+0x7fe>
struct tcp_seg *old_ooseq = pcb->ooseq;
8013f88: 687b ldr r3, [r7, #4]
8013f8a: 6f5b ldr r3, [r3, #116] ; 0x74
8013f8c: 60fb str r3, [r7, #12]
pcb->ooseq = pcb->ooseq->next;
8013f8e: 687b ldr r3, [r7, #4]
8013f90: 6f5b ldr r3, [r3, #116] ; 0x74
8013f92: 681a ldr r2, [r3, #0]
8013f94: 687b ldr r3, [r7, #4]
8013f96: 675a str r2, [r3, #116] ; 0x74
tcp_seg_free(old_ooseq);
8013f98: 68f8 ldr r0, [r7, #12]
8013f9a: f7fd fd96 bl 8011aca <tcp_seg_free>
while (pcb->ooseq != NULL) {
8013f9e: 687b ldr r3, [r7, #4]
8013fa0: 6f5b ldr r3, [r3, #116] ; 0x74
8013fa2: 2b00 cmp r3, #0
8013fa4: d1f0 bne.n 8013f88 <tcp_receive+0x7e8>
8013fa6: e0c8 b.n 801413a <tcp_receive+0x99a>
}
} else {
struct tcp_seg *next = pcb->ooseq;
8013fa8: 687b ldr r3, [r7, #4]
8013faa: 6f5b ldr r3, [r3, #116] ; 0x74
8013fac: 63fb str r3, [r7, #60] ; 0x3c
/* Remove all segments on ooseq that are covered by inseg already.
* FIN is copied from ooseq to inseg if present. */
while (next &&
8013fae: e052 b.n 8014056 <tcp_receive+0x8b6>
TCP_SEQ_GEQ(seqno + tcplen,
next->tcphdr->seqno + next->len)) {
struct tcp_seg *tmp;
/* inseg cannot have FIN here (already processed above) */
if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
8013fb0: 6bfb ldr r3, [r7, #60] ; 0x3c
8013fb2: 68db ldr r3, [r3, #12]
8013fb4: 899b ldrh r3, [r3, #12]
8013fb6: b29b uxth r3, r3
8013fb8: 4618 mov r0, r3
8013fba: f7fa ff3f bl 800ee3c <lwip_htons>
8013fbe: 4603 mov r3, r0
8013fc0: b2db uxtb r3, r3
8013fc2: f003 0301 and.w r3, r3, #1
8013fc6: 2b00 cmp r3, #0
8013fc8: d03d beq.n 8014046 <tcp_receive+0x8a6>
(TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) {
8013fca: 4b17 ldr r3, [pc, #92] ; (8014028 <tcp_receive+0x888>)
8013fcc: 68db ldr r3, [r3, #12]
8013fce: 899b ldrh r3, [r3, #12]
8013fd0: b29b uxth r3, r3
8013fd2: 4618 mov r0, r3
8013fd4: f7fa ff32 bl 800ee3c <lwip_htons>
8013fd8: 4603 mov r3, r0
8013fda: b2db uxtb r3, r3
8013fdc: f003 0302 and.w r3, r3, #2
if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
8013fe0: 2b00 cmp r3, #0
8013fe2: d130 bne.n 8014046 <tcp_receive+0x8a6>
TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN);
8013fe4: 4b10 ldr r3, [pc, #64] ; (8014028 <tcp_receive+0x888>)
8013fe6: 68db ldr r3, [r3, #12]
8013fe8: 899b ldrh r3, [r3, #12]
8013fea: b29c uxth r4, r3
8013fec: 2001 movs r0, #1
8013fee: f7fa ff25 bl 800ee3c <lwip_htons>
8013ff2: 4603 mov r3, r0
8013ff4: 461a mov r2, r3
8013ff6: 4b0c ldr r3, [pc, #48] ; (8014028 <tcp_receive+0x888>)
8013ff8: 68db ldr r3, [r3, #12]
8013ffa: 4322 orrs r2, r4
8013ffc: b292 uxth r2, r2
8013ffe: 819a strh r2, [r3, #12]
tcplen = TCP_TCPLEN(&inseg);
8014000: 4b09 ldr r3, [pc, #36] ; (8014028 <tcp_receive+0x888>)
8014002: 891c ldrh r4, [r3, #8]
8014004: 4b08 ldr r3, [pc, #32] ; (8014028 <tcp_receive+0x888>)
8014006: 68db ldr r3, [r3, #12]
8014008: 899b ldrh r3, [r3, #12]
801400a: b29b uxth r3, r3
801400c: 4618 mov r0, r3
801400e: f7fa ff15 bl 800ee3c <lwip_htons>
8014012: 4603 mov r3, r0
8014014: b2db uxtb r3, r3
8014016: f003 0303 and.w r3, r3, #3
801401a: 2b00 cmp r3, #0
801401c: d00e beq.n 801403c <tcp_receive+0x89c>
801401e: 2301 movs r3, #1
8014020: e00d b.n 801403e <tcp_receive+0x89e>
8014022: bf00 nop
8014024: 20008740 .word 0x20008740
8014028: 20008720 .word 0x20008720
801402c: 2000874a .word 0x2000874a
8014030: 0801d484 .word 0x0801d484
8014034: 0801d82c .word 0x0801d82c
8014038: 0801d4d0 .word 0x0801d4d0
801403c: 2300 movs r3, #0
801403e: 4423 add r3, r4
8014040: b29a uxth r2, r3
8014042: 4b98 ldr r3, [pc, #608] ; (80142a4 <tcp_receive+0xb04>)
8014044: 801a strh r2, [r3, #0]
}
tmp = next;
8014046: 6bfb ldr r3, [r7, #60] ; 0x3c
8014048: 613b str r3, [r7, #16]
next = next->next;
801404a: 6bfb ldr r3, [r7, #60] ; 0x3c
801404c: 681b ldr r3, [r3, #0]
801404e: 63fb str r3, [r7, #60] ; 0x3c
tcp_seg_free(tmp);
8014050: 6938 ldr r0, [r7, #16]
8014052: f7fd fd3a bl 8011aca <tcp_seg_free>
while (next &&
8014056: 6bfb ldr r3, [r7, #60] ; 0x3c
8014058: 2b00 cmp r3, #0
801405a: d00e beq.n 801407a <tcp_receive+0x8da>
TCP_SEQ_GEQ(seqno + tcplen,
801405c: 4b91 ldr r3, [pc, #580] ; (80142a4 <tcp_receive+0xb04>)
801405e: 881b ldrh r3, [r3, #0]
8014060: 461a mov r2, r3
8014062: 4b91 ldr r3, [pc, #580] ; (80142a8 <tcp_receive+0xb08>)
8014064: 681b ldr r3, [r3, #0]
8014066: 441a add r2, r3
8014068: 6bfb ldr r3, [r7, #60] ; 0x3c
801406a: 68db ldr r3, [r3, #12]
801406c: 685b ldr r3, [r3, #4]
801406e: 6bf9 ldr r1, [r7, #60] ; 0x3c
8014070: 8909 ldrh r1, [r1, #8]
8014072: 440b add r3, r1
8014074: 1ad3 subs r3, r2, r3
while (next &&
8014076: 2b00 cmp r3, #0
8014078: da9a bge.n 8013fb0 <tcp_receive+0x810>
}
/* Now trim right side of inseg if it overlaps with the first
* segment on ooseq */
if (next &&
801407a: 6bfb ldr r3, [r7, #60] ; 0x3c
801407c: 2b00 cmp r3, #0
801407e: d059 beq.n 8014134 <tcp_receive+0x994>
TCP_SEQ_GT(seqno + tcplen,
8014080: 4b88 ldr r3, [pc, #544] ; (80142a4 <tcp_receive+0xb04>)
8014082: 881b ldrh r3, [r3, #0]
8014084: 461a mov r2, r3
8014086: 4b88 ldr r3, [pc, #544] ; (80142a8 <tcp_receive+0xb08>)
8014088: 681b ldr r3, [r3, #0]
801408a: 441a add r2, r3
801408c: 6bfb ldr r3, [r7, #60] ; 0x3c
801408e: 68db ldr r3, [r3, #12]
8014090: 685b ldr r3, [r3, #4]
8014092: 1ad3 subs r3, r2, r3
if (next &&
8014094: 2b00 cmp r3, #0
8014096: dd4d ble.n 8014134 <tcp_receive+0x994>
next->tcphdr->seqno)) {
/* inseg cannot have FIN here (already processed above) */
inseg.len = (u16_t)(next->tcphdr->seqno - seqno);
8014098: 6bfb ldr r3, [r7, #60] ; 0x3c
801409a: 68db ldr r3, [r3, #12]
801409c: 685b ldr r3, [r3, #4]
801409e: b29a uxth r2, r3
80140a0: 4b81 ldr r3, [pc, #516] ; (80142a8 <tcp_receive+0xb08>)
80140a2: 681b ldr r3, [r3, #0]
80140a4: b29b uxth r3, r3
80140a6: 1ad3 subs r3, r2, r3
80140a8: b29a uxth r2, r3
80140aa: 4b80 ldr r3, [pc, #512] ; (80142ac <tcp_receive+0xb0c>)
80140ac: 811a strh r2, [r3, #8]
if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
80140ae: 4b7f ldr r3, [pc, #508] ; (80142ac <tcp_receive+0xb0c>)
80140b0: 68db ldr r3, [r3, #12]
80140b2: 899b ldrh r3, [r3, #12]
80140b4: b29b uxth r3, r3
80140b6: 4618 mov r0, r3
80140b8: f7fa fec0 bl 800ee3c <lwip_htons>
80140bc: 4603 mov r3, r0
80140be: b2db uxtb r3, r3
80140c0: f003 0302 and.w r3, r3, #2
80140c4: 2b00 cmp r3, #0
80140c6: d005 beq.n 80140d4 <tcp_receive+0x934>
inseg.len -= 1;
80140c8: 4b78 ldr r3, [pc, #480] ; (80142ac <tcp_receive+0xb0c>)
80140ca: 891b ldrh r3, [r3, #8]
80140cc: 3b01 subs r3, #1
80140ce: b29a uxth r2, r3
80140d0: 4b76 ldr r3, [pc, #472] ; (80142ac <tcp_receive+0xb0c>)
80140d2: 811a strh r2, [r3, #8]
}
pbuf_realloc(inseg.p, inseg.len);
80140d4: 4b75 ldr r3, [pc, #468] ; (80142ac <tcp_receive+0xb0c>)
80140d6: 685b ldr r3, [r3, #4]
80140d8: 4a74 ldr r2, [pc, #464] ; (80142ac <tcp_receive+0xb0c>)
80140da: 8912 ldrh r2, [r2, #8]
80140dc: 4611 mov r1, r2
80140de: 4618 mov r0, r3
80140e0: f7fc f8de bl 80102a0 <pbuf_realloc>
tcplen = TCP_TCPLEN(&inseg);
80140e4: 4b71 ldr r3, [pc, #452] ; (80142ac <tcp_receive+0xb0c>)
80140e6: 891c ldrh r4, [r3, #8]
80140e8: 4b70 ldr r3, [pc, #448] ; (80142ac <tcp_receive+0xb0c>)
80140ea: 68db ldr r3, [r3, #12]
80140ec: 899b ldrh r3, [r3, #12]
80140ee: b29b uxth r3, r3
80140f0: 4618 mov r0, r3
80140f2: f7fa fea3 bl 800ee3c <lwip_htons>
80140f6: 4603 mov r3, r0
80140f8: b2db uxtb r3, r3
80140fa: f003 0303 and.w r3, r3, #3
80140fe: 2b00 cmp r3, #0
8014100: d001 beq.n 8014106 <tcp_receive+0x966>
8014102: 2301 movs r3, #1
8014104: e000 b.n 8014108 <tcp_receive+0x968>
8014106: 2300 movs r3, #0
8014108: 4423 add r3, r4
801410a: b29a uxth r2, r3
801410c: 4b65 ldr r3, [pc, #404] ; (80142a4 <tcp_receive+0xb04>)
801410e: 801a strh r2, [r3, #0]
LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n",
8014110: 4b64 ldr r3, [pc, #400] ; (80142a4 <tcp_receive+0xb04>)
8014112: 881b ldrh r3, [r3, #0]
8014114: 461a mov r2, r3
8014116: 4b64 ldr r3, [pc, #400] ; (80142a8 <tcp_receive+0xb08>)
8014118: 681b ldr r3, [r3, #0]
801411a: 441a add r2, r3
801411c: 6bfb ldr r3, [r7, #60] ; 0x3c
801411e: 68db ldr r3, [r3, #12]
8014120: 685b ldr r3, [r3, #4]
8014122: 429a cmp r2, r3
8014124: d006 beq.n 8014134 <tcp_receive+0x994>
8014126: 4b62 ldr r3, [pc, #392] ; (80142b0 <tcp_receive+0xb10>)
8014128: f240 52fc movw r2, #1532 ; 0x5fc
801412c: 4961 ldr r1, [pc, #388] ; (80142b4 <tcp_receive+0xb14>)
801412e: 4862 ldr r0, [pc, #392] ; (80142b8 <tcp_receive+0xb18>)
8014130: f006 ff48 bl 801afc4 <iprintf>
(seqno + tcplen) == next->tcphdr->seqno);
}
pcb->ooseq = next;
8014134: 687b ldr r3, [r7, #4]
8014136: 6bfa ldr r2, [r7, #60] ; 0x3c
8014138: 675a str r2, [r3, #116] ; 0x74
}
}
#endif /* TCP_QUEUE_OOSEQ */
pcb->rcv_nxt = seqno + tcplen;
801413a: 4b5a ldr r3, [pc, #360] ; (80142a4 <tcp_receive+0xb04>)
801413c: 881b ldrh r3, [r3, #0]
801413e: 461a mov r2, r3
8014140: 4b59 ldr r3, [pc, #356] ; (80142a8 <tcp_receive+0xb08>)
8014142: 681b ldr r3, [r3, #0]
8014144: 441a add r2, r3
8014146: 687b ldr r3, [r7, #4]
8014148: 625a str r2, [r3, #36] ; 0x24
/* Update the receiver's (our) window. */
LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen);
801414a: 687b ldr r3, [r7, #4]
801414c: 8d1a ldrh r2, [r3, #40] ; 0x28
801414e: 4b55 ldr r3, [pc, #340] ; (80142a4 <tcp_receive+0xb04>)
8014150: 881b ldrh r3, [r3, #0]
8014152: 429a cmp r2, r3
8014154: d206 bcs.n 8014164 <tcp_receive+0x9c4>
8014156: 4b56 ldr r3, [pc, #344] ; (80142b0 <tcp_receive+0xb10>)
8014158: f240 6207 movw r2, #1543 ; 0x607
801415c: 4957 ldr r1, [pc, #348] ; (80142bc <tcp_receive+0xb1c>)
801415e: 4856 ldr r0, [pc, #344] ; (80142b8 <tcp_receive+0xb18>)
8014160: f006 ff30 bl 801afc4 <iprintf>
pcb->rcv_wnd -= tcplen;
8014164: 687b ldr r3, [r7, #4]
8014166: 8d1a ldrh r2, [r3, #40] ; 0x28
8014168: 4b4e ldr r3, [pc, #312] ; (80142a4 <tcp_receive+0xb04>)
801416a: 881b ldrh r3, [r3, #0]
801416c: 1ad3 subs r3, r2, r3
801416e: b29a uxth r2, r3
8014170: 687b ldr r3, [r7, #4]
8014172: 851a strh r2, [r3, #40] ; 0x28
tcp_update_rcv_ann_wnd(pcb);
8014174: 6878 ldr r0, [r7, #4]
8014176: f7fc ffc9 bl 801110c <tcp_update_rcv_ann_wnd>
chains its data on this pbuf as well.
If the segment was a FIN, we set the TF_GOT_FIN flag that will
be used to indicate to the application that the remote side has
closed its end of the connection. */
if (inseg.p->tot_len > 0) {
801417a: 4b4c ldr r3, [pc, #304] ; (80142ac <tcp_receive+0xb0c>)
801417c: 685b ldr r3, [r3, #4]
801417e: 891b ldrh r3, [r3, #8]
8014180: 2b00 cmp r3, #0
8014182: d006 beq.n 8014192 <tcp_receive+0x9f2>
recv_data = inseg.p;
8014184: 4b49 ldr r3, [pc, #292] ; (80142ac <tcp_receive+0xb0c>)
8014186: 685b ldr r3, [r3, #4]
8014188: 4a4d ldr r2, [pc, #308] ; (80142c0 <tcp_receive+0xb20>)
801418a: 6013 str r3, [r2, #0]
/* Since this pbuf now is the responsibility of the
application, we delete our reference to it so that we won't
(mistakingly) deallocate it. */
inseg.p = NULL;
801418c: 4b47 ldr r3, [pc, #284] ; (80142ac <tcp_receive+0xb0c>)
801418e: 2200 movs r2, #0
8014190: 605a str r2, [r3, #4]
}
if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
8014192: 4b46 ldr r3, [pc, #280] ; (80142ac <tcp_receive+0xb0c>)
8014194: 68db ldr r3, [r3, #12]
8014196: 899b ldrh r3, [r3, #12]
8014198: b29b uxth r3, r3
801419a: 4618 mov r0, r3
801419c: f7fa fe4e bl 800ee3c <lwip_htons>
80141a0: 4603 mov r3, r0
80141a2: b2db uxtb r3, r3
80141a4: f003 0301 and.w r3, r3, #1
80141a8: 2b00 cmp r3, #0
80141aa: f000 80b8 beq.w 801431e <tcp_receive+0xb7e>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
recv_flags |= TF_GOT_FIN;
80141ae: 4b45 ldr r3, [pc, #276] ; (80142c4 <tcp_receive+0xb24>)
80141b0: 781b ldrb r3, [r3, #0]
80141b2: f043 0320 orr.w r3, r3, #32
80141b6: b2da uxtb r2, r3
80141b8: 4b42 ldr r3, [pc, #264] ; (80142c4 <tcp_receive+0xb24>)
80141ba: 701a strb r2, [r3, #0]
}
#if TCP_QUEUE_OOSEQ
/* We now check if we have segments on the ->ooseq queue that
are now in sequence. */
while (pcb->ooseq != NULL &&
80141bc: e0af b.n 801431e <tcp_receive+0xb7e>
pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
struct tcp_seg *cseg = pcb->ooseq;
80141be: 687b ldr r3, [r7, #4]
80141c0: 6f5b ldr r3, [r3, #116] ; 0x74
80141c2: 60bb str r3, [r7, #8]
seqno = pcb->ooseq->tcphdr->seqno;
80141c4: 687b ldr r3, [r7, #4]
80141c6: 6f5b ldr r3, [r3, #116] ; 0x74
80141c8: 68db ldr r3, [r3, #12]
80141ca: 685b ldr r3, [r3, #4]
80141cc: 4a36 ldr r2, [pc, #216] ; (80142a8 <tcp_receive+0xb08>)
80141ce: 6013 str r3, [r2, #0]
pcb->rcv_nxt += TCP_TCPLEN(cseg);
80141d0: 68bb ldr r3, [r7, #8]
80141d2: 891b ldrh r3, [r3, #8]
80141d4: 461c mov r4, r3
80141d6: 68bb ldr r3, [r7, #8]
80141d8: 68db ldr r3, [r3, #12]
80141da: 899b ldrh r3, [r3, #12]
80141dc: b29b uxth r3, r3
80141de: 4618 mov r0, r3
80141e0: f7fa fe2c bl 800ee3c <lwip_htons>
80141e4: 4603 mov r3, r0
80141e6: b2db uxtb r3, r3
80141e8: f003 0303 and.w r3, r3, #3
80141ec: 2b00 cmp r3, #0
80141ee: d001 beq.n 80141f4 <tcp_receive+0xa54>
80141f0: 2301 movs r3, #1
80141f2: e000 b.n 80141f6 <tcp_receive+0xa56>
80141f4: 2300 movs r3, #0
80141f6: 191a adds r2, r3, r4
80141f8: 687b ldr r3, [r7, #4]
80141fa: 6a5b ldr r3, [r3, #36] ; 0x24
80141fc: 441a add r2, r3
80141fe: 687b ldr r3, [r7, #4]
8014200: 625a str r2, [r3, #36] ; 0x24
LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n",
8014202: 687b ldr r3, [r7, #4]
8014204: 8d1b ldrh r3, [r3, #40] ; 0x28
8014206: 461c mov r4, r3
8014208: 68bb ldr r3, [r7, #8]
801420a: 891b ldrh r3, [r3, #8]
801420c: 461d mov r5, r3
801420e: 68bb ldr r3, [r7, #8]
8014210: 68db ldr r3, [r3, #12]
8014212: 899b ldrh r3, [r3, #12]
8014214: b29b uxth r3, r3
8014216: 4618 mov r0, r3
8014218: f7fa fe10 bl 800ee3c <lwip_htons>
801421c: 4603 mov r3, r0
801421e: b2db uxtb r3, r3
8014220: f003 0303 and.w r3, r3, #3
8014224: 2b00 cmp r3, #0
8014226: d001 beq.n 801422c <tcp_receive+0xa8c>
8014228: 2301 movs r3, #1
801422a: e000 b.n 801422e <tcp_receive+0xa8e>
801422c: 2300 movs r3, #0
801422e: 442b add r3, r5
8014230: 429c cmp r4, r3
8014232: d206 bcs.n 8014242 <tcp_receive+0xaa2>
8014234: 4b1e ldr r3, [pc, #120] ; (80142b0 <tcp_receive+0xb10>)
8014236: f240 622b movw r2, #1579 ; 0x62b
801423a: 4923 ldr r1, [pc, #140] ; (80142c8 <tcp_receive+0xb28>)
801423c: 481e ldr r0, [pc, #120] ; (80142b8 <tcp_receive+0xb18>)
801423e: f006 fec1 bl 801afc4 <iprintf>
pcb->rcv_wnd >= TCP_TCPLEN(cseg));
pcb->rcv_wnd -= TCP_TCPLEN(cseg);
8014242: 68bb ldr r3, [r7, #8]
8014244: 891b ldrh r3, [r3, #8]
8014246: 461c mov r4, r3
8014248: 68bb ldr r3, [r7, #8]
801424a: 68db ldr r3, [r3, #12]
801424c: 899b ldrh r3, [r3, #12]
801424e: b29b uxth r3, r3
8014250: 4618 mov r0, r3
8014252: f7fa fdf3 bl 800ee3c <lwip_htons>
8014256: 4603 mov r3, r0
8014258: b2db uxtb r3, r3
801425a: f003 0303 and.w r3, r3, #3
801425e: 2b00 cmp r3, #0
8014260: d001 beq.n 8014266 <tcp_receive+0xac6>
8014262: 2301 movs r3, #1
8014264: e000 b.n 8014268 <tcp_receive+0xac8>
8014266: 2300 movs r3, #0
8014268: 1919 adds r1, r3, r4
801426a: 687b ldr r3, [r7, #4]
801426c: 8d1a ldrh r2, [r3, #40] ; 0x28
801426e: b28b uxth r3, r1
8014270: 1ad3 subs r3, r2, r3
8014272: b29a uxth r2, r3
8014274: 687b ldr r3, [r7, #4]
8014276: 851a strh r2, [r3, #40] ; 0x28
tcp_update_rcv_ann_wnd(pcb);
8014278: 6878 ldr r0, [r7, #4]
801427a: f7fc ff47 bl 801110c <tcp_update_rcv_ann_wnd>
if (cseg->p->tot_len > 0) {
801427e: 68bb ldr r3, [r7, #8]
8014280: 685b ldr r3, [r3, #4]
8014282: 891b ldrh r3, [r3, #8]
8014284: 2b00 cmp r3, #0
8014286: d028 beq.n 80142da <tcp_receive+0xb3a>
/* Chain this pbuf onto the pbuf that we will pass to
the application. */
/* With window scaling, this can overflow recv_data->tot_len, but
that's not a problem since we explicitly fix that before passing
recv_data to the application. */
if (recv_data) {
8014288: 4b0d ldr r3, [pc, #52] ; (80142c0 <tcp_receive+0xb20>)
801428a: 681b ldr r3, [r3, #0]
801428c: 2b00 cmp r3, #0
801428e: d01d beq.n 80142cc <tcp_receive+0xb2c>
pbuf_cat(recv_data, cseg->p);
8014290: 4b0b ldr r3, [pc, #44] ; (80142c0 <tcp_receive+0xb20>)
8014292: 681a ldr r2, [r3, #0]
8014294: 68bb ldr r3, [r7, #8]
8014296: 685b ldr r3, [r3, #4]
8014298: 4619 mov r1, r3
801429a: 4610 mov r0, r2
801429c: f7fc fa54 bl 8010748 <pbuf_cat>
80142a0: e018 b.n 80142d4 <tcp_receive+0xb34>
80142a2: bf00 nop
80142a4: 2000874a .word 0x2000874a
80142a8: 20008740 .word 0x20008740
80142ac: 20008720 .word 0x20008720
80142b0: 0801d484 .word 0x0801d484
80142b4: 0801d864 .word 0x0801d864
80142b8: 0801d4d0 .word 0x0801d4d0
80142bc: 0801d8a0 .word 0x0801d8a0
80142c0: 20008750 .word 0x20008750
80142c4: 2000874d .word 0x2000874d
80142c8: 0801d8c0 .word 0x0801d8c0
} else {
recv_data = cseg->p;
80142cc: 68bb ldr r3, [r7, #8]
80142ce: 685b ldr r3, [r3, #4]
80142d0: 4a70 ldr r2, [pc, #448] ; (8014494 <tcp_receive+0xcf4>)
80142d2: 6013 str r3, [r2, #0]
}
cseg->p = NULL;
80142d4: 68bb ldr r3, [r7, #8]
80142d6: 2200 movs r2, #0
80142d8: 605a str r2, [r3, #4]
}
if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
80142da: 68bb ldr r3, [r7, #8]
80142dc: 68db ldr r3, [r3, #12]
80142de: 899b ldrh r3, [r3, #12]
80142e0: b29b uxth r3, r3
80142e2: 4618 mov r0, r3
80142e4: f7fa fdaa bl 800ee3c <lwip_htons>
80142e8: 4603 mov r3, r0
80142ea: b2db uxtb r3, r3
80142ec: f003 0301 and.w r3, r3, #1
80142f0: 2b00 cmp r3, #0
80142f2: d00d beq.n 8014310 <tcp_receive+0xb70>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
recv_flags |= TF_GOT_FIN;
80142f4: 4b68 ldr r3, [pc, #416] ; (8014498 <tcp_receive+0xcf8>)
80142f6: 781b ldrb r3, [r3, #0]
80142f8: f043 0320 orr.w r3, r3, #32
80142fc: b2da uxtb r2, r3
80142fe: 4b66 ldr r3, [pc, #408] ; (8014498 <tcp_receive+0xcf8>)
8014300: 701a strb r2, [r3, #0]
if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */
8014302: 687b ldr r3, [r7, #4]
8014304: 7d1b ldrb r3, [r3, #20]
8014306: 2b04 cmp r3, #4
8014308: d102 bne.n 8014310 <tcp_receive+0xb70>
pcb->state = CLOSE_WAIT;
801430a: 687b ldr r3, [r7, #4]
801430c: 2207 movs r2, #7
801430e: 751a strb r2, [r3, #20]
}
}
pcb->ooseq = cseg->next;
8014310: 68bb ldr r3, [r7, #8]
8014312: 681a ldr r2, [r3, #0]
8014314: 687b ldr r3, [r7, #4]
8014316: 675a str r2, [r3, #116] ; 0x74
tcp_seg_free(cseg);
8014318: 68b8 ldr r0, [r7, #8]
801431a: f7fd fbd6 bl 8011aca <tcp_seg_free>
while (pcb->ooseq != NULL &&
801431e: 687b ldr r3, [r7, #4]
8014320: 6f5b ldr r3, [r3, #116] ; 0x74
8014322: 2b00 cmp r3, #0
8014324: d008 beq.n 8014338 <tcp_receive+0xb98>
pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
8014326: 687b ldr r3, [r7, #4]
8014328: 6f5b ldr r3, [r3, #116] ; 0x74
801432a: 68db ldr r3, [r3, #12]
801432c: 685a ldr r2, [r3, #4]
801432e: 687b ldr r3, [r7, #4]
8014330: 6a5b ldr r3, [r3, #36] ; 0x24
while (pcb->ooseq != NULL &&
8014332: 429a cmp r2, r3
8014334: f43f af43 beq.w 80141be <tcp_receive+0xa1e>
#endif /* LWIP_TCP_SACK_OUT */
#endif /* TCP_QUEUE_OOSEQ */
/* Acknowledge the segment(s). */
tcp_ack(pcb);
8014338: 687b ldr r3, [r7, #4]
801433a: 8b5b ldrh r3, [r3, #26]
801433c: f003 0301 and.w r3, r3, #1
8014340: 2b00 cmp r3, #0
8014342: d00e beq.n 8014362 <tcp_receive+0xbc2>
8014344: 687b ldr r3, [r7, #4]
8014346: 8b5b ldrh r3, [r3, #26]
8014348: f023 0301 bic.w r3, r3, #1
801434c: b29a uxth r2, r3
801434e: 687b ldr r3, [r7, #4]
8014350: 835a strh r2, [r3, #26]
8014352: 687b ldr r3, [r7, #4]
8014354: 8b5b ldrh r3, [r3, #26]
8014356: f043 0302 orr.w r3, r3, #2
801435a: b29a uxth r2, r3
801435c: 687b ldr r3, [r7, #4]
801435e: 835a strh r2, [r3, #26]
if (pcb->rcv_nxt == seqno) {
8014360: e188 b.n 8014674 <tcp_receive+0xed4>
tcp_ack(pcb);
8014362: 687b ldr r3, [r7, #4]
8014364: 8b5b ldrh r3, [r3, #26]
8014366: f043 0301 orr.w r3, r3, #1
801436a: b29a uxth r2, r3
801436c: 687b ldr r3, [r7, #4]
801436e: 835a strh r2, [r3, #26]
if (pcb->rcv_nxt == seqno) {
8014370: e180 b.n 8014674 <tcp_receive+0xed4>
} else {
/* We get here if the incoming segment is out-of-sequence. */
#if TCP_QUEUE_OOSEQ
/* We queue the segment on the ->ooseq queue. */
if (pcb->ooseq == NULL) {
8014372: 687b ldr r3, [r7, #4]
8014374: 6f5b ldr r3, [r3, #116] ; 0x74
8014376: 2b00 cmp r3, #0
8014378: d106 bne.n 8014388 <tcp_receive+0xbe8>
pcb->ooseq = tcp_seg_copy(&inseg);
801437a: 4848 ldr r0, [pc, #288] ; (801449c <tcp_receive+0xcfc>)
801437c: f7fd fbbe bl 8011afc <tcp_seg_copy>
8014380: 4602 mov r2, r0
8014382: 687b ldr r3, [r7, #4]
8014384: 675a str r2, [r3, #116] ; 0x74
8014386: e16d b.n 8014664 <tcp_receive+0xec4>
#if LWIP_TCP_SACK_OUT
/* This is the left edge of the lowest possible SACK range.
It may start before the newly received segment (possibly adjusted below). */
u32_t sackbeg = TCP_SEQ_LT(seqno, pcb->ooseq->tcphdr->seqno) ? seqno : pcb->ooseq->tcphdr->seqno;
#endif /* LWIP_TCP_SACK_OUT */
struct tcp_seg *next, *prev = NULL;
8014388: 2300 movs r3, #0
801438a: 637b str r3, [r7, #52] ; 0x34
for (next = pcb->ooseq; next != NULL; next = next->next) {
801438c: 687b ldr r3, [r7, #4]
801438e: 6f5b ldr r3, [r3, #116] ; 0x74
8014390: 63bb str r3, [r7, #56] ; 0x38
8014392: e157 b.n 8014644 <tcp_receive+0xea4>
if (seqno == next->tcphdr->seqno) {
8014394: 6bbb ldr r3, [r7, #56] ; 0x38
8014396: 68db ldr r3, [r3, #12]
8014398: 685a ldr r2, [r3, #4]
801439a: 4b41 ldr r3, [pc, #260] ; (80144a0 <tcp_receive+0xd00>)
801439c: 681b ldr r3, [r3, #0]
801439e: 429a cmp r2, r3
80143a0: d11d bne.n 80143de <tcp_receive+0xc3e>
/* The sequence number of the incoming segment is the
same as the sequence number of the segment on
->ooseq. We check the lengths to see which one to
discard. */
if (inseg.len > next->len) {
80143a2: 4b3e ldr r3, [pc, #248] ; (801449c <tcp_receive+0xcfc>)
80143a4: 891a ldrh r2, [r3, #8]
80143a6: 6bbb ldr r3, [r7, #56] ; 0x38
80143a8: 891b ldrh r3, [r3, #8]
80143aa: 429a cmp r2, r3
80143ac: f240 814f bls.w 801464e <tcp_receive+0xeae>
/* The incoming segment is larger than the old
segment. We replace some segments with the new
one. */
struct tcp_seg *cseg = tcp_seg_copy(&inseg);
80143b0: 483a ldr r0, [pc, #232] ; (801449c <tcp_receive+0xcfc>)
80143b2: f7fd fba3 bl 8011afc <tcp_seg_copy>
80143b6: 6178 str r0, [r7, #20]
if (cseg != NULL) {
80143b8: 697b ldr r3, [r7, #20]
80143ba: 2b00 cmp r3, #0
80143bc: f000 8149 beq.w 8014652 <tcp_receive+0xeb2>
if (prev != NULL) {
80143c0: 6b7b ldr r3, [r7, #52] ; 0x34
80143c2: 2b00 cmp r3, #0
80143c4: d003 beq.n 80143ce <tcp_receive+0xc2e>
prev->next = cseg;
80143c6: 6b7b ldr r3, [r7, #52] ; 0x34
80143c8: 697a ldr r2, [r7, #20]
80143ca: 601a str r2, [r3, #0]
80143cc: e002 b.n 80143d4 <tcp_receive+0xc34>
} else {
pcb->ooseq = cseg;
80143ce: 687b ldr r3, [r7, #4]
80143d0: 697a ldr r2, [r7, #20]
80143d2: 675a str r2, [r3, #116] ; 0x74
}
tcp_oos_insert_segment(cseg, next);
80143d4: 6bb9 ldr r1, [r7, #56] ; 0x38
80143d6: 6978 ldr r0, [r7, #20]
80143d8: f7ff f8de bl 8013598 <tcp_oos_insert_segment>
}
break;
80143dc: e139 b.n 8014652 <tcp_receive+0xeb2>
segment was smaller than the old one; in either
case, we ditch the incoming segment. */
break;
}
} else {
if (prev == NULL) {
80143de: 6b7b ldr r3, [r7, #52] ; 0x34
80143e0: 2b00 cmp r3, #0
80143e2: d117 bne.n 8014414 <tcp_receive+0xc74>
if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
80143e4: 4b2e ldr r3, [pc, #184] ; (80144a0 <tcp_receive+0xd00>)
80143e6: 681a ldr r2, [r3, #0]
80143e8: 6bbb ldr r3, [r7, #56] ; 0x38
80143ea: 68db ldr r3, [r3, #12]
80143ec: 685b ldr r3, [r3, #4]
80143ee: 1ad3 subs r3, r2, r3
80143f0: 2b00 cmp r3, #0
80143f2: da57 bge.n 80144a4 <tcp_receive+0xd04>
/* The sequence number of the incoming segment is lower
than the sequence number of the first segment on the
queue. We put the incoming segment first on the
queue. */
struct tcp_seg *cseg = tcp_seg_copy(&inseg);
80143f4: 4829 ldr r0, [pc, #164] ; (801449c <tcp_receive+0xcfc>)
80143f6: f7fd fb81 bl 8011afc <tcp_seg_copy>
80143fa: 61b8 str r0, [r7, #24]
if (cseg != NULL) {
80143fc: 69bb ldr r3, [r7, #24]
80143fe: 2b00 cmp r3, #0
8014400: f000 8129 beq.w 8014656 <tcp_receive+0xeb6>
pcb->ooseq = cseg;
8014404: 687b ldr r3, [r7, #4]
8014406: 69ba ldr r2, [r7, #24]
8014408: 675a str r2, [r3, #116] ; 0x74
tcp_oos_insert_segment(cseg, next);
801440a: 6bb9 ldr r1, [r7, #56] ; 0x38
801440c: 69b8 ldr r0, [r7, #24]
801440e: f7ff f8c3 bl 8013598 <tcp_oos_insert_segment>
}
break;
8014412: e120 b.n 8014656 <tcp_receive+0xeb6>
}
} else {
/*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno + 1, next->tcphdr->seqno - 1)) {
8014414: 4b22 ldr r3, [pc, #136] ; (80144a0 <tcp_receive+0xd00>)
8014416: 681a ldr r2, [r3, #0]
8014418: 6b7b ldr r3, [r7, #52] ; 0x34
801441a: 68db ldr r3, [r3, #12]
801441c: 685b ldr r3, [r3, #4]
801441e: 1ad3 subs r3, r2, r3
8014420: 3b01 subs r3, #1
8014422: 2b00 cmp r3, #0
8014424: db3e blt.n 80144a4 <tcp_receive+0xd04>
8014426: 4b1e ldr r3, [pc, #120] ; (80144a0 <tcp_receive+0xd00>)
8014428: 681a ldr r2, [r3, #0]
801442a: 6bbb ldr r3, [r7, #56] ; 0x38
801442c: 68db ldr r3, [r3, #12]
801442e: 685b ldr r3, [r3, #4]
8014430: 1ad3 subs r3, r2, r3
8014432: 3301 adds r3, #1
8014434: 2b00 cmp r3, #0
8014436: dc35 bgt.n 80144a4 <tcp_receive+0xd04>
/* The sequence number of the incoming segment is in
between the sequence numbers of the previous and
the next segment on ->ooseq. We trim trim the previous
segment, delete next segments that included in received segment
and trim received, if needed. */
struct tcp_seg *cseg = tcp_seg_copy(&inseg);
8014438: 4818 ldr r0, [pc, #96] ; (801449c <tcp_receive+0xcfc>)
801443a: f7fd fb5f bl 8011afc <tcp_seg_copy>
801443e: 61f8 str r0, [r7, #28]
if (cseg != NULL) {
8014440: 69fb ldr r3, [r7, #28]
8014442: 2b00 cmp r3, #0
8014444: f000 8109 beq.w 801465a <tcp_receive+0xeba>
if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
8014448: 6b7b ldr r3, [r7, #52] ; 0x34
801444a: 68db ldr r3, [r3, #12]
801444c: 685b ldr r3, [r3, #4]
801444e: 6b7a ldr r2, [r7, #52] ; 0x34
8014450: 8912 ldrh r2, [r2, #8]
8014452: 441a add r2, r3
8014454: 4b12 ldr r3, [pc, #72] ; (80144a0 <tcp_receive+0xd00>)
8014456: 681b ldr r3, [r3, #0]
8014458: 1ad3 subs r3, r2, r3
801445a: 2b00 cmp r3, #0
801445c: dd12 ble.n 8014484 <tcp_receive+0xce4>
/* We need to trim the prev segment. */
prev->len = (u16_t)(seqno - prev->tcphdr->seqno);
801445e: 4b10 ldr r3, [pc, #64] ; (80144a0 <tcp_receive+0xd00>)
8014460: 681b ldr r3, [r3, #0]
8014462: b29a uxth r2, r3
8014464: 6b7b ldr r3, [r7, #52] ; 0x34
8014466: 68db ldr r3, [r3, #12]
8014468: 685b ldr r3, [r3, #4]
801446a: b29b uxth r3, r3
801446c: 1ad3 subs r3, r2, r3
801446e: b29a uxth r2, r3
8014470: 6b7b ldr r3, [r7, #52] ; 0x34
8014472: 811a strh r2, [r3, #8]
pbuf_realloc(prev->p, prev->len);
8014474: 6b7b ldr r3, [r7, #52] ; 0x34
8014476: 685a ldr r2, [r3, #4]
8014478: 6b7b ldr r3, [r7, #52] ; 0x34
801447a: 891b ldrh r3, [r3, #8]
801447c: 4619 mov r1, r3
801447e: 4610 mov r0, r2
8014480: f7fb ff0e bl 80102a0 <pbuf_realloc>
}
prev->next = cseg;
8014484: 6b7b ldr r3, [r7, #52] ; 0x34
8014486: 69fa ldr r2, [r7, #28]
8014488: 601a str r2, [r3, #0]
tcp_oos_insert_segment(cseg, next);
801448a: 6bb9 ldr r1, [r7, #56] ; 0x38
801448c: 69f8 ldr r0, [r7, #28]
801448e: f7ff f883 bl 8013598 <tcp_oos_insert_segment>
}
break;
8014492: e0e2 b.n 801465a <tcp_receive+0xeba>
8014494: 20008750 .word 0x20008750
8014498: 2000874d .word 0x2000874d
801449c: 20008720 .word 0x20008720
80144a0: 20008740 .word 0x20008740
#endif /* LWIP_TCP_SACK_OUT */
/* We don't use 'prev' below, so let's set it to current 'next'.
This way even if we break the loop below, 'prev' will be pointing
at the segment right in front of the newly added one. */
prev = next;
80144a4: 6bbb ldr r3, [r7, #56] ; 0x38
80144a6: 637b str r3, [r7, #52] ; 0x34
/* If the "next" segment is the last segment on the
ooseq queue, we add the incoming segment to the end
of the list. */
if (next->next == NULL &&
80144a8: 6bbb ldr r3, [r7, #56] ; 0x38
80144aa: 681b ldr r3, [r3, #0]
80144ac: 2b00 cmp r3, #0
80144ae: f040 80c6 bne.w 801463e <tcp_receive+0xe9e>
TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
80144b2: 4b80 ldr r3, [pc, #512] ; (80146b4 <tcp_receive+0xf14>)
80144b4: 681a ldr r2, [r3, #0]
80144b6: 6bbb ldr r3, [r7, #56] ; 0x38
80144b8: 68db ldr r3, [r3, #12]
80144ba: 685b ldr r3, [r3, #4]
80144bc: 1ad3 subs r3, r2, r3
if (next->next == NULL &&
80144be: 2b00 cmp r3, #0
80144c0: f340 80bd ble.w 801463e <tcp_receive+0xe9e>
if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
80144c4: 6bbb ldr r3, [r7, #56] ; 0x38
80144c6: 68db ldr r3, [r3, #12]
80144c8: 899b ldrh r3, [r3, #12]
80144ca: b29b uxth r3, r3
80144cc: 4618 mov r0, r3
80144ce: f7fa fcb5 bl 800ee3c <lwip_htons>
80144d2: 4603 mov r3, r0
80144d4: b2db uxtb r3, r3
80144d6: f003 0301 and.w r3, r3, #1
80144da: 2b00 cmp r3, #0
80144dc: f040 80bf bne.w 801465e <tcp_receive+0xebe>
/* segment "next" already contains all data */
break;
}
next->next = tcp_seg_copy(&inseg);
80144e0: 4875 ldr r0, [pc, #468] ; (80146b8 <tcp_receive+0xf18>)
80144e2: f7fd fb0b bl 8011afc <tcp_seg_copy>
80144e6: 4602 mov r2, r0
80144e8: 6bbb ldr r3, [r7, #56] ; 0x38
80144ea: 601a str r2, [r3, #0]
if (next->next != NULL) {
80144ec: 6bbb ldr r3, [r7, #56] ; 0x38
80144ee: 681b ldr r3, [r3, #0]
80144f0: 2b00 cmp r3, #0
80144f2: f000 80b6 beq.w 8014662 <tcp_receive+0xec2>
if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
80144f6: 6bbb ldr r3, [r7, #56] ; 0x38
80144f8: 68db ldr r3, [r3, #12]
80144fa: 685b ldr r3, [r3, #4]
80144fc: 6bba ldr r2, [r7, #56] ; 0x38
80144fe: 8912 ldrh r2, [r2, #8]
8014500: 441a add r2, r3
8014502: 4b6c ldr r3, [pc, #432] ; (80146b4 <tcp_receive+0xf14>)
8014504: 681b ldr r3, [r3, #0]
8014506: 1ad3 subs r3, r2, r3
8014508: 2b00 cmp r3, #0
801450a: dd12 ble.n 8014532 <tcp_receive+0xd92>
/* We need to trim the last segment. */
next->len = (u16_t)(seqno - next->tcphdr->seqno);
801450c: 4b69 ldr r3, [pc, #420] ; (80146b4 <tcp_receive+0xf14>)
801450e: 681b ldr r3, [r3, #0]
8014510: b29a uxth r2, r3
8014512: 6bbb ldr r3, [r7, #56] ; 0x38
8014514: 68db ldr r3, [r3, #12]
8014516: 685b ldr r3, [r3, #4]
8014518: b29b uxth r3, r3
801451a: 1ad3 subs r3, r2, r3
801451c: b29a uxth r2, r3
801451e: 6bbb ldr r3, [r7, #56] ; 0x38
8014520: 811a strh r2, [r3, #8]
pbuf_realloc(next->p, next->len);
8014522: 6bbb ldr r3, [r7, #56] ; 0x38
8014524: 685a ldr r2, [r3, #4]
8014526: 6bbb ldr r3, [r7, #56] ; 0x38
8014528: 891b ldrh r3, [r3, #8]
801452a: 4619 mov r1, r3
801452c: 4610 mov r0, r2
801452e: f7fb feb7 bl 80102a0 <pbuf_realloc>
}
/* check if the remote side overruns our receive window */
if (TCP_SEQ_GT((u32_t)tcplen + seqno, pcb->rcv_nxt + (u32_t)pcb->rcv_wnd)) {
8014532: 4b62 ldr r3, [pc, #392] ; (80146bc <tcp_receive+0xf1c>)
8014534: 881b ldrh r3, [r3, #0]
8014536: 461a mov r2, r3
8014538: 4b5e ldr r3, [pc, #376] ; (80146b4 <tcp_receive+0xf14>)
801453a: 681b ldr r3, [r3, #0]
801453c: 441a add r2, r3
801453e: 687b ldr r3, [r7, #4]
8014540: 6a5b ldr r3, [r3, #36] ; 0x24
8014542: 6879 ldr r1, [r7, #4]
8014544: 8d09 ldrh r1, [r1, #40] ; 0x28
8014546: 440b add r3, r1
8014548: 1ad3 subs r3, r2, r3
801454a: 2b00 cmp r3, #0
801454c: f340 8089 ble.w 8014662 <tcp_receive+0xec2>
LWIP_DEBUGF(TCP_INPUT_DEBUG,
("tcp_receive: other end overran receive window"
"seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) {
8014550: 6bbb ldr r3, [r7, #56] ; 0x38
8014552: 681b ldr r3, [r3, #0]
8014554: 68db ldr r3, [r3, #12]
8014556: 899b ldrh r3, [r3, #12]
8014558: b29b uxth r3, r3
801455a: 4618 mov r0, r3
801455c: f7fa fc6e bl 800ee3c <lwip_htons>
8014560: 4603 mov r3, r0
8014562: b2db uxtb r3, r3
8014564: f003 0301 and.w r3, r3, #1
8014568: 2b00 cmp r3, #0
801456a: d022 beq.n 80145b2 <tcp_receive+0xe12>
/* Must remove the FIN from the header as we're trimming
* that byte of sequence-space from the packet */
TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) & ~TCP_FIN);
801456c: 6bbb ldr r3, [r7, #56] ; 0x38
801456e: 681b ldr r3, [r3, #0]
8014570: 68db ldr r3, [r3, #12]
8014572: 899b ldrh r3, [r3, #12]
8014574: b29b uxth r3, r3
8014576: b21b sxth r3, r3
8014578: f423 537c bic.w r3, r3, #16128 ; 0x3f00
801457c: b21c sxth r4, r3
801457e: 6bbb ldr r3, [r7, #56] ; 0x38
8014580: 681b ldr r3, [r3, #0]
8014582: 68db ldr r3, [r3, #12]
8014584: 899b ldrh r3, [r3, #12]
8014586: b29b uxth r3, r3
8014588: 4618 mov r0, r3
801458a: f7fa fc57 bl 800ee3c <lwip_htons>
801458e: 4603 mov r3, r0
8014590: b2db uxtb r3, r3
8014592: b29b uxth r3, r3
8014594: f003 033e and.w r3, r3, #62 ; 0x3e
8014598: b29b uxth r3, r3
801459a: 4618 mov r0, r3
801459c: f7fa fc4e bl 800ee3c <lwip_htons>
80145a0: 4603 mov r3, r0
80145a2: b21b sxth r3, r3
80145a4: 4323 orrs r3, r4
80145a6: b21a sxth r2, r3
80145a8: 6bbb ldr r3, [r7, #56] ; 0x38
80145aa: 681b ldr r3, [r3, #0]
80145ac: 68db ldr r3, [r3, #12]
80145ae: b292 uxth r2, r2
80145b0: 819a strh r2, [r3, #12]
}
/* Adjust length of segment to fit in the window. */
next->next->len = (u16_t)(pcb->rcv_nxt + pcb->rcv_wnd - seqno);
80145b2: 687b ldr r3, [r7, #4]
80145b4: 6a5b ldr r3, [r3, #36] ; 0x24
80145b6: b29a uxth r2, r3
80145b8: 687b ldr r3, [r7, #4]
80145ba: 8d1b ldrh r3, [r3, #40] ; 0x28
80145bc: 4413 add r3, r2
80145be: b299 uxth r1, r3
80145c0: 4b3c ldr r3, [pc, #240] ; (80146b4 <tcp_receive+0xf14>)
80145c2: 681b ldr r3, [r3, #0]
80145c4: b29a uxth r2, r3
80145c6: 6bbb ldr r3, [r7, #56] ; 0x38
80145c8: 681b ldr r3, [r3, #0]
80145ca: 1a8a subs r2, r1, r2
80145cc: b292 uxth r2, r2
80145ce: 811a strh r2, [r3, #8]
pbuf_realloc(next->next->p, next->next->len);
80145d0: 6bbb ldr r3, [r7, #56] ; 0x38
80145d2: 681b ldr r3, [r3, #0]
80145d4: 685a ldr r2, [r3, #4]
80145d6: 6bbb ldr r3, [r7, #56] ; 0x38
80145d8: 681b ldr r3, [r3, #0]
80145da: 891b ldrh r3, [r3, #8]
80145dc: 4619 mov r1, r3
80145de: 4610 mov r0, r2
80145e0: f7fb fe5e bl 80102a0 <pbuf_realloc>
tcplen = TCP_TCPLEN(next->next);
80145e4: 6bbb ldr r3, [r7, #56] ; 0x38
80145e6: 681b ldr r3, [r3, #0]
80145e8: 891c ldrh r4, [r3, #8]
80145ea: 6bbb ldr r3, [r7, #56] ; 0x38
80145ec: 681b ldr r3, [r3, #0]
80145ee: 68db ldr r3, [r3, #12]
80145f0: 899b ldrh r3, [r3, #12]
80145f2: b29b uxth r3, r3
80145f4: 4618 mov r0, r3
80145f6: f7fa fc21 bl 800ee3c <lwip_htons>
80145fa: 4603 mov r3, r0
80145fc: b2db uxtb r3, r3
80145fe: f003 0303 and.w r3, r3, #3
8014602: 2b00 cmp r3, #0
8014604: d001 beq.n 801460a <tcp_receive+0xe6a>
8014606: 2301 movs r3, #1
8014608: e000 b.n 801460c <tcp_receive+0xe6c>
801460a: 2300 movs r3, #0
801460c: 4423 add r3, r4
801460e: b29a uxth r2, r3
8014610: 4b2a ldr r3, [pc, #168] ; (80146bc <tcp_receive+0xf1c>)
8014612: 801a strh r2, [r3, #0]
LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
8014614: 4b29 ldr r3, [pc, #164] ; (80146bc <tcp_receive+0xf1c>)
8014616: 881b ldrh r3, [r3, #0]
8014618: 461a mov r2, r3
801461a: 4b26 ldr r3, [pc, #152] ; (80146b4 <tcp_receive+0xf14>)
801461c: 681b ldr r3, [r3, #0]
801461e: 441a add r2, r3
8014620: 687b ldr r3, [r7, #4]
8014622: 6a5b ldr r3, [r3, #36] ; 0x24
8014624: 6879 ldr r1, [r7, #4]
8014626: 8d09 ldrh r1, [r1, #40] ; 0x28
8014628: 440b add r3, r1
801462a: 429a cmp r2, r3
801462c: d019 beq.n 8014662 <tcp_receive+0xec2>
801462e: 4b24 ldr r3, [pc, #144] ; (80146c0 <tcp_receive+0xf20>)
8014630: f44f 62df mov.w r2, #1784 ; 0x6f8
8014634: 4923 ldr r1, [pc, #140] ; (80146c4 <tcp_receive+0xf24>)
8014636: 4824 ldr r0, [pc, #144] ; (80146c8 <tcp_receive+0xf28>)
8014638: f006 fcc4 bl 801afc4 <iprintf>
(seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd));
}
}
break;
801463c: e011 b.n 8014662 <tcp_receive+0xec2>
for (next = pcb->ooseq; next != NULL; next = next->next) {
801463e: 6bbb ldr r3, [r7, #56] ; 0x38
8014640: 681b ldr r3, [r3, #0]
8014642: 63bb str r3, [r7, #56] ; 0x38
8014644: 6bbb ldr r3, [r7, #56] ; 0x38
8014646: 2b00 cmp r3, #0
8014648: f47f aea4 bne.w 8014394 <tcp_receive+0xbf4>
801464c: e00a b.n 8014664 <tcp_receive+0xec4>
break;
801464e: bf00 nop
8014650: e008 b.n 8014664 <tcp_receive+0xec4>
break;
8014652: bf00 nop
8014654: e006 b.n 8014664 <tcp_receive+0xec4>
break;
8014656: bf00 nop
8014658: e004 b.n 8014664 <tcp_receive+0xec4>
break;
801465a: bf00 nop
801465c: e002 b.n 8014664 <tcp_receive+0xec4>
break;
801465e: bf00 nop
8014660: e000 b.n 8014664 <tcp_receive+0xec4>
break;
8014662: bf00 nop
#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */
#endif /* TCP_QUEUE_OOSEQ */
/* We send the ACK packet after we've (potentially) dealt with SACKs,
so they can be included in the acknowledgment. */
tcp_send_empty_ack(pcb);
8014664: 6878 ldr r0, [r7, #4]
8014666: f001 fa33 bl 8015ad0 <tcp_send_empty_ack>
if (pcb->rcv_nxt == seqno) {
801466a: e003 b.n 8014674 <tcp_receive+0xed4>
}
} else {
/* The incoming segment is not within the window. */
tcp_send_empty_ack(pcb);
801466c: 6878 ldr r0, [r7, #4]
801466e: f001 fa2f bl 8015ad0 <tcp_send_empty_ack>
if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
8014672: e01a b.n 80146aa <tcp_receive+0xf0a>
8014674: e019 b.n 80146aa <tcp_receive+0xf0a>
}
} else {
/* Segments with length 0 is taken care of here. Segments that
fall out of the window are ACKed. */
if (!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
8014676: 4b0f ldr r3, [pc, #60] ; (80146b4 <tcp_receive+0xf14>)
8014678: 681a ldr r2, [r3, #0]
801467a: 687b ldr r3, [r7, #4]
801467c: 6a5b ldr r3, [r3, #36] ; 0x24
801467e: 1ad3 subs r3, r2, r3
8014680: 2b00 cmp r3, #0
8014682: db0a blt.n 801469a <tcp_receive+0xefa>
8014684: 4b0b ldr r3, [pc, #44] ; (80146b4 <tcp_receive+0xf14>)
8014686: 681a ldr r2, [r3, #0]
8014688: 687b ldr r3, [r7, #4]
801468a: 6a5b ldr r3, [r3, #36] ; 0x24
801468c: 6879 ldr r1, [r7, #4]
801468e: 8d09 ldrh r1, [r1, #40] ; 0x28
8014690: 440b add r3, r1
8014692: 1ad3 subs r3, r2, r3
8014694: 3301 adds r3, #1
8014696: 2b00 cmp r3, #0
8014698: dd07 ble.n 80146aa <tcp_receive+0xf0a>
tcp_ack_now(pcb);
801469a: 687b ldr r3, [r7, #4]
801469c: 8b5b ldrh r3, [r3, #26]
801469e: f043 0302 orr.w r3, r3, #2
80146a2: b29a uxth r2, r3
80146a4: 687b ldr r3, [r7, #4]
80146a6: 835a strh r2, [r3, #26]
}
}
}
80146a8: e7ff b.n 80146aa <tcp_receive+0xf0a>
80146aa: bf00 nop
80146ac: 3750 adds r7, #80 ; 0x50
80146ae: 46bd mov sp, r7
80146b0: bdb0 pop {r4, r5, r7, pc}
80146b2: bf00 nop
80146b4: 20008740 .word 0x20008740
80146b8: 20008720 .word 0x20008720
80146bc: 2000874a .word 0x2000874a
80146c0: 0801d484 .word 0x0801d484
80146c4: 0801d82c .word 0x0801d82c
80146c8: 0801d4d0 .word 0x0801d4d0
080146cc <tcp_get_next_optbyte>:
static u8_t
tcp_get_next_optbyte(void)
{
80146cc: b480 push {r7}
80146ce: b083 sub sp, #12
80146d0: af00 add r7, sp, #0
u16_t optidx = tcp_optidx++;
80146d2: 4b15 ldr r3, [pc, #84] ; (8014728 <tcp_get_next_optbyte+0x5c>)
80146d4: 881b ldrh r3, [r3, #0]
80146d6: 1c5a adds r2, r3, #1
80146d8: b291 uxth r1, r2
80146da: 4a13 ldr r2, [pc, #76] ; (8014728 <tcp_get_next_optbyte+0x5c>)
80146dc: 8011 strh r1, [r2, #0]
80146de: 80fb strh r3, [r7, #6]
if ((tcphdr_opt2 == NULL) || (optidx < tcphdr_opt1len)) {
80146e0: 4b12 ldr r3, [pc, #72] ; (801472c <tcp_get_next_optbyte+0x60>)
80146e2: 681b ldr r3, [r3, #0]
80146e4: 2b00 cmp r3, #0
80146e6: d004 beq.n 80146f2 <tcp_get_next_optbyte+0x26>
80146e8: 4b11 ldr r3, [pc, #68] ; (8014730 <tcp_get_next_optbyte+0x64>)
80146ea: 881b ldrh r3, [r3, #0]
80146ec: 88fa ldrh r2, [r7, #6]
80146ee: 429a cmp r2, r3
80146f0: d208 bcs.n 8014704 <tcp_get_next_optbyte+0x38>
u8_t *opts = (u8_t *)tcphdr + TCP_HLEN;
80146f2: 4b10 ldr r3, [pc, #64] ; (8014734 <tcp_get_next_optbyte+0x68>)
80146f4: 681b ldr r3, [r3, #0]
80146f6: 3314 adds r3, #20
80146f8: 603b str r3, [r7, #0]
return opts[optidx];
80146fa: 88fb ldrh r3, [r7, #6]
80146fc: 683a ldr r2, [r7, #0]
80146fe: 4413 add r3, r2
8014700: 781b ldrb r3, [r3, #0]
8014702: e00b b.n 801471c <tcp_get_next_optbyte+0x50>
} else {
u8_t idx = (u8_t)(optidx - tcphdr_opt1len);
8014704: 88fb ldrh r3, [r7, #6]
8014706: b2da uxtb r2, r3
8014708: 4b09 ldr r3, [pc, #36] ; (8014730 <tcp_get_next_optbyte+0x64>)
801470a: 881b ldrh r3, [r3, #0]
801470c: b2db uxtb r3, r3
801470e: 1ad3 subs r3, r2, r3
8014710: 717b strb r3, [r7, #5]
return tcphdr_opt2[idx];
8014712: 4b06 ldr r3, [pc, #24] ; (801472c <tcp_get_next_optbyte+0x60>)
8014714: 681a ldr r2, [r3, #0]
8014716: 797b ldrb r3, [r7, #5]
8014718: 4413 add r3, r2
801471a: 781b ldrb r3, [r3, #0]
}
}
801471c: 4618 mov r0, r3
801471e: 370c adds r7, #12
8014720: 46bd mov sp, r7
8014722: f85d 7b04 ldr.w r7, [sp], #4
8014726: 4770 bx lr
8014728: 2000873c .word 0x2000873c
801472c: 20008738 .word 0x20008738
8014730: 20008736 .word 0x20008736
8014734: 20008730 .word 0x20008730
08014738 <tcp_parseopt>:
*
* @param pcb the tcp_pcb for which a segment arrived
*/
static void
tcp_parseopt(struct tcp_pcb *pcb)
{
8014738: b580 push {r7, lr}
801473a: b084 sub sp, #16
801473c: af00 add r7, sp, #0
801473e: 6078 str r0, [r7, #4]
u16_t mss;
#if LWIP_TCP_TIMESTAMPS
u32_t tsval;
#endif
LWIP_ASSERT("tcp_parseopt: invalid pcb", pcb != NULL);
8014740: 687b ldr r3, [r7, #4]
8014742: 2b00 cmp r3, #0
8014744: d106 bne.n 8014754 <tcp_parseopt+0x1c>
8014746: 4b32 ldr r3, [pc, #200] ; (8014810 <tcp_parseopt+0xd8>)
8014748: f240 727d movw r2, #1917 ; 0x77d
801474c: 4931 ldr r1, [pc, #196] ; (8014814 <tcp_parseopt+0xdc>)
801474e: 4832 ldr r0, [pc, #200] ; (8014818 <tcp_parseopt+0xe0>)
8014750: f006 fc38 bl 801afc4 <iprintf>
/* Parse the TCP MSS option, if present. */
if (tcphdr_optlen != 0) {
8014754: 4b31 ldr r3, [pc, #196] ; (801481c <tcp_parseopt+0xe4>)
8014756: 881b ldrh r3, [r3, #0]
8014758: 2b00 cmp r3, #0
801475a: d055 beq.n 8014808 <tcp_parseopt+0xd0>
for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
801475c: 4b30 ldr r3, [pc, #192] ; (8014820 <tcp_parseopt+0xe8>)
801475e: 2200 movs r2, #0
8014760: 801a strh r2, [r3, #0]
8014762: e045 b.n 80147f0 <tcp_parseopt+0xb8>
u8_t opt = tcp_get_next_optbyte();
8014764: f7ff ffb2 bl 80146cc <tcp_get_next_optbyte>
8014768: 4603 mov r3, r0
801476a: 73fb strb r3, [r7, #15]
switch (opt) {
801476c: 7bfb ldrb r3, [r7, #15]
801476e: 2b02 cmp r3, #2
8014770: d006 beq.n 8014780 <tcp_parseopt+0x48>
8014772: 2b02 cmp r3, #2
8014774: dc2b bgt.n 80147ce <tcp_parseopt+0x96>
8014776: 2b00 cmp r3, #0
8014778: d041 beq.n 80147fe <tcp_parseopt+0xc6>
801477a: 2b01 cmp r3, #1
801477c: d127 bne.n 80147ce <tcp_parseopt+0x96>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n"));
return;
case LWIP_TCP_OPT_NOP:
/* NOP option. */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n"));
break;
801477e: e037 b.n 80147f0 <tcp_parseopt+0xb8>
case LWIP_TCP_OPT_MSS:
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n"));
if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_MSS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_MSS) > tcphdr_optlen) {
8014780: f7ff ffa4 bl 80146cc <tcp_get_next_optbyte>
8014784: 4603 mov r3, r0
8014786: 2b04 cmp r3, #4
8014788: d13b bne.n 8014802 <tcp_parseopt+0xca>
801478a: 4b25 ldr r3, [pc, #148] ; (8014820 <tcp_parseopt+0xe8>)
801478c: 881b ldrh r3, [r3, #0]
801478e: 3301 adds r3, #1
8014790: 4a22 ldr r2, [pc, #136] ; (801481c <tcp_parseopt+0xe4>)
8014792: 8812 ldrh r2, [r2, #0]
8014794: 4293 cmp r3, r2
8014796: da34 bge.n 8014802 <tcp_parseopt+0xca>
/* Bad length */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
return;
}
/* An MSS option with the right option length. */
mss = (u16_t)(tcp_get_next_optbyte() << 8);
8014798: f7ff ff98 bl 80146cc <tcp_get_next_optbyte>
801479c: 4603 mov r3, r0
801479e: b29b uxth r3, r3
80147a0: 021b lsls r3, r3, #8
80147a2: 81bb strh r3, [r7, #12]
mss |= tcp_get_next_optbyte();
80147a4: f7ff ff92 bl 80146cc <tcp_get_next_optbyte>
80147a8: 4603 mov r3, r0
80147aa: b29a uxth r2, r3
80147ac: 89bb ldrh r3, [r7, #12]
80147ae: 4313 orrs r3, r2
80147b0: 81bb strh r3, [r7, #12]
/* Limit the mss to the configured TCP_MSS and prevent division by zero */
pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss;
80147b2: 89bb ldrh r3, [r7, #12]
80147b4: f5b3 7f06 cmp.w r3, #536 ; 0x218
80147b8: d804 bhi.n 80147c4 <tcp_parseopt+0x8c>
80147ba: 89bb ldrh r3, [r7, #12]
80147bc: 2b00 cmp r3, #0
80147be: d001 beq.n 80147c4 <tcp_parseopt+0x8c>
80147c0: 89ba ldrh r2, [r7, #12]
80147c2: e001 b.n 80147c8 <tcp_parseopt+0x90>
80147c4: f44f 7206 mov.w r2, #536 ; 0x218
80147c8: 687b ldr r3, [r7, #4]
80147ca: 865a strh r2, [r3, #50] ; 0x32
break;
80147cc: e010 b.n 80147f0 <tcp_parseopt+0xb8>
}
break;
#endif /* LWIP_TCP_SACK_OUT */
default:
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n"));
data = tcp_get_next_optbyte();
80147ce: f7ff ff7d bl 80146cc <tcp_get_next_optbyte>
80147d2: 4603 mov r3, r0
80147d4: 72fb strb r3, [r7, #11]
if (data < 2) {
80147d6: 7afb ldrb r3, [r7, #11]
80147d8: 2b01 cmp r3, #1
80147da: d914 bls.n 8014806 <tcp_parseopt+0xce>
and we don't process them further. */
return;
}
/* All other options have a length field, so that we easily
can skip past them. */
tcp_optidx += data - 2;
80147dc: 7afb ldrb r3, [r7, #11]
80147de: b29a uxth r2, r3
80147e0: 4b0f ldr r3, [pc, #60] ; (8014820 <tcp_parseopt+0xe8>)
80147e2: 881b ldrh r3, [r3, #0]
80147e4: 4413 add r3, r2
80147e6: b29b uxth r3, r3
80147e8: 3b02 subs r3, #2
80147ea: b29a uxth r2, r3
80147ec: 4b0c ldr r3, [pc, #48] ; (8014820 <tcp_parseopt+0xe8>)
80147ee: 801a strh r2, [r3, #0]
for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
80147f0: 4b0b ldr r3, [pc, #44] ; (8014820 <tcp_parseopt+0xe8>)
80147f2: 881a ldrh r2, [r3, #0]
80147f4: 4b09 ldr r3, [pc, #36] ; (801481c <tcp_parseopt+0xe4>)
80147f6: 881b ldrh r3, [r3, #0]
80147f8: 429a cmp r2, r3
80147fa: d3b3 bcc.n 8014764 <tcp_parseopt+0x2c>
80147fc: e004 b.n 8014808 <tcp_parseopt+0xd0>
return;
80147fe: bf00 nop
8014800: e002 b.n 8014808 <tcp_parseopt+0xd0>
return;
8014802: bf00 nop
8014804: e000 b.n 8014808 <tcp_parseopt+0xd0>
return;
8014806: bf00 nop
}
}
}
}
8014808: 3710 adds r7, #16
801480a: 46bd mov sp, r7
801480c: bd80 pop {r7, pc}
801480e: bf00 nop
8014810: 0801d484 .word 0x0801d484
8014814: 0801d8e8 .word 0x0801d8e8
8014818: 0801d4d0 .word 0x0801d4d0
801481c: 20008734 .word 0x20008734
8014820: 2000873c .word 0x2000873c
08014824 <tcp_trigger_input_pcb_close>:
void
tcp_trigger_input_pcb_close(void)
{
8014824: b480 push {r7}
8014826: af00 add r7, sp, #0
recv_flags |= TF_CLOSED;
8014828: 4b05 ldr r3, [pc, #20] ; (8014840 <tcp_trigger_input_pcb_close+0x1c>)
801482a: 781b ldrb r3, [r3, #0]
801482c: f043 0310 orr.w r3, r3, #16
8014830: b2da uxtb r2, r3
8014832: 4b03 ldr r3, [pc, #12] ; (8014840 <tcp_trigger_input_pcb_close+0x1c>)
8014834: 701a strb r2, [r3, #0]
}
8014836: bf00 nop
8014838: 46bd mov sp, r7
801483a: f85d 7b04 ldr.w r7, [sp], #4
801483e: 4770 bx lr
8014840: 2000874d .word 0x2000874d
08014844 <tcp_route>:
static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif);
/* tcp_route: common code that returns a fixed bound netif or calls ip_route */
static struct netif *
tcp_route(const struct tcp_pcb *pcb, const ip_addr_t *src, const ip_addr_t *dst)
{
8014844: b580 push {r7, lr}
8014846: b084 sub sp, #16
8014848: af00 add r7, sp, #0
801484a: 60f8 str r0, [r7, #12]
801484c: 60b9 str r1, [r7, #8]
801484e: 607a str r2, [r7, #4]
LWIP_UNUSED_ARG(src); /* in case IPv4-only and source-based routing is disabled */
if ((pcb != NULL) && (pcb->netif_idx != NETIF_NO_INDEX)) {
8014850: 68fb ldr r3, [r7, #12]
8014852: 2b00 cmp r3, #0
8014854: d00a beq.n 801486c <tcp_route+0x28>
8014856: 68fb ldr r3, [r7, #12]
8014858: 7a1b ldrb r3, [r3, #8]
801485a: 2b00 cmp r3, #0
801485c: d006 beq.n 801486c <tcp_route+0x28>
return netif_get_by_index(pcb->netif_idx);
801485e: 68fb ldr r3, [r7, #12]
8014860: 7a1b ldrb r3, [r3, #8]
8014862: 4618 mov r0, r3
8014864: f7fb fb14 bl 800fe90 <netif_get_by_index>
8014868: 4603 mov r3, r0
801486a: e003 b.n 8014874 <tcp_route+0x30>
} else {
return ip_route(src, dst);
801486c: 6878 ldr r0, [r7, #4]
801486e: f005 f847 bl 8019900 <ip4_route>
8014872: 4603 mov r3, r0
}
}
8014874: 4618 mov r0, r3
8014876: 3710 adds r7, #16
8014878: 46bd mov sp, r7
801487a: bd80 pop {r7, pc}
0801487c <tcp_create_segment>:
* The TCP header is filled in except ackno and wnd.
* p is freed on failure.
*/
static struct tcp_seg *
tcp_create_segment(const struct tcp_pcb *pcb, struct pbuf *p, u8_t hdrflags, u32_t seqno, u8_t optflags)
{
801487c: b590 push {r4, r7, lr}
801487e: b087 sub sp, #28
8014880: af00 add r7, sp, #0
8014882: 60f8 str r0, [r7, #12]
8014884: 60b9 str r1, [r7, #8]
8014886: 603b str r3, [r7, #0]
8014888: 4613 mov r3, r2
801488a: 71fb strb r3, [r7, #7]
struct tcp_seg *seg;
u8_t optlen;
LWIP_ASSERT("tcp_create_segment: invalid pcb", pcb != NULL);
801488c: 68fb ldr r3, [r7, #12]
801488e: 2b00 cmp r3, #0
8014890: d105 bne.n 801489e <tcp_create_segment+0x22>
8014892: 4b44 ldr r3, [pc, #272] ; (80149a4 <tcp_create_segment+0x128>)
8014894: 22a3 movs r2, #163 ; 0xa3
8014896: 4944 ldr r1, [pc, #272] ; (80149a8 <tcp_create_segment+0x12c>)
8014898: 4844 ldr r0, [pc, #272] ; (80149ac <tcp_create_segment+0x130>)
801489a: f006 fb93 bl 801afc4 <iprintf>
LWIP_ASSERT("tcp_create_segment: invalid pbuf", p != NULL);
801489e: 68bb ldr r3, [r7, #8]
80148a0: 2b00 cmp r3, #0
80148a2: d105 bne.n 80148b0 <tcp_create_segment+0x34>
80148a4: 4b3f ldr r3, [pc, #252] ; (80149a4 <tcp_create_segment+0x128>)
80148a6: 22a4 movs r2, #164 ; 0xa4
80148a8: 4941 ldr r1, [pc, #260] ; (80149b0 <tcp_create_segment+0x134>)
80148aa: 4840 ldr r0, [pc, #256] ; (80149ac <tcp_create_segment+0x130>)
80148ac: f006 fb8a bl 801afc4 <iprintf>
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
80148b0: f897 3028 ldrb.w r3, [r7, #40] ; 0x28
80148b4: 009b lsls r3, r3, #2
80148b6: b2db uxtb r3, r3
80148b8: f003 0304 and.w r3, r3, #4
80148bc: 75fb strb r3, [r7, #23]
if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) {
80148be: 2003 movs r0, #3
80148c0: f7fa ff72 bl 800f7a8 <memp_malloc>
80148c4: 6138 str r0, [r7, #16]
80148c6: 693b ldr r3, [r7, #16]
80148c8: 2b00 cmp r3, #0
80148ca: d104 bne.n 80148d6 <tcp_create_segment+0x5a>
LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no memory.\n"));
pbuf_free(p);
80148cc: 68b8 ldr r0, [r7, #8]
80148ce: f7fb fe6d bl 80105ac <pbuf_free>
return NULL;
80148d2: 2300 movs r3, #0
80148d4: e061 b.n 801499a <tcp_create_segment+0x11e>
}
seg->flags = optflags;
80148d6: 693b ldr r3, [r7, #16]
80148d8: f897 2028 ldrb.w r2, [r7, #40] ; 0x28
80148dc: 729a strb r2, [r3, #10]
seg->next = NULL;
80148de: 693b ldr r3, [r7, #16]
80148e0: 2200 movs r2, #0
80148e2: 601a str r2, [r3, #0]
seg->p = p;
80148e4: 693b ldr r3, [r7, #16]
80148e6: 68ba ldr r2, [r7, #8]
80148e8: 605a str r2, [r3, #4]
LWIP_ASSERT("p->tot_len >= optlen", p->tot_len >= optlen);
80148ea: 68bb ldr r3, [r7, #8]
80148ec: 891a ldrh r2, [r3, #8]
80148ee: 7dfb ldrb r3, [r7, #23]
80148f0: b29b uxth r3, r3
80148f2: 429a cmp r2, r3
80148f4: d205 bcs.n 8014902 <tcp_create_segment+0x86>
80148f6: 4b2b ldr r3, [pc, #172] ; (80149a4 <tcp_create_segment+0x128>)
80148f8: 22b0 movs r2, #176 ; 0xb0
80148fa: 492e ldr r1, [pc, #184] ; (80149b4 <tcp_create_segment+0x138>)
80148fc: 482b ldr r0, [pc, #172] ; (80149ac <tcp_create_segment+0x130>)
80148fe: f006 fb61 bl 801afc4 <iprintf>
seg->len = p->tot_len - optlen;
8014902: 68bb ldr r3, [r7, #8]
8014904: 891a ldrh r2, [r3, #8]
8014906: 7dfb ldrb r3, [r7, #23]
8014908: b29b uxth r3, r3
801490a: 1ad3 subs r3, r2, r3
801490c: b29a uxth r2, r3
801490e: 693b ldr r3, [r7, #16]
8014910: 811a strh r2, [r3, #8]
LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED",
(optflags & TF_SEG_DATA_CHECKSUMMED) == 0);
#endif /* TCP_CHECKSUM_ON_COPY */
/* build TCP header */
if (pbuf_add_header(p, TCP_HLEN)) {
8014912: 2114 movs r1, #20
8014914: 68b8 ldr r0, [r7, #8]
8014916: f7fb fdb3 bl 8010480 <pbuf_add_header>
801491a: 4603 mov r3, r0
801491c: 2b00 cmp r3, #0
801491e: d004 beq.n 801492a <tcp_create_segment+0xae>
LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no room for TCP header in pbuf.\n"));
TCP_STATS_INC(tcp.err);
tcp_seg_free(seg);
8014920: 6938 ldr r0, [r7, #16]
8014922: f7fd f8d2 bl 8011aca <tcp_seg_free>
return NULL;
8014926: 2300 movs r3, #0
8014928: e037 b.n 801499a <tcp_create_segment+0x11e>
}
seg->tcphdr = (struct tcp_hdr *)seg->p->payload;
801492a: 693b ldr r3, [r7, #16]
801492c: 685b ldr r3, [r3, #4]
801492e: 685a ldr r2, [r3, #4]
8014930: 693b ldr r3, [r7, #16]
8014932: 60da str r2, [r3, #12]
seg->tcphdr->src = lwip_htons(pcb->local_port);
8014934: 68fb ldr r3, [r7, #12]
8014936: 8ada ldrh r2, [r3, #22]
8014938: 693b ldr r3, [r7, #16]
801493a: 68dc ldr r4, [r3, #12]
801493c: 4610 mov r0, r2
801493e: f7fa fa7d bl 800ee3c <lwip_htons>
8014942: 4603 mov r3, r0
8014944: 8023 strh r3, [r4, #0]
seg->tcphdr->dest = lwip_htons(pcb->remote_port);
8014946: 68fb ldr r3, [r7, #12]
8014948: 8b1a ldrh r2, [r3, #24]
801494a: 693b ldr r3, [r7, #16]
801494c: 68dc ldr r4, [r3, #12]
801494e: 4610 mov r0, r2
8014950: f7fa fa74 bl 800ee3c <lwip_htons>
8014954: 4603 mov r3, r0
8014956: 8063 strh r3, [r4, #2]
seg->tcphdr->seqno = lwip_htonl(seqno);
8014958: 693b ldr r3, [r7, #16]
801495a: 68dc ldr r4, [r3, #12]
801495c: 6838 ldr r0, [r7, #0]
801495e: f7fa fa82 bl 800ee66 <lwip_htonl>
8014962: 4603 mov r3, r0
8014964: 6063 str r3, [r4, #4]
/* ackno is set in tcp_output */
TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), hdrflags);
8014966: 7dfb ldrb r3, [r7, #23]
8014968: 089b lsrs r3, r3, #2
801496a: b2db uxtb r3, r3
801496c: b29b uxth r3, r3
801496e: 3305 adds r3, #5
8014970: b29b uxth r3, r3
8014972: 031b lsls r3, r3, #12
8014974: b29a uxth r2, r3
8014976: 79fb ldrb r3, [r7, #7]
8014978: b29b uxth r3, r3
801497a: 4313 orrs r3, r2
801497c: b29a uxth r2, r3
801497e: 693b ldr r3, [r7, #16]
8014980: 68dc ldr r4, [r3, #12]
8014982: 4610 mov r0, r2
8014984: f7fa fa5a bl 800ee3c <lwip_htons>
8014988: 4603 mov r3, r0
801498a: 81a3 strh r3, [r4, #12]
/* wnd and chksum are set in tcp_output */
seg->tcphdr->urgp = 0;
801498c: 693b ldr r3, [r7, #16]
801498e: 68db ldr r3, [r3, #12]
8014990: 2200 movs r2, #0
8014992: 749a strb r2, [r3, #18]
8014994: 2200 movs r2, #0
8014996: 74da strb r2, [r3, #19]
return seg;
8014998: 693b ldr r3, [r7, #16]
}
801499a: 4618 mov r0, r3
801499c: 371c adds r7, #28
801499e: 46bd mov sp, r7
80149a0: bd90 pop {r4, r7, pc}
80149a2: bf00 nop
80149a4: 0801d904 .word 0x0801d904
80149a8: 0801d938 .word 0x0801d938
80149ac: 0801d958 .word 0x0801d958
80149b0: 0801d980 .word 0x0801d980
80149b4: 0801d9a4 .word 0x0801d9a4
080149b8 <tcp_split_unsent_seg>:
* @param pcb the tcp_pcb for which to split the unsent head
* @param split the amount of payload to remain in the head
*/
err_t
tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split)
{
80149b8: b590 push {r4, r7, lr}
80149ba: b08b sub sp, #44 ; 0x2c
80149bc: af02 add r7, sp, #8
80149be: 6078 str r0, [r7, #4]
80149c0: 460b mov r3, r1
80149c2: 807b strh r3, [r7, #2]
struct tcp_seg *seg = NULL, *useg = NULL;
80149c4: 2300 movs r3, #0
80149c6: 61fb str r3, [r7, #28]
80149c8: 2300 movs r3, #0
80149ca: 617b str r3, [r7, #20]
struct pbuf *p = NULL;
80149cc: 2300 movs r3, #0
80149ce: 613b str r3, [r7, #16]
u16_t chksum = 0;
u8_t chksum_swapped = 0;
struct pbuf *q;
#endif /* TCP_CHECKSUM_ON_COPY */
LWIP_ASSERT("tcp_split_unsent_seg: invalid pcb", pcb != NULL);
80149d0: 687b ldr r3, [r7, #4]
80149d2: 2b00 cmp r3, #0
80149d4: d106 bne.n 80149e4 <tcp_split_unsent_seg+0x2c>
80149d6: 4b95 ldr r3, [pc, #596] ; (8014c2c <tcp_split_unsent_seg+0x274>)
80149d8: f240 324b movw r2, #843 ; 0x34b
80149dc: 4994 ldr r1, [pc, #592] ; (8014c30 <tcp_split_unsent_seg+0x278>)
80149de: 4895 ldr r0, [pc, #596] ; (8014c34 <tcp_split_unsent_seg+0x27c>)
80149e0: f006 faf0 bl 801afc4 <iprintf>
useg = pcb->unsent;
80149e4: 687b ldr r3, [r7, #4]
80149e6: 6edb ldr r3, [r3, #108] ; 0x6c
80149e8: 617b str r3, [r7, #20]
if (useg == NULL) {
80149ea: 697b ldr r3, [r7, #20]
80149ec: 2b00 cmp r3, #0
80149ee: d102 bne.n 80149f6 <tcp_split_unsent_seg+0x3e>
return ERR_MEM;
80149f0: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
80149f4: e116 b.n 8014c24 <tcp_split_unsent_seg+0x26c>
}
if (split == 0) {
80149f6: 887b ldrh r3, [r7, #2]
80149f8: 2b00 cmp r3, #0
80149fa: d109 bne.n 8014a10 <tcp_split_unsent_seg+0x58>
LWIP_ASSERT("Can't split segment into length 0", 0);
80149fc: 4b8b ldr r3, [pc, #556] ; (8014c2c <tcp_split_unsent_seg+0x274>)
80149fe: f240 3253 movw r2, #851 ; 0x353
8014a02: 498d ldr r1, [pc, #564] ; (8014c38 <tcp_split_unsent_seg+0x280>)
8014a04: 488b ldr r0, [pc, #556] ; (8014c34 <tcp_split_unsent_seg+0x27c>)
8014a06: f006 fadd bl 801afc4 <iprintf>
return ERR_VAL;
8014a0a: f06f 0305 mvn.w r3, #5
8014a0e: e109 b.n 8014c24 <tcp_split_unsent_seg+0x26c>
}
if (useg->len <= split) {
8014a10: 697b ldr r3, [r7, #20]
8014a12: 891b ldrh r3, [r3, #8]
8014a14: 887a ldrh r2, [r7, #2]
8014a16: 429a cmp r2, r3
8014a18: d301 bcc.n 8014a1e <tcp_split_unsent_seg+0x66>
return ERR_OK;
8014a1a: 2300 movs r3, #0
8014a1c: e102 b.n 8014c24 <tcp_split_unsent_seg+0x26c>
}
LWIP_ASSERT("split <= mss", split <= pcb->mss);
8014a1e: 687b ldr r3, [r7, #4]
8014a20: 8e5b ldrh r3, [r3, #50] ; 0x32
8014a22: 887a ldrh r2, [r7, #2]
8014a24: 429a cmp r2, r3
8014a26: d906 bls.n 8014a36 <tcp_split_unsent_seg+0x7e>
8014a28: 4b80 ldr r3, [pc, #512] ; (8014c2c <tcp_split_unsent_seg+0x274>)
8014a2a: f240 325b movw r2, #859 ; 0x35b
8014a2e: 4983 ldr r1, [pc, #524] ; (8014c3c <tcp_split_unsent_seg+0x284>)
8014a30: 4880 ldr r0, [pc, #512] ; (8014c34 <tcp_split_unsent_seg+0x27c>)
8014a32: f006 fac7 bl 801afc4 <iprintf>
LWIP_ASSERT("useg->len > 0", useg->len > 0);
8014a36: 697b ldr r3, [r7, #20]
8014a38: 891b ldrh r3, [r3, #8]
8014a3a: 2b00 cmp r3, #0
8014a3c: d106 bne.n 8014a4c <tcp_split_unsent_seg+0x94>
8014a3e: 4b7b ldr r3, [pc, #492] ; (8014c2c <tcp_split_unsent_seg+0x274>)
8014a40: f44f 7257 mov.w r2, #860 ; 0x35c
8014a44: 497e ldr r1, [pc, #504] ; (8014c40 <tcp_split_unsent_seg+0x288>)
8014a46: 487b ldr r0, [pc, #492] ; (8014c34 <tcp_split_unsent_seg+0x27c>)
8014a48: f006 fabc bl 801afc4 <iprintf>
* to split this packet so we may actually exceed the max value by
* one!
*/
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: split_unsent_seg: %u\n", (unsigned int)pcb->snd_queuelen));
optflags = useg->flags;
8014a4c: 697b ldr r3, [r7, #20]
8014a4e: 7a9b ldrb r3, [r3, #10]
8014a50: 73fb strb r3, [r7, #15]
#if TCP_CHECKSUM_ON_COPY
/* Remove since checksum is not stored until after tcp_create_segment() */
optflags &= ~TF_SEG_DATA_CHECKSUMMED;
#endif /* TCP_CHECKSUM_ON_COPY */
optlen = LWIP_TCP_OPT_LENGTH(optflags);
8014a52: 7bfb ldrb r3, [r7, #15]
8014a54: 009b lsls r3, r3, #2
8014a56: b2db uxtb r3, r3
8014a58: f003 0304 and.w r3, r3, #4
8014a5c: 73bb strb r3, [r7, #14]
remainder = useg->len - split;
8014a5e: 697b ldr r3, [r7, #20]
8014a60: 891a ldrh r2, [r3, #8]
8014a62: 887b ldrh r3, [r7, #2]
8014a64: 1ad3 subs r3, r2, r3
8014a66: 81bb strh r3, [r7, #12]
/* Create new pbuf for the remainder of the split */
p = pbuf_alloc(PBUF_TRANSPORT, remainder + optlen, PBUF_RAM);
8014a68: 7bbb ldrb r3, [r7, #14]
8014a6a: b29a uxth r2, r3
8014a6c: 89bb ldrh r3, [r7, #12]
8014a6e: 4413 add r3, r2
8014a70: b29b uxth r3, r3
8014a72: f44f 7220 mov.w r2, #640 ; 0x280
8014a76: 4619 mov r1, r3
8014a78: 2036 movs r0, #54 ; 0x36
8014a7a: f7fb fab3 bl 800ffe4 <pbuf_alloc>
8014a7e: 6138 str r0, [r7, #16]
if (p == NULL) {
8014a80: 693b ldr r3, [r7, #16]
8014a82: 2b00 cmp r3, #0
8014a84: f000 80b7 beq.w 8014bf6 <tcp_split_unsent_seg+0x23e>
("tcp_split_unsent_seg: could not allocate memory for pbuf remainder %u\n", remainder));
goto memerr;
}
/* Offset into the original pbuf is past TCP/IP headers, options, and split amount */
offset = useg->p->tot_len - useg->len + split;
8014a88: 697b ldr r3, [r7, #20]
8014a8a: 685b ldr r3, [r3, #4]
8014a8c: 891a ldrh r2, [r3, #8]
8014a8e: 697b ldr r3, [r7, #20]
8014a90: 891b ldrh r3, [r3, #8]
8014a92: 1ad3 subs r3, r2, r3
8014a94: b29a uxth r2, r3
8014a96: 887b ldrh r3, [r7, #2]
8014a98: 4413 add r3, r2
8014a9a: 817b strh r3, [r7, #10]
/* Copy remainder into new pbuf, headers and options will not be filled out */
if (pbuf_copy_partial(useg->p, (u8_t *)p->payload + optlen, remainder, offset ) != remainder) {
8014a9c: 697b ldr r3, [r7, #20]
8014a9e: 6858 ldr r0, [r3, #4]
8014aa0: 693b ldr r3, [r7, #16]
8014aa2: 685a ldr r2, [r3, #4]
8014aa4: 7bbb ldrb r3, [r7, #14]
8014aa6: 18d1 adds r1, r2, r3
8014aa8: 897b ldrh r3, [r7, #10]
8014aaa: 89ba ldrh r2, [r7, #12]
8014aac: f7fb ff84 bl 80109b8 <pbuf_copy_partial>
8014ab0: 4603 mov r3, r0
8014ab2: 461a mov r2, r3
8014ab4: 89bb ldrh r3, [r7, #12]
8014ab6: 4293 cmp r3, r2
8014ab8: f040 809f bne.w 8014bfa <tcp_split_unsent_seg+0x242>
#endif /* TCP_CHECKSUM_ON_COPY */
/* Options are created when calling tcp_output() */
/* Migrate flags from original segment */
split_flags = TCPH_FLAGS(useg->tcphdr);
8014abc: 697b ldr r3, [r7, #20]
8014abe: 68db ldr r3, [r3, #12]
8014ac0: 899b ldrh r3, [r3, #12]
8014ac2: b29b uxth r3, r3
8014ac4: 4618 mov r0, r3
8014ac6: f7fa f9b9 bl 800ee3c <lwip_htons>
8014aca: 4603 mov r3, r0
8014acc: b2db uxtb r3, r3
8014ace: f003 033f and.w r3, r3, #63 ; 0x3f
8014ad2: 76fb strb r3, [r7, #27]
remainder_flags = 0; /* ACK added in tcp_output() */
8014ad4: 2300 movs r3, #0
8014ad6: 76bb strb r3, [r7, #26]
if (split_flags & TCP_PSH) {
8014ad8: 7efb ldrb r3, [r7, #27]
8014ada: f003 0308 and.w r3, r3, #8
8014ade: 2b00 cmp r3, #0
8014ae0: d007 beq.n 8014af2 <tcp_split_unsent_seg+0x13a>
split_flags &= ~TCP_PSH;
8014ae2: 7efb ldrb r3, [r7, #27]
8014ae4: f023 0308 bic.w r3, r3, #8
8014ae8: 76fb strb r3, [r7, #27]
remainder_flags |= TCP_PSH;
8014aea: 7ebb ldrb r3, [r7, #26]
8014aec: f043 0308 orr.w r3, r3, #8
8014af0: 76bb strb r3, [r7, #26]
}
if (split_flags & TCP_FIN) {
8014af2: 7efb ldrb r3, [r7, #27]
8014af4: f003 0301 and.w r3, r3, #1
8014af8: 2b00 cmp r3, #0
8014afa: d007 beq.n 8014b0c <tcp_split_unsent_seg+0x154>
split_flags &= ~TCP_FIN;
8014afc: 7efb ldrb r3, [r7, #27]
8014afe: f023 0301 bic.w r3, r3, #1
8014b02: 76fb strb r3, [r7, #27]
remainder_flags |= TCP_FIN;
8014b04: 7ebb ldrb r3, [r7, #26]
8014b06: f043 0301 orr.w r3, r3, #1
8014b0a: 76bb strb r3, [r7, #26]
}
/* SYN should be left on split, RST should not be present with data */
seg = tcp_create_segment(pcb, p, remainder_flags, lwip_ntohl(useg->tcphdr->seqno) + split, optflags);
8014b0c: 697b ldr r3, [r7, #20]
8014b0e: 68db ldr r3, [r3, #12]
8014b10: 685b ldr r3, [r3, #4]
8014b12: 4618 mov r0, r3
8014b14: f7fa f9a7 bl 800ee66 <lwip_htonl>
8014b18: 4602 mov r2, r0
8014b1a: 887b ldrh r3, [r7, #2]
8014b1c: 18d1 adds r1, r2, r3
8014b1e: 7eba ldrb r2, [r7, #26]
8014b20: 7bfb ldrb r3, [r7, #15]
8014b22: 9300 str r3, [sp, #0]
8014b24: 460b mov r3, r1
8014b26: 6939 ldr r1, [r7, #16]
8014b28: 6878 ldr r0, [r7, #4]
8014b2a: f7ff fea7 bl 801487c <tcp_create_segment>
8014b2e: 61f8 str r0, [r7, #28]
if (seg == NULL) {
8014b30: 69fb ldr r3, [r7, #28]
8014b32: 2b00 cmp r3, #0
8014b34: d063 beq.n 8014bfe <tcp_split_unsent_seg+0x246>
seg->chksum_swapped = chksum_swapped;
seg->flags |= TF_SEG_DATA_CHECKSUMMED;
#endif /* TCP_CHECKSUM_ON_COPY */
/* Remove this segment from the queue since trimming it may free pbufs */
pcb->snd_queuelen -= pbuf_clen(useg->p);
8014b36: 697b ldr r3, [r7, #20]
8014b38: 685b ldr r3, [r3, #4]
8014b3a: 4618 mov r0, r3
8014b3c: f7fb fdc4 bl 80106c8 <pbuf_clen>
8014b40: 4603 mov r3, r0
8014b42: 461a mov r2, r3
8014b44: 687b ldr r3, [r7, #4]
8014b46: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014b4a: 1a9b subs r3, r3, r2
8014b4c: b29a uxth r2, r3
8014b4e: 687b ldr r3, [r7, #4]
8014b50: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
/* Trim the original pbuf into our split size. At this point our remainder segment must be setup
successfully because we are modifying the original segment */
pbuf_realloc(useg->p, useg->p->tot_len - remainder);
8014b54: 697b ldr r3, [r7, #20]
8014b56: 6858 ldr r0, [r3, #4]
8014b58: 697b ldr r3, [r7, #20]
8014b5a: 685b ldr r3, [r3, #4]
8014b5c: 891a ldrh r2, [r3, #8]
8014b5e: 89bb ldrh r3, [r7, #12]
8014b60: 1ad3 subs r3, r2, r3
8014b62: b29b uxth r3, r3
8014b64: 4619 mov r1, r3
8014b66: f7fb fb9b bl 80102a0 <pbuf_realloc>
useg->len -= remainder;
8014b6a: 697b ldr r3, [r7, #20]
8014b6c: 891a ldrh r2, [r3, #8]
8014b6e: 89bb ldrh r3, [r7, #12]
8014b70: 1ad3 subs r3, r2, r3
8014b72: b29a uxth r2, r3
8014b74: 697b ldr r3, [r7, #20]
8014b76: 811a strh r2, [r3, #8]
TCPH_SET_FLAG(useg->tcphdr, split_flags);
8014b78: 697b ldr r3, [r7, #20]
8014b7a: 68db ldr r3, [r3, #12]
8014b7c: 899b ldrh r3, [r3, #12]
8014b7e: b29c uxth r4, r3
8014b80: 7efb ldrb r3, [r7, #27]
8014b82: b29b uxth r3, r3
8014b84: 4618 mov r0, r3
8014b86: f7fa f959 bl 800ee3c <lwip_htons>
8014b8a: 4603 mov r3, r0
8014b8c: 461a mov r2, r3
8014b8e: 697b ldr r3, [r7, #20]
8014b90: 68db ldr r3, [r3, #12]
8014b92: 4322 orrs r2, r4
8014b94: b292 uxth r2, r2
8014b96: 819a strh r2, [r3, #12]
/* By trimming, realloc may have actually shrunk the pbuf, so clear oversize_left */
useg->oversize_left = 0;
#endif /* TCP_OVERSIZE_DBGCHECK */
/* Add back to the queue with new trimmed pbuf */
pcb->snd_queuelen += pbuf_clen(useg->p);
8014b98: 697b ldr r3, [r7, #20]
8014b9a: 685b ldr r3, [r3, #4]
8014b9c: 4618 mov r0, r3
8014b9e: f7fb fd93 bl 80106c8 <pbuf_clen>
8014ba2: 4603 mov r3, r0
8014ba4: 461a mov r2, r3
8014ba6: 687b ldr r3, [r7, #4]
8014ba8: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014bac: 4413 add r3, r2
8014bae: b29a uxth r2, r3
8014bb0: 687b ldr r3, [r7, #4]
8014bb2: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
#endif /* TCP_CHECKSUM_ON_COPY */
/* Update number of segments on the queues. Note that length now may
* exceed TCP_SND_QUEUELEN! We don't have to touch pcb->snd_buf
* because the total amount of data is constant when packet is split */
pcb->snd_queuelen += pbuf_clen(seg->p);
8014bb6: 69fb ldr r3, [r7, #28]
8014bb8: 685b ldr r3, [r3, #4]
8014bba: 4618 mov r0, r3
8014bbc: f7fb fd84 bl 80106c8 <pbuf_clen>
8014bc0: 4603 mov r3, r0
8014bc2: 461a mov r2, r3
8014bc4: 687b ldr r3, [r7, #4]
8014bc6: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014bca: 4413 add r3, r2
8014bcc: b29a uxth r2, r3
8014bce: 687b ldr r3, [r7, #4]
8014bd0: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
/* Finally insert remainder into queue after split (which stays head) */
seg->next = useg->next;
8014bd4: 697b ldr r3, [r7, #20]
8014bd6: 681a ldr r2, [r3, #0]
8014bd8: 69fb ldr r3, [r7, #28]
8014bda: 601a str r2, [r3, #0]
useg->next = seg;
8014bdc: 697b ldr r3, [r7, #20]
8014bde: 69fa ldr r2, [r7, #28]
8014be0: 601a str r2, [r3, #0]
#if TCP_OVERSIZE
/* If remainder is last segment on the unsent, ensure we clear the oversize amount
* because the remainder is always sized to the exact remaining amount */
if (seg->next == NULL) {
8014be2: 69fb ldr r3, [r7, #28]
8014be4: 681b ldr r3, [r3, #0]
8014be6: 2b00 cmp r3, #0
8014be8: d103 bne.n 8014bf2 <tcp_split_unsent_seg+0x23a>
pcb->unsent_oversize = 0;
8014bea: 687b ldr r3, [r7, #4]
8014bec: 2200 movs r2, #0
8014bee: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
}
#endif /* TCP_OVERSIZE */
return ERR_OK;
8014bf2: 2300 movs r3, #0
8014bf4: e016 b.n 8014c24 <tcp_split_unsent_seg+0x26c>
goto memerr;
8014bf6: bf00 nop
8014bf8: e002 b.n 8014c00 <tcp_split_unsent_seg+0x248>
goto memerr;
8014bfa: bf00 nop
8014bfc: e000 b.n 8014c00 <tcp_split_unsent_seg+0x248>
goto memerr;
8014bfe: bf00 nop
memerr:
TCP_STATS_INC(tcp.memerr);
LWIP_ASSERT("seg == NULL", seg == NULL);
8014c00: 69fb ldr r3, [r7, #28]
8014c02: 2b00 cmp r3, #0
8014c04: d006 beq.n 8014c14 <tcp_split_unsent_seg+0x25c>
8014c06: 4b09 ldr r3, [pc, #36] ; (8014c2c <tcp_split_unsent_seg+0x274>)
8014c08: f44f 7276 mov.w r2, #984 ; 0x3d8
8014c0c: 490d ldr r1, [pc, #52] ; (8014c44 <tcp_split_unsent_seg+0x28c>)
8014c0e: 4809 ldr r0, [pc, #36] ; (8014c34 <tcp_split_unsent_seg+0x27c>)
8014c10: f006 f9d8 bl 801afc4 <iprintf>
if (p != NULL) {
8014c14: 693b ldr r3, [r7, #16]
8014c16: 2b00 cmp r3, #0
8014c18: d002 beq.n 8014c20 <tcp_split_unsent_seg+0x268>
pbuf_free(p);
8014c1a: 6938 ldr r0, [r7, #16]
8014c1c: f7fb fcc6 bl 80105ac <pbuf_free>
}
return ERR_MEM;
8014c20: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
}
8014c24: 4618 mov r0, r3
8014c26: 3724 adds r7, #36 ; 0x24
8014c28: 46bd mov sp, r7
8014c2a: bd90 pop {r4, r7, pc}
8014c2c: 0801d904 .word 0x0801d904
8014c30: 0801dc98 .word 0x0801dc98
8014c34: 0801d958 .word 0x0801d958
8014c38: 0801dcbc .word 0x0801dcbc
8014c3c: 0801dce0 .word 0x0801dce0
8014c40: 0801dcf0 .word 0x0801dcf0
8014c44: 0801dd00 .word 0x0801dd00
08014c48 <tcp_send_fin>:
* @param pcb the tcp_pcb over which to send a segment
* @return ERR_OK if sent, another err_t otherwise
*/
err_t
tcp_send_fin(struct tcp_pcb *pcb)
{
8014c48: b590 push {r4, r7, lr}
8014c4a: b085 sub sp, #20
8014c4c: af00 add r7, sp, #0
8014c4e: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_send_fin: invalid pcb", pcb != NULL);
8014c50: 687b ldr r3, [r7, #4]
8014c52: 2b00 cmp r3, #0
8014c54: d106 bne.n 8014c64 <tcp_send_fin+0x1c>
8014c56: 4b21 ldr r3, [pc, #132] ; (8014cdc <tcp_send_fin+0x94>)
8014c58: f240 32eb movw r2, #1003 ; 0x3eb
8014c5c: 4920 ldr r1, [pc, #128] ; (8014ce0 <tcp_send_fin+0x98>)
8014c5e: 4821 ldr r0, [pc, #132] ; (8014ce4 <tcp_send_fin+0x9c>)
8014c60: f006 f9b0 bl 801afc4 <iprintf>
/* first, try to add the fin to the last unsent segment */
if (pcb->unsent != NULL) {
8014c64: 687b ldr r3, [r7, #4]
8014c66: 6edb ldr r3, [r3, #108] ; 0x6c
8014c68: 2b00 cmp r3, #0
8014c6a: d02e beq.n 8014cca <tcp_send_fin+0x82>
struct tcp_seg *last_unsent;
for (last_unsent = pcb->unsent; last_unsent->next != NULL;
8014c6c: 687b ldr r3, [r7, #4]
8014c6e: 6edb ldr r3, [r3, #108] ; 0x6c
8014c70: 60fb str r3, [r7, #12]
8014c72: e002 b.n 8014c7a <tcp_send_fin+0x32>
last_unsent = last_unsent->next);
8014c74: 68fb ldr r3, [r7, #12]
8014c76: 681b ldr r3, [r3, #0]
8014c78: 60fb str r3, [r7, #12]
for (last_unsent = pcb->unsent; last_unsent->next != NULL;
8014c7a: 68fb ldr r3, [r7, #12]
8014c7c: 681b ldr r3, [r3, #0]
8014c7e: 2b00 cmp r3, #0
8014c80: d1f8 bne.n 8014c74 <tcp_send_fin+0x2c>
if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) {
8014c82: 68fb ldr r3, [r7, #12]
8014c84: 68db ldr r3, [r3, #12]
8014c86: 899b ldrh r3, [r3, #12]
8014c88: b29b uxth r3, r3
8014c8a: 4618 mov r0, r3
8014c8c: f7fa f8d6 bl 800ee3c <lwip_htons>
8014c90: 4603 mov r3, r0
8014c92: b2db uxtb r3, r3
8014c94: f003 0307 and.w r3, r3, #7
8014c98: 2b00 cmp r3, #0
8014c9a: d116 bne.n 8014cca <tcp_send_fin+0x82>
/* no SYN/FIN/RST flag in the header, we can add the FIN flag */
TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN);
8014c9c: 68fb ldr r3, [r7, #12]
8014c9e: 68db ldr r3, [r3, #12]
8014ca0: 899b ldrh r3, [r3, #12]
8014ca2: b29c uxth r4, r3
8014ca4: 2001 movs r0, #1
8014ca6: f7fa f8c9 bl 800ee3c <lwip_htons>
8014caa: 4603 mov r3, r0
8014cac: 461a mov r2, r3
8014cae: 68fb ldr r3, [r7, #12]
8014cb0: 68db ldr r3, [r3, #12]
8014cb2: 4322 orrs r2, r4
8014cb4: b292 uxth r2, r2
8014cb6: 819a strh r2, [r3, #12]
tcp_set_flags(pcb, TF_FIN);
8014cb8: 687b ldr r3, [r7, #4]
8014cba: 8b5b ldrh r3, [r3, #26]
8014cbc: f043 0320 orr.w r3, r3, #32
8014cc0: b29a uxth r2, r3
8014cc2: 687b ldr r3, [r7, #4]
8014cc4: 835a strh r2, [r3, #26]
return ERR_OK;
8014cc6: 2300 movs r3, #0
8014cc8: e004 b.n 8014cd4 <tcp_send_fin+0x8c>
}
}
/* no data, no length, flags, copy=1, no optdata */
return tcp_enqueue_flags(pcb, TCP_FIN);
8014cca: 2101 movs r1, #1
8014ccc: 6878 ldr r0, [r7, #4]
8014cce: f000 f80b bl 8014ce8 <tcp_enqueue_flags>
8014cd2: 4603 mov r3, r0
}
8014cd4: 4618 mov r0, r3
8014cd6: 3714 adds r7, #20
8014cd8: 46bd mov sp, r7
8014cda: bd90 pop {r4, r7, pc}
8014cdc: 0801d904 .word 0x0801d904
8014ce0: 0801dd0c .word 0x0801dd0c
8014ce4: 0801d958 .word 0x0801d958
08014ce8 <tcp_enqueue_flags>:
* @param pcb Protocol control block for the TCP connection.
* @param flags TCP header flags to set in the outgoing segment.
*/
err_t
tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags)
{
8014ce8: b580 push {r7, lr}
8014cea: b08a sub sp, #40 ; 0x28
8014cec: af02 add r7, sp, #8
8014cee: 6078 str r0, [r7, #4]
8014cf0: 460b mov r3, r1
8014cf2: 70fb strb r3, [r7, #3]
struct pbuf *p;
struct tcp_seg *seg;
u8_t optflags = 0;
8014cf4: 2300 movs r3, #0
8014cf6: 77fb strb r3, [r7, #31]
u8_t optlen = 0;
8014cf8: 2300 movs r3, #0
8014cfa: 75fb strb r3, [r7, #23]
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)",
8014cfc: 78fb ldrb r3, [r7, #3]
8014cfe: f003 0303 and.w r3, r3, #3
8014d02: 2b00 cmp r3, #0
8014d04: d106 bne.n 8014d14 <tcp_enqueue_flags+0x2c>
8014d06: 4b67 ldr r3, [pc, #412] ; (8014ea4 <tcp_enqueue_flags+0x1bc>)
8014d08: f240 4211 movw r2, #1041 ; 0x411
8014d0c: 4966 ldr r1, [pc, #408] ; (8014ea8 <tcp_enqueue_flags+0x1c0>)
8014d0e: 4867 ldr r0, [pc, #412] ; (8014eac <tcp_enqueue_flags+0x1c4>)
8014d10: f006 f958 bl 801afc4 <iprintf>
(flags & (TCP_SYN | TCP_FIN)) != 0);
LWIP_ASSERT("tcp_enqueue_flags: invalid pcb", pcb != NULL);
8014d14: 687b ldr r3, [r7, #4]
8014d16: 2b00 cmp r3, #0
8014d18: d106 bne.n 8014d28 <tcp_enqueue_flags+0x40>
8014d1a: 4b62 ldr r3, [pc, #392] ; (8014ea4 <tcp_enqueue_flags+0x1bc>)
8014d1c: f240 4213 movw r2, #1043 ; 0x413
8014d20: 4963 ldr r1, [pc, #396] ; (8014eb0 <tcp_enqueue_flags+0x1c8>)
8014d22: 4862 ldr r0, [pc, #392] ; (8014eac <tcp_enqueue_flags+0x1c4>)
8014d24: f006 f94e bl 801afc4 <iprintf>
/* No need to check pcb->snd_queuelen if only SYN or FIN are allowed! */
/* Get options for this segment. This is a special case since this is the
only place where a SYN can be sent. */
if (flags & TCP_SYN) {
8014d28: 78fb ldrb r3, [r7, #3]
8014d2a: f003 0302 and.w r3, r3, #2
8014d2e: 2b00 cmp r3, #0
8014d30: d001 beq.n 8014d36 <tcp_enqueue_flags+0x4e>
optflags = TF_SEG_OPTS_MSS;
8014d32: 2301 movs r3, #1
8014d34: 77fb strb r3, [r7, #31]
/* Make sure the timestamp option is only included in data segments if we
agreed about it with the remote host (and in active open SYN segments). */
optflags |= TF_SEG_OPTS_TS;
}
#endif /* LWIP_TCP_TIMESTAMPS */
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
8014d36: 7ffb ldrb r3, [r7, #31]
8014d38: 009b lsls r3, r3, #2
8014d3a: b2db uxtb r3, r3
8014d3c: f003 0304 and.w r3, r3, #4
8014d40: 75fb strb r3, [r7, #23]
/* Allocate pbuf with room for TCP header + options */
if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
8014d42: 7dfb ldrb r3, [r7, #23]
8014d44: b29b uxth r3, r3
8014d46: f44f 7220 mov.w r2, #640 ; 0x280
8014d4a: 4619 mov r1, r3
8014d4c: 2036 movs r0, #54 ; 0x36
8014d4e: f7fb f949 bl 800ffe4 <pbuf_alloc>
8014d52: 6138 str r0, [r7, #16]
8014d54: 693b ldr r3, [r7, #16]
8014d56: 2b00 cmp r3, #0
8014d58: d109 bne.n 8014d6e <tcp_enqueue_flags+0x86>
tcp_set_flags(pcb, TF_NAGLEMEMERR);
8014d5a: 687b ldr r3, [r7, #4]
8014d5c: 8b5b ldrh r3, [r3, #26]
8014d5e: f043 0380 orr.w r3, r3, #128 ; 0x80
8014d62: b29a uxth r2, r3
8014d64: 687b ldr r3, [r7, #4]
8014d66: 835a strh r2, [r3, #26]
TCP_STATS_INC(tcp.memerr);
return ERR_MEM;
8014d68: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8014d6c: e095 b.n 8014e9a <tcp_enqueue_flags+0x1b2>
}
LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen",
8014d6e: 693b ldr r3, [r7, #16]
8014d70: 895a ldrh r2, [r3, #10]
8014d72: 7dfb ldrb r3, [r7, #23]
8014d74: b29b uxth r3, r3
8014d76: 429a cmp r2, r3
8014d78: d206 bcs.n 8014d88 <tcp_enqueue_flags+0xa0>
8014d7a: 4b4a ldr r3, [pc, #296] ; (8014ea4 <tcp_enqueue_flags+0x1bc>)
8014d7c: f240 4239 movw r2, #1081 ; 0x439
8014d80: 494c ldr r1, [pc, #304] ; (8014eb4 <tcp_enqueue_flags+0x1cc>)
8014d82: 484a ldr r0, [pc, #296] ; (8014eac <tcp_enqueue_flags+0x1c4>)
8014d84: f006 f91e bl 801afc4 <iprintf>
(p->len >= optlen));
/* Allocate memory for tcp_seg, and fill in fields. */
if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) {
8014d88: 687b ldr r3, [r7, #4]
8014d8a: 6dd9 ldr r1, [r3, #92] ; 0x5c
8014d8c: 78fa ldrb r2, [r7, #3]
8014d8e: 7ffb ldrb r3, [r7, #31]
8014d90: 9300 str r3, [sp, #0]
8014d92: 460b mov r3, r1
8014d94: 6939 ldr r1, [r7, #16]
8014d96: 6878 ldr r0, [r7, #4]
8014d98: f7ff fd70 bl 801487c <tcp_create_segment>
8014d9c: 60f8 str r0, [r7, #12]
8014d9e: 68fb ldr r3, [r7, #12]
8014da0: 2b00 cmp r3, #0
8014da2: d109 bne.n 8014db8 <tcp_enqueue_flags+0xd0>
tcp_set_flags(pcb, TF_NAGLEMEMERR);
8014da4: 687b ldr r3, [r7, #4]
8014da6: 8b5b ldrh r3, [r3, #26]
8014da8: f043 0380 orr.w r3, r3, #128 ; 0x80
8014dac: b29a uxth r2, r3
8014dae: 687b ldr r3, [r7, #4]
8014db0: 835a strh r2, [r3, #26]
TCP_STATS_INC(tcp.memerr);
return ERR_MEM;
8014db2: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8014db6: e070 b.n 8014e9a <tcp_enqueue_flags+0x1b2>
}
LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % LWIP_MIN(MEM_ALIGNMENT, 4)) == 0);
8014db8: 68fb ldr r3, [r7, #12]
8014dba: 68db ldr r3, [r3, #12]
8014dbc: f003 0303 and.w r3, r3, #3
8014dc0: 2b00 cmp r3, #0
8014dc2: d006 beq.n 8014dd2 <tcp_enqueue_flags+0xea>
8014dc4: 4b37 ldr r3, [pc, #220] ; (8014ea4 <tcp_enqueue_flags+0x1bc>)
8014dc6: f240 4242 movw r2, #1090 ; 0x442
8014dca: 493b ldr r1, [pc, #236] ; (8014eb8 <tcp_enqueue_flags+0x1d0>)
8014dcc: 4837 ldr r0, [pc, #220] ; (8014eac <tcp_enqueue_flags+0x1c4>)
8014dce: f006 f8f9 bl 801afc4 <iprintf>
LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0);
8014dd2: 68fb ldr r3, [r7, #12]
8014dd4: 891b ldrh r3, [r3, #8]
8014dd6: 2b00 cmp r3, #0
8014dd8: d006 beq.n 8014de8 <tcp_enqueue_flags+0x100>
8014dda: 4b32 ldr r3, [pc, #200] ; (8014ea4 <tcp_enqueue_flags+0x1bc>)
8014ddc: f240 4243 movw r2, #1091 ; 0x443
8014de0: 4936 ldr r1, [pc, #216] ; (8014ebc <tcp_enqueue_flags+0x1d4>)
8014de2: 4832 ldr r0, [pc, #200] ; (8014eac <tcp_enqueue_flags+0x1c4>)
8014de4: f006 f8ee bl 801afc4 <iprintf>
lwip_ntohl(seg->tcphdr->seqno),
lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
(u16_t)flags));
/* Now append seg to pcb->unsent queue */
if (pcb->unsent == NULL) {
8014de8: 687b ldr r3, [r7, #4]
8014dea: 6edb ldr r3, [r3, #108] ; 0x6c
8014dec: 2b00 cmp r3, #0
8014dee: d103 bne.n 8014df8 <tcp_enqueue_flags+0x110>
pcb->unsent = seg;
8014df0: 687b ldr r3, [r7, #4]
8014df2: 68fa ldr r2, [r7, #12]
8014df4: 66da str r2, [r3, #108] ; 0x6c
8014df6: e00d b.n 8014e14 <tcp_enqueue_flags+0x12c>
} else {
struct tcp_seg *useg;
for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
8014df8: 687b ldr r3, [r7, #4]
8014dfa: 6edb ldr r3, [r3, #108] ; 0x6c
8014dfc: 61bb str r3, [r7, #24]
8014dfe: e002 b.n 8014e06 <tcp_enqueue_flags+0x11e>
8014e00: 69bb ldr r3, [r7, #24]
8014e02: 681b ldr r3, [r3, #0]
8014e04: 61bb str r3, [r7, #24]
8014e06: 69bb ldr r3, [r7, #24]
8014e08: 681b ldr r3, [r3, #0]
8014e0a: 2b00 cmp r3, #0
8014e0c: d1f8 bne.n 8014e00 <tcp_enqueue_flags+0x118>
useg->next = seg;
8014e0e: 69bb ldr r3, [r7, #24]
8014e10: 68fa ldr r2, [r7, #12]
8014e12: 601a str r2, [r3, #0]
}
#if TCP_OVERSIZE
/* The new unsent tail has no space */
pcb->unsent_oversize = 0;
8014e14: 687b ldr r3, [r7, #4]
8014e16: 2200 movs r2, #0
8014e18: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
#endif /* TCP_OVERSIZE */
/* SYN and FIN bump the sequence number */
if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
8014e1c: 78fb ldrb r3, [r7, #3]
8014e1e: f003 0302 and.w r3, r3, #2
8014e22: 2b00 cmp r3, #0
8014e24: d104 bne.n 8014e30 <tcp_enqueue_flags+0x148>
8014e26: 78fb ldrb r3, [r7, #3]
8014e28: f003 0301 and.w r3, r3, #1
8014e2c: 2b00 cmp r3, #0
8014e2e: d004 beq.n 8014e3a <tcp_enqueue_flags+0x152>
pcb->snd_lbb++;
8014e30: 687b ldr r3, [r7, #4]
8014e32: 6ddb ldr r3, [r3, #92] ; 0x5c
8014e34: 1c5a adds r2, r3, #1
8014e36: 687b ldr r3, [r7, #4]
8014e38: 65da str r2, [r3, #92] ; 0x5c
/* optlen does not influence snd_buf */
}
if (flags & TCP_FIN) {
8014e3a: 78fb ldrb r3, [r7, #3]
8014e3c: f003 0301 and.w r3, r3, #1
8014e40: 2b00 cmp r3, #0
8014e42: d006 beq.n 8014e52 <tcp_enqueue_flags+0x16a>
tcp_set_flags(pcb, TF_FIN);
8014e44: 687b ldr r3, [r7, #4]
8014e46: 8b5b ldrh r3, [r3, #26]
8014e48: f043 0320 orr.w r3, r3, #32
8014e4c: b29a uxth r2, r3
8014e4e: 687b ldr r3, [r7, #4]
8014e50: 835a strh r2, [r3, #26]
}
/* update number of segments on the queues */
pcb->snd_queuelen += pbuf_clen(seg->p);
8014e52: 68fb ldr r3, [r7, #12]
8014e54: 685b ldr r3, [r3, #4]
8014e56: 4618 mov r0, r3
8014e58: f7fb fc36 bl 80106c8 <pbuf_clen>
8014e5c: 4603 mov r3, r0
8014e5e: 461a mov r2, r3
8014e60: 687b ldr r3, [r7, #4]
8014e62: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014e66: 4413 add r3, r2
8014e68: b29a uxth r2, r3
8014e6a: 687b ldr r3, [r7, #4]
8014e6c: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
if (pcb->snd_queuelen != 0) {
8014e70: 687b ldr r3, [r7, #4]
8014e72: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014e76: 2b00 cmp r3, #0
8014e78: d00e beq.n 8014e98 <tcp_enqueue_flags+0x1b0>
LWIP_ASSERT("tcp_enqueue_flags: invalid queue length",
8014e7a: 687b ldr r3, [r7, #4]
8014e7c: 6f1b ldr r3, [r3, #112] ; 0x70
8014e7e: 2b00 cmp r3, #0
8014e80: d10a bne.n 8014e98 <tcp_enqueue_flags+0x1b0>
8014e82: 687b ldr r3, [r7, #4]
8014e84: 6edb ldr r3, [r3, #108] ; 0x6c
8014e86: 2b00 cmp r3, #0
8014e88: d106 bne.n 8014e98 <tcp_enqueue_flags+0x1b0>
8014e8a: 4b06 ldr r3, [pc, #24] ; (8014ea4 <tcp_enqueue_flags+0x1bc>)
8014e8c: f240 4265 movw r2, #1125 ; 0x465
8014e90: 490b ldr r1, [pc, #44] ; (8014ec0 <tcp_enqueue_flags+0x1d8>)
8014e92: 4806 ldr r0, [pc, #24] ; (8014eac <tcp_enqueue_flags+0x1c4>)
8014e94: f006 f896 bl 801afc4 <iprintf>
pcb->unacked != NULL || pcb->unsent != NULL);
}
return ERR_OK;
8014e98: 2300 movs r3, #0
}
8014e9a: 4618 mov r0, r3
8014e9c: 3720 adds r7, #32
8014e9e: 46bd mov sp, r7
8014ea0: bd80 pop {r7, pc}
8014ea2: bf00 nop
8014ea4: 0801d904 .word 0x0801d904
8014ea8: 0801dd28 .word 0x0801dd28
8014eac: 0801d958 .word 0x0801d958
8014eb0: 0801dd80 .word 0x0801dd80
8014eb4: 0801dda0 .word 0x0801dda0
8014eb8: 0801dddc .word 0x0801dddc
8014ebc: 0801ddf4 .word 0x0801ddf4
8014ec0: 0801de20 .word 0x0801de20
08014ec4 <tcp_output>:
* @return ERR_OK if data has been sent or nothing to send
* another err_t on error
*/
err_t
tcp_output(struct tcp_pcb *pcb)
{
8014ec4: b5b0 push {r4, r5, r7, lr}
8014ec6: b08a sub sp, #40 ; 0x28
8014ec8: af00 add r7, sp, #0
8014eca: 6078 str r0, [r7, #4]
s16_t i = 0;
#endif /* TCP_CWND_DEBUG */
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("tcp_output: invalid pcb", pcb != NULL);
8014ecc: 687b ldr r3, [r7, #4]
8014ece: 2b00 cmp r3, #0
8014ed0: d106 bne.n 8014ee0 <tcp_output+0x1c>
8014ed2: 4b9e ldr r3, [pc, #632] ; (801514c <tcp_output+0x288>)
8014ed4: f240 42e1 movw r2, #1249 ; 0x4e1
8014ed8: 499d ldr r1, [pc, #628] ; (8015150 <tcp_output+0x28c>)
8014eda: 489e ldr r0, [pc, #632] ; (8015154 <tcp_output+0x290>)
8014edc: f006 f872 bl 801afc4 <iprintf>
/* pcb->state LISTEN not allowed here */
LWIP_ASSERT("don't call tcp_output for listen-pcbs",
8014ee0: 687b ldr r3, [r7, #4]
8014ee2: 7d1b ldrb r3, [r3, #20]
8014ee4: 2b01 cmp r3, #1
8014ee6: d106 bne.n 8014ef6 <tcp_output+0x32>
8014ee8: 4b98 ldr r3, [pc, #608] ; (801514c <tcp_output+0x288>)
8014eea: f240 42e3 movw r2, #1251 ; 0x4e3
8014eee: 499a ldr r1, [pc, #616] ; (8015158 <tcp_output+0x294>)
8014ef0: 4898 ldr r0, [pc, #608] ; (8015154 <tcp_output+0x290>)
8014ef2: f006 f867 bl 801afc4 <iprintf>
/* First, check if we are invoked by the TCP input processing
code. If so, we do not output anything. Instead, we rely on the
input processing code to call us when input processing is done
with. */
if (tcp_input_pcb == pcb) {
8014ef6: 4b99 ldr r3, [pc, #612] ; (801515c <tcp_output+0x298>)
8014ef8: 681b ldr r3, [r3, #0]
8014efa: 687a ldr r2, [r7, #4]
8014efc: 429a cmp r2, r3
8014efe: d101 bne.n 8014f04 <tcp_output+0x40>
return ERR_OK;
8014f00: 2300 movs r3, #0
8014f02: e1ce b.n 80152a2 <tcp_output+0x3de>
}
wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
8014f04: 687b ldr r3, [r7, #4]
8014f06: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8014f0a: 687b ldr r3, [r7, #4]
8014f0c: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8014f10: 4293 cmp r3, r2
8014f12: bf28 it cs
8014f14: 4613 movcs r3, r2
8014f16: b29b uxth r3, r3
8014f18: 61bb str r3, [r7, #24]
seg = pcb->unsent;
8014f1a: 687b ldr r3, [r7, #4]
8014f1c: 6edb ldr r3, [r3, #108] ; 0x6c
8014f1e: 627b str r3, [r7, #36] ; 0x24
if (seg == NULL) {
8014f20: 6a7b ldr r3, [r7, #36] ; 0x24
8014f22: 2b00 cmp r3, #0
8014f24: d10b bne.n 8014f3e <tcp_output+0x7a>
", seg == NULL, ack %"U32_F"\n",
pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack));
/* If the TF_ACK_NOW flag is set and the ->unsent queue is empty, construct
* an empty ACK segment and send it. */
if (pcb->flags & TF_ACK_NOW) {
8014f26: 687b ldr r3, [r7, #4]
8014f28: 8b5b ldrh r3, [r3, #26]
8014f2a: f003 0302 and.w r3, r3, #2
8014f2e: 2b00 cmp r3, #0
8014f30: f000 81aa beq.w 8015288 <tcp_output+0x3c4>
return tcp_send_empty_ack(pcb);
8014f34: 6878 ldr r0, [r7, #4]
8014f36: f000 fdcb bl 8015ad0 <tcp_send_empty_ack>
8014f3a: 4603 mov r3, r0
8014f3c: e1b1 b.n 80152a2 <tcp_output+0x3de>
pcb->snd_wnd, pcb->cwnd, wnd,
lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
lwip_ntohl(seg->tcphdr->seqno), pcb->lastack));
}
netif = tcp_route(pcb, &pcb->local_ip, &pcb->remote_ip);
8014f3e: 6879 ldr r1, [r7, #4]
8014f40: 687b ldr r3, [r7, #4]
8014f42: 3304 adds r3, #4
8014f44: 461a mov r2, r3
8014f46: 6878 ldr r0, [r7, #4]
8014f48: f7ff fc7c bl 8014844 <tcp_route>
8014f4c: 6178 str r0, [r7, #20]
if (netif == NULL) {
8014f4e: 697b ldr r3, [r7, #20]
8014f50: 2b00 cmp r3, #0
8014f52: d102 bne.n 8014f5a <tcp_output+0x96>
return ERR_RTE;
8014f54: f06f 0303 mvn.w r3, #3
8014f58: e1a3 b.n 80152a2 <tcp_output+0x3de>
}
/* If we don't have a local IP address, we get one from netif */
if (ip_addr_isany(&pcb->local_ip)) {
8014f5a: 687b ldr r3, [r7, #4]
8014f5c: 2b00 cmp r3, #0
8014f5e: d003 beq.n 8014f68 <tcp_output+0xa4>
8014f60: 687b ldr r3, [r7, #4]
8014f62: 681b ldr r3, [r3, #0]
8014f64: 2b00 cmp r3, #0
8014f66: d111 bne.n 8014f8c <tcp_output+0xc8>
const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, &pcb->remote_ip);
8014f68: 697b ldr r3, [r7, #20]
8014f6a: 2b00 cmp r3, #0
8014f6c: d002 beq.n 8014f74 <tcp_output+0xb0>
8014f6e: 697b ldr r3, [r7, #20]
8014f70: 3304 adds r3, #4
8014f72: e000 b.n 8014f76 <tcp_output+0xb2>
8014f74: 2300 movs r3, #0
8014f76: 613b str r3, [r7, #16]
if (local_ip == NULL) {
8014f78: 693b ldr r3, [r7, #16]
8014f7a: 2b00 cmp r3, #0
8014f7c: d102 bne.n 8014f84 <tcp_output+0xc0>
return ERR_RTE;
8014f7e: f06f 0303 mvn.w r3, #3
8014f82: e18e b.n 80152a2 <tcp_output+0x3de>
}
ip_addr_copy(pcb->local_ip, *local_ip);
8014f84: 693b ldr r3, [r7, #16]
8014f86: 681a ldr r2, [r3, #0]
8014f88: 687b ldr r3, [r7, #4]
8014f8a: 601a str r2, [r3, #0]
}
/* Handle the current segment not fitting within the window */
if (lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd) {
8014f8c: 6a7b ldr r3, [r7, #36] ; 0x24
8014f8e: 68db ldr r3, [r3, #12]
8014f90: 685b ldr r3, [r3, #4]
8014f92: 4618 mov r0, r3
8014f94: f7f9 ff67 bl 800ee66 <lwip_htonl>
8014f98: 4602 mov r2, r0
8014f9a: 687b ldr r3, [r7, #4]
8014f9c: 6c5b ldr r3, [r3, #68] ; 0x44
8014f9e: 1ad3 subs r3, r2, r3
8014fa0: 6a7a ldr r2, [r7, #36] ; 0x24
8014fa2: 8912 ldrh r2, [r2, #8]
8014fa4: 4413 add r3, r2
8014fa6: 69ba ldr r2, [r7, #24]
8014fa8: 429a cmp r2, r3
8014faa: d227 bcs.n 8014ffc <tcp_output+0x138>
* within the remaining (could be 0) send window and RTO timer is not running (we
* have no in-flight data). If window is still too small after persist timer fires,
* then we split the segment. We don't consider the congestion window since a cwnd
* smaller than 1 SMSS implies in-flight data
*/
if (wnd == pcb->snd_wnd && pcb->unacked == NULL && pcb->persist_backoff == 0) {
8014fac: 687b ldr r3, [r7, #4]
8014fae: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8014fb2: 461a mov r2, r3
8014fb4: 69bb ldr r3, [r7, #24]
8014fb6: 4293 cmp r3, r2
8014fb8: d114 bne.n 8014fe4 <tcp_output+0x120>
8014fba: 687b ldr r3, [r7, #4]
8014fbc: 6f1b ldr r3, [r3, #112] ; 0x70
8014fbe: 2b00 cmp r3, #0
8014fc0: d110 bne.n 8014fe4 <tcp_output+0x120>
8014fc2: 687b ldr r3, [r7, #4]
8014fc4: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
8014fc8: 2b00 cmp r3, #0
8014fca: d10b bne.n 8014fe4 <tcp_output+0x120>
pcb->persist_cnt = 0;
8014fcc: 687b ldr r3, [r7, #4]
8014fce: 2200 movs r2, #0
8014fd0: f883 2098 strb.w r2, [r3, #152] ; 0x98
pcb->persist_backoff = 1;
8014fd4: 687b ldr r3, [r7, #4]
8014fd6: 2201 movs r2, #1
8014fd8: f883 2099 strb.w r2, [r3, #153] ; 0x99
pcb->persist_probe = 0;
8014fdc: 687b ldr r3, [r7, #4]
8014fde: 2200 movs r2, #0
8014fe0: f883 209a strb.w r2, [r3, #154] ; 0x9a
}
/* We need an ACK, but can't send data now, so send an empty ACK */
if (pcb->flags & TF_ACK_NOW) {
8014fe4: 687b ldr r3, [r7, #4]
8014fe6: 8b5b ldrh r3, [r3, #26]
8014fe8: f003 0302 and.w r3, r3, #2
8014fec: 2b00 cmp r3, #0
8014fee: f000 814d beq.w 801528c <tcp_output+0x3c8>
return tcp_send_empty_ack(pcb);
8014ff2: 6878 ldr r0, [r7, #4]
8014ff4: f000 fd6c bl 8015ad0 <tcp_send_empty_ack>
8014ff8: 4603 mov r3, r0
8014ffa: e152 b.n 80152a2 <tcp_output+0x3de>
}
goto output_done;
}
/* Stop persist timer, above conditions are not active */
pcb->persist_backoff = 0;
8014ffc: 687b ldr r3, [r7, #4]
8014ffe: 2200 movs r2, #0
8015000: f883 2099 strb.w r2, [r3, #153] ; 0x99
/* useg should point to last segment on unacked queue */
useg = pcb->unacked;
8015004: 687b ldr r3, [r7, #4]
8015006: 6f1b ldr r3, [r3, #112] ; 0x70
8015008: 623b str r3, [r7, #32]
if (useg != NULL) {
801500a: 6a3b ldr r3, [r7, #32]
801500c: 2b00 cmp r3, #0
801500e: f000 811c beq.w 801524a <tcp_output+0x386>
for (; useg->next != NULL; useg = useg->next);
8015012: e002 b.n 801501a <tcp_output+0x156>
8015014: 6a3b ldr r3, [r7, #32]
8015016: 681b ldr r3, [r3, #0]
8015018: 623b str r3, [r7, #32]
801501a: 6a3b ldr r3, [r7, #32]
801501c: 681b ldr r3, [r3, #0]
801501e: 2b00 cmp r3, #0
8015020: d1f8 bne.n 8015014 <tcp_output+0x150>
}
/* data available and window allows it to be sent? */
while (seg != NULL &&
8015022: e112 b.n 801524a <tcp_output+0x386>
lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
LWIP_ASSERT("RST not expected here!",
8015024: 6a7b ldr r3, [r7, #36] ; 0x24
8015026: 68db ldr r3, [r3, #12]
8015028: 899b ldrh r3, [r3, #12]
801502a: b29b uxth r3, r3
801502c: 4618 mov r0, r3
801502e: f7f9 ff05 bl 800ee3c <lwip_htons>
8015032: 4603 mov r3, r0
8015034: b2db uxtb r3, r3
8015036: f003 0304 and.w r3, r3, #4
801503a: 2b00 cmp r3, #0
801503c: d006 beq.n 801504c <tcp_output+0x188>
801503e: 4b43 ldr r3, [pc, #268] ; (801514c <tcp_output+0x288>)
8015040: f240 5236 movw r2, #1334 ; 0x536
8015044: 4946 ldr r1, [pc, #280] ; (8015160 <tcp_output+0x29c>)
8015046: 4843 ldr r0, [pc, #268] ; (8015154 <tcp_output+0x290>)
8015048: f005 ffbc bl 801afc4 <iprintf>
* - if tcp_write had a memory error before (prevent delayed ACK timeout) or
* - if FIN was already enqueued for this PCB (SYN is always alone in a segment -
* either seg->next != NULL or pcb->unacked == NULL;
* RST is no sent using tcp_write/tcp_output.
*/
if ((tcp_do_output_nagle(pcb) == 0) &&
801504c: 687b ldr r3, [r7, #4]
801504e: 6f1b ldr r3, [r3, #112] ; 0x70
8015050: 2b00 cmp r3, #0
8015052: d01f beq.n 8015094 <tcp_output+0x1d0>
8015054: 687b ldr r3, [r7, #4]
8015056: 8b5b ldrh r3, [r3, #26]
8015058: f003 0344 and.w r3, r3, #68 ; 0x44
801505c: 2b00 cmp r3, #0
801505e: d119 bne.n 8015094 <tcp_output+0x1d0>
8015060: 687b ldr r3, [r7, #4]
8015062: 6edb ldr r3, [r3, #108] ; 0x6c
8015064: 2b00 cmp r3, #0
8015066: d00b beq.n 8015080 <tcp_output+0x1bc>
8015068: 687b ldr r3, [r7, #4]
801506a: 6edb ldr r3, [r3, #108] ; 0x6c
801506c: 681b ldr r3, [r3, #0]
801506e: 2b00 cmp r3, #0
8015070: d110 bne.n 8015094 <tcp_output+0x1d0>
8015072: 687b ldr r3, [r7, #4]
8015074: 6edb ldr r3, [r3, #108] ; 0x6c
8015076: 891a ldrh r2, [r3, #8]
8015078: 687b ldr r3, [r7, #4]
801507a: 8e5b ldrh r3, [r3, #50] ; 0x32
801507c: 429a cmp r2, r3
801507e: d209 bcs.n 8015094 <tcp_output+0x1d0>
8015080: 687b ldr r3, [r7, #4]
8015082: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64
8015086: 2b00 cmp r3, #0
8015088: d004 beq.n 8015094 <tcp_output+0x1d0>
801508a: 687b ldr r3, [r7, #4]
801508c: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8015090: 2b08 cmp r3, #8
8015092: d901 bls.n 8015098 <tcp_output+0x1d4>
8015094: 2301 movs r3, #1
8015096: e000 b.n 801509a <tcp_output+0x1d6>
8015098: 2300 movs r3, #0
801509a: 2b00 cmp r3, #0
801509c: d106 bne.n 80150ac <tcp_output+0x1e8>
((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)) {
801509e: 687b ldr r3, [r7, #4]
80150a0: 8b5b ldrh r3, [r3, #26]
80150a2: f003 03a0 and.w r3, r3, #160 ; 0xa0
if ((tcp_do_output_nagle(pcb) == 0) &&
80150a6: 2b00 cmp r3, #0
80150a8: f000 80e4 beq.w 8015274 <tcp_output+0x3b0>
pcb->lastack,
lwip_ntohl(seg->tcphdr->seqno), pcb->lastack, i));
++i;
#endif /* TCP_CWND_DEBUG */
if (pcb->state != SYN_SENT) {
80150ac: 687b ldr r3, [r7, #4]
80150ae: 7d1b ldrb r3, [r3, #20]
80150b0: 2b02 cmp r3, #2
80150b2: d00d beq.n 80150d0 <tcp_output+0x20c>
TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
80150b4: 6a7b ldr r3, [r7, #36] ; 0x24
80150b6: 68db ldr r3, [r3, #12]
80150b8: 899b ldrh r3, [r3, #12]
80150ba: b29c uxth r4, r3
80150bc: 2010 movs r0, #16
80150be: f7f9 febd bl 800ee3c <lwip_htons>
80150c2: 4603 mov r3, r0
80150c4: 461a mov r2, r3
80150c6: 6a7b ldr r3, [r7, #36] ; 0x24
80150c8: 68db ldr r3, [r3, #12]
80150ca: 4322 orrs r2, r4
80150cc: b292 uxth r2, r2
80150ce: 819a strh r2, [r3, #12]
}
err = tcp_output_segment(seg, pcb, netif);
80150d0: 697a ldr r2, [r7, #20]
80150d2: 6879 ldr r1, [r7, #4]
80150d4: 6a78 ldr r0, [r7, #36] ; 0x24
80150d6: f000 f909 bl 80152ec <tcp_output_segment>
80150da: 4603 mov r3, r0
80150dc: 73fb strb r3, [r7, #15]
if (err != ERR_OK) {
80150de: f997 300f ldrsb.w r3, [r7, #15]
80150e2: 2b00 cmp r3, #0
80150e4: d009 beq.n 80150fa <tcp_output+0x236>
/* segment could not be sent, for whatever reason */
tcp_set_flags(pcb, TF_NAGLEMEMERR);
80150e6: 687b ldr r3, [r7, #4]
80150e8: 8b5b ldrh r3, [r3, #26]
80150ea: f043 0380 orr.w r3, r3, #128 ; 0x80
80150ee: b29a uxth r2, r3
80150f0: 687b ldr r3, [r7, #4]
80150f2: 835a strh r2, [r3, #26]
return err;
80150f4: f997 300f ldrsb.w r3, [r7, #15]
80150f8: e0d3 b.n 80152a2 <tcp_output+0x3de>
}
#if TCP_OVERSIZE_DBGCHECK
seg->oversize_left = 0;
#endif /* TCP_OVERSIZE_DBGCHECK */
pcb->unsent = seg->next;
80150fa: 6a7b ldr r3, [r7, #36] ; 0x24
80150fc: 681a ldr r2, [r3, #0]
80150fe: 687b ldr r3, [r7, #4]
8015100: 66da str r2, [r3, #108] ; 0x6c
if (pcb->state != SYN_SENT) {
8015102: 687b ldr r3, [r7, #4]
8015104: 7d1b ldrb r3, [r3, #20]
8015106: 2b02 cmp r3, #2
8015108: d006 beq.n 8015118 <tcp_output+0x254>
tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
801510a: 687b ldr r3, [r7, #4]
801510c: 8b5b ldrh r3, [r3, #26]
801510e: f023 0303 bic.w r3, r3, #3
8015112: b29a uxth r2, r3
8015114: 687b ldr r3, [r7, #4]
8015116: 835a strh r2, [r3, #26]
}
snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
8015118: 6a7b ldr r3, [r7, #36] ; 0x24
801511a: 68db ldr r3, [r3, #12]
801511c: 685b ldr r3, [r3, #4]
801511e: 4618 mov r0, r3
8015120: f7f9 fea1 bl 800ee66 <lwip_htonl>
8015124: 4604 mov r4, r0
8015126: 6a7b ldr r3, [r7, #36] ; 0x24
8015128: 891b ldrh r3, [r3, #8]
801512a: 461d mov r5, r3
801512c: 6a7b ldr r3, [r7, #36] ; 0x24
801512e: 68db ldr r3, [r3, #12]
8015130: 899b ldrh r3, [r3, #12]
8015132: b29b uxth r3, r3
8015134: 4618 mov r0, r3
8015136: f7f9 fe81 bl 800ee3c <lwip_htons>
801513a: 4603 mov r3, r0
801513c: b2db uxtb r3, r3
801513e: f003 0303 and.w r3, r3, #3
8015142: 2b00 cmp r3, #0
8015144: d00e beq.n 8015164 <tcp_output+0x2a0>
8015146: 2301 movs r3, #1
8015148: e00d b.n 8015166 <tcp_output+0x2a2>
801514a: bf00 nop
801514c: 0801d904 .word 0x0801d904
8015150: 0801de48 .word 0x0801de48
8015154: 0801d958 .word 0x0801d958
8015158: 0801de60 .word 0x0801de60
801515c: 2000f850 .word 0x2000f850
8015160: 0801de88 .word 0x0801de88
8015164: 2300 movs r3, #0
8015166: 442b add r3, r5
8015168: 4423 add r3, r4
801516a: 60bb str r3, [r7, #8]
if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
801516c: 687b ldr r3, [r7, #4]
801516e: 6d1a ldr r2, [r3, #80] ; 0x50
8015170: 68bb ldr r3, [r7, #8]
8015172: 1ad3 subs r3, r2, r3
8015174: 2b00 cmp r3, #0
8015176: da02 bge.n 801517e <tcp_output+0x2ba>
pcb->snd_nxt = snd_nxt;
8015178: 687b ldr r3, [r7, #4]
801517a: 68ba ldr r2, [r7, #8]
801517c: 651a str r2, [r3, #80] ; 0x50
}
/* put segment on unacknowledged list if length > 0 */
if (TCP_TCPLEN(seg) > 0) {
801517e: 6a7b ldr r3, [r7, #36] ; 0x24
8015180: 891b ldrh r3, [r3, #8]
8015182: 461c mov r4, r3
8015184: 6a7b ldr r3, [r7, #36] ; 0x24
8015186: 68db ldr r3, [r3, #12]
8015188: 899b ldrh r3, [r3, #12]
801518a: b29b uxth r3, r3
801518c: 4618 mov r0, r3
801518e: f7f9 fe55 bl 800ee3c <lwip_htons>
8015192: 4603 mov r3, r0
8015194: b2db uxtb r3, r3
8015196: f003 0303 and.w r3, r3, #3
801519a: 2b00 cmp r3, #0
801519c: d001 beq.n 80151a2 <tcp_output+0x2de>
801519e: 2301 movs r3, #1
80151a0: e000 b.n 80151a4 <tcp_output+0x2e0>
80151a2: 2300 movs r3, #0
80151a4: 4423 add r3, r4
80151a6: 2b00 cmp r3, #0
80151a8: d049 beq.n 801523e <tcp_output+0x37a>
seg->next = NULL;
80151aa: 6a7b ldr r3, [r7, #36] ; 0x24
80151ac: 2200 movs r2, #0
80151ae: 601a str r2, [r3, #0]
/* unacked list is empty? */
if (pcb->unacked == NULL) {
80151b0: 687b ldr r3, [r7, #4]
80151b2: 6f1b ldr r3, [r3, #112] ; 0x70
80151b4: 2b00 cmp r3, #0
80151b6: d105 bne.n 80151c4 <tcp_output+0x300>
pcb->unacked = seg;
80151b8: 687b ldr r3, [r7, #4]
80151ba: 6a7a ldr r2, [r7, #36] ; 0x24
80151bc: 671a str r2, [r3, #112] ; 0x70
useg = seg;
80151be: 6a7b ldr r3, [r7, #36] ; 0x24
80151c0: 623b str r3, [r7, #32]
80151c2: e03f b.n 8015244 <tcp_output+0x380>
/* unacked list is not empty? */
} else {
/* In the case of fast retransmit, the packet should not go to the tail
* of the unacked queue, but rather somewhere before it. We need to check for
* this case. -STJ Jul 27, 2004 */
if (TCP_SEQ_LT(lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(useg->tcphdr->seqno))) {
80151c4: 6a7b ldr r3, [r7, #36] ; 0x24
80151c6: 68db ldr r3, [r3, #12]
80151c8: 685b ldr r3, [r3, #4]
80151ca: 4618 mov r0, r3
80151cc: f7f9 fe4b bl 800ee66 <lwip_htonl>
80151d0: 4604 mov r4, r0
80151d2: 6a3b ldr r3, [r7, #32]
80151d4: 68db ldr r3, [r3, #12]
80151d6: 685b ldr r3, [r3, #4]
80151d8: 4618 mov r0, r3
80151da: f7f9 fe44 bl 800ee66 <lwip_htonl>
80151de: 4603 mov r3, r0
80151e0: 1ae3 subs r3, r4, r3
80151e2: 2b00 cmp r3, #0
80151e4: da24 bge.n 8015230 <tcp_output+0x36c>
/* add segment to before tail of unacked list, keeping the list sorted */
struct tcp_seg **cur_seg = &(pcb->unacked);
80151e6: 687b ldr r3, [r7, #4]
80151e8: 3370 adds r3, #112 ; 0x70
80151ea: 61fb str r3, [r7, #28]
while (*cur_seg &&
80151ec: e002 b.n 80151f4 <tcp_output+0x330>
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
cur_seg = &((*cur_seg)->next );
80151ee: 69fb ldr r3, [r7, #28]
80151f0: 681b ldr r3, [r3, #0]
80151f2: 61fb str r3, [r7, #28]
while (*cur_seg &&
80151f4: 69fb ldr r3, [r7, #28]
80151f6: 681b ldr r3, [r3, #0]
80151f8: 2b00 cmp r3, #0
80151fa: d011 beq.n 8015220 <tcp_output+0x35c>
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
80151fc: 69fb ldr r3, [r7, #28]
80151fe: 681b ldr r3, [r3, #0]
8015200: 68db ldr r3, [r3, #12]
8015202: 685b ldr r3, [r3, #4]
8015204: 4618 mov r0, r3
8015206: f7f9 fe2e bl 800ee66 <lwip_htonl>
801520a: 4604 mov r4, r0
801520c: 6a7b ldr r3, [r7, #36] ; 0x24
801520e: 68db ldr r3, [r3, #12]
8015210: 685b ldr r3, [r3, #4]
8015212: 4618 mov r0, r3
8015214: f7f9 fe27 bl 800ee66 <lwip_htonl>
8015218: 4603 mov r3, r0
801521a: 1ae3 subs r3, r4, r3
while (*cur_seg &&
801521c: 2b00 cmp r3, #0
801521e: dbe6 blt.n 80151ee <tcp_output+0x32a>
}
seg->next = (*cur_seg);
8015220: 69fb ldr r3, [r7, #28]
8015222: 681a ldr r2, [r3, #0]
8015224: 6a7b ldr r3, [r7, #36] ; 0x24
8015226: 601a str r2, [r3, #0]
(*cur_seg) = seg;
8015228: 69fb ldr r3, [r7, #28]
801522a: 6a7a ldr r2, [r7, #36] ; 0x24
801522c: 601a str r2, [r3, #0]
801522e: e009 b.n 8015244 <tcp_output+0x380>
} else {
/* add segment to tail of unacked list */
useg->next = seg;
8015230: 6a3b ldr r3, [r7, #32]
8015232: 6a7a ldr r2, [r7, #36] ; 0x24
8015234: 601a str r2, [r3, #0]
useg = useg->next;
8015236: 6a3b ldr r3, [r7, #32]
8015238: 681b ldr r3, [r3, #0]
801523a: 623b str r3, [r7, #32]
801523c: e002 b.n 8015244 <tcp_output+0x380>
}
}
/* do not queue empty segments on the unacked list */
} else {
tcp_seg_free(seg);
801523e: 6a78 ldr r0, [r7, #36] ; 0x24
8015240: f7fc fc43 bl 8011aca <tcp_seg_free>
}
seg = pcb->unsent;
8015244: 687b ldr r3, [r7, #4]
8015246: 6edb ldr r3, [r3, #108] ; 0x6c
8015248: 627b str r3, [r7, #36] ; 0x24
while (seg != NULL &&
801524a: 6a7b ldr r3, [r7, #36] ; 0x24
801524c: 2b00 cmp r3, #0
801524e: d012 beq.n 8015276 <tcp_output+0x3b2>
lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
8015250: 6a7b ldr r3, [r7, #36] ; 0x24
8015252: 68db ldr r3, [r3, #12]
8015254: 685b ldr r3, [r3, #4]
8015256: 4618 mov r0, r3
8015258: f7f9 fe05 bl 800ee66 <lwip_htonl>
801525c: 4602 mov r2, r0
801525e: 687b ldr r3, [r7, #4]
8015260: 6c5b ldr r3, [r3, #68] ; 0x44
8015262: 1ad3 subs r3, r2, r3
8015264: 6a7a ldr r2, [r7, #36] ; 0x24
8015266: 8912 ldrh r2, [r2, #8]
8015268: 4413 add r3, r2
while (seg != NULL &&
801526a: 69ba ldr r2, [r7, #24]
801526c: 429a cmp r2, r3
801526e: f4bf aed9 bcs.w 8015024 <tcp_output+0x160>
8015272: e000 b.n 8015276 <tcp_output+0x3b2>
break;
8015274: bf00 nop
}
#if TCP_OVERSIZE
if (pcb->unsent == NULL) {
8015276: 687b ldr r3, [r7, #4]
8015278: 6edb ldr r3, [r3, #108] ; 0x6c
801527a: 2b00 cmp r3, #0
801527c: d108 bne.n 8015290 <tcp_output+0x3cc>
/* last unsent has been removed, reset unsent_oversize */
pcb->unsent_oversize = 0;
801527e: 687b ldr r3, [r7, #4]
8015280: 2200 movs r2, #0
8015282: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
8015286: e004 b.n 8015292 <tcp_output+0x3ce>
goto output_done;
8015288: bf00 nop
801528a: e002 b.n 8015292 <tcp_output+0x3ce>
goto output_done;
801528c: bf00 nop
801528e: e000 b.n 8015292 <tcp_output+0x3ce>
}
#endif /* TCP_OVERSIZE */
output_done:
8015290: bf00 nop
tcp_clear_flags(pcb, TF_NAGLEMEMERR);
8015292: 687b ldr r3, [r7, #4]
8015294: 8b5b ldrh r3, [r3, #26]
8015296: f023 0380 bic.w r3, r3, #128 ; 0x80
801529a: b29a uxth r2, r3
801529c: 687b ldr r3, [r7, #4]
801529e: 835a strh r2, [r3, #26]
return ERR_OK;
80152a0: 2300 movs r3, #0
}
80152a2: 4618 mov r0, r3
80152a4: 3728 adds r7, #40 ; 0x28
80152a6: 46bd mov sp, r7
80152a8: bdb0 pop {r4, r5, r7, pc}
80152aa: bf00 nop
080152ac <tcp_output_segment_busy>:
* @arg seg the tcp segment to check
* @return 1 if ref != 1, 0 if ref == 1
*/
static int
tcp_output_segment_busy(const struct tcp_seg *seg)
{
80152ac: b580 push {r7, lr}
80152ae: b082 sub sp, #8
80152b0: af00 add r7, sp, #0
80152b2: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_output_segment_busy: invalid seg", seg != NULL);
80152b4: 687b ldr r3, [r7, #4]
80152b6: 2b00 cmp r3, #0
80152b8: d106 bne.n 80152c8 <tcp_output_segment_busy+0x1c>
80152ba: 4b09 ldr r3, [pc, #36] ; (80152e0 <tcp_output_segment_busy+0x34>)
80152bc: f240 529a movw r2, #1434 ; 0x59a
80152c0: 4908 ldr r1, [pc, #32] ; (80152e4 <tcp_output_segment_busy+0x38>)
80152c2: 4809 ldr r0, [pc, #36] ; (80152e8 <tcp_output_segment_busy+0x3c>)
80152c4: f005 fe7e bl 801afc4 <iprintf>
/* We only need to check the first pbuf here:
If a pbuf is queued for transmission, a driver calls pbuf_ref(),
which only changes the ref count of the first pbuf */
if (seg->p->ref != 1) {
80152c8: 687b ldr r3, [r7, #4]
80152ca: 685b ldr r3, [r3, #4]
80152cc: 7b9b ldrb r3, [r3, #14]
80152ce: 2b01 cmp r3, #1
80152d0: d001 beq.n 80152d6 <tcp_output_segment_busy+0x2a>
/* other reference found */
return 1;
80152d2: 2301 movs r3, #1
80152d4: e000 b.n 80152d8 <tcp_output_segment_busy+0x2c>
}
/* no other references found */
return 0;
80152d6: 2300 movs r3, #0
}
80152d8: 4618 mov r0, r3
80152da: 3708 adds r7, #8
80152dc: 46bd mov sp, r7
80152de: bd80 pop {r7, pc}
80152e0: 0801d904 .word 0x0801d904
80152e4: 0801dea0 .word 0x0801dea0
80152e8: 0801d958 .word 0x0801d958
080152ec <tcp_output_segment>:
* @param pcb the tcp_pcb for the TCP connection used to send the segment
* @param netif the netif used to send the segment
*/
static err_t
tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif)
{
80152ec: b5b0 push {r4, r5, r7, lr}
80152ee: b08c sub sp, #48 ; 0x30
80152f0: af04 add r7, sp, #16
80152f2: 60f8 str r0, [r7, #12]
80152f4: 60b9 str r1, [r7, #8]
80152f6: 607a str r2, [r7, #4]
u32_t *opts;
#if TCP_CHECKSUM_ON_COPY
int seg_chksum_was_swapped = 0;
#endif
LWIP_ASSERT("tcp_output_segment: invalid seg", seg != NULL);
80152f8: 68fb ldr r3, [r7, #12]
80152fa: 2b00 cmp r3, #0
80152fc: d106 bne.n 801530c <tcp_output_segment+0x20>
80152fe: 4b63 ldr r3, [pc, #396] ; (801548c <tcp_output_segment+0x1a0>)
8015300: f44f 62b7 mov.w r2, #1464 ; 0x5b8
8015304: 4962 ldr r1, [pc, #392] ; (8015490 <tcp_output_segment+0x1a4>)
8015306: 4863 ldr r0, [pc, #396] ; (8015494 <tcp_output_segment+0x1a8>)
8015308: f005 fe5c bl 801afc4 <iprintf>
LWIP_ASSERT("tcp_output_segment: invalid pcb", pcb != NULL);
801530c: 68bb ldr r3, [r7, #8]
801530e: 2b00 cmp r3, #0
8015310: d106 bne.n 8015320 <tcp_output_segment+0x34>
8015312: 4b5e ldr r3, [pc, #376] ; (801548c <tcp_output_segment+0x1a0>)
8015314: f240 52b9 movw r2, #1465 ; 0x5b9
8015318: 495f ldr r1, [pc, #380] ; (8015498 <tcp_output_segment+0x1ac>)
801531a: 485e ldr r0, [pc, #376] ; (8015494 <tcp_output_segment+0x1a8>)
801531c: f005 fe52 bl 801afc4 <iprintf>
LWIP_ASSERT("tcp_output_segment: invalid netif", netif != NULL);
8015320: 687b ldr r3, [r7, #4]
8015322: 2b00 cmp r3, #0
8015324: d106 bne.n 8015334 <tcp_output_segment+0x48>
8015326: 4b59 ldr r3, [pc, #356] ; (801548c <tcp_output_segment+0x1a0>)
8015328: f240 52ba movw r2, #1466 ; 0x5ba
801532c: 495b ldr r1, [pc, #364] ; (801549c <tcp_output_segment+0x1b0>)
801532e: 4859 ldr r0, [pc, #356] ; (8015494 <tcp_output_segment+0x1a8>)
8015330: f005 fe48 bl 801afc4 <iprintf>
if (tcp_output_segment_busy(seg)) {
8015334: 68f8 ldr r0, [r7, #12]
8015336: f7ff ffb9 bl 80152ac <tcp_output_segment_busy>
801533a: 4603 mov r3, r0
801533c: 2b00 cmp r3, #0
801533e: d001 beq.n 8015344 <tcp_output_segment+0x58>
/* This should not happen: rexmit functions should have checked this.
However, since this function modifies p->len, we must not continue in this case. */
LWIP_DEBUGF(TCP_RTO_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_output_segment: segment busy\n"));
return ERR_OK;
8015340: 2300 movs r3, #0
8015342: e09f b.n 8015484 <tcp_output_segment+0x198>
}
/* The TCP header has already been constructed, but the ackno and
wnd fields remain. */
seg->tcphdr->ackno = lwip_htonl(pcb->rcv_nxt);
8015344: 68bb ldr r3, [r7, #8]
8015346: 6a5a ldr r2, [r3, #36] ; 0x24
8015348: 68fb ldr r3, [r7, #12]
801534a: 68dc ldr r4, [r3, #12]
801534c: 4610 mov r0, r2
801534e: f7f9 fd8a bl 800ee66 <lwip_htonl>
8015352: 4603 mov r3, r0
8015354: 60a3 str r3, [r4, #8]
the window scale option) is never scaled. */
seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(pcb->rcv_ann_wnd));
} else
#endif /* LWIP_WND_SCALE */
{
seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
8015356: 68bb ldr r3, [r7, #8]
8015358: 8d5a ldrh r2, [r3, #42] ; 0x2a
801535a: 68fb ldr r3, [r7, #12]
801535c: 68dc ldr r4, [r3, #12]
801535e: 4610 mov r0, r2
8015360: f7f9 fd6c bl 800ee3c <lwip_htons>
8015364: 4603 mov r3, r0
8015366: 81e3 strh r3, [r4, #14]
}
pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
8015368: 68bb ldr r3, [r7, #8]
801536a: 6a5b ldr r3, [r3, #36] ; 0x24
801536c: 68ba ldr r2, [r7, #8]
801536e: 8d52 ldrh r2, [r2, #42] ; 0x2a
8015370: 441a add r2, r3
8015372: 68bb ldr r3, [r7, #8]
8015374: 62da str r2, [r3, #44] ; 0x2c
/* Add any requested options. NB MSS option is only set on SYN
packets, so ignore it here */
/* cast through void* to get rid of alignment warnings */
opts = (u32_t *)(void *)(seg->tcphdr + 1);
8015376: 68fb ldr r3, [r7, #12]
8015378: 68db ldr r3, [r3, #12]
801537a: 3314 adds r3, #20
801537c: 61fb str r3, [r7, #28]
if (seg->flags & TF_SEG_OPTS_MSS) {
801537e: 68fb ldr r3, [r7, #12]
8015380: 7a9b ldrb r3, [r3, #10]
8015382: f003 0301 and.w r3, r3, #1
8015386: 2b00 cmp r3, #0
8015388: d015 beq.n 80153b6 <tcp_output_segment+0xca>
u16_t mss;
#if TCP_CALCULATE_EFF_SEND_MSS
mss = tcp_eff_send_mss_netif(TCP_MSS, netif, &pcb->remote_ip);
801538a: 68bb ldr r3, [r7, #8]
801538c: 3304 adds r3, #4
801538e: 461a mov r2, r3
8015390: 6879 ldr r1, [r7, #4]
8015392: f44f 7006 mov.w r0, #536 ; 0x218
8015396: f7fc fe8f bl 80120b8 <tcp_eff_send_mss_netif>
801539a: 4603 mov r3, r0
801539c: 837b strh r3, [r7, #26]
#else /* TCP_CALCULATE_EFF_SEND_MSS */
mss = TCP_MSS;
#endif /* TCP_CALCULATE_EFF_SEND_MSS */
*opts = TCP_BUILD_MSS_OPTION(mss);
801539e: 8b7b ldrh r3, [r7, #26]
80153a0: f043 7301 orr.w r3, r3, #33816576 ; 0x2040000
80153a4: 4618 mov r0, r3
80153a6: f7f9 fd5e bl 800ee66 <lwip_htonl>
80153aa: 4602 mov r2, r0
80153ac: 69fb ldr r3, [r7, #28]
80153ae: 601a str r2, [r3, #0]
opts += 1;
80153b0: 69fb ldr r3, [r7, #28]
80153b2: 3304 adds r3, #4
80153b4: 61fb str r3, [r7, #28]
}
#endif
/* Set retransmission timer running if it is not currently enabled
This must be set before checking the route. */
if (pcb->rtime < 0) {
80153b6: 68bb ldr r3, [r7, #8]
80153b8: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
80153bc: 2b00 cmp r3, #0
80153be: da02 bge.n 80153c6 <tcp_output_segment+0xda>
pcb->rtime = 0;
80153c0: 68bb ldr r3, [r7, #8]
80153c2: 2200 movs r2, #0
80153c4: 861a strh r2, [r3, #48] ; 0x30
}
if (pcb->rttest == 0) {
80153c6: 68bb ldr r3, [r7, #8]
80153c8: 6b5b ldr r3, [r3, #52] ; 0x34
80153ca: 2b00 cmp r3, #0
80153cc: d10c bne.n 80153e8 <tcp_output_segment+0xfc>
pcb->rttest = tcp_ticks;
80153ce: 4b34 ldr r3, [pc, #208] ; (80154a0 <tcp_output_segment+0x1b4>)
80153d0: 681a ldr r2, [r3, #0]
80153d2: 68bb ldr r3, [r7, #8]
80153d4: 635a str r2, [r3, #52] ; 0x34
pcb->rtseq = lwip_ntohl(seg->tcphdr->seqno);
80153d6: 68fb ldr r3, [r7, #12]
80153d8: 68db ldr r3, [r3, #12]
80153da: 685b ldr r3, [r3, #4]
80153dc: 4618 mov r0, r3
80153de: f7f9 fd42 bl 800ee66 <lwip_htonl>
80153e2: 4602 mov r2, r0
80153e4: 68bb ldr r3, [r7, #8]
80153e6: 639a str r2, [r3, #56] ; 0x38
}
LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
lwip_htonl(seg->tcphdr->seqno), lwip_htonl(seg->tcphdr->seqno) +
seg->len));
len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
80153e8: 68fb ldr r3, [r7, #12]
80153ea: 68da ldr r2, [r3, #12]
80153ec: 68fb ldr r3, [r7, #12]
80153ee: 685b ldr r3, [r3, #4]
80153f0: 685b ldr r3, [r3, #4]
80153f2: 1ad3 subs r3, r2, r3
80153f4: 833b strh r3, [r7, #24]
if (len == 0) {
/** Exclude retransmitted segments from this count. */
MIB2_STATS_INC(mib2.tcpoutsegs);
}
seg->p->len -= len;
80153f6: 68fb ldr r3, [r7, #12]
80153f8: 685b ldr r3, [r3, #4]
80153fa: 8959 ldrh r1, [r3, #10]
80153fc: 68fb ldr r3, [r7, #12]
80153fe: 685b ldr r3, [r3, #4]
8015400: 8b3a ldrh r2, [r7, #24]
8015402: 1a8a subs r2, r1, r2
8015404: b292 uxth r2, r2
8015406: 815a strh r2, [r3, #10]
seg->p->tot_len -= len;
8015408: 68fb ldr r3, [r7, #12]
801540a: 685b ldr r3, [r3, #4]
801540c: 8919 ldrh r1, [r3, #8]
801540e: 68fb ldr r3, [r7, #12]
8015410: 685b ldr r3, [r3, #4]
8015412: 8b3a ldrh r2, [r7, #24]
8015414: 1a8a subs r2, r1, r2
8015416: b292 uxth r2, r2
8015418: 811a strh r2, [r3, #8]
seg->p->payload = seg->tcphdr;
801541a: 68fb ldr r3, [r7, #12]
801541c: 685b ldr r3, [r3, #4]
801541e: 68fa ldr r2, [r7, #12]
8015420: 68d2 ldr r2, [r2, #12]
8015422: 605a str r2, [r3, #4]
seg->tcphdr->chksum = 0;
8015424: 68fb ldr r3, [r7, #12]
8015426: 68db ldr r3, [r3, #12]
8015428: 2200 movs r2, #0
801542a: 741a strb r2, [r3, #16]
801542c: 2200 movs r2, #0
801542e: 745a strb r2, [r3, #17]
#ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS
opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(seg->p, seg->tcphdr, pcb, opts);
#endif
LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(seg->tcphdr + 1)) + LWIP_TCP_OPT_LENGTH_SEGMENT(seg->flags, pcb));
8015430: 68fb ldr r3, [r7, #12]
8015432: 68db ldr r3, [r3, #12]
8015434: f103 0214 add.w r2, r3, #20
8015438: 68fb ldr r3, [r7, #12]
801543a: 7a9b ldrb r3, [r3, #10]
801543c: 009b lsls r3, r3, #2
801543e: f003 0304 and.w r3, r3, #4
8015442: 4413 add r3, r2
8015444: 69fa ldr r2, [r7, #28]
8015446: 429a cmp r2, r3
8015448: d006 beq.n 8015458 <tcp_output_segment+0x16c>
801544a: 4b10 ldr r3, [pc, #64] ; (801548c <tcp_output_segment+0x1a0>)
801544c: f240 621c movw r2, #1564 ; 0x61c
8015450: 4914 ldr r1, [pc, #80] ; (80154a4 <tcp_output_segment+0x1b8>)
8015452: 4810 ldr r0, [pc, #64] ; (8015494 <tcp_output_segment+0x1a8>)
8015454: f005 fdb6 bl 801afc4 <iprintf>
}
#endif /* CHECKSUM_GEN_TCP */
TCP_STATS_INC(tcp.xmit);
NETIF_SET_HINTS(netif, &(pcb->netif_hints));
err = ip_output_if(seg->p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl,
8015458: 68fb ldr r3, [r7, #12]
801545a: 6858 ldr r0, [r3, #4]
801545c: 68b9 ldr r1, [r7, #8]
801545e: 68bb ldr r3, [r7, #8]
8015460: 1d1c adds r4, r3, #4
8015462: 68bb ldr r3, [r7, #8]
8015464: 7add ldrb r5, [r3, #11]
8015466: 68bb ldr r3, [r7, #8]
8015468: 7a9b ldrb r3, [r3, #10]
801546a: 687a ldr r2, [r7, #4]
801546c: 9202 str r2, [sp, #8]
801546e: 2206 movs r2, #6
8015470: 9201 str r2, [sp, #4]
8015472: 9300 str r3, [sp, #0]
8015474: 462b mov r3, r5
8015476: 4622 mov r2, r4
8015478: f004 fc1e bl 8019cb8 <ip4_output_if>
801547c: 4603 mov r3, r0
801547e: 75fb strb r3, [r7, #23]
seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum);
seg->chksum_swapped = 1;
}
#endif
return err;
8015480: f997 3017 ldrsb.w r3, [r7, #23]
}
8015484: 4618 mov r0, r3
8015486: 3720 adds r7, #32
8015488: 46bd mov sp, r7
801548a: bdb0 pop {r4, r5, r7, pc}
801548c: 0801d904 .word 0x0801d904
8015490: 0801dec8 .word 0x0801dec8
8015494: 0801d958 .word 0x0801d958
8015498: 0801dee8 .word 0x0801dee8
801549c: 0801df08 .word 0x0801df08
80154a0: 2000f840 .word 0x2000f840
80154a4: 0801df2c .word 0x0801df2c
080154a8 <tcp_rexmit_rto_prepare>:
*
* @param pcb the tcp_pcb for which to re-enqueue all unacked segments
*/
err_t
tcp_rexmit_rto_prepare(struct tcp_pcb *pcb)
{
80154a8: b5b0 push {r4, r5, r7, lr}
80154aa: b084 sub sp, #16
80154ac: af00 add r7, sp, #0
80154ae: 6078 str r0, [r7, #4]
struct tcp_seg *seg;
LWIP_ASSERT("tcp_rexmit_rto_prepare: invalid pcb", pcb != NULL);
80154b0: 687b ldr r3, [r7, #4]
80154b2: 2b00 cmp r3, #0
80154b4: d106 bne.n 80154c4 <tcp_rexmit_rto_prepare+0x1c>
80154b6: 4b31 ldr r3, [pc, #196] ; (801557c <tcp_rexmit_rto_prepare+0xd4>)
80154b8: f240 6263 movw r2, #1635 ; 0x663
80154bc: 4930 ldr r1, [pc, #192] ; (8015580 <tcp_rexmit_rto_prepare+0xd8>)
80154be: 4831 ldr r0, [pc, #196] ; (8015584 <tcp_rexmit_rto_prepare+0xdc>)
80154c0: f005 fd80 bl 801afc4 <iprintf>
if (pcb->unacked == NULL) {
80154c4: 687b ldr r3, [r7, #4]
80154c6: 6f1b ldr r3, [r3, #112] ; 0x70
80154c8: 2b00 cmp r3, #0
80154ca: d102 bne.n 80154d2 <tcp_rexmit_rto_prepare+0x2a>
return ERR_VAL;
80154cc: f06f 0305 mvn.w r3, #5
80154d0: e050 b.n 8015574 <tcp_rexmit_rto_prepare+0xcc>
/* Move all unacked segments to the head of the unsent queue.
However, give up if any of the unsent pbufs are still referenced by the
netif driver due to deferred transmission. No point loading the link further
if it is struggling to flush its buffered writes. */
for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
80154d2: 687b ldr r3, [r7, #4]
80154d4: 6f1b ldr r3, [r3, #112] ; 0x70
80154d6: 60fb str r3, [r7, #12]
80154d8: e00b b.n 80154f2 <tcp_rexmit_rto_prepare+0x4a>
if (tcp_output_segment_busy(seg)) {
80154da: 68f8 ldr r0, [r7, #12]
80154dc: f7ff fee6 bl 80152ac <tcp_output_segment_busy>
80154e0: 4603 mov r3, r0
80154e2: 2b00 cmp r3, #0
80154e4: d002 beq.n 80154ec <tcp_rexmit_rto_prepare+0x44>
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
return ERR_VAL;
80154e6: f06f 0305 mvn.w r3, #5
80154ea: e043 b.n 8015574 <tcp_rexmit_rto_prepare+0xcc>
for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
80154ec: 68fb ldr r3, [r7, #12]
80154ee: 681b ldr r3, [r3, #0]
80154f0: 60fb str r3, [r7, #12]
80154f2: 68fb ldr r3, [r7, #12]
80154f4: 681b ldr r3, [r3, #0]
80154f6: 2b00 cmp r3, #0
80154f8: d1ef bne.n 80154da <tcp_rexmit_rto_prepare+0x32>
}
}
if (tcp_output_segment_busy(seg)) {
80154fa: 68f8 ldr r0, [r7, #12]
80154fc: f7ff fed6 bl 80152ac <tcp_output_segment_busy>
8015500: 4603 mov r3, r0
8015502: 2b00 cmp r3, #0
8015504: d002 beq.n 801550c <tcp_rexmit_rto_prepare+0x64>
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
return ERR_VAL;
8015506: f06f 0305 mvn.w r3, #5
801550a: e033 b.n 8015574 <tcp_rexmit_rto_prepare+0xcc>
}
/* concatenate unsent queue after unacked queue */
seg->next = pcb->unsent;
801550c: 687b ldr r3, [r7, #4]
801550e: 6eda ldr r2, [r3, #108] ; 0x6c
8015510: 68fb ldr r3, [r7, #12]
8015512: 601a str r2, [r3, #0]
if (pcb->unsent == NULL) {
pcb->unsent_oversize = seg->oversize_left;
}
#endif /* TCP_OVERSIZE_DBGCHECK */
/* unsent queue is the concatenated queue (of unacked, unsent) */
pcb->unsent = pcb->unacked;
8015514: 687b ldr r3, [r7, #4]
8015516: 6f1a ldr r2, [r3, #112] ; 0x70
8015518: 687b ldr r3, [r7, #4]
801551a: 66da str r2, [r3, #108] ; 0x6c
/* unacked queue is now empty */
pcb->unacked = NULL;
801551c: 687b ldr r3, [r7, #4]
801551e: 2200 movs r2, #0
8015520: 671a str r2, [r3, #112] ; 0x70
/* Mark RTO in-progress */
tcp_set_flags(pcb, TF_RTO);
8015522: 687b ldr r3, [r7, #4]
8015524: 8b5b ldrh r3, [r3, #26]
8015526: f443 6300 orr.w r3, r3, #2048 ; 0x800
801552a: b29a uxth r2, r3
801552c: 687b ldr r3, [r7, #4]
801552e: 835a strh r2, [r3, #26]
/* Record the next byte following retransmit */
pcb->rto_end = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
8015530: 68fb ldr r3, [r7, #12]
8015532: 68db ldr r3, [r3, #12]
8015534: 685b ldr r3, [r3, #4]
8015536: 4618 mov r0, r3
8015538: f7f9 fc95 bl 800ee66 <lwip_htonl>
801553c: 4604 mov r4, r0
801553e: 68fb ldr r3, [r7, #12]
8015540: 891b ldrh r3, [r3, #8]
8015542: 461d mov r5, r3
8015544: 68fb ldr r3, [r7, #12]
8015546: 68db ldr r3, [r3, #12]
8015548: 899b ldrh r3, [r3, #12]
801554a: b29b uxth r3, r3
801554c: 4618 mov r0, r3
801554e: f7f9 fc75 bl 800ee3c <lwip_htons>
8015552: 4603 mov r3, r0
8015554: b2db uxtb r3, r3
8015556: f003 0303 and.w r3, r3, #3
801555a: 2b00 cmp r3, #0
801555c: d001 beq.n 8015562 <tcp_rexmit_rto_prepare+0xba>
801555e: 2301 movs r3, #1
8015560: e000 b.n 8015564 <tcp_rexmit_rto_prepare+0xbc>
8015562: 2300 movs r3, #0
8015564: 442b add r3, r5
8015566: 18e2 adds r2, r4, r3
8015568: 687b ldr r3, [r7, #4]
801556a: 64da str r2, [r3, #76] ; 0x4c
/* Don't take any RTT measurements after retransmitting. */
pcb->rttest = 0;
801556c: 687b ldr r3, [r7, #4]
801556e: 2200 movs r2, #0
8015570: 635a str r2, [r3, #52] ; 0x34
return ERR_OK;
8015572: 2300 movs r3, #0
}
8015574: 4618 mov r0, r3
8015576: 3710 adds r7, #16
8015578: 46bd mov sp, r7
801557a: bdb0 pop {r4, r5, r7, pc}
801557c: 0801d904 .word 0x0801d904
8015580: 0801df40 .word 0x0801df40
8015584: 0801d958 .word 0x0801d958
08015588 <tcp_rexmit_rto_commit>:
*
* @param pcb the tcp_pcb for which to re-enqueue all unacked segments
*/
void
tcp_rexmit_rto_commit(struct tcp_pcb *pcb)
{
8015588: b580 push {r7, lr}
801558a: b082 sub sp, #8
801558c: af00 add r7, sp, #0
801558e: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_rexmit_rto_commit: invalid pcb", pcb != NULL);
8015590: 687b ldr r3, [r7, #4]
8015592: 2b00 cmp r3, #0
8015594: d106 bne.n 80155a4 <tcp_rexmit_rto_commit+0x1c>
8015596: 4b0d ldr r3, [pc, #52] ; (80155cc <tcp_rexmit_rto_commit+0x44>)
8015598: f44f 62d3 mov.w r2, #1688 ; 0x698
801559c: 490c ldr r1, [pc, #48] ; (80155d0 <tcp_rexmit_rto_commit+0x48>)
801559e: 480d ldr r0, [pc, #52] ; (80155d4 <tcp_rexmit_rto_commit+0x4c>)
80155a0: f005 fd10 bl 801afc4 <iprintf>
/* increment number of retransmissions */
if (pcb->nrtx < 0xFF) {
80155a4: 687b ldr r3, [r7, #4]
80155a6: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80155aa: 2bff cmp r3, #255 ; 0xff
80155ac: d007 beq.n 80155be <tcp_rexmit_rto_commit+0x36>
++pcb->nrtx;
80155ae: 687b ldr r3, [r7, #4]
80155b0: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80155b4: 3301 adds r3, #1
80155b6: b2da uxtb r2, r3
80155b8: 687b ldr r3, [r7, #4]
80155ba: f883 2042 strb.w r2, [r3, #66] ; 0x42
}
/* Do the actual retransmission */
tcp_output(pcb);
80155be: 6878 ldr r0, [r7, #4]
80155c0: f7ff fc80 bl 8014ec4 <tcp_output>
}
80155c4: bf00 nop
80155c6: 3708 adds r7, #8
80155c8: 46bd mov sp, r7
80155ca: bd80 pop {r7, pc}
80155cc: 0801d904 .word 0x0801d904
80155d0: 0801df64 .word 0x0801df64
80155d4: 0801d958 .word 0x0801d958
080155d8 <tcp_rexmit_rto>:
*
* @param pcb the tcp_pcb for which to re-enqueue all unacked segments
*/
void
tcp_rexmit_rto(struct tcp_pcb *pcb)
{
80155d8: b580 push {r7, lr}
80155da: b082 sub sp, #8
80155dc: af00 add r7, sp, #0
80155de: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_rexmit_rto: invalid pcb", pcb != NULL);
80155e0: 687b ldr r3, [r7, #4]
80155e2: 2b00 cmp r3, #0
80155e4: d106 bne.n 80155f4 <tcp_rexmit_rto+0x1c>
80155e6: 4b0a ldr r3, [pc, #40] ; (8015610 <tcp_rexmit_rto+0x38>)
80155e8: f240 62ad movw r2, #1709 ; 0x6ad
80155ec: 4909 ldr r1, [pc, #36] ; (8015614 <tcp_rexmit_rto+0x3c>)
80155ee: 480a ldr r0, [pc, #40] ; (8015618 <tcp_rexmit_rto+0x40>)
80155f0: f005 fce8 bl 801afc4 <iprintf>
if (tcp_rexmit_rto_prepare(pcb) == ERR_OK) {
80155f4: 6878 ldr r0, [r7, #4]
80155f6: f7ff ff57 bl 80154a8 <tcp_rexmit_rto_prepare>
80155fa: 4603 mov r3, r0
80155fc: 2b00 cmp r3, #0
80155fe: d102 bne.n 8015606 <tcp_rexmit_rto+0x2e>
tcp_rexmit_rto_commit(pcb);
8015600: 6878 ldr r0, [r7, #4]
8015602: f7ff ffc1 bl 8015588 <tcp_rexmit_rto_commit>
}
}
8015606: bf00 nop
8015608: 3708 adds r7, #8
801560a: 46bd mov sp, r7
801560c: bd80 pop {r7, pc}
801560e: bf00 nop
8015610: 0801d904 .word 0x0801d904
8015614: 0801df88 .word 0x0801df88
8015618: 0801d958 .word 0x0801d958
0801561c <tcp_rexmit>:
*
* @param pcb the tcp_pcb for which to retransmit the first unacked segment
*/
err_t
tcp_rexmit(struct tcp_pcb *pcb)
{
801561c: b590 push {r4, r7, lr}
801561e: b085 sub sp, #20
8015620: af00 add r7, sp, #0
8015622: 6078 str r0, [r7, #4]
struct tcp_seg *seg;
struct tcp_seg **cur_seg;
LWIP_ASSERT("tcp_rexmit: invalid pcb", pcb != NULL);
8015624: 687b ldr r3, [r7, #4]
8015626: 2b00 cmp r3, #0
8015628: d106 bne.n 8015638 <tcp_rexmit+0x1c>
801562a: 4b2f ldr r3, [pc, #188] ; (80156e8 <tcp_rexmit+0xcc>)
801562c: f240 62c1 movw r2, #1729 ; 0x6c1
8015630: 492e ldr r1, [pc, #184] ; (80156ec <tcp_rexmit+0xd0>)
8015632: 482f ldr r0, [pc, #188] ; (80156f0 <tcp_rexmit+0xd4>)
8015634: f005 fcc6 bl 801afc4 <iprintf>
if (pcb->unacked == NULL) {
8015638: 687b ldr r3, [r7, #4]
801563a: 6f1b ldr r3, [r3, #112] ; 0x70
801563c: 2b00 cmp r3, #0
801563e: d102 bne.n 8015646 <tcp_rexmit+0x2a>
return ERR_VAL;
8015640: f06f 0305 mvn.w r3, #5
8015644: e04c b.n 80156e0 <tcp_rexmit+0xc4>
}
seg = pcb->unacked;
8015646: 687b ldr r3, [r7, #4]
8015648: 6f1b ldr r3, [r3, #112] ; 0x70
801564a: 60bb str r3, [r7, #8]
/* Give up if the segment is still referenced by the netif driver
due to deferred transmission. */
if (tcp_output_segment_busy(seg)) {
801564c: 68b8 ldr r0, [r7, #8]
801564e: f7ff fe2d bl 80152ac <tcp_output_segment_busy>
8015652: 4603 mov r3, r0
8015654: 2b00 cmp r3, #0
8015656: d002 beq.n 801565e <tcp_rexmit+0x42>
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit busy\n"));
return ERR_VAL;
8015658: f06f 0305 mvn.w r3, #5
801565c: e040 b.n 80156e0 <tcp_rexmit+0xc4>
}
/* Move the first unacked segment to the unsent queue */
/* Keep the unsent queue sorted. */
pcb->unacked = seg->next;
801565e: 68bb ldr r3, [r7, #8]
8015660: 681a ldr r2, [r3, #0]
8015662: 687b ldr r3, [r7, #4]
8015664: 671a str r2, [r3, #112] ; 0x70
cur_seg = &(pcb->unsent);
8015666: 687b ldr r3, [r7, #4]
8015668: 336c adds r3, #108 ; 0x6c
801566a: 60fb str r3, [r7, #12]
while (*cur_seg &&
801566c: e002 b.n 8015674 <tcp_rexmit+0x58>
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
cur_seg = &((*cur_seg)->next );
801566e: 68fb ldr r3, [r7, #12]
8015670: 681b ldr r3, [r3, #0]
8015672: 60fb str r3, [r7, #12]
while (*cur_seg &&
8015674: 68fb ldr r3, [r7, #12]
8015676: 681b ldr r3, [r3, #0]
8015678: 2b00 cmp r3, #0
801567a: d011 beq.n 80156a0 <tcp_rexmit+0x84>
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
801567c: 68fb ldr r3, [r7, #12]
801567e: 681b ldr r3, [r3, #0]
8015680: 68db ldr r3, [r3, #12]
8015682: 685b ldr r3, [r3, #4]
8015684: 4618 mov r0, r3
8015686: f7f9 fbee bl 800ee66 <lwip_htonl>
801568a: 4604 mov r4, r0
801568c: 68bb ldr r3, [r7, #8]
801568e: 68db ldr r3, [r3, #12]
8015690: 685b ldr r3, [r3, #4]
8015692: 4618 mov r0, r3
8015694: f7f9 fbe7 bl 800ee66 <lwip_htonl>
8015698: 4603 mov r3, r0
801569a: 1ae3 subs r3, r4, r3
while (*cur_seg &&
801569c: 2b00 cmp r3, #0
801569e: dbe6 blt.n 801566e <tcp_rexmit+0x52>
}
seg->next = *cur_seg;
80156a0: 68fb ldr r3, [r7, #12]
80156a2: 681a ldr r2, [r3, #0]
80156a4: 68bb ldr r3, [r7, #8]
80156a6: 601a str r2, [r3, #0]
*cur_seg = seg;
80156a8: 68fb ldr r3, [r7, #12]
80156aa: 68ba ldr r2, [r7, #8]
80156ac: 601a str r2, [r3, #0]
#if TCP_OVERSIZE
if (seg->next == NULL) {
80156ae: 68bb ldr r3, [r7, #8]
80156b0: 681b ldr r3, [r3, #0]
80156b2: 2b00 cmp r3, #0
80156b4: d103 bne.n 80156be <tcp_rexmit+0xa2>
/* the retransmitted segment is last in unsent, so reset unsent_oversize */
pcb->unsent_oversize = 0;
80156b6: 687b ldr r3, [r7, #4]
80156b8: 2200 movs r2, #0
80156ba: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
}
#endif /* TCP_OVERSIZE */
if (pcb->nrtx < 0xFF) {
80156be: 687b ldr r3, [r7, #4]
80156c0: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80156c4: 2bff cmp r3, #255 ; 0xff
80156c6: d007 beq.n 80156d8 <tcp_rexmit+0xbc>
++pcb->nrtx;
80156c8: 687b ldr r3, [r7, #4]
80156ca: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80156ce: 3301 adds r3, #1
80156d0: b2da uxtb r2, r3
80156d2: 687b ldr r3, [r7, #4]
80156d4: f883 2042 strb.w r2, [r3, #66] ; 0x42
}
/* Don't take any rtt measurements after retransmitting. */
pcb->rttest = 0;
80156d8: 687b ldr r3, [r7, #4]
80156da: 2200 movs r2, #0
80156dc: 635a str r2, [r3, #52] ; 0x34
/* Do the actual retransmission. */
MIB2_STATS_INC(mib2.tcpretranssegs);
/* No need to call tcp_output: we are always called from tcp_input()
and thus tcp_output directly returns. */
return ERR_OK;
80156de: 2300 movs r3, #0
}
80156e0: 4618 mov r0, r3
80156e2: 3714 adds r7, #20
80156e4: 46bd mov sp, r7
80156e6: bd90 pop {r4, r7, pc}
80156e8: 0801d904 .word 0x0801d904
80156ec: 0801dfa4 .word 0x0801dfa4
80156f0: 0801d958 .word 0x0801d958
080156f4 <tcp_rexmit_fast>:
*
* @param pcb the tcp_pcb for which to retransmit the first unacked segment
*/
void
tcp_rexmit_fast(struct tcp_pcb *pcb)
{
80156f4: b580 push {r7, lr}
80156f6: b082 sub sp, #8
80156f8: af00 add r7, sp, #0
80156fa: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_rexmit_fast: invalid pcb", pcb != NULL);
80156fc: 687b ldr r3, [r7, #4]
80156fe: 2b00 cmp r3, #0
8015700: d106 bne.n 8015710 <tcp_rexmit_fast+0x1c>
8015702: 4b2a ldr r3, [pc, #168] ; (80157ac <tcp_rexmit_fast+0xb8>)
8015704: f240 62f9 movw r2, #1785 ; 0x6f9
8015708: 4929 ldr r1, [pc, #164] ; (80157b0 <tcp_rexmit_fast+0xbc>)
801570a: 482a ldr r0, [pc, #168] ; (80157b4 <tcp_rexmit_fast+0xc0>)
801570c: f005 fc5a bl 801afc4 <iprintf>
if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) {
8015710: 687b ldr r3, [r7, #4]
8015712: 6f1b ldr r3, [r3, #112] ; 0x70
8015714: 2b00 cmp r3, #0
8015716: d045 beq.n 80157a4 <tcp_rexmit_fast+0xb0>
8015718: 687b ldr r3, [r7, #4]
801571a: 8b5b ldrh r3, [r3, #26]
801571c: f003 0304 and.w r3, r3, #4
8015720: 2b00 cmp r3, #0
8015722: d13f bne.n 80157a4 <tcp_rexmit_fast+0xb0>
LWIP_DEBUGF(TCP_FR_DEBUG,
("tcp_receive: dupacks %"U16_F" (%"U32_F
"), fast retransmit %"U32_F"\n",
(u16_t)pcb->dupacks, pcb->lastack,
lwip_ntohl(pcb->unacked->tcphdr->seqno)));
if (tcp_rexmit(pcb) == ERR_OK) {
8015724: 6878 ldr r0, [r7, #4]
8015726: f7ff ff79 bl 801561c <tcp_rexmit>
801572a: 4603 mov r3, r0
801572c: 2b00 cmp r3, #0
801572e: d139 bne.n 80157a4 <tcp_rexmit_fast+0xb0>
/* Set ssthresh to half of the minimum of the current
* cwnd and the advertised window */
pcb->ssthresh = LWIP_MIN(pcb->cwnd, pcb->snd_wnd) / 2;
8015730: 687b ldr r3, [r7, #4]
8015732: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8015736: 687b ldr r3, [r7, #4]
8015738: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
801573c: 4293 cmp r3, r2
801573e: bf28 it cs
8015740: 4613 movcs r3, r2
8015742: b29b uxth r3, r3
8015744: 2b00 cmp r3, #0
8015746: da00 bge.n 801574a <tcp_rexmit_fast+0x56>
8015748: 3301 adds r3, #1
801574a: 105b asrs r3, r3, #1
801574c: b29a uxth r2, r3
801574e: 687b ldr r3, [r7, #4]
8015750: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
/* The minimum value for ssthresh should be 2 MSS */
if (pcb->ssthresh < (2U * pcb->mss)) {
8015754: 687b ldr r3, [r7, #4]
8015756: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a
801575a: 461a mov r2, r3
801575c: 687b ldr r3, [r7, #4]
801575e: 8e5b ldrh r3, [r3, #50] ; 0x32
8015760: 005b lsls r3, r3, #1
8015762: 429a cmp r2, r3
8015764: d206 bcs.n 8015774 <tcp_rexmit_fast+0x80>
LWIP_DEBUGF(TCP_FR_DEBUG,
("tcp_receive: The minimum value for ssthresh %"TCPWNDSIZE_F
" should be min 2 mss %"U16_F"...\n",
pcb->ssthresh, (u16_t)(2 * pcb->mss)));
pcb->ssthresh = 2 * pcb->mss;
8015766: 687b ldr r3, [r7, #4]
8015768: 8e5b ldrh r3, [r3, #50] ; 0x32
801576a: 005b lsls r3, r3, #1
801576c: b29a uxth r2, r3
801576e: 687b ldr r3, [r7, #4]
8015770: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
}
pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
8015774: 687b ldr r3, [r7, #4]
8015776: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a
801577a: 687b ldr r3, [r7, #4]
801577c: 8e5b ldrh r3, [r3, #50] ; 0x32
801577e: 4619 mov r1, r3
8015780: 0049 lsls r1, r1, #1
8015782: 440b add r3, r1
8015784: b29b uxth r3, r3
8015786: 4413 add r3, r2
8015788: b29a uxth r2, r3
801578a: 687b ldr r3, [r7, #4]
801578c: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
tcp_set_flags(pcb, TF_INFR);
8015790: 687b ldr r3, [r7, #4]
8015792: 8b5b ldrh r3, [r3, #26]
8015794: f043 0304 orr.w r3, r3, #4
8015798: b29a uxth r2, r3
801579a: 687b ldr r3, [r7, #4]
801579c: 835a strh r2, [r3, #26]
/* Reset the retransmission timer to prevent immediate rto retransmissions */
pcb->rtime = 0;
801579e: 687b ldr r3, [r7, #4]
80157a0: 2200 movs r2, #0
80157a2: 861a strh r2, [r3, #48] ; 0x30
}
}
}
80157a4: bf00 nop
80157a6: 3708 adds r7, #8
80157a8: 46bd mov sp, r7
80157aa: bd80 pop {r7, pc}
80157ac: 0801d904 .word 0x0801d904
80157b0: 0801dfbc .word 0x0801dfbc
80157b4: 0801d958 .word 0x0801d958
080157b8 <tcp_output_alloc_header_common>:
static struct pbuf *
tcp_output_alloc_header_common(u32_t ackno, u16_t optlen, u16_t datalen,
u32_t seqno_be /* already in network byte order */,
u16_t src_port, u16_t dst_port, u8_t flags, u16_t wnd)
{
80157b8: b580 push {r7, lr}
80157ba: b086 sub sp, #24
80157bc: af00 add r7, sp, #0
80157be: 60f8 str r0, [r7, #12]
80157c0: 607b str r3, [r7, #4]
80157c2: 460b mov r3, r1
80157c4: 817b strh r3, [r7, #10]
80157c6: 4613 mov r3, r2
80157c8: 813b strh r3, [r7, #8]
struct tcp_hdr *tcphdr;
struct pbuf *p;
p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM);
80157ca: 897a ldrh r2, [r7, #10]
80157cc: 893b ldrh r3, [r7, #8]
80157ce: 4413 add r3, r2
80157d0: b29b uxth r3, r3
80157d2: 3314 adds r3, #20
80157d4: b29b uxth r3, r3
80157d6: f44f 7220 mov.w r2, #640 ; 0x280
80157da: 4619 mov r1, r3
80157dc: 2022 movs r0, #34 ; 0x22
80157de: f7fa fc01 bl 800ffe4 <pbuf_alloc>
80157e2: 6178 str r0, [r7, #20]
if (p != NULL) {
80157e4: 697b ldr r3, [r7, #20]
80157e6: 2b00 cmp r3, #0
80157e8: d04d beq.n 8015886 <tcp_output_alloc_header_common+0xce>
LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
80157ea: 897b ldrh r3, [r7, #10]
80157ec: 3313 adds r3, #19
80157ee: 697a ldr r2, [r7, #20]
80157f0: 8952 ldrh r2, [r2, #10]
80157f2: 4293 cmp r3, r2
80157f4: db06 blt.n 8015804 <tcp_output_alloc_header_common+0x4c>
80157f6: 4b26 ldr r3, [pc, #152] ; (8015890 <tcp_output_alloc_header_common+0xd8>)
80157f8: f240 7223 movw r2, #1827 ; 0x723
80157fc: 4925 ldr r1, [pc, #148] ; (8015894 <tcp_output_alloc_header_common+0xdc>)
80157fe: 4826 ldr r0, [pc, #152] ; (8015898 <tcp_output_alloc_header_common+0xe0>)
8015800: f005 fbe0 bl 801afc4 <iprintf>
(p->len >= TCP_HLEN + optlen));
tcphdr = (struct tcp_hdr *)p->payload;
8015804: 697b ldr r3, [r7, #20]
8015806: 685b ldr r3, [r3, #4]
8015808: 613b str r3, [r7, #16]
tcphdr->src = lwip_htons(src_port);
801580a: 8c3b ldrh r3, [r7, #32]
801580c: 4618 mov r0, r3
801580e: f7f9 fb15 bl 800ee3c <lwip_htons>
8015812: 4603 mov r3, r0
8015814: 461a mov r2, r3
8015816: 693b ldr r3, [r7, #16]
8015818: 801a strh r2, [r3, #0]
tcphdr->dest = lwip_htons(dst_port);
801581a: 8cbb ldrh r3, [r7, #36] ; 0x24
801581c: 4618 mov r0, r3
801581e: f7f9 fb0d bl 800ee3c <lwip_htons>
8015822: 4603 mov r3, r0
8015824: 461a mov r2, r3
8015826: 693b ldr r3, [r7, #16]
8015828: 805a strh r2, [r3, #2]
tcphdr->seqno = seqno_be;
801582a: 693b ldr r3, [r7, #16]
801582c: 687a ldr r2, [r7, #4]
801582e: 605a str r2, [r3, #4]
tcphdr->ackno = lwip_htonl(ackno);
8015830: 68f8 ldr r0, [r7, #12]
8015832: f7f9 fb18 bl 800ee66 <lwip_htonl>
8015836: 4602 mov r2, r0
8015838: 693b ldr r3, [r7, #16]
801583a: 609a str r2, [r3, #8]
TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), flags);
801583c: 897b ldrh r3, [r7, #10]
801583e: 089b lsrs r3, r3, #2
8015840: b29b uxth r3, r3
8015842: 3305 adds r3, #5
8015844: b29b uxth r3, r3
8015846: 031b lsls r3, r3, #12
8015848: b29a uxth r2, r3
801584a: f897 3028 ldrb.w r3, [r7, #40] ; 0x28
801584e: b29b uxth r3, r3
8015850: 4313 orrs r3, r2
8015852: b29b uxth r3, r3
8015854: 4618 mov r0, r3
8015856: f7f9 faf1 bl 800ee3c <lwip_htons>
801585a: 4603 mov r3, r0
801585c: 461a mov r2, r3
801585e: 693b ldr r3, [r7, #16]
8015860: 819a strh r2, [r3, #12]
tcphdr->wnd = lwip_htons(wnd);
8015862: 8dbb ldrh r3, [r7, #44] ; 0x2c
8015864: 4618 mov r0, r3
8015866: f7f9 fae9 bl 800ee3c <lwip_htons>
801586a: 4603 mov r3, r0
801586c: 461a mov r2, r3
801586e: 693b ldr r3, [r7, #16]
8015870: 81da strh r2, [r3, #14]
tcphdr->chksum = 0;
8015872: 693b ldr r3, [r7, #16]
8015874: 2200 movs r2, #0
8015876: 741a strb r2, [r3, #16]
8015878: 2200 movs r2, #0
801587a: 745a strb r2, [r3, #17]
tcphdr->urgp = 0;
801587c: 693b ldr r3, [r7, #16]
801587e: 2200 movs r2, #0
8015880: 749a strb r2, [r3, #18]
8015882: 2200 movs r2, #0
8015884: 74da strb r2, [r3, #19]
}
return p;
8015886: 697b ldr r3, [r7, #20]
}
8015888: 4618 mov r0, r3
801588a: 3718 adds r7, #24
801588c: 46bd mov sp, r7
801588e: bd80 pop {r7, pc}
8015890: 0801d904 .word 0x0801d904
8015894: 0801dfdc .word 0x0801dfdc
8015898: 0801d958 .word 0x0801d958
0801589c <tcp_output_alloc_header>:
* @return pbuf with p->payload being the tcp_hdr
*/
static struct pbuf *
tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen,
u32_t seqno_be /* already in network byte order */)
{
801589c: b5b0 push {r4, r5, r7, lr}
801589e: b08a sub sp, #40 ; 0x28
80158a0: af04 add r7, sp, #16
80158a2: 60f8 str r0, [r7, #12]
80158a4: 607b str r3, [r7, #4]
80158a6: 460b mov r3, r1
80158a8: 817b strh r3, [r7, #10]
80158aa: 4613 mov r3, r2
80158ac: 813b strh r3, [r7, #8]
struct pbuf *p;
LWIP_ASSERT("tcp_output_alloc_header: invalid pcb", pcb != NULL);
80158ae: 68fb ldr r3, [r7, #12]
80158b0: 2b00 cmp r3, #0
80158b2: d106 bne.n 80158c2 <tcp_output_alloc_header+0x26>
80158b4: 4b15 ldr r3, [pc, #84] ; (801590c <tcp_output_alloc_header+0x70>)
80158b6: f240 7242 movw r2, #1858 ; 0x742
80158ba: 4915 ldr r1, [pc, #84] ; (8015910 <tcp_output_alloc_header+0x74>)
80158bc: 4815 ldr r0, [pc, #84] ; (8015914 <tcp_output_alloc_header+0x78>)
80158be: f005 fb81 bl 801afc4 <iprintf>
p = tcp_output_alloc_header_common(pcb->rcv_nxt, optlen, datalen,
80158c2: 68fb ldr r3, [r7, #12]
80158c4: 6a58 ldr r0, [r3, #36] ; 0x24
80158c6: 68fb ldr r3, [r7, #12]
80158c8: 8adb ldrh r3, [r3, #22]
80158ca: 68fa ldr r2, [r7, #12]
80158cc: 8b12 ldrh r2, [r2, #24]
80158ce: 68f9 ldr r1, [r7, #12]
80158d0: 8d49 ldrh r1, [r1, #42] ; 0x2a
80158d2: 893d ldrh r5, [r7, #8]
80158d4: 897c ldrh r4, [r7, #10]
80158d6: 9103 str r1, [sp, #12]
80158d8: 2110 movs r1, #16
80158da: 9102 str r1, [sp, #8]
80158dc: 9201 str r2, [sp, #4]
80158de: 9300 str r3, [sp, #0]
80158e0: 687b ldr r3, [r7, #4]
80158e2: 462a mov r2, r5
80158e4: 4621 mov r1, r4
80158e6: f7ff ff67 bl 80157b8 <tcp_output_alloc_header_common>
80158ea: 6178 str r0, [r7, #20]
seqno_be, pcb->local_port, pcb->remote_port, TCP_ACK,
TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
if (p != NULL) {
80158ec: 697b ldr r3, [r7, #20]
80158ee: 2b00 cmp r3, #0
80158f0: d006 beq.n 8015900 <tcp_output_alloc_header+0x64>
/* If we're sending a packet, update the announced right window edge */
pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
80158f2: 68fb ldr r3, [r7, #12]
80158f4: 6a5b ldr r3, [r3, #36] ; 0x24
80158f6: 68fa ldr r2, [r7, #12]
80158f8: 8d52 ldrh r2, [r2, #42] ; 0x2a
80158fa: 441a add r2, r3
80158fc: 68fb ldr r3, [r7, #12]
80158fe: 62da str r2, [r3, #44] ; 0x2c
}
return p;
8015900: 697b ldr r3, [r7, #20]
}
8015902: 4618 mov r0, r3
8015904: 3718 adds r7, #24
8015906: 46bd mov sp, r7
8015908: bdb0 pop {r4, r5, r7, pc}
801590a: bf00 nop
801590c: 0801d904 .word 0x0801d904
8015910: 0801e00c .word 0x0801e00c
8015914: 0801d958 .word 0x0801d958
08015918 <tcp_output_fill_options>:
/* Fill in options for control segments */
static void
tcp_output_fill_options(const struct tcp_pcb *pcb, struct pbuf *p, u8_t optflags, u8_t num_sacks)
{
8015918: b580 push {r7, lr}
801591a: b088 sub sp, #32
801591c: af00 add r7, sp, #0
801591e: 60f8 str r0, [r7, #12]
8015920: 60b9 str r1, [r7, #8]
8015922: 4611 mov r1, r2
8015924: 461a mov r2, r3
8015926: 460b mov r3, r1
8015928: 71fb strb r3, [r7, #7]
801592a: 4613 mov r3, r2
801592c: 71bb strb r3, [r7, #6]
struct tcp_hdr *tcphdr;
u32_t *opts;
u16_t sacks_len = 0;
801592e: 2300 movs r3, #0
8015930: 83fb strh r3, [r7, #30]
LWIP_ASSERT("tcp_output_fill_options: invalid pbuf", p != NULL);
8015932: 68bb ldr r3, [r7, #8]
8015934: 2b00 cmp r3, #0
8015936: d106 bne.n 8015946 <tcp_output_fill_options+0x2e>
8015938: 4b13 ldr r3, [pc, #76] ; (8015988 <tcp_output_fill_options+0x70>)
801593a: f240 7256 movw r2, #1878 ; 0x756
801593e: 4913 ldr r1, [pc, #76] ; (801598c <tcp_output_fill_options+0x74>)
8015940: 4813 ldr r0, [pc, #76] ; (8015990 <tcp_output_fill_options+0x78>)
8015942: f005 fb3f bl 801afc4 <iprintf>
tcphdr = (struct tcp_hdr *)p->payload;
8015946: 68bb ldr r3, [r7, #8]
8015948: 685b ldr r3, [r3, #4]
801594a: 61bb str r3, [r7, #24]
opts = (u32_t *)(void *)(tcphdr + 1);
801594c: 69bb ldr r3, [r7, #24]
801594e: 3314 adds r3, #20
8015950: 617b str r3, [r7, #20]
opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, tcphdr, pcb, opts);
#endif
LWIP_UNUSED_ARG(pcb);
LWIP_UNUSED_ARG(sacks_len);
LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(tcphdr + 1)) + sacks_len * 4 + LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb));
8015952: 69bb ldr r3, [r7, #24]
8015954: f103 0214 add.w r2, r3, #20
8015958: 8bfb ldrh r3, [r7, #30]
801595a: 009b lsls r3, r3, #2
801595c: 4619 mov r1, r3
801595e: 79fb ldrb r3, [r7, #7]
8015960: 009b lsls r3, r3, #2
8015962: f003 0304 and.w r3, r3, #4
8015966: 440b add r3, r1
8015968: 4413 add r3, r2
801596a: 697a ldr r2, [r7, #20]
801596c: 429a cmp r2, r3
801596e: d006 beq.n 801597e <tcp_output_fill_options+0x66>
8015970: 4b05 ldr r3, [pc, #20] ; (8015988 <tcp_output_fill_options+0x70>)
8015972: f240 7275 movw r2, #1909 ; 0x775
8015976: 4907 ldr r1, [pc, #28] ; (8015994 <tcp_output_fill_options+0x7c>)
8015978: 4805 ldr r0, [pc, #20] ; (8015990 <tcp_output_fill_options+0x78>)
801597a: f005 fb23 bl 801afc4 <iprintf>
LWIP_UNUSED_ARG(optflags); /* for LWIP_NOASSERT */
LWIP_UNUSED_ARG(opts); /* for LWIP_NOASSERT */
}
801597e: bf00 nop
8015980: 3720 adds r7, #32
8015982: 46bd mov sp, r7
8015984: bd80 pop {r7, pc}
8015986: bf00 nop
8015988: 0801d904 .word 0x0801d904
801598c: 0801e034 .word 0x0801e034
8015990: 0801d958 .word 0x0801d958
8015994: 0801df2c .word 0x0801df2c
08015998 <tcp_output_control_segment>:
* header checksum and calling ip_output_if while handling netif hints and stats.
*/
static err_t
tcp_output_control_segment(const struct tcp_pcb *pcb, struct pbuf *p,
const ip_addr_t *src, const ip_addr_t *dst)
{
8015998: b580 push {r7, lr}
801599a: b08a sub sp, #40 ; 0x28
801599c: af04 add r7, sp, #16
801599e: 60f8 str r0, [r7, #12]
80159a0: 60b9 str r1, [r7, #8]
80159a2: 607a str r2, [r7, #4]
80159a4: 603b str r3, [r7, #0]
err_t err;
struct netif *netif;
LWIP_ASSERT("tcp_output_control_segment: invalid pbuf", p != NULL);
80159a6: 68bb ldr r3, [r7, #8]
80159a8: 2b00 cmp r3, #0
80159aa: d106 bne.n 80159ba <tcp_output_control_segment+0x22>
80159ac: 4b1c ldr r3, [pc, #112] ; (8015a20 <tcp_output_control_segment+0x88>)
80159ae: f240 7287 movw r2, #1927 ; 0x787
80159b2: 491c ldr r1, [pc, #112] ; (8015a24 <tcp_output_control_segment+0x8c>)
80159b4: 481c ldr r0, [pc, #112] ; (8015a28 <tcp_output_control_segment+0x90>)
80159b6: f005 fb05 bl 801afc4 <iprintf>
netif = tcp_route(pcb, src, dst);
80159ba: 683a ldr r2, [r7, #0]
80159bc: 6879 ldr r1, [r7, #4]
80159be: 68f8 ldr r0, [r7, #12]
80159c0: f7fe ff40 bl 8014844 <tcp_route>
80159c4: 6138 str r0, [r7, #16]
if (netif == NULL) {
80159c6: 693b ldr r3, [r7, #16]
80159c8: 2b00 cmp r3, #0
80159ca: d102 bne.n 80159d2 <tcp_output_control_segment+0x3a>
err = ERR_RTE;
80159cc: 23fc movs r3, #252 ; 0xfc
80159ce: 75fb strb r3, [r7, #23]
80159d0: e01c b.n 8015a0c <tcp_output_control_segment+0x74>
struct tcp_hdr *tcphdr = (struct tcp_hdr *)p->payload;
tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len,
src, dst);
}
#endif
if (pcb != NULL) {
80159d2: 68fb ldr r3, [r7, #12]
80159d4: 2b00 cmp r3, #0
80159d6: d006 beq.n 80159e6 <tcp_output_control_segment+0x4e>
NETIF_SET_HINTS(netif, LWIP_CONST_CAST(struct netif_hint*, &(pcb->netif_hints)));
ttl = pcb->ttl;
80159d8: 68fb ldr r3, [r7, #12]
80159da: 7adb ldrb r3, [r3, #11]
80159dc: 75bb strb r3, [r7, #22]
tos = pcb->tos;
80159de: 68fb ldr r3, [r7, #12]
80159e0: 7a9b ldrb r3, [r3, #10]
80159e2: 757b strb r3, [r7, #21]
80159e4: e003 b.n 80159ee <tcp_output_control_segment+0x56>
} else {
/* Send output with hardcoded TTL/HL since we have no access to the pcb */
ttl = TCP_TTL;
80159e6: 23ff movs r3, #255 ; 0xff
80159e8: 75bb strb r3, [r7, #22]
tos = 0;
80159ea: 2300 movs r3, #0
80159ec: 757b strb r3, [r7, #21]
}
TCP_STATS_INC(tcp.xmit);
err = ip_output_if(p, src, dst, ttl, tos, IP_PROTO_TCP, netif);
80159ee: 7dba ldrb r2, [r7, #22]
80159f0: 693b ldr r3, [r7, #16]
80159f2: 9302 str r3, [sp, #8]
80159f4: 2306 movs r3, #6
80159f6: 9301 str r3, [sp, #4]
80159f8: 7d7b ldrb r3, [r7, #21]
80159fa: 9300 str r3, [sp, #0]
80159fc: 4613 mov r3, r2
80159fe: 683a ldr r2, [r7, #0]
8015a00: 6879 ldr r1, [r7, #4]
8015a02: 68b8 ldr r0, [r7, #8]
8015a04: f004 f958 bl 8019cb8 <ip4_output_if>
8015a08: 4603 mov r3, r0
8015a0a: 75fb strb r3, [r7, #23]
NETIF_RESET_HINTS(netif);
}
pbuf_free(p);
8015a0c: 68b8 ldr r0, [r7, #8]
8015a0e: f7fa fdcd bl 80105ac <pbuf_free>
return err;
8015a12: f997 3017 ldrsb.w r3, [r7, #23]
}
8015a16: 4618 mov r0, r3
8015a18: 3718 adds r7, #24
8015a1a: 46bd mov sp, r7
8015a1c: bd80 pop {r7, pc}
8015a1e: bf00 nop
8015a20: 0801d904 .word 0x0801d904
8015a24: 0801e05c .word 0x0801e05c
8015a28: 0801d958 .word 0x0801d958
08015a2c <tcp_rst>:
*/
void
tcp_rst(const struct tcp_pcb *pcb, u32_t seqno, u32_t ackno,
const ip_addr_t *local_ip, const ip_addr_t *remote_ip,
u16_t local_port, u16_t remote_port)
{
8015a2c: b590 push {r4, r7, lr}
8015a2e: b08b sub sp, #44 ; 0x2c
8015a30: af04 add r7, sp, #16
8015a32: 60f8 str r0, [r7, #12]
8015a34: 60b9 str r1, [r7, #8]
8015a36: 607a str r2, [r7, #4]
8015a38: 603b str r3, [r7, #0]
struct pbuf *p;
u16_t wnd;
u8_t optlen;
LWIP_ASSERT("tcp_rst: invalid local_ip", local_ip != NULL);
8015a3a: 683b ldr r3, [r7, #0]
8015a3c: 2b00 cmp r3, #0
8015a3e: d106 bne.n 8015a4e <tcp_rst+0x22>
8015a40: 4b1f ldr r3, [pc, #124] ; (8015ac0 <tcp_rst+0x94>)
8015a42: f240 72c4 movw r2, #1988 ; 0x7c4
8015a46: 491f ldr r1, [pc, #124] ; (8015ac4 <tcp_rst+0x98>)
8015a48: 481f ldr r0, [pc, #124] ; (8015ac8 <tcp_rst+0x9c>)
8015a4a: f005 fabb bl 801afc4 <iprintf>
LWIP_ASSERT("tcp_rst: invalid remote_ip", remote_ip != NULL);
8015a4e: 6abb ldr r3, [r7, #40] ; 0x28
8015a50: 2b00 cmp r3, #0
8015a52: d106 bne.n 8015a62 <tcp_rst+0x36>
8015a54: 4b1a ldr r3, [pc, #104] ; (8015ac0 <tcp_rst+0x94>)
8015a56: f240 72c5 movw r2, #1989 ; 0x7c5
8015a5a: 491c ldr r1, [pc, #112] ; (8015acc <tcp_rst+0xa0>)
8015a5c: 481a ldr r0, [pc, #104] ; (8015ac8 <tcp_rst+0x9c>)
8015a5e: f005 fab1 bl 801afc4 <iprintf>
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
8015a62: 2300 movs r3, #0
8015a64: 75fb strb r3, [r7, #23]
#if LWIP_WND_SCALE
wnd = PP_HTONS(((TCP_WND >> TCP_RCV_SCALE) & 0xFFFF));
#else
wnd = PP_HTONS(TCP_WND);
8015a66: f246 0308 movw r3, #24584 ; 0x6008
8015a6a: 82bb strh r3, [r7, #20]
#endif
p = tcp_output_alloc_header_common(ackno, optlen, 0, lwip_htonl(seqno), local_port,
8015a6c: 7dfb ldrb r3, [r7, #23]
8015a6e: b29c uxth r4, r3
8015a70: 68b8 ldr r0, [r7, #8]
8015a72: f7f9 f9f8 bl 800ee66 <lwip_htonl>
8015a76: 4602 mov r2, r0
8015a78: 8abb ldrh r3, [r7, #20]
8015a7a: 9303 str r3, [sp, #12]
8015a7c: 2314 movs r3, #20
8015a7e: 9302 str r3, [sp, #8]
8015a80: 8e3b ldrh r3, [r7, #48] ; 0x30
8015a82: 9301 str r3, [sp, #4]
8015a84: 8dbb ldrh r3, [r7, #44] ; 0x2c
8015a86: 9300 str r3, [sp, #0]
8015a88: 4613 mov r3, r2
8015a8a: 2200 movs r2, #0
8015a8c: 4621 mov r1, r4
8015a8e: 6878 ldr r0, [r7, #4]
8015a90: f7ff fe92 bl 80157b8 <tcp_output_alloc_header_common>
8015a94: 6138 str r0, [r7, #16]
remote_port, TCP_RST | TCP_ACK, wnd);
if (p == NULL) {
8015a96: 693b ldr r3, [r7, #16]
8015a98: 2b00 cmp r3, #0
8015a9a: d00c beq.n 8015ab6 <tcp_rst+0x8a>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
return;
}
tcp_output_fill_options(pcb, p, 0, optlen);
8015a9c: 7dfb ldrb r3, [r7, #23]
8015a9e: 2200 movs r2, #0
8015aa0: 6939 ldr r1, [r7, #16]
8015aa2: 68f8 ldr r0, [r7, #12]
8015aa4: f7ff ff38 bl 8015918 <tcp_output_fill_options>
MIB2_STATS_INC(mib2.tcpoutrsts);
tcp_output_control_segment(pcb, p, local_ip, remote_ip);
8015aa8: 6abb ldr r3, [r7, #40] ; 0x28
8015aaa: 683a ldr r2, [r7, #0]
8015aac: 6939 ldr r1, [r7, #16]
8015aae: 68f8 ldr r0, [r7, #12]
8015ab0: f7ff ff72 bl 8015998 <tcp_output_control_segment>
8015ab4: e000 b.n 8015ab8 <tcp_rst+0x8c>
return;
8015ab6: bf00 nop
LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
}
8015ab8: 371c adds r7, #28
8015aba: 46bd mov sp, r7
8015abc: bd90 pop {r4, r7, pc}
8015abe: bf00 nop
8015ac0: 0801d904 .word 0x0801d904
8015ac4: 0801e088 .word 0x0801e088
8015ac8: 0801d958 .word 0x0801d958
8015acc: 0801e0a4 .word 0x0801e0a4
08015ad0 <tcp_send_empty_ack>:
*
* @param pcb Protocol control block for the TCP connection to send the ACK
*/
err_t
tcp_send_empty_ack(struct tcp_pcb *pcb)
{
8015ad0: b590 push {r4, r7, lr}
8015ad2: b087 sub sp, #28
8015ad4: af00 add r7, sp, #0
8015ad6: 6078 str r0, [r7, #4]
err_t err;
struct pbuf *p;
u8_t optlen, optflags = 0;
8015ad8: 2300 movs r3, #0
8015ada: 75fb strb r3, [r7, #23]
u8_t num_sacks = 0;
8015adc: 2300 movs r3, #0
8015ade: 75bb strb r3, [r7, #22]
LWIP_ASSERT("tcp_send_empty_ack: invalid pcb", pcb != NULL);
8015ae0: 687b ldr r3, [r7, #4]
8015ae2: 2b00 cmp r3, #0
8015ae4: d106 bne.n 8015af4 <tcp_send_empty_ack+0x24>
8015ae6: 4b28 ldr r3, [pc, #160] ; (8015b88 <tcp_send_empty_ack+0xb8>)
8015ae8: f240 72ea movw r2, #2026 ; 0x7ea
8015aec: 4927 ldr r1, [pc, #156] ; (8015b8c <tcp_send_empty_ack+0xbc>)
8015aee: 4828 ldr r0, [pc, #160] ; (8015b90 <tcp_send_empty_ack+0xc0>)
8015af0: f005 fa68 bl 801afc4 <iprintf>
#if LWIP_TCP_TIMESTAMPS
if (pcb->flags & TF_TIMESTAMP) {
optflags = TF_SEG_OPTS_TS;
}
#endif
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
8015af4: 7dfb ldrb r3, [r7, #23]
8015af6: 009b lsls r3, r3, #2
8015af8: b2db uxtb r3, r3
8015afa: f003 0304 and.w r3, r3, #4
8015afe: 757b strb r3, [r7, #21]
if ((num_sacks = tcp_get_num_sacks(pcb, optlen)) > 0) {
optlen += 4 + num_sacks * 8; /* 4 bytes for header (including 2*NOP), plus 8B for each SACK */
}
#endif
p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt));
8015b00: 7d7b ldrb r3, [r7, #21]
8015b02: b29c uxth r4, r3
8015b04: 687b ldr r3, [r7, #4]
8015b06: 6d1b ldr r3, [r3, #80] ; 0x50
8015b08: 4618 mov r0, r3
8015b0a: f7f9 f9ac bl 800ee66 <lwip_htonl>
8015b0e: 4603 mov r3, r0
8015b10: 2200 movs r2, #0
8015b12: 4621 mov r1, r4
8015b14: 6878 ldr r0, [r7, #4]
8015b16: f7ff fec1 bl 801589c <tcp_output_alloc_header>
8015b1a: 6138 str r0, [r7, #16]
if (p == NULL) {
8015b1c: 693b ldr r3, [r7, #16]
8015b1e: 2b00 cmp r3, #0
8015b20: d109 bne.n 8015b36 <tcp_send_empty_ack+0x66>
/* let tcp_fasttmr retry sending this ACK */
tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8015b22: 687b ldr r3, [r7, #4]
8015b24: 8b5b ldrh r3, [r3, #26]
8015b26: f043 0303 orr.w r3, r3, #3
8015b2a: b29a uxth r2, r3
8015b2c: 687b ldr r3, [r7, #4]
8015b2e: 835a strh r2, [r3, #26]
LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
return ERR_BUF;
8015b30: f06f 0301 mvn.w r3, #1
8015b34: e023 b.n 8015b7e <tcp_send_empty_ack+0xae>
}
tcp_output_fill_options(pcb, p, optflags, num_sacks);
8015b36: 7dbb ldrb r3, [r7, #22]
8015b38: 7dfa ldrb r2, [r7, #23]
8015b3a: 6939 ldr r1, [r7, #16]
8015b3c: 6878 ldr r0, [r7, #4]
8015b3e: f7ff feeb bl 8015918 <tcp_output_fill_options>
pcb->ts_lastacksent = pcb->rcv_nxt;
#endif
LWIP_DEBUGF(TCP_OUTPUT_DEBUG,
("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
8015b42: 687a ldr r2, [r7, #4]
8015b44: 687b ldr r3, [r7, #4]
8015b46: 3304 adds r3, #4
8015b48: 6939 ldr r1, [r7, #16]
8015b4a: 6878 ldr r0, [r7, #4]
8015b4c: f7ff ff24 bl 8015998 <tcp_output_control_segment>
8015b50: 4603 mov r3, r0
8015b52: 73fb strb r3, [r7, #15]
if (err != ERR_OK) {
8015b54: f997 300f ldrsb.w r3, [r7, #15]
8015b58: 2b00 cmp r3, #0
8015b5a: d007 beq.n 8015b6c <tcp_send_empty_ack+0x9c>
/* let tcp_fasttmr retry sending this ACK */
tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8015b5c: 687b ldr r3, [r7, #4]
8015b5e: 8b5b ldrh r3, [r3, #26]
8015b60: f043 0303 orr.w r3, r3, #3
8015b64: b29a uxth r2, r3
8015b66: 687b ldr r3, [r7, #4]
8015b68: 835a strh r2, [r3, #26]
8015b6a: e006 b.n 8015b7a <tcp_send_empty_ack+0xaa>
} else {
/* remove ACK flags from the PCB, as we sent an empty ACK now */
tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8015b6c: 687b ldr r3, [r7, #4]
8015b6e: 8b5b ldrh r3, [r3, #26]
8015b70: f023 0303 bic.w r3, r3, #3
8015b74: b29a uxth r2, r3
8015b76: 687b ldr r3, [r7, #4]
8015b78: 835a strh r2, [r3, #26]
}
return err;
8015b7a: f997 300f ldrsb.w r3, [r7, #15]
}
8015b7e: 4618 mov r0, r3
8015b80: 371c adds r7, #28
8015b82: 46bd mov sp, r7
8015b84: bd90 pop {r4, r7, pc}
8015b86: bf00 nop
8015b88: 0801d904 .word 0x0801d904
8015b8c: 0801e0c0 .word 0x0801e0c0
8015b90: 0801d958 .word 0x0801d958
08015b94 <tcp_keepalive>:
*
* @param pcb the tcp_pcb for which to send a keepalive packet
*/
err_t
tcp_keepalive(struct tcp_pcb *pcb)
{
8015b94: b590 push {r4, r7, lr}
8015b96: b087 sub sp, #28
8015b98: af00 add r7, sp, #0
8015b9a: 6078 str r0, [r7, #4]
err_t err;
struct pbuf *p;
u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
8015b9c: 2300 movs r3, #0
8015b9e: 75fb strb r3, [r7, #23]
LWIP_ASSERT("tcp_keepalive: invalid pcb", pcb != NULL);
8015ba0: 687b ldr r3, [r7, #4]
8015ba2: 2b00 cmp r3, #0
8015ba4: d106 bne.n 8015bb4 <tcp_keepalive+0x20>
8015ba6: 4b18 ldr r3, [pc, #96] ; (8015c08 <tcp_keepalive+0x74>)
8015ba8: f640 0224 movw r2, #2084 ; 0x824
8015bac: 4917 ldr r1, [pc, #92] ; (8015c0c <tcp_keepalive+0x78>)
8015bae: 4818 ldr r0, [pc, #96] ; (8015c10 <tcp_keepalive+0x7c>)
8015bb0: f005 fa08 bl 801afc4 <iprintf>
LWIP_DEBUGF(TCP_DEBUG, ("\n"));
LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt - 1));
8015bb4: 7dfb ldrb r3, [r7, #23]
8015bb6: b29c uxth r4, r3
8015bb8: 687b ldr r3, [r7, #4]
8015bba: 6d1b ldr r3, [r3, #80] ; 0x50
8015bbc: 3b01 subs r3, #1
8015bbe: 4618 mov r0, r3
8015bc0: f7f9 f951 bl 800ee66 <lwip_htonl>
8015bc4: 4603 mov r3, r0
8015bc6: 2200 movs r2, #0
8015bc8: 4621 mov r1, r4
8015bca: 6878 ldr r0, [r7, #4]
8015bcc: f7ff fe66 bl 801589c <tcp_output_alloc_header>
8015bd0: 6138 str r0, [r7, #16]
if (p == NULL) {
8015bd2: 693b ldr r3, [r7, #16]
8015bd4: 2b00 cmp r3, #0
8015bd6: d102 bne.n 8015bde <tcp_keepalive+0x4a>
LWIP_DEBUGF(TCP_DEBUG,
("tcp_keepalive: could not allocate memory for pbuf\n"));
return ERR_MEM;
8015bd8: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8015bdc: e010 b.n 8015c00 <tcp_keepalive+0x6c>
}
tcp_output_fill_options(pcb, p, 0, optlen);
8015bde: 7dfb ldrb r3, [r7, #23]
8015be0: 2200 movs r2, #0
8015be2: 6939 ldr r1, [r7, #16]
8015be4: 6878 ldr r0, [r7, #4]
8015be6: f7ff fe97 bl 8015918 <tcp_output_fill_options>
err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
8015bea: 687a ldr r2, [r7, #4]
8015bec: 687b ldr r3, [r7, #4]
8015bee: 3304 adds r3, #4
8015bf0: 6939 ldr r1, [r7, #16]
8015bf2: 6878 ldr r0, [r7, #4]
8015bf4: f7ff fed0 bl 8015998 <tcp_output_control_segment>
8015bf8: 4603 mov r3, r0
8015bfa: 73fb strb r3, [r7, #15]
LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F" err %d.\n",
pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
return err;
8015bfc: f997 300f ldrsb.w r3, [r7, #15]
}
8015c00: 4618 mov r0, r3
8015c02: 371c adds r7, #28
8015c04: 46bd mov sp, r7
8015c06: bd90 pop {r4, r7, pc}
8015c08: 0801d904 .word 0x0801d904
8015c0c: 0801e0e0 .word 0x0801e0e0
8015c10: 0801d958 .word 0x0801d958
08015c14 <tcp_zero_window_probe>:
*
* @param pcb the tcp_pcb for which to send a zero-window probe packet
*/
err_t
tcp_zero_window_probe(struct tcp_pcb *pcb)
{
8015c14: b590 push {r4, r7, lr}
8015c16: b08b sub sp, #44 ; 0x2c
8015c18: af00 add r7, sp, #0
8015c1a: 6078 str r0, [r7, #4]
struct tcp_hdr *tcphdr;
struct tcp_seg *seg;
u16_t len;
u8_t is_fin;
u32_t snd_nxt;
u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
8015c1c: 2300 movs r3, #0
8015c1e: f887 3027 strb.w r3, [r7, #39] ; 0x27
LWIP_ASSERT("tcp_zero_window_probe: invalid pcb", pcb != NULL);
8015c22: 687b ldr r3, [r7, #4]
8015c24: 2b00 cmp r3, #0
8015c26: d106 bne.n 8015c36 <tcp_zero_window_probe+0x22>
8015c28: 4b4c ldr r3, [pc, #304] ; (8015d5c <tcp_zero_window_probe+0x148>)
8015c2a: f640 024f movw r2, #2127 ; 0x84f
8015c2e: 494c ldr r1, [pc, #304] ; (8015d60 <tcp_zero_window_probe+0x14c>)
8015c30: 484c ldr r0, [pc, #304] ; (8015d64 <tcp_zero_window_probe+0x150>)
8015c32: f005 f9c7 bl 801afc4 <iprintf>
("tcp_zero_window_probe: tcp_ticks %"U32_F
" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
/* Only consider unsent, persist timer should be off when there is data in-flight */
seg = pcb->unsent;
8015c36: 687b ldr r3, [r7, #4]
8015c38: 6edb ldr r3, [r3, #108] ; 0x6c
8015c3a: 623b str r3, [r7, #32]
if (seg == NULL) {
8015c3c: 6a3b ldr r3, [r7, #32]
8015c3e: 2b00 cmp r3, #0
8015c40: d101 bne.n 8015c46 <tcp_zero_window_probe+0x32>
/* Not expected, persist timer should be off when the send buffer is empty */
return ERR_OK;
8015c42: 2300 movs r3, #0
8015c44: e086 b.n 8015d54 <tcp_zero_window_probe+0x140>
/* increment probe count. NOTE: we record probe even if it fails
to actually transmit due to an error. This ensures memory exhaustion/
routing problem doesn't leave a zero-window pcb as an indefinite zombie.
RTO mechanism has similar behavior, see pcb->nrtx */
if (pcb->persist_probe < 0xFF) {
8015c46: 687b ldr r3, [r7, #4]
8015c48: f893 309a ldrb.w r3, [r3, #154] ; 0x9a
8015c4c: 2bff cmp r3, #255 ; 0xff
8015c4e: d007 beq.n 8015c60 <tcp_zero_window_probe+0x4c>
++pcb->persist_probe;
8015c50: 687b ldr r3, [r7, #4]
8015c52: f893 309a ldrb.w r3, [r3, #154] ; 0x9a
8015c56: 3301 adds r3, #1
8015c58: b2da uxtb r2, r3
8015c5a: 687b ldr r3, [r7, #4]
8015c5c: f883 209a strb.w r2, [r3, #154] ; 0x9a
}
is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0);
8015c60: 6a3b ldr r3, [r7, #32]
8015c62: 68db ldr r3, [r3, #12]
8015c64: 899b ldrh r3, [r3, #12]
8015c66: b29b uxth r3, r3
8015c68: 4618 mov r0, r3
8015c6a: f7f9 f8e7 bl 800ee3c <lwip_htons>
8015c6e: 4603 mov r3, r0
8015c70: b2db uxtb r3, r3
8015c72: f003 0301 and.w r3, r3, #1
8015c76: 2b00 cmp r3, #0
8015c78: d005 beq.n 8015c86 <tcp_zero_window_probe+0x72>
8015c7a: 6a3b ldr r3, [r7, #32]
8015c7c: 891b ldrh r3, [r3, #8]
8015c7e: 2b00 cmp r3, #0
8015c80: d101 bne.n 8015c86 <tcp_zero_window_probe+0x72>
8015c82: 2301 movs r3, #1
8015c84: e000 b.n 8015c88 <tcp_zero_window_probe+0x74>
8015c86: 2300 movs r3, #0
8015c88: 77fb strb r3, [r7, #31]
/* we want to send one seqno: either FIN or data (no options) */
len = is_fin ? 0 : 1;
8015c8a: 7ffb ldrb r3, [r7, #31]
8015c8c: 2b00 cmp r3, #0
8015c8e: bf0c ite eq
8015c90: 2301 moveq r3, #1
8015c92: 2300 movne r3, #0
8015c94: b2db uxtb r3, r3
8015c96: 83bb strh r3, [r7, #28]
p = tcp_output_alloc_header(pcb, optlen, len, seg->tcphdr->seqno);
8015c98: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8015c9c: b299 uxth r1, r3
8015c9e: 6a3b ldr r3, [r7, #32]
8015ca0: 68db ldr r3, [r3, #12]
8015ca2: 685b ldr r3, [r3, #4]
8015ca4: 8bba ldrh r2, [r7, #28]
8015ca6: 6878 ldr r0, [r7, #4]
8015ca8: f7ff fdf8 bl 801589c <tcp_output_alloc_header>
8015cac: 61b8 str r0, [r7, #24]
if (p == NULL) {
8015cae: 69bb ldr r3, [r7, #24]
8015cb0: 2b00 cmp r3, #0
8015cb2: d102 bne.n 8015cba <tcp_zero_window_probe+0xa6>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n"));
return ERR_MEM;
8015cb4: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8015cb8: e04c b.n 8015d54 <tcp_zero_window_probe+0x140>
}
tcphdr = (struct tcp_hdr *)p->payload;
8015cba: 69bb ldr r3, [r7, #24]
8015cbc: 685b ldr r3, [r3, #4]
8015cbe: 617b str r3, [r7, #20]
if (is_fin) {
8015cc0: 7ffb ldrb r3, [r7, #31]
8015cc2: 2b00 cmp r3, #0
8015cc4: d011 beq.n 8015cea <tcp_zero_window_probe+0xd6>
/* FIN segment, no data */
TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN);
8015cc6: 697b ldr r3, [r7, #20]
8015cc8: 899b ldrh r3, [r3, #12]
8015cca: b29b uxth r3, r3
8015ccc: b21b sxth r3, r3
8015cce: f423 537c bic.w r3, r3, #16128 ; 0x3f00
8015cd2: b21c sxth r4, r3
8015cd4: 2011 movs r0, #17
8015cd6: f7f9 f8b1 bl 800ee3c <lwip_htons>
8015cda: 4603 mov r3, r0
8015cdc: b21b sxth r3, r3
8015cde: 4323 orrs r3, r4
8015ce0: b21b sxth r3, r3
8015ce2: b29a uxth r2, r3
8015ce4: 697b ldr r3, [r7, #20]
8015ce6: 819a strh r2, [r3, #12]
8015ce8: e010 b.n 8015d0c <tcp_zero_window_probe+0xf8>
} else {
/* Data segment, copy in one byte from the head of the unacked queue */
char *d = ((char *)p->payload + TCP_HLEN);
8015cea: 69bb ldr r3, [r7, #24]
8015cec: 685b ldr r3, [r3, #4]
8015cee: 3314 adds r3, #20
8015cf0: 613b str r3, [r7, #16]
/* Depending on whether the segment has already been sent (unacked) or not
(unsent), seg->p->payload points to the IP header or TCP header.
Ensure we copy the first TCP data byte: */
pbuf_copy_partial(seg->p, d, 1, seg->p->tot_len - seg->len);
8015cf2: 6a3b ldr r3, [r7, #32]
8015cf4: 6858 ldr r0, [r3, #4]
8015cf6: 6a3b ldr r3, [r7, #32]
8015cf8: 685b ldr r3, [r3, #4]
8015cfa: 891a ldrh r2, [r3, #8]
8015cfc: 6a3b ldr r3, [r7, #32]
8015cfe: 891b ldrh r3, [r3, #8]
8015d00: 1ad3 subs r3, r2, r3
8015d02: b29b uxth r3, r3
8015d04: 2201 movs r2, #1
8015d06: 6939 ldr r1, [r7, #16]
8015d08: f7fa fe56 bl 80109b8 <pbuf_copy_partial>
}
/* The byte may be acknowledged without the window being opened. */
snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + 1;
8015d0c: 6a3b ldr r3, [r7, #32]
8015d0e: 68db ldr r3, [r3, #12]
8015d10: 685b ldr r3, [r3, #4]
8015d12: 4618 mov r0, r3
8015d14: f7f9 f8a7 bl 800ee66 <lwip_htonl>
8015d18: 4603 mov r3, r0
8015d1a: 3301 adds r3, #1
8015d1c: 60fb str r3, [r7, #12]
if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
8015d1e: 687b ldr r3, [r7, #4]
8015d20: 6d1a ldr r2, [r3, #80] ; 0x50
8015d22: 68fb ldr r3, [r7, #12]
8015d24: 1ad3 subs r3, r2, r3
8015d26: 2b00 cmp r3, #0
8015d28: da02 bge.n 8015d30 <tcp_zero_window_probe+0x11c>
pcb->snd_nxt = snd_nxt;
8015d2a: 687b ldr r3, [r7, #4]
8015d2c: 68fa ldr r2, [r7, #12]
8015d2e: 651a str r2, [r3, #80] ; 0x50
}
tcp_output_fill_options(pcb, p, 0, optlen);
8015d30: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8015d34: 2200 movs r2, #0
8015d36: 69b9 ldr r1, [r7, #24]
8015d38: 6878 ldr r0, [r7, #4]
8015d3a: f7ff fded bl 8015918 <tcp_output_fill_options>
err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
8015d3e: 687a ldr r2, [r7, #4]
8015d40: 687b ldr r3, [r7, #4]
8015d42: 3304 adds r3, #4
8015d44: 69b9 ldr r1, [r7, #24]
8015d46: 6878 ldr r0, [r7, #4]
8015d48: f7ff fe26 bl 8015998 <tcp_output_control_segment>
8015d4c: 4603 mov r3, r0
8015d4e: 72fb strb r3, [r7, #11]
LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F
" ackno %"U32_F" err %d.\n",
pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
return err;
8015d50: f997 300b ldrsb.w r3, [r7, #11]
}
8015d54: 4618 mov r0, r3
8015d56: 372c adds r7, #44 ; 0x2c
8015d58: 46bd mov sp, r7
8015d5a: bd90 pop {r4, r7, pc}
8015d5c: 0801d904 .word 0x0801d904
8015d60: 0801e0fc .word 0x0801e0fc
8015d64: 0801d958 .word 0x0801d958
08015d68 <tcpip_tcp_timer>:
*
* @param arg unused argument
*/
static void
tcpip_tcp_timer(void *arg)
{
8015d68: b580 push {r7, lr}
8015d6a: b082 sub sp, #8
8015d6c: af00 add r7, sp, #0
8015d6e: 6078 str r0, [r7, #4]
LWIP_UNUSED_ARG(arg);
/* call TCP timer handler */
tcp_tmr();
8015d70: f7fa ff10 bl 8010b94 <tcp_tmr>
/* timer still needed? */
if (tcp_active_pcbs || tcp_tw_pcbs) {
8015d74: 4b0a ldr r3, [pc, #40] ; (8015da0 <tcpip_tcp_timer+0x38>)
8015d76: 681b ldr r3, [r3, #0]
8015d78: 2b00 cmp r3, #0
8015d7a: d103 bne.n 8015d84 <tcpip_tcp_timer+0x1c>
8015d7c: 4b09 ldr r3, [pc, #36] ; (8015da4 <tcpip_tcp_timer+0x3c>)
8015d7e: 681b ldr r3, [r3, #0]
8015d80: 2b00 cmp r3, #0
8015d82: d005 beq.n 8015d90 <tcpip_tcp_timer+0x28>
/* restart timer */
sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
8015d84: 2200 movs r2, #0
8015d86: 4908 ldr r1, [pc, #32] ; (8015da8 <tcpip_tcp_timer+0x40>)
8015d88: 20fa movs r0, #250 ; 0xfa
8015d8a: f000 f8f3 bl 8015f74 <sys_timeout>
8015d8e: e003 b.n 8015d98 <tcpip_tcp_timer+0x30>
} else {
/* disable timer */
tcpip_tcp_timer_active = 0;
8015d90: 4b06 ldr r3, [pc, #24] ; (8015dac <tcpip_tcp_timer+0x44>)
8015d92: 2200 movs r2, #0
8015d94: 601a str r2, [r3, #0]
}
}
8015d96: bf00 nop
8015d98: bf00 nop
8015d9a: 3708 adds r7, #8
8015d9c: 46bd mov sp, r7
8015d9e: bd80 pop {r7, pc}
8015da0: 2000f83c .word 0x2000f83c
8015da4: 2000f84c .word 0x2000f84c
8015da8: 08015d69 .word 0x08015d69
8015dac: 2000875c .word 0x2000875c
08015db0 <tcp_timer_needed>:
* the reason is to have the TCP timer only running when
* there are active (or time-wait) PCBs.
*/
void
tcp_timer_needed(void)
{
8015db0: b580 push {r7, lr}
8015db2: af00 add r7, sp, #0
LWIP_ASSERT_CORE_LOCKED();
/* timer is off but needed again? */
if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
8015db4: 4b0a ldr r3, [pc, #40] ; (8015de0 <tcp_timer_needed+0x30>)
8015db6: 681b ldr r3, [r3, #0]
8015db8: 2b00 cmp r3, #0
8015dba: d10f bne.n 8015ddc <tcp_timer_needed+0x2c>
8015dbc: 4b09 ldr r3, [pc, #36] ; (8015de4 <tcp_timer_needed+0x34>)
8015dbe: 681b ldr r3, [r3, #0]
8015dc0: 2b00 cmp r3, #0
8015dc2: d103 bne.n 8015dcc <tcp_timer_needed+0x1c>
8015dc4: 4b08 ldr r3, [pc, #32] ; (8015de8 <tcp_timer_needed+0x38>)
8015dc6: 681b ldr r3, [r3, #0]
8015dc8: 2b00 cmp r3, #0
8015dca: d007 beq.n 8015ddc <tcp_timer_needed+0x2c>
/* enable and start timer */
tcpip_tcp_timer_active = 1;
8015dcc: 4b04 ldr r3, [pc, #16] ; (8015de0 <tcp_timer_needed+0x30>)
8015dce: 2201 movs r2, #1
8015dd0: 601a str r2, [r3, #0]
sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
8015dd2: 2200 movs r2, #0
8015dd4: 4905 ldr r1, [pc, #20] ; (8015dec <tcp_timer_needed+0x3c>)
8015dd6: 20fa movs r0, #250 ; 0xfa
8015dd8: f000 f8cc bl 8015f74 <sys_timeout>
}
}
8015ddc: bf00 nop
8015dde: bd80 pop {r7, pc}
8015de0: 2000875c .word 0x2000875c
8015de4: 2000f83c .word 0x2000f83c
8015de8: 2000f84c .word 0x2000f84c
8015dec: 08015d69 .word 0x08015d69
08015df0 <sys_timeout_abs>:
#if LWIP_DEBUG_TIMERNAMES
sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg, const char *handler_name)
#else /* LWIP_DEBUG_TIMERNAMES */
sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg)
#endif
{
8015df0: b580 push {r7, lr}
8015df2: b086 sub sp, #24
8015df4: af00 add r7, sp, #0
8015df6: 60f8 str r0, [r7, #12]
8015df8: 60b9 str r1, [r7, #8]
8015dfa: 607a str r2, [r7, #4]
struct sys_timeo *timeout, *t;
timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT);
8015dfc: 200a movs r0, #10
8015dfe: f7f9 fcd3 bl 800f7a8 <memp_malloc>
8015e02: 6138 str r0, [r7, #16]
if (timeout == NULL) {
8015e04: 693b ldr r3, [r7, #16]
8015e06: 2b00 cmp r3, #0
8015e08: d109 bne.n 8015e1e <sys_timeout_abs+0x2e>
LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL);
8015e0a: 693b ldr r3, [r7, #16]
8015e0c: 2b00 cmp r3, #0
8015e0e: d151 bne.n 8015eb4 <sys_timeout_abs+0xc4>
8015e10: 4b2a ldr r3, [pc, #168] ; (8015ebc <sys_timeout_abs+0xcc>)
8015e12: 22be movs r2, #190 ; 0xbe
8015e14: 492a ldr r1, [pc, #168] ; (8015ec0 <sys_timeout_abs+0xd0>)
8015e16: 482b ldr r0, [pc, #172] ; (8015ec4 <sys_timeout_abs+0xd4>)
8015e18: f005 f8d4 bl 801afc4 <iprintf>
return;
8015e1c: e04a b.n 8015eb4 <sys_timeout_abs+0xc4>
}
timeout->next = NULL;
8015e1e: 693b ldr r3, [r7, #16]
8015e20: 2200 movs r2, #0
8015e22: 601a str r2, [r3, #0]
timeout->h = handler;
8015e24: 693b ldr r3, [r7, #16]
8015e26: 68ba ldr r2, [r7, #8]
8015e28: 609a str r2, [r3, #8]
timeout->arg = arg;
8015e2a: 693b ldr r3, [r7, #16]
8015e2c: 687a ldr r2, [r7, #4]
8015e2e: 60da str r2, [r3, #12]
timeout->time = abs_time;
8015e30: 693b ldr r3, [r7, #16]
8015e32: 68fa ldr r2, [r7, #12]
8015e34: 605a str r2, [r3, #4]
timeout->handler_name = handler_name;
LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p abs_time=%"U32_F" handler=%s arg=%p\n",
(void *)timeout, abs_time, handler_name, (void *)arg));
#endif /* LWIP_DEBUG_TIMERNAMES */
if (next_timeout == NULL) {
8015e36: 4b24 ldr r3, [pc, #144] ; (8015ec8 <sys_timeout_abs+0xd8>)
8015e38: 681b ldr r3, [r3, #0]
8015e3a: 2b00 cmp r3, #0
8015e3c: d103 bne.n 8015e46 <sys_timeout_abs+0x56>
next_timeout = timeout;
8015e3e: 4a22 ldr r2, [pc, #136] ; (8015ec8 <sys_timeout_abs+0xd8>)
8015e40: 693b ldr r3, [r7, #16]
8015e42: 6013 str r3, [r2, #0]
return;
8015e44: e037 b.n 8015eb6 <sys_timeout_abs+0xc6>
}
if (TIME_LESS_THAN(timeout->time, next_timeout->time)) {
8015e46: 693b ldr r3, [r7, #16]
8015e48: 685a ldr r2, [r3, #4]
8015e4a: 4b1f ldr r3, [pc, #124] ; (8015ec8 <sys_timeout_abs+0xd8>)
8015e4c: 681b ldr r3, [r3, #0]
8015e4e: 685b ldr r3, [r3, #4]
8015e50: 1ad3 subs r3, r2, r3
8015e52: 0fdb lsrs r3, r3, #31
8015e54: f003 0301 and.w r3, r3, #1
8015e58: b2db uxtb r3, r3
8015e5a: 2b00 cmp r3, #0
8015e5c: d007 beq.n 8015e6e <sys_timeout_abs+0x7e>
timeout->next = next_timeout;
8015e5e: 4b1a ldr r3, [pc, #104] ; (8015ec8 <sys_timeout_abs+0xd8>)
8015e60: 681a ldr r2, [r3, #0]
8015e62: 693b ldr r3, [r7, #16]
8015e64: 601a str r2, [r3, #0]
next_timeout = timeout;
8015e66: 4a18 ldr r2, [pc, #96] ; (8015ec8 <sys_timeout_abs+0xd8>)
8015e68: 693b ldr r3, [r7, #16]
8015e6a: 6013 str r3, [r2, #0]
8015e6c: e023 b.n 8015eb6 <sys_timeout_abs+0xc6>
} else {
for (t = next_timeout; t != NULL; t = t->next) {
8015e6e: 4b16 ldr r3, [pc, #88] ; (8015ec8 <sys_timeout_abs+0xd8>)
8015e70: 681b ldr r3, [r3, #0]
8015e72: 617b str r3, [r7, #20]
8015e74: e01a b.n 8015eac <sys_timeout_abs+0xbc>
if ((t->next == NULL) || TIME_LESS_THAN(timeout->time, t->next->time)) {
8015e76: 697b ldr r3, [r7, #20]
8015e78: 681b ldr r3, [r3, #0]
8015e7a: 2b00 cmp r3, #0
8015e7c: d00b beq.n 8015e96 <sys_timeout_abs+0xa6>
8015e7e: 693b ldr r3, [r7, #16]
8015e80: 685a ldr r2, [r3, #4]
8015e82: 697b ldr r3, [r7, #20]
8015e84: 681b ldr r3, [r3, #0]
8015e86: 685b ldr r3, [r3, #4]
8015e88: 1ad3 subs r3, r2, r3
8015e8a: 0fdb lsrs r3, r3, #31
8015e8c: f003 0301 and.w r3, r3, #1
8015e90: b2db uxtb r3, r3
8015e92: 2b00 cmp r3, #0
8015e94: d007 beq.n 8015ea6 <sys_timeout_abs+0xb6>
timeout->next = t->next;
8015e96: 697b ldr r3, [r7, #20]
8015e98: 681a ldr r2, [r3, #0]
8015e9a: 693b ldr r3, [r7, #16]
8015e9c: 601a str r2, [r3, #0]
t->next = timeout;
8015e9e: 697b ldr r3, [r7, #20]
8015ea0: 693a ldr r2, [r7, #16]
8015ea2: 601a str r2, [r3, #0]
break;
8015ea4: e007 b.n 8015eb6 <sys_timeout_abs+0xc6>
for (t = next_timeout; t != NULL; t = t->next) {
8015ea6: 697b ldr r3, [r7, #20]
8015ea8: 681b ldr r3, [r3, #0]
8015eaa: 617b str r3, [r7, #20]
8015eac: 697b ldr r3, [r7, #20]
8015eae: 2b00 cmp r3, #0
8015eb0: d1e1 bne.n 8015e76 <sys_timeout_abs+0x86>
8015eb2: e000 b.n 8015eb6 <sys_timeout_abs+0xc6>
return;
8015eb4: bf00 nop
}
}
}
}
8015eb6: 3718 adds r7, #24
8015eb8: 46bd mov sp, r7
8015eba: bd80 pop {r7, pc}
8015ebc: 0801e120 .word 0x0801e120
8015ec0: 0801e154 .word 0x0801e154
8015ec4: 0801e194 .word 0x0801e194
8015ec8: 20008754 .word 0x20008754
08015ecc <lwip_cyclic_timer>:
#if !LWIP_TESTMODE
static
#endif
void
lwip_cyclic_timer(void *arg)
{
8015ecc: b580 push {r7, lr}
8015ece: b086 sub sp, #24
8015ed0: af00 add r7, sp, #0
8015ed2: 6078 str r0, [r7, #4]
u32_t now;
u32_t next_timeout_time;
const struct lwip_cyclic_timer *cyclic = (const struct lwip_cyclic_timer *)arg;
8015ed4: 687b ldr r3, [r7, #4]
8015ed6: 617b str r3, [r7, #20]
#if LWIP_DEBUG_TIMERNAMES
LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name));
#endif
cyclic->handler();
8015ed8: 697b ldr r3, [r7, #20]
8015eda: 685b ldr r3, [r3, #4]
8015edc: 4798 blx r3
now = sys_now();
8015ede: f7f5 fc0f bl 800b700 <sys_now>
8015ee2: 6138 str r0, [r7, #16]
next_timeout_time = (u32_t)(current_timeout_due_time + cyclic->interval_ms); /* overflow handled by TIME_LESS_THAN macro */
8015ee4: 697b ldr r3, [r7, #20]
8015ee6: 681a ldr r2, [r3, #0]
8015ee8: 4b0f ldr r3, [pc, #60] ; (8015f28 <lwip_cyclic_timer+0x5c>)
8015eea: 681b ldr r3, [r3, #0]
8015eec: 4413 add r3, r2
8015eee: 60fb str r3, [r7, #12]
if (TIME_LESS_THAN(next_timeout_time, now)) {
8015ef0: 68fa ldr r2, [r7, #12]
8015ef2: 693b ldr r3, [r7, #16]
8015ef4: 1ad3 subs r3, r2, r3
8015ef6: 0fdb lsrs r3, r3, #31
8015ef8: f003 0301 and.w r3, r3, #1
8015efc: b2db uxtb r3, r3
8015efe: 2b00 cmp r3, #0
8015f00: d009 beq.n 8015f16 <lwip_cyclic_timer+0x4a>
/* timer would immediately expire again -> "overload" -> restart without any correction */
#if LWIP_DEBUG_TIMERNAMES
sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg, cyclic->handler_name);
#else
sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg);
8015f02: 697b ldr r3, [r7, #20]
8015f04: 681a ldr r2, [r3, #0]
8015f06: 693b ldr r3, [r7, #16]
8015f08: 4413 add r3, r2
8015f0a: 687a ldr r2, [r7, #4]
8015f0c: 4907 ldr r1, [pc, #28] ; (8015f2c <lwip_cyclic_timer+0x60>)
8015f0e: 4618 mov r0, r3
8015f10: f7ff ff6e bl 8015df0 <sys_timeout_abs>
sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg, cyclic->handler_name);
#else
sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
#endif
}
}
8015f14: e004 b.n 8015f20 <lwip_cyclic_timer+0x54>
sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
8015f16: 687a ldr r2, [r7, #4]
8015f18: 4904 ldr r1, [pc, #16] ; (8015f2c <lwip_cyclic_timer+0x60>)
8015f1a: 68f8 ldr r0, [r7, #12]
8015f1c: f7ff ff68 bl 8015df0 <sys_timeout_abs>
}
8015f20: bf00 nop
8015f22: 3718 adds r7, #24
8015f24: 46bd mov sp, r7
8015f26: bd80 pop {r7, pc}
8015f28: 20008758 .word 0x20008758
8015f2c: 08015ecd .word 0x08015ecd
08015f30 <sys_timeouts_init>:
/** Initialize this module */
void sys_timeouts_init(void)
{
8015f30: b580 push {r7, lr}
8015f32: b082 sub sp, #8
8015f34: af00 add r7, sp, #0
size_t i;
/* tcp_tmr() at index 0 is started on demand */
for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
8015f36: 2301 movs r3, #1
8015f38: 607b str r3, [r7, #4]
8015f3a: e00e b.n 8015f5a <sys_timeouts_init+0x2a>
/* we have to cast via size_t to get rid of const warning
(this is OK as cyclic_timer() casts back to const* */
sys_timeout(lwip_cyclic_timers[i].interval_ms, lwip_cyclic_timer, LWIP_CONST_CAST(void *, &lwip_cyclic_timers[i]));
8015f3c: 4a0b ldr r2, [pc, #44] ; (8015f6c <sys_timeouts_init+0x3c>)
8015f3e: 687b ldr r3, [r7, #4]
8015f40: f852 0033 ldr.w r0, [r2, r3, lsl #3]
8015f44: 687b ldr r3, [r7, #4]
8015f46: 00db lsls r3, r3, #3
8015f48: 4a08 ldr r2, [pc, #32] ; (8015f6c <sys_timeouts_init+0x3c>)
8015f4a: 4413 add r3, r2
8015f4c: 461a mov r2, r3
8015f4e: 4908 ldr r1, [pc, #32] ; (8015f70 <sys_timeouts_init+0x40>)
8015f50: f000 f810 bl 8015f74 <sys_timeout>
for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
8015f54: 687b ldr r3, [r7, #4]
8015f56: 3301 adds r3, #1
8015f58: 607b str r3, [r7, #4]
8015f5a: 687b ldr r3, [r7, #4]
8015f5c: 2b04 cmp r3, #4
8015f5e: d9ed bls.n 8015f3c <sys_timeouts_init+0xc>
}
}
8015f60: bf00 nop
8015f62: bf00 nop
8015f64: 3708 adds r7, #8
8015f66: 46bd mov sp, r7
8015f68: bd80 pop {r7, pc}
8015f6a: bf00 nop
8015f6c: 08021014 .word 0x08021014
8015f70: 08015ecd .word 0x08015ecd
08015f74 <sys_timeout>:
sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char *handler_name)
#else /* LWIP_DEBUG_TIMERNAMES */
void
sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg)
#endif /* LWIP_DEBUG_TIMERNAMES */
{
8015f74: b580 push {r7, lr}
8015f76: b086 sub sp, #24
8015f78: af00 add r7, sp, #0
8015f7a: 60f8 str r0, [r7, #12]
8015f7c: 60b9 str r1, [r7, #8]
8015f7e: 607a str r2, [r7, #4]
u32_t next_timeout_time;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("Timeout time too long, max is LWIP_UINT32_MAX/4 msecs", msecs <= (LWIP_UINT32_MAX / 4));
8015f80: 68fb ldr r3, [r7, #12]
8015f82: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8015f86: d306 bcc.n 8015f96 <sys_timeout+0x22>
8015f88: 4b0a ldr r3, [pc, #40] ; (8015fb4 <sys_timeout+0x40>)
8015f8a: f240 1229 movw r2, #297 ; 0x129
8015f8e: 490a ldr r1, [pc, #40] ; (8015fb8 <sys_timeout+0x44>)
8015f90: 480a ldr r0, [pc, #40] ; (8015fbc <sys_timeout+0x48>)
8015f92: f005 f817 bl 801afc4 <iprintf>
next_timeout_time = (u32_t)(sys_now() + msecs); /* overflow handled by TIME_LESS_THAN macro */
8015f96: f7f5 fbb3 bl 800b700 <sys_now>
8015f9a: 4602 mov r2, r0
8015f9c: 68fb ldr r3, [r7, #12]
8015f9e: 4413 add r3, r2
8015fa0: 617b str r3, [r7, #20]
#if LWIP_DEBUG_TIMERNAMES
sys_timeout_abs(next_timeout_time, handler, arg, handler_name);
#else
sys_timeout_abs(next_timeout_time, handler, arg);
8015fa2: 687a ldr r2, [r7, #4]
8015fa4: 68b9 ldr r1, [r7, #8]
8015fa6: 6978 ldr r0, [r7, #20]
8015fa8: f7ff ff22 bl 8015df0 <sys_timeout_abs>
#endif
}
8015fac: bf00 nop
8015fae: 3718 adds r7, #24
8015fb0: 46bd mov sp, r7
8015fb2: bd80 pop {r7, pc}
8015fb4: 0801e120 .word 0x0801e120
8015fb8: 0801e1bc .word 0x0801e1bc
8015fbc: 0801e194 .word 0x0801e194
08015fc0 <sys_check_timeouts>:
*
* Must be called periodically from your main loop.
*/
void
sys_check_timeouts(void)
{
8015fc0: b580 push {r7, lr}
8015fc2: b084 sub sp, #16
8015fc4: af00 add r7, sp, #0
u32_t now;
LWIP_ASSERT_CORE_LOCKED();
/* Process only timers expired at the start of the function. */
now = sys_now();
8015fc6: f7f5 fb9b bl 800b700 <sys_now>
8015fca: 60f8 str r0, [r7, #12]
sys_timeout_handler handler;
void *arg;
PBUF_CHECK_FREE_OOSEQ();
tmptimeout = next_timeout;
8015fcc: 4b17 ldr r3, [pc, #92] ; (801602c <sys_check_timeouts+0x6c>)
8015fce: 681b ldr r3, [r3, #0]
8015fd0: 60bb str r3, [r7, #8]
if (tmptimeout == NULL) {
8015fd2: 68bb ldr r3, [r7, #8]
8015fd4: 2b00 cmp r3, #0
8015fd6: d022 beq.n 801601e <sys_check_timeouts+0x5e>
return;
}
if (TIME_LESS_THAN(now, tmptimeout->time)) {
8015fd8: 68bb ldr r3, [r7, #8]
8015fda: 685b ldr r3, [r3, #4]
8015fdc: 68fa ldr r2, [r7, #12]
8015fde: 1ad3 subs r3, r2, r3
8015fe0: 0fdb lsrs r3, r3, #31
8015fe2: f003 0301 and.w r3, r3, #1
8015fe6: b2db uxtb r3, r3
8015fe8: 2b00 cmp r3, #0
8015fea: d11a bne.n 8016022 <sys_check_timeouts+0x62>
return;
}
/* Timeout has expired */
next_timeout = tmptimeout->next;
8015fec: 68bb ldr r3, [r7, #8]
8015fee: 681b ldr r3, [r3, #0]
8015ff0: 4a0e ldr r2, [pc, #56] ; (801602c <sys_check_timeouts+0x6c>)
8015ff2: 6013 str r3, [r2, #0]
handler = tmptimeout->h;
8015ff4: 68bb ldr r3, [r7, #8]
8015ff6: 689b ldr r3, [r3, #8]
8015ff8: 607b str r3, [r7, #4]
arg = tmptimeout->arg;
8015ffa: 68bb ldr r3, [r7, #8]
8015ffc: 68db ldr r3, [r3, #12]
8015ffe: 603b str r3, [r7, #0]
current_timeout_due_time = tmptimeout->time;
8016000: 68bb ldr r3, [r7, #8]
8016002: 685b ldr r3, [r3, #4]
8016004: 4a0a ldr r2, [pc, #40] ; (8016030 <sys_check_timeouts+0x70>)
8016006: 6013 str r3, [r2, #0]
if (handler != NULL) {
LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s t=%"U32_F" arg=%p\n",
tmptimeout->handler_name, sys_now() - tmptimeout->time, arg));
}
#endif /* LWIP_DEBUG_TIMERNAMES */
memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
8016008: 68b9 ldr r1, [r7, #8]
801600a: 200a movs r0, #10
801600c: f7f9 fc1e bl 800f84c <memp_free>
if (handler != NULL) {
8016010: 687b ldr r3, [r7, #4]
8016012: 2b00 cmp r3, #0
8016014: d0da beq.n 8015fcc <sys_check_timeouts+0xc>
handler(arg);
8016016: 687b ldr r3, [r7, #4]
8016018: 6838 ldr r0, [r7, #0]
801601a: 4798 blx r3
do {
801601c: e7d6 b.n 8015fcc <sys_check_timeouts+0xc>
return;
801601e: bf00 nop
8016020: e000 b.n 8016024 <sys_check_timeouts+0x64>
return;
8016022: bf00 nop
}
LWIP_TCPIP_THREAD_ALIVE();
/* Repeat until all expired timers have been called */
} while (1);
}
8016024: 3710 adds r7, #16
8016026: 46bd mov sp, r7
8016028: bd80 pop {r7, pc}
801602a: bf00 nop
801602c: 20008754 .word 0x20008754
8016030: 20008758 .word 0x20008758
08016034 <sys_timeouts_sleeptime>:
/** Return the time left before the next timeout is due. If no timeouts are
* enqueued, returns 0xffffffff
*/
u32_t
sys_timeouts_sleeptime(void)
{
8016034: b580 push {r7, lr}
8016036: b082 sub sp, #8
8016038: af00 add r7, sp, #0
u32_t now;
LWIP_ASSERT_CORE_LOCKED();
if (next_timeout == NULL) {
801603a: 4b16 ldr r3, [pc, #88] ; (8016094 <sys_timeouts_sleeptime+0x60>)
801603c: 681b ldr r3, [r3, #0]
801603e: 2b00 cmp r3, #0
8016040: d102 bne.n 8016048 <sys_timeouts_sleeptime+0x14>
return SYS_TIMEOUTS_SLEEPTIME_INFINITE;
8016042: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8016046: e020 b.n 801608a <sys_timeouts_sleeptime+0x56>
}
now = sys_now();
8016048: f7f5 fb5a bl 800b700 <sys_now>
801604c: 6078 str r0, [r7, #4]
if (TIME_LESS_THAN(next_timeout->time, now)) {
801604e: 4b11 ldr r3, [pc, #68] ; (8016094 <sys_timeouts_sleeptime+0x60>)
8016050: 681b ldr r3, [r3, #0]
8016052: 685a ldr r2, [r3, #4]
8016054: 687b ldr r3, [r7, #4]
8016056: 1ad3 subs r3, r2, r3
8016058: 0fdb lsrs r3, r3, #31
801605a: f003 0301 and.w r3, r3, #1
801605e: b2db uxtb r3, r3
8016060: 2b00 cmp r3, #0
8016062: d001 beq.n 8016068 <sys_timeouts_sleeptime+0x34>
return 0;
8016064: 2300 movs r3, #0
8016066: e010 b.n 801608a <sys_timeouts_sleeptime+0x56>
} else {
u32_t ret = (u32_t)(next_timeout->time - now);
8016068: 4b0a ldr r3, [pc, #40] ; (8016094 <sys_timeouts_sleeptime+0x60>)
801606a: 681b ldr r3, [r3, #0]
801606c: 685a ldr r2, [r3, #4]
801606e: 687b ldr r3, [r7, #4]
8016070: 1ad3 subs r3, r2, r3
8016072: 603b str r3, [r7, #0]
LWIP_ASSERT("invalid sleeptime", ret <= LWIP_MAX_TIMEOUT);
8016074: 683b ldr r3, [r7, #0]
8016076: 2b00 cmp r3, #0
8016078: da06 bge.n 8016088 <sys_timeouts_sleeptime+0x54>
801607a: 4b07 ldr r3, [pc, #28] ; (8016098 <sys_timeouts_sleeptime+0x64>)
801607c: f44f 72dc mov.w r2, #440 ; 0x1b8
8016080: 4906 ldr r1, [pc, #24] ; (801609c <sys_timeouts_sleeptime+0x68>)
8016082: 4807 ldr r0, [pc, #28] ; (80160a0 <sys_timeouts_sleeptime+0x6c>)
8016084: f004 ff9e bl 801afc4 <iprintf>
return ret;
8016088: 683b ldr r3, [r7, #0]
}
}
801608a: 4618 mov r0, r3
801608c: 3708 adds r7, #8
801608e: 46bd mov sp, r7
8016090: bd80 pop {r7, pc}
8016092: bf00 nop
8016094: 20008754 .word 0x20008754
8016098: 0801e120 .word 0x0801e120
801609c: 0801e1f4 .word 0x0801e1f4
80160a0: 0801e194 .word 0x0801e194
080160a4 <udp_init>:
/**
* Initialize this module.
*/
void
udp_init(void)
{
80160a4: b580 push {r7, lr}
80160a6: af00 add r7, sp, #0
#ifdef LWIP_RAND
udp_port = UDP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
80160a8: f004 ffa4 bl 801aff4 <rand>
80160ac: 4603 mov r3, r0
80160ae: b29b uxth r3, r3
80160b0: f3c3 030d ubfx r3, r3, #0, #14
80160b4: b29b uxth r3, r3
80160b6: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000
80160ba: b29a uxth r2, r3
80160bc: 4b01 ldr r3, [pc, #4] ; (80160c4 <udp_init+0x20>)
80160be: 801a strh r2, [r3, #0]
#endif /* LWIP_RAND */
}
80160c0: bf00 nop
80160c2: bd80 pop {r7, pc}
80160c4: 20000070 .word 0x20000070
080160c8 <udp_new_port>:
*
* @return a new (free) local UDP port number
*/
static u16_t
udp_new_port(void)
{
80160c8: b480 push {r7}
80160ca: b083 sub sp, #12
80160cc: af00 add r7, sp, #0
u16_t n = 0;
80160ce: 2300 movs r3, #0
80160d0: 80fb strh r3, [r7, #6]
struct udp_pcb *pcb;
again:
if (udp_port++ == UDP_LOCAL_PORT_RANGE_END) {
80160d2: 4b17 ldr r3, [pc, #92] ; (8016130 <udp_new_port+0x68>)
80160d4: 881b ldrh r3, [r3, #0]
80160d6: 1c5a adds r2, r3, #1
80160d8: b291 uxth r1, r2
80160da: 4a15 ldr r2, [pc, #84] ; (8016130 <udp_new_port+0x68>)
80160dc: 8011 strh r1, [r2, #0]
80160de: f64f 72ff movw r2, #65535 ; 0xffff
80160e2: 4293 cmp r3, r2
80160e4: d103 bne.n 80160ee <udp_new_port+0x26>
udp_port = UDP_LOCAL_PORT_RANGE_START;
80160e6: 4b12 ldr r3, [pc, #72] ; (8016130 <udp_new_port+0x68>)
80160e8: f44f 4240 mov.w r2, #49152 ; 0xc000
80160ec: 801a strh r2, [r3, #0]
}
/* Check all PCBs. */
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
80160ee: 4b11 ldr r3, [pc, #68] ; (8016134 <udp_new_port+0x6c>)
80160f0: 681b ldr r3, [r3, #0]
80160f2: 603b str r3, [r7, #0]
80160f4: e011 b.n 801611a <udp_new_port+0x52>
if (pcb->local_port == udp_port) {
80160f6: 683b ldr r3, [r7, #0]
80160f8: 8a5a ldrh r2, [r3, #18]
80160fa: 4b0d ldr r3, [pc, #52] ; (8016130 <udp_new_port+0x68>)
80160fc: 881b ldrh r3, [r3, #0]
80160fe: 429a cmp r2, r3
8016100: d108 bne.n 8016114 <udp_new_port+0x4c>
if (++n > (UDP_LOCAL_PORT_RANGE_END - UDP_LOCAL_PORT_RANGE_START)) {
8016102: 88fb ldrh r3, [r7, #6]
8016104: 3301 adds r3, #1
8016106: 80fb strh r3, [r7, #6]
8016108: 88fb ldrh r3, [r7, #6]
801610a: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
801610e: d3e0 bcc.n 80160d2 <udp_new_port+0xa>
return 0;
8016110: 2300 movs r3, #0
8016112: e007 b.n 8016124 <udp_new_port+0x5c>
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
8016114: 683b ldr r3, [r7, #0]
8016116: 68db ldr r3, [r3, #12]
8016118: 603b str r3, [r7, #0]
801611a: 683b ldr r3, [r7, #0]
801611c: 2b00 cmp r3, #0
801611e: d1ea bne.n 80160f6 <udp_new_port+0x2e>
}
goto again;
}
}
return udp_port;
8016120: 4b03 ldr r3, [pc, #12] ; (8016130 <udp_new_port+0x68>)
8016122: 881b ldrh r3, [r3, #0]
}
8016124: 4618 mov r0, r3
8016126: 370c adds r7, #12
8016128: 46bd mov sp, r7
801612a: f85d 7b04 ldr.w r7, [sp], #4
801612e: 4770 bx lr
8016130: 20000070 .word 0x20000070
8016134: 2000f854 .word 0x2000f854
08016138 <udp_input_local_match>:
* @param broadcast 1 if his is an IPv4 broadcast (global or subnet-only), 0 otherwise (only used for IPv4)
* @return 1 on match, 0 otherwise
*/
static u8_t
udp_input_local_match(struct udp_pcb *pcb, struct netif *inp, u8_t broadcast)
{
8016138: b580 push {r7, lr}
801613a: b084 sub sp, #16
801613c: af00 add r7, sp, #0
801613e: 60f8 str r0, [r7, #12]
8016140: 60b9 str r1, [r7, #8]
8016142: 4613 mov r3, r2
8016144: 71fb strb r3, [r7, #7]
LWIP_UNUSED_ARG(inp); /* in IPv6 only case */
LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */
LWIP_ASSERT("udp_input_local_match: invalid pcb", pcb != NULL);
8016146: 68fb ldr r3, [r7, #12]
8016148: 2b00 cmp r3, #0
801614a: d105 bne.n 8016158 <udp_input_local_match+0x20>
801614c: 4b27 ldr r3, [pc, #156] ; (80161ec <udp_input_local_match+0xb4>)
801614e: 2287 movs r2, #135 ; 0x87
8016150: 4927 ldr r1, [pc, #156] ; (80161f0 <udp_input_local_match+0xb8>)
8016152: 4828 ldr r0, [pc, #160] ; (80161f4 <udp_input_local_match+0xbc>)
8016154: f004 ff36 bl 801afc4 <iprintf>
LWIP_ASSERT("udp_input_local_match: invalid netif", inp != NULL);
8016158: 68bb ldr r3, [r7, #8]
801615a: 2b00 cmp r3, #0
801615c: d105 bne.n 801616a <udp_input_local_match+0x32>
801615e: 4b23 ldr r3, [pc, #140] ; (80161ec <udp_input_local_match+0xb4>)
8016160: 2288 movs r2, #136 ; 0x88
8016162: 4925 ldr r1, [pc, #148] ; (80161f8 <udp_input_local_match+0xc0>)
8016164: 4823 ldr r0, [pc, #140] ; (80161f4 <udp_input_local_match+0xbc>)
8016166: f004 ff2d bl 801afc4 <iprintf>
/* check if PCB is bound to specific netif */
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
801616a: 68fb ldr r3, [r7, #12]
801616c: 7a1b ldrb r3, [r3, #8]
801616e: 2b00 cmp r3, #0
8016170: d00b beq.n 801618a <udp_input_local_match+0x52>
(pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
8016172: 68fb ldr r3, [r7, #12]
8016174: 7a1a ldrb r2, [r3, #8]
8016176: 4b21 ldr r3, [pc, #132] ; (80161fc <udp_input_local_match+0xc4>)
8016178: 685b ldr r3, [r3, #4]
801617a: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
801617e: 3301 adds r3, #1
8016180: b2db uxtb r3, r3
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
8016182: 429a cmp r2, r3
8016184: d001 beq.n 801618a <udp_input_local_match+0x52>
return 0;
8016186: 2300 movs r3, #0
8016188: e02b b.n 80161e2 <udp_input_local_match+0xaa>
/* Only need to check PCB if incoming IP version matches PCB IP version */
if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) {
#if LWIP_IPV4
/* Special case: IPv4 broadcast: all or broadcasts in my subnet
* Note: broadcast variable can only be 1 if it is an IPv4 broadcast */
if (broadcast != 0) {
801618a: 79fb ldrb r3, [r7, #7]
801618c: 2b00 cmp r3, #0
801618e: d018 beq.n 80161c2 <udp_input_local_match+0x8a>
#if IP_SOF_BROADCAST_RECV
if (ip_get_option(pcb, SOF_BROADCAST))
#endif /* IP_SOF_BROADCAST_RECV */
{
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
8016190: 68fb ldr r3, [r7, #12]
8016192: 2b00 cmp r3, #0
8016194: d013 beq.n 80161be <udp_input_local_match+0x86>
8016196: 68fb ldr r3, [r7, #12]
8016198: 681b ldr r3, [r3, #0]
801619a: 2b00 cmp r3, #0
801619c: d00f beq.n 80161be <udp_input_local_match+0x86>
((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
801619e: 4b17 ldr r3, [pc, #92] ; (80161fc <udp_input_local_match+0xc4>)
80161a0: 695b ldr r3, [r3, #20]
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
80161a2: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
80161a6: d00a beq.n 80161be <udp_input_local_match+0x86>
ip4_addr_netcmp(ip_2_ip4(&pcb->local_ip), ip4_current_dest_addr(), netif_ip4_netmask(inp))) {
80161a8: 68fb ldr r3, [r7, #12]
80161aa: 681a ldr r2, [r3, #0]
80161ac: 4b13 ldr r3, [pc, #76] ; (80161fc <udp_input_local_match+0xc4>)
80161ae: 695b ldr r3, [r3, #20]
80161b0: 405a eors r2, r3
80161b2: 68bb ldr r3, [r7, #8]
80161b4: 3308 adds r3, #8
80161b6: 681b ldr r3, [r3, #0]
80161b8: 4013 ands r3, r2
((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
80161ba: 2b00 cmp r3, #0
80161bc: d110 bne.n 80161e0 <udp_input_local_match+0xa8>
return 1;
80161be: 2301 movs r3, #1
80161c0: e00f b.n 80161e2 <udp_input_local_match+0xaa>
}
}
} else
#endif /* LWIP_IPV4 */
/* Handle IPv4 and IPv6: all or exact match */
if (ip_addr_isany(&pcb->local_ip) || ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
80161c2: 68fb ldr r3, [r7, #12]
80161c4: 2b00 cmp r3, #0
80161c6: d009 beq.n 80161dc <udp_input_local_match+0xa4>
80161c8: 68fb ldr r3, [r7, #12]
80161ca: 681b ldr r3, [r3, #0]
80161cc: 2b00 cmp r3, #0
80161ce: d005 beq.n 80161dc <udp_input_local_match+0xa4>
80161d0: 68fb ldr r3, [r7, #12]
80161d2: 681a ldr r2, [r3, #0]
80161d4: 4b09 ldr r3, [pc, #36] ; (80161fc <udp_input_local_match+0xc4>)
80161d6: 695b ldr r3, [r3, #20]
80161d8: 429a cmp r2, r3
80161da: d101 bne.n 80161e0 <udp_input_local_match+0xa8>
return 1;
80161dc: 2301 movs r3, #1
80161de: e000 b.n 80161e2 <udp_input_local_match+0xaa>
}
}
return 0;
80161e0: 2300 movs r3, #0
}
80161e2: 4618 mov r0, r3
80161e4: 3710 adds r7, #16
80161e6: 46bd mov sp, r7
80161e8: bd80 pop {r7, pc}
80161ea: bf00 nop
80161ec: 0801e208 .word 0x0801e208
80161f0: 0801e238 .word 0x0801e238
80161f4: 0801e25c .word 0x0801e25c
80161f8: 0801e284 .word 0x0801e284
80161fc: 2000c108 .word 0x2000c108
08016200 <udp_input>:
* @param inp network interface on which the datagram was received.
*
*/
void
udp_input(struct pbuf *p, struct netif *inp)
{
8016200: b590 push {r4, r7, lr}
8016202: b08d sub sp, #52 ; 0x34
8016204: af02 add r7, sp, #8
8016206: 6078 str r0, [r7, #4]
8016208: 6039 str r1, [r7, #0]
struct udp_hdr *udphdr;
struct udp_pcb *pcb, *prev;
struct udp_pcb *uncon_pcb;
u16_t src, dest;
u8_t broadcast;
u8_t for_us = 0;
801620a: 2300 movs r3, #0
801620c: 76fb strb r3, [r7, #27]
LWIP_UNUSED_ARG(inp);
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("udp_input: invalid pbuf", p != NULL);
801620e: 687b ldr r3, [r7, #4]
8016210: 2b00 cmp r3, #0
8016212: d105 bne.n 8016220 <udp_input+0x20>
8016214: 4b7c ldr r3, [pc, #496] ; (8016408 <udp_input+0x208>)
8016216: 22cf movs r2, #207 ; 0xcf
8016218: 497c ldr r1, [pc, #496] ; (801640c <udp_input+0x20c>)
801621a: 487d ldr r0, [pc, #500] ; (8016410 <udp_input+0x210>)
801621c: f004 fed2 bl 801afc4 <iprintf>
LWIP_ASSERT("udp_input: invalid netif", inp != NULL);
8016220: 683b ldr r3, [r7, #0]
8016222: 2b00 cmp r3, #0
8016224: d105 bne.n 8016232 <udp_input+0x32>
8016226: 4b78 ldr r3, [pc, #480] ; (8016408 <udp_input+0x208>)
8016228: 22d0 movs r2, #208 ; 0xd0
801622a: 497a ldr r1, [pc, #488] ; (8016414 <udp_input+0x214>)
801622c: 4878 ldr r0, [pc, #480] ; (8016410 <udp_input+0x210>)
801622e: f004 fec9 bl 801afc4 <iprintf>
PERF_START;
UDP_STATS_INC(udp.recv);
/* Check minimum length (UDP header) */
if (p->len < UDP_HLEN) {
8016232: 687b ldr r3, [r7, #4]
8016234: 895b ldrh r3, [r3, #10]
8016236: 2b07 cmp r3, #7
8016238: d803 bhi.n 8016242 <udp_input+0x42>
LWIP_DEBUGF(UDP_DEBUG,
("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
UDP_STATS_INC(udp.lenerr);
UDP_STATS_INC(udp.drop);
MIB2_STATS_INC(mib2.udpinerrors);
pbuf_free(p);
801623a: 6878 ldr r0, [r7, #4]
801623c: f7fa f9b6 bl 80105ac <pbuf_free>
goto end;
8016240: e0de b.n 8016400 <udp_input+0x200>
}
udphdr = (struct udp_hdr *)p->payload;
8016242: 687b ldr r3, [r7, #4]
8016244: 685b ldr r3, [r3, #4]
8016246: 617b str r3, [r7, #20]
/* is broadcast packet ? */
broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif());
8016248: 4b73 ldr r3, [pc, #460] ; (8016418 <udp_input+0x218>)
801624a: 695b ldr r3, [r3, #20]
801624c: 4a72 ldr r2, [pc, #456] ; (8016418 <udp_input+0x218>)
801624e: 6812 ldr r2, [r2, #0]
8016250: 4611 mov r1, r2
8016252: 4618 mov r0, r3
8016254: f003 fe08 bl 8019e68 <ip4_addr_isbroadcast_u32>
8016258: 4603 mov r3, r0
801625a: 74fb strb r3, [r7, #19]
LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
/* convert src and dest ports to host byte order */
src = lwip_ntohs(udphdr->src);
801625c: 697b ldr r3, [r7, #20]
801625e: 881b ldrh r3, [r3, #0]
8016260: b29b uxth r3, r3
8016262: 4618 mov r0, r3
8016264: f7f8 fdea bl 800ee3c <lwip_htons>
8016268: 4603 mov r3, r0
801626a: 823b strh r3, [r7, #16]
dest = lwip_ntohs(udphdr->dest);
801626c: 697b ldr r3, [r7, #20]
801626e: 885b ldrh r3, [r3, #2]
8016270: b29b uxth r3, r3
8016272: 4618 mov r0, r3
8016274: f7f8 fde2 bl 800ee3c <lwip_htons>
8016278: 4603 mov r3, r0
801627a: 81fb strh r3, [r7, #14]
ip_addr_debug_print_val(UDP_DEBUG, *ip_current_dest_addr());
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", lwip_ntohs(udphdr->dest)));
ip_addr_debug_print_val(UDP_DEBUG, *ip_current_src_addr());
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", lwip_ntohs(udphdr->src)));
pcb = NULL;
801627c: 2300 movs r3, #0
801627e: 627b str r3, [r7, #36] ; 0x24
prev = NULL;
8016280: 2300 movs r3, #0
8016282: 623b str r3, [r7, #32]
uncon_pcb = NULL;
8016284: 2300 movs r3, #0
8016286: 61fb str r3, [r7, #28]
/* Iterate through the UDP pcb list for a matching pcb.
* 'Perfect match' pcbs (connected to the remote port & ip address) are
* preferred. If no perfect match is found, the first unconnected pcb that
* matches the local port and ip address gets the datagram. */
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
8016288: 4b64 ldr r3, [pc, #400] ; (801641c <udp_input+0x21c>)
801628a: 681b ldr r3, [r3, #0]
801628c: 627b str r3, [r7, #36] ; 0x24
801628e: e054 b.n 801633a <udp_input+0x13a>
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", pcb->local_port));
ip_addr_debug_print_val(UDP_DEBUG, pcb->remote_ip);
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", pcb->remote_port));
/* compare PCB local addr+port to UDP destination addr+port */
if ((pcb->local_port == dest) &&
8016290: 6a7b ldr r3, [r7, #36] ; 0x24
8016292: 8a5b ldrh r3, [r3, #18]
8016294: 89fa ldrh r2, [r7, #14]
8016296: 429a cmp r2, r3
8016298: d14a bne.n 8016330 <udp_input+0x130>
(udp_input_local_match(pcb, inp, broadcast) != 0)) {
801629a: 7cfb ldrb r3, [r7, #19]
801629c: 461a mov r2, r3
801629e: 6839 ldr r1, [r7, #0]
80162a0: 6a78 ldr r0, [r7, #36] ; 0x24
80162a2: f7ff ff49 bl 8016138 <udp_input_local_match>
80162a6: 4603 mov r3, r0
if ((pcb->local_port == dest) &&
80162a8: 2b00 cmp r3, #0
80162aa: d041 beq.n 8016330 <udp_input+0x130>
if ((pcb->flags & UDP_FLAGS_CONNECTED) == 0) {
80162ac: 6a7b ldr r3, [r7, #36] ; 0x24
80162ae: 7c1b ldrb r3, [r3, #16]
80162b0: f003 0304 and.w r3, r3, #4
80162b4: 2b00 cmp r3, #0
80162b6: d11d bne.n 80162f4 <udp_input+0xf4>
if (uncon_pcb == NULL) {
80162b8: 69fb ldr r3, [r7, #28]
80162ba: 2b00 cmp r3, #0
80162bc: d102 bne.n 80162c4 <udp_input+0xc4>
/* the first unconnected matching PCB */
uncon_pcb = pcb;
80162be: 6a7b ldr r3, [r7, #36] ; 0x24
80162c0: 61fb str r3, [r7, #28]
80162c2: e017 b.n 80162f4 <udp_input+0xf4>
#if LWIP_IPV4
} else if (broadcast && ip4_current_dest_addr()->addr == IPADDR_BROADCAST) {
80162c4: 7cfb ldrb r3, [r7, #19]
80162c6: 2b00 cmp r3, #0
80162c8: d014 beq.n 80162f4 <udp_input+0xf4>
80162ca: 4b53 ldr r3, [pc, #332] ; (8016418 <udp_input+0x218>)
80162cc: 695b ldr r3, [r3, #20]
80162ce: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
80162d2: d10f bne.n 80162f4 <udp_input+0xf4>
/* global broadcast address (only valid for IPv4; match was checked before) */
if (!IP_IS_V4_VAL(uncon_pcb->local_ip) || !ip4_addr_cmp(ip_2_ip4(&uncon_pcb->local_ip), netif_ip4_addr(inp))) {
80162d4: 69fb ldr r3, [r7, #28]
80162d6: 681a ldr r2, [r3, #0]
80162d8: 683b ldr r3, [r7, #0]
80162da: 3304 adds r3, #4
80162dc: 681b ldr r3, [r3, #0]
80162de: 429a cmp r2, r3
80162e0: d008 beq.n 80162f4 <udp_input+0xf4>
/* uncon_pcb does not match the input netif, check this pcb */
if (IP_IS_V4_VAL(pcb->local_ip) && ip4_addr_cmp(ip_2_ip4(&pcb->local_ip), netif_ip4_addr(inp))) {
80162e2: 6a7b ldr r3, [r7, #36] ; 0x24
80162e4: 681a ldr r2, [r3, #0]
80162e6: 683b ldr r3, [r7, #0]
80162e8: 3304 adds r3, #4
80162ea: 681b ldr r3, [r3, #0]
80162ec: 429a cmp r2, r3
80162ee: d101 bne.n 80162f4 <udp_input+0xf4>
/* better match */
uncon_pcb = pcb;
80162f0: 6a7b ldr r3, [r7, #36] ; 0x24
80162f2: 61fb str r3, [r7, #28]
}
#endif /* SO_REUSE */
}
/* compare PCB remote addr+port to UDP source addr+port */
if ((pcb->remote_port == src) &&
80162f4: 6a7b ldr r3, [r7, #36] ; 0x24
80162f6: 8a9b ldrh r3, [r3, #20]
80162f8: 8a3a ldrh r2, [r7, #16]
80162fa: 429a cmp r2, r3
80162fc: d118 bne.n 8016330 <udp_input+0x130>
(ip_addr_isany_val(pcb->remote_ip) ||
80162fe: 6a7b ldr r3, [r7, #36] ; 0x24
8016300: 685b ldr r3, [r3, #4]
if ((pcb->remote_port == src) &&
8016302: 2b00 cmp r3, #0
8016304: d005 beq.n 8016312 <udp_input+0x112>
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) {
8016306: 6a7b ldr r3, [r7, #36] ; 0x24
8016308: 685a ldr r2, [r3, #4]
801630a: 4b43 ldr r3, [pc, #268] ; (8016418 <udp_input+0x218>)
801630c: 691b ldr r3, [r3, #16]
(ip_addr_isany_val(pcb->remote_ip) ||
801630e: 429a cmp r2, r3
8016310: d10e bne.n 8016330 <udp_input+0x130>
/* the first fully matching PCB */
if (prev != NULL) {
8016312: 6a3b ldr r3, [r7, #32]
8016314: 2b00 cmp r3, #0
8016316: d014 beq.n 8016342 <udp_input+0x142>
/* move the pcb to the front of udp_pcbs so that is
found faster next time */
prev->next = pcb->next;
8016318: 6a7b ldr r3, [r7, #36] ; 0x24
801631a: 68da ldr r2, [r3, #12]
801631c: 6a3b ldr r3, [r7, #32]
801631e: 60da str r2, [r3, #12]
pcb->next = udp_pcbs;
8016320: 4b3e ldr r3, [pc, #248] ; (801641c <udp_input+0x21c>)
8016322: 681a ldr r2, [r3, #0]
8016324: 6a7b ldr r3, [r7, #36] ; 0x24
8016326: 60da str r2, [r3, #12]
udp_pcbs = pcb;
8016328: 4a3c ldr r2, [pc, #240] ; (801641c <udp_input+0x21c>)
801632a: 6a7b ldr r3, [r7, #36] ; 0x24
801632c: 6013 str r3, [r2, #0]
} else {
UDP_STATS_INC(udp.cachehit);
}
break;
801632e: e008 b.n 8016342 <udp_input+0x142>
}
}
prev = pcb;
8016330: 6a7b ldr r3, [r7, #36] ; 0x24
8016332: 623b str r3, [r7, #32]
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
8016334: 6a7b ldr r3, [r7, #36] ; 0x24
8016336: 68db ldr r3, [r3, #12]
8016338: 627b str r3, [r7, #36] ; 0x24
801633a: 6a7b ldr r3, [r7, #36] ; 0x24
801633c: 2b00 cmp r3, #0
801633e: d1a7 bne.n 8016290 <udp_input+0x90>
8016340: e000 b.n 8016344 <udp_input+0x144>
break;
8016342: bf00 nop
}
/* no fully matching pcb found? then look for an unconnected pcb */
if (pcb == NULL) {
8016344: 6a7b ldr r3, [r7, #36] ; 0x24
8016346: 2b00 cmp r3, #0
8016348: d101 bne.n 801634e <udp_input+0x14e>
pcb = uncon_pcb;
801634a: 69fb ldr r3, [r7, #28]
801634c: 627b str r3, [r7, #36] ; 0x24
}
/* Check checksum if this is a match or if it was directed at us. */
if (pcb != NULL) {
801634e: 6a7b ldr r3, [r7, #36] ; 0x24
8016350: 2b00 cmp r3, #0
8016352: d002 beq.n 801635a <udp_input+0x15a>
for_us = 1;
8016354: 2301 movs r3, #1
8016356: 76fb strb r3, [r7, #27]
8016358: e00a b.n 8016370 <udp_input+0x170>
for_us = netif_get_ip6_addr_match(inp, ip6_current_dest_addr()) >= 0;
}
#endif /* LWIP_IPV6 */
#if LWIP_IPV4
if (!ip_current_is_v6()) {
for_us = ip4_addr_cmp(netif_ip4_addr(inp), ip4_current_dest_addr());
801635a: 683b ldr r3, [r7, #0]
801635c: 3304 adds r3, #4
801635e: 681a ldr r2, [r3, #0]
8016360: 4b2d ldr r3, [pc, #180] ; (8016418 <udp_input+0x218>)
8016362: 695b ldr r3, [r3, #20]
8016364: 429a cmp r2, r3
8016366: bf0c ite eq
8016368: 2301 moveq r3, #1
801636a: 2300 movne r3, #0
801636c: b2db uxtb r3, r3
801636e: 76fb strb r3, [r7, #27]
}
#endif /* LWIP_IPV4 */
}
if (for_us) {
8016370: 7efb ldrb r3, [r7, #27]
8016372: 2b00 cmp r3, #0
8016374: d041 beq.n 80163fa <udp_input+0x1fa>
}
}
}
}
#endif /* CHECKSUM_CHECK_UDP */
if (pbuf_remove_header(p, UDP_HLEN)) {
8016376: 2108 movs r1, #8
8016378: 6878 ldr r0, [r7, #4]
801637a: f7fa f891 bl 80104a0 <pbuf_remove_header>
801637e: 4603 mov r3, r0
8016380: 2b00 cmp r3, #0
8016382: d00a beq.n 801639a <udp_input+0x19a>
/* Can we cope with this failing? Just assert for now */
LWIP_ASSERT("pbuf_remove_header failed\n", 0);
8016384: 4b20 ldr r3, [pc, #128] ; (8016408 <udp_input+0x208>)
8016386: f44f 72b8 mov.w r2, #368 ; 0x170
801638a: 4925 ldr r1, [pc, #148] ; (8016420 <udp_input+0x220>)
801638c: 4820 ldr r0, [pc, #128] ; (8016410 <udp_input+0x210>)
801638e: f004 fe19 bl 801afc4 <iprintf>
UDP_STATS_INC(udp.drop);
MIB2_STATS_INC(mib2.udpinerrors);
pbuf_free(p);
8016392: 6878 ldr r0, [r7, #4]
8016394: f7fa f90a bl 80105ac <pbuf_free>
goto end;
8016398: e032 b.n 8016400 <udp_input+0x200>
}
if (pcb != NULL) {
801639a: 6a7b ldr r3, [r7, #36] ; 0x24
801639c: 2b00 cmp r3, #0
801639e: d012 beq.n 80163c6 <udp_input+0x1c6>
}
}
}
#endif /* SO_REUSE && SO_REUSE_RXTOALL */
/* callback */
if (pcb->recv != NULL) {
80163a0: 6a7b ldr r3, [r7, #36] ; 0x24
80163a2: 699b ldr r3, [r3, #24]
80163a4: 2b00 cmp r3, #0
80163a6: d00a beq.n 80163be <udp_input+0x1be>
/* now the recv function is responsible for freeing p */
pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src);
80163a8: 6a7b ldr r3, [r7, #36] ; 0x24
80163aa: 699c ldr r4, [r3, #24]
80163ac: 6a7b ldr r3, [r7, #36] ; 0x24
80163ae: 69d8 ldr r0, [r3, #28]
80163b0: 8a3b ldrh r3, [r7, #16]
80163b2: 9300 str r3, [sp, #0]
80163b4: 4b1b ldr r3, [pc, #108] ; (8016424 <udp_input+0x224>)
80163b6: 687a ldr r2, [r7, #4]
80163b8: 6a79 ldr r1, [r7, #36] ; 0x24
80163ba: 47a0 blx r4
} else {
pbuf_free(p);
}
end:
PERF_STOP("udp_input");
return;
80163bc: e021 b.n 8016402 <udp_input+0x202>
pbuf_free(p);
80163be: 6878 ldr r0, [r7, #4]
80163c0: f7fa f8f4 bl 80105ac <pbuf_free>
goto end;
80163c4: e01c b.n 8016400 <udp_input+0x200>
if (!broadcast && !ip_addr_ismulticast(ip_current_dest_addr())) {
80163c6: 7cfb ldrb r3, [r7, #19]
80163c8: 2b00 cmp r3, #0
80163ca: d112 bne.n 80163f2 <udp_input+0x1f2>
80163cc: 4b12 ldr r3, [pc, #72] ; (8016418 <udp_input+0x218>)
80163ce: 695b ldr r3, [r3, #20]
80163d0: f003 03f0 and.w r3, r3, #240 ; 0xf0
80163d4: 2be0 cmp r3, #224 ; 0xe0
80163d6: d00c beq.n 80163f2 <udp_input+0x1f2>
pbuf_header_force(p, (s16_t)(ip_current_header_tot_len() + UDP_HLEN));
80163d8: 4b0f ldr r3, [pc, #60] ; (8016418 <udp_input+0x218>)
80163da: 899b ldrh r3, [r3, #12]
80163dc: 3308 adds r3, #8
80163de: b29b uxth r3, r3
80163e0: b21b sxth r3, r3
80163e2: 4619 mov r1, r3
80163e4: 6878 ldr r0, [r7, #4]
80163e6: f7fa f8ce bl 8010586 <pbuf_header_force>
icmp_port_unreach(ip_current_is_v6(), p);
80163ea: 2103 movs r1, #3
80163ec: 6878 ldr r0, [r7, #4]
80163ee: f003 f9fd bl 80197ec <icmp_dest_unreach>
pbuf_free(p);
80163f2: 6878 ldr r0, [r7, #4]
80163f4: f7fa f8da bl 80105ac <pbuf_free>
return;
80163f8: e003 b.n 8016402 <udp_input+0x202>
pbuf_free(p);
80163fa: 6878 ldr r0, [r7, #4]
80163fc: f7fa f8d6 bl 80105ac <pbuf_free>
return;
8016400: bf00 nop
UDP_STATS_INC(udp.drop);
MIB2_STATS_INC(mib2.udpinerrors);
pbuf_free(p);
PERF_STOP("udp_input");
#endif /* CHECKSUM_CHECK_UDP */
}
8016402: 372c adds r7, #44 ; 0x2c
8016404: 46bd mov sp, r7
8016406: bd90 pop {r4, r7, pc}
8016408: 0801e208 .word 0x0801e208
801640c: 0801e2ac .word 0x0801e2ac
8016410: 0801e25c .word 0x0801e25c
8016414: 0801e2c4 .word 0x0801e2c4
8016418: 2000c108 .word 0x2000c108
801641c: 2000f854 .word 0x2000f854
8016420: 0801e2e0 .word 0x0801e2e0
8016424: 2000c118 .word 0x2000c118
08016428 <udp_sendto_if>:
* @see udp_disconnect() udp_send()
*/
err_t
udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p,
const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif)
{
8016428: b580 push {r7, lr}
801642a: b088 sub sp, #32
801642c: af02 add r7, sp, #8
801642e: 60f8 str r0, [r7, #12]
8016430: 60b9 str r1, [r7, #8]
8016432: 607a str r2, [r7, #4]
8016434: 807b strh r3, [r7, #2]
u16_t chksum)
{
#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
const ip_addr_t *src_ip;
LWIP_ERROR("udp_sendto_if: invalid pcb", pcb != NULL, return ERR_ARG);
8016436: 68fb ldr r3, [r7, #12]
8016438: 2b00 cmp r3, #0
801643a: d109 bne.n 8016450 <udp_sendto_if+0x28>
801643c: 4b2e ldr r3, [pc, #184] ; (80164f8 <udp_sendto_if+0xd0>)
801643e: f44f 7220 mov.w r2, #640 ; 0x280
8016442: 492e ldr r1, [pc, #184] ; (80164fc <udp_sendto_if+0xd4>)
8016444: 482e ldr r0, [pc, #184] ; (8016500 <udp_sendto_if+0xd8>)
8016446: f004 fdbd bl 801afc4 <iprintf>
801644a: f06f 030f mvn.w r3, #15
801644e: e04f b.n 80164f0 <udp_sendto_if+0xc8>
LWIP_ERROR("udp_sendto_if: invalid pbuf", p != NULL, return ERR_ARG);
8016450: 68bb ldr r3, [r7, #8]
8016452: 2b00 cmp r3, #0
8016454: d109 bne.n 801646a <udp_sendto_if+0x42>
8016456: 4b28 ldr r3, [pc, #160] ; (80164f8 <udp_sendto_if+0xd0>)
8016458: f240 2281 movw r2, #641 ; 0x281
801645c: 4929 ldr r1, [pc, #164] ; (8016504 <udp_sendto_if+0xdc>)
801645e: 4828 ldr r0, [pc, #160] ; (8016500 <udp_sendto_if+0xd8>)
8016460: f004 fdb0 bl 801afc4 <iprintf>
8016464: f06f 030f mvn.w r3, #15
8016468: e042 b.n 80164f0 <udp_sendto_if+0xc8>
LWIP_ERROR("udp_sendto_if: invalid dst_ip", dst_ip != NULL, return ERR_ARG);
801646a: 687b ldr r3, [r7, #4]
801646c: 2b00 cmp r3, #0
801646e: d109 bne.n 8016484 <udp_sendto_if+0x5c>
8016470: 4b21 ldr r3, [pc, #132] ; (80164f8 <udp_sendto_if+0xd0>)
8016472: f240 2282 movw r2, #642 ; 0x282
8016476: 4924 ldr r1, [pc, #144] ; (8016508 <udp_sendto_if+0xe0>)
8016478: 4821 ldr r0, [pc, #132] ; (8016500 <udp_sendto_if+0xd8>)
801647a: f004 fda3 bl 801afc4 <iprintf>
801647e: f06f 030f mvn.w r3, #15
8016482: e035 b.n 80164f0 <udp_sendto_if+0xc8>
LWIP_ERROR("udp_sendto_if: invalid netif", netif != NULL, return ERR_ARG);
8016484: 6a3b ldr r3, [r7, #32]
8016486: 2b00 cmp r3, #0
8016488: d109 bne.n 801649e <udp_sendto_if+0x76>
801648a: 4b1b ldr r3, [pc, #108] ; (80164f8 <udp_sendto_if+0xd0>)
801648c: f240 2283 movw r2, #643 ; 0x283
8016490: 491e ldr r1, [pc, #120] ; (801650c <udp_sendto_if+0xe4>)
8016492: 481b ldr r0, [pc, #108] ; (8016500 <udp_sendto_if+0xd8>)
8016494: f004 fd96 bl 801afc4 <iprintf>
8016498: f06f 030f mvn.w r3, #15
801649c: e028 b.n 80164f0 <udp_sendto_if+0xc8>
#endif /* LWIP_IPV6 */
#if LWIP_IPV4 && LWIP_IPV6
else
#endif /* LWIP_IPV4 && LWIP_IPV6 */
#if LWIP_IPV4
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
801649e: 68fb ldr r3, [r7, #12]
80164a0: 2b00 cmp r3, #0
80164a2: d009 beq.n 80164b8 <udp_sendto_if+0x90>
80164a4: 68fb ldr r3, [r7, #12]
80164a6: 681b ldr r3, [r3, #0]
80164a8: 2b00 cmp r3, #0
80164aa: d005 beq.n 80164b8 <udp_sendto_if+0x90>
ip4_addr_ismulticast(ip_2_ip4(&pcb->local_ip))) {
80164ac: 68fb ldr r3, [r7, #12]
80164ae: 681b ldr r3, [r3, #0]
80164b0: f003 03f0 and.w r3, r3, #240 ; 0xf0
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
80164b4: 2be0 cmp r3, #224 ; 0xe0
80164b6: d103 bne.n 80164c0 <udp_sendto_if+0x98>
/* if the local_ip is any or multicast
* use the outgoing network interface IP address as source address */
src_ip = netif_ip_addr4(netif);
80164b8: 6a3b ldr r3, [r7, #32]
80164ba: 3304 adds r3, #4
80164bc: 617b str r3, [r7, #20]
80164be: e00b b.n 80164d8 <udp_sendto_if+0xb0>
} else {
/* check if UDP PCB local IP address is correct
* this could be an old address if netif->ip_addr has changed */
if (!ip4_addr_cmp(ip_2_ip4(&(pcb->local_ip)), netif_ip4_addr(netif))) {
80164c0: 68fb ldr r3, [r7, #12]
80164c2: 681a ldr r2, [r3, #0]
80164c4: 6a3b ldr r3, [r7, #32]
80164c6: 3304 adds r3, #4
80164c8: 681b ldr r3, [r3, #0]
80164ca: 429a cmp r2, r3
80164cc: d002 beq.n 80164d4 <udp_sendto_if+0xac>
/* local_ip doesn't match, drop the packet */
return ERR_RTE;
80164ce: f06f 0303 mvn.w r3, #3
80164d2: e00d b.n 80164f0 <udp_sendto_if+0xc8>
}
/* use UDP PCB local IP address as source address */
src_ip = &pcb->local_ip;
80164d4: 68fb ldr r3, [r7, #12]
80164d6: 617b str r3, [r7, #20]
}
#endif /* LWIP_IPV4 */
#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
return udp_sendto_if_src_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum, src_ip);
#else /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
return udp_sendto_if_src(pcb, p, dst_ip, dst_port, netif, src_ip);
80164d8: 887a ldrh r2, [r7, #2]
80164da: 697b ldr r3, [r7, #20]
80164dc: 9301 str r3, [sp, #4]
80164de: 6a3b ldr r3, [r7, #32]
80164e0: 9300 str r3, [sp, #0]
80164e2: 4613 mov r3, r2
80164e4: 687a ldr r2, [r7, #4]
80164e6: 68b9 ldr r1, [r7, #8]
80164e8: 68f8 ldr r0, [r7, #12]
80164ea: f000 f811 bl 8016510 <udp_sendto_if_src>
80164ee: 4603 mov r3, r0
#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
}
80164f0: 4618 mov r0, r3
80164f2: 3718 adds r7, #24
80164f4: 46bd mov sp, r7
80164f6: bd80 pop {r7, pc}
80164f8: 0801e208 .word 0x0801e208
80164fc: 0801e37c .word 0x0801e37c
8016500: 0801e25c .word 0x0801e25c
8016504: 0801e398 .word 0x0801e398
8016508: 0801e3b4 .word 0x0801e3b4
801650c: 0801e3d4 .word 0x0801e3d4
08016510 <udp_sendto_if_src>:
/** @ingroup udp_raw
* Same as @ref udp_sendto_if, but with source address */
err_t
udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p,
const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif, const ip_addr_t *src_ip)
{
8016510: b580 push {r7, lr}
8016512: b08c sub sp, #48 ; 0x30
8016514: af04 add r7, sp, #16
8016516: 60f8 str r0, [r7, #12]
8016518: 60b9 str r1, [r7, #8]
801651a: 607a str r2, [r7, #4]
801651c: 807b strh r3, [r7, #2]
u8_t ip_proto;
u8_t ttl;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("udp_sendto_if_src: invalid pcb", pcb != NULL, return ERR_ARG);
801651e: 68fb ldr r3, [r7, #12]
8016520: 2b00 cmp r3, #0
8016522: d109 bne.n 8016538 <udp_sendto_if_src+0x28>
8016524: 4b65 ldr r3, [pc, #404] ; (80166bc <udp_sendto_if_src+0x1ac>)
8016526: f240 22d1 movw r2, #721 ; 0x2d1
801652a: 4965 ldr r1, [pc, #404] ; (80166c0 <udp_sendto_if_src+0x1b0>)
801652c: 4865 ldr r0, [pc, #404] ; (80166c4 <udp_sendto_if_src+0x1b4>)
801652e: f004 fd49 bl 801afc4 <iprintf>
8016532: f06f 030f mvn.w r3, #15
8016536: e0bc b.n 80166b2 <udp_sendto_if_src+0x1a2>
LWIP_ERROR("udp_sendto_if_src: invalid pbuf", p != NULL, return ERR_ARG);
8016538: 68bb ldr r3, [r7, #8]
801653a: 2b00 cmp r3, #0
801653c: d109 bne.n 8016552 <udp_sendto_if_src+0x42>
801653e: 4b5f ldr r3, [pc, #380] ; (80166bc <udp_sendto_if_src+0x1ac>)
8016540: f240 22d2 movw r2, #722 ; 0x2d2
8016544: 4960 ldr r1, [pc, #384] ; (80166c8 <udp_sendto_if_src+0x1b8>)
8016546: 485f ldr r0, [pc, #380] ; (80166c4 <udp_sendto_if_src+0x1b4>)
8016548: f004 fd3c bl 801afc4 <iprintf>
801654c: f06f 030f mvn.w r3, #15
8016550: e0af b.n 80166b2 <udp_sendto_if_src+0x1a2>
LWIP_ERROR("udp_sendto_if_src: invalid dst_ip", dst_ip != NULL, return ERR_ARG);
8016552: 687b ldr r3, [r7, #4]
8016554: 2b00 cmp r3, #0
8016556: d109 bne.n 801656c <udp_sendto_if_src+0x5c>
8016558: 4b58 ldr r3, [pc, #352] ; (80166bc <udp_sendto_if_src+0x1ac>)
801655a: f240 22d3 movw r2, #723 ; 0x2d3
801655e: 495b ldr r1, [pc, #364] ; (80166cc <udp_sendto_if_src+0x1bc>)
8016560: 4858 ldr r0, [pc, #352] ; (80166c4 <udp_sendto_if_src+0x1b4>)
8016562: f004 fd2f bl 801afc4 <iprintf>
8016566: f06f 030f mvn.w r3, #15
801656a: e0a2 b.n 80166b2 <udp_sendto_if_src+0x1a2>
LWIP_ERROR("udp_sendto_if_src: invalid src_ip", src_ip != NULL, return ERR_ARG);
801656c: 6afb ldr r3, [r7, #44] ; 0x2c
801656e: 2b00 cmp r3, #0
8016570: d109 bne.n 8016586 <udp_sendto_if_src+0x76>
8016572: 4b52 ldr r3, [pc, #328] ; (80166bc <udp_sendto_if_src+0x1ac>)
8016574: f44f 7235 mov.w r2, #724 ; 0x2d4
8016578: 4955 ldr r1, [pc, #340] ; (80166d0 <udp_sendto_if_src+0x1c0>)
801657a: 4852 ldr r0, [pc, #328] ; (80166c4 <udp_sendto_if_src+0x1b4>)
801657c: f004 fd22 bl 801afc4 <iprintf>
8016580: f06f 030f mvn.w r3, #15
8016584: e095 b.n 80166b2 <udp_sendto_if_src+0x1a2>
LWIP_ERROR("udp_sendto_if_src: invalid netif", netif != NULL, return ERR_ARG);
8016586: 6abb ldr r3, [r7, #40] ; 0x28
8016588: 2b00 cmp r3, #0
801658a: d109 bne.n 80165a0 <udp_sendto_if_src+0x90>
801658c: 4b4b ldr r3, [pc, #300] ; (80166bc <udp_sendto_if_src+0x1ac>)
801658e: f240 22d5 movw r2, #725 ; 0x2d5
8016592: 4950 ldr r1, [pc, #320] ; (80166d4 <udp_sendto_if_src+0x1c4>)
8016594: 484b ldr r0, [pc, #300] ; (80166c4 <udp_sendto_if_src+0x1b4>)
8016596: f004 fd15 bl 801afc4 <iprintf>
801659a: f06f 030f mvn.w r3, #15
801659e: e088 b.n 80166b2 <udp_sendto_if_src+0x1a2>
return ERR_VAL;
}
#endif /* LWIP_IPV4 && IP_SOF_BROADCAST */
/* if the PCB is not yet bound to a port, bind it here */
if (pcb->local_port == 0) {
80165a0: 68fb ldr r3, [r7, #12]
80165a2: 8a5b ldrh r3, [r3, #18]
80165a4: 2b00 cmp r3, #0
80165a6: d10f bne.n 80165c8 <udp_sendto_if_src+0xb8>
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n"));
err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
80165a8: 68f9 ldr r1, [r7, #12]
80165aa: 68fb ldr r3, [r7, #12]
80165ac: 8a5b ldrh r3, [r3, #18]
80165ae: 461a mov r2, r3
80165b0: 68f8 ldr r0, [r7, #12]
80165b2: f000 f893 bl 80166dc <udp_bind>
80165b6: 4603 mov r3, r0
80165b8: 76fb strb r3, [r7, #27]
if (err != ERR_OK) {
80165ba: f997 301b ldrsb.w r3, [r7, #27]
80165be: 2b00 cmp r3, #0
80165c0: d002 beq.n 80165c8 <udp_sendto_if_src+0xb8>
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n"));
return err;
80165c2: f997 301b ldrsb.w r3, [r7, #27]
80165c6: e074 b.n 80166b2 <udp_sendto_if_src+0x1a2>
}
}
/* packet too large to add a UDP header without causing an overflow? */
if ((u16_t)(p->tot_len + UDP_HLEN) < p->tot_len) {
80165c8: 68bb ldr r3, [r7, #8]
80165ca: 891b ldrh r3, [r3, #8]
80165cc: f64f 72f7 movw r2, #65527 ; 0xfff7
80165d0: 4293 cmp r3, r2
80165d2: d902 bls.n 80165da <udp_sendto_if_src+0xca>
return ERR_MEM;
80165d4: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
80165d8: e06b b.n 80166b2 <udp_sendto_if_src+0x1a2>
}
/* not enough space to add an UDP header to first pbuf in given p chain? */
if (pbuf_add_header(p, UDP_HLEN)) {
80165da: 2108 movs r1, #8
80165dc: 68b8 ldr r0, [r7, #8]
80165de: f7f9 ff4f bl 8010480 <pbuf_add_header>
80165e2: 4603 mov r3, r0
80165e4: 2b00 cmp r3, #0
80165e6: d015 beq.n 8016614 <udp_sendto_if_src+0x104>
/* allocate header in a separate new pbuf */
q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
80165e8: f44f 7220 mov.w r2, #640 ; 0x280
80165ec: 2108 movs r1, #8
80165ee: 2022 movs r0, #34 ; 0x22
80165f0: f7f9 fcf8 bl 800ffe4 <pbuf_alloc>
80165f4: 61f8 str r0, [r7, #28]
/* new header pbuf could not be allocated? */
if (q == NULL) {
80165f6: 69fb ldr r3, [r7, #28]
80165f8: 2b00 cmp r3, #0
80165fa: d102 bne.n 8016602 <udp_sendto_if_src+0xf2>
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n"));
return ERR_MEM;
80165fc: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8016600: e057 b.n 80166b2 <udp_sendto_if_src+0x1a2>
}
if (p->tot_len != 0) {
8016602: 68bb ldr r3, [r7, #8]
8016604: 891b ldrh r3, [r3, #8]
8016606: 2b00 cmp r3, #0
8016608: d006 beq.n 8016618 <udp_sendto_if_src+0x108>
/* chain header q in front of given pbuf p (only if p contains data) */
pbuf_chain(q, p);
801660a: 68b9 ldr r1, [r7, #8]
801660c: 69f8 ldr r0, [r7, #28]
801660e: f7fa f8f1 bl 80107f4 <pbuf_chain>
8016612: e001 b.n 8016618 <udp_sendto_if_src+0x108>
LWIP_DEBUGF(UDP_DEBUG,
("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
} else {
/* adding space for header within p succeeded */
/* first pbuf q equals given pbuf */
q = p;
8016614: 68bb ldr r3, [r7, #8]
8016616: 61fb str r3, [r7, #28]
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
}
LWIP_ASSERT("check that first pbuf can hold struct udp_hdr",
8016618: 69fb ldr r3, [r7, #28]
801661a: 895b ldrh r3, [r3, #10]
801661c: 2b07 cmp r3, #7
801661e: d806 bhi.n 801662e <udp_sendto_if_src+0x11e>
8016620: 4b26 ldr r3, [pc, #152] ; (80166bc <udp_sendto_if_src+0x1ac>)
8016622: f240 320d movw r2, #781 ; 0x30d
8016626: 492c ldr r1, [pc, #176] ; (80166d8 <udp_sendto_if_src+0x1c8>)
8016628: 4826 ldr r0, [pc, #152] ; (80166c4 <udp_sendto_if_src+0x1b4>)
801662a: f004 fccb bl 801afc4 <iprintf>
(q->len >= sizeof(struct udp_hdr)));
/* q now represents the packet to be sent */
udphdr = (struct udp_hdr *)q->payload;
801662e: 69fb ldr r3, [r7, #28]
8016630: 685b ldr r3, [r3, #4]
8016632: 617b str r3, [r7, #20]
udphdr->src = lwip_htons(pcb->local_port);
8016634: 68fb ldr r3, [r7, #12]
8016636: 8a5b ldrh r3, [r3, #18]
8016638: 4618 mov r0, r3
801663a: f7f8 fbff bl 800ee3c <lwip_htons>
801663e: 4603 mov r3, r0
8016640: 461a mov r2, r3
8016642: 697b ldr r3, [r7, #20]
8016644: 801a strh r2, [r3, #0]
udphdr->dest = lwip_htons(dst_port);
8016646: 887b ldrh r3, [r7, #2]
8016648: 4618 mov r0, r3
801664a: f7f8 fbf7 bl 800ee3c <lwip_htons>
801664e: 4603 mov r3, r0
8016650: 461a mov r2, r3
8016652: 697b ldr r3, [r7, #20]
8016654: 805a strh r2, [r3, #2]
/* in UDP, 0 checksum means 'no checksum' */
udphdr->chksum = 0x0000;
8016656: 697b ldr r3, [r7, #20]
8016658: 2200 movs r2, #0
801665a: 719a strb r2, [r3, #6]
801665c: 2200 movs r2, #0
801665e: 71da strb r2, [r3, #7]
ip_proto = IP_PROTO_UDPLITE;
} else
#endif /* LWIP_UDPLITE */
{ /* UDP */
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len));
udphdr->len = lwip_htons(q->tot_len);
8016660: 69fb ldr r3, [r7, #28]
8016662: 891b ldrh r3, [r3, #8]
8016664: 4618 mov r0, r3
8016666: f7f8 fbe9 bl 800ee3c <lwip_htons>
801666a: 4603 mov r3, r0
801666c: 461a mov r2, r3
801666e: 697b ldr r3, [r7, #20]
8016670: 809a strh r2, [r3, #4]
}
udphdr->chksum = udpchksum;
}
}
#endif /* CHECKSUM_GEN_UDP */
ip_proto = IP_PROTO_UDP;
8016672: 2311 movs r3, #17
8016674: 74fb strb r3, [r7, #19]
/* Determine TTL to use */
#if LWIP_MULTICAST_TX_OPTIONS
ttl = (ip_addr_ismulticast(dst_ip) ? udp_get_multicast_ttl(pcb) : pcb->ttl);
#else /* LWIP_MULTICAST_TX_OPTIONS */
ttl = pcb->ttl;
8016676: 68fb ldr r3, [r7, #12]
8016678: 7adb ldrb r3, [r3, #11]
801667a: 74bb strb r3, [r7, #18]
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum));
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,0x%02"X16_F",)\n", (u16_t)ip_proto));
/* output to IP */
NETIF_SET_HINTS(netif, &(pcb->netif_hints));
err = ip_output_if_src(q, src_ip, dst_ip, ttl, pcb->tos, ip_proto, netif);
801667c: 68fb ldr r3, [r7, #12]
801667e: 7a9b ldrb r3, [r3, #10]
8016680: 7cb9 ldrb r1, [r7, #18]
8016682: 6aba ldr r2, [r7, #40] ; 0x28
8016684: 9202 str r2, [sp, #8]
8016686: 7cfa ldrb r2, [r7, #19]
8016688: 9201 str r2, [sp, #4]
801668a: 9300 str r3, [sp, #0]
801668c: 460b mov r3, r1
801668e: 687a ldr r2, [r7, #4]
8016690: 6af9 ldr r1, [r7, #44] ; 0x2c
8016692: 69f8 ldr r0, [r7, #28]
8016694: f003 fb3a bl 8019d0c <ip4_output_if_src>
8016698: 4603 mov r3, r0
801669a: 76fb strb r3, [r7, #27]
/* @todo: must this be increased even if error occurred? */
MIB2_STATS_INC(mib2.udpoutdatagrams);
/* did we chain a separate header pbuf earlier? */
if (q != p) {
801669c: 69fa ldr r2, [r7, #28]
801669e: 68bb ldr r3, [r7, #8]
80166a0: 429a cmp r2, r3
80166a2: d004 beq.n 80166ae <udp_sendto_if_src+0x19e>
/* free the header pbuf */
pbuf_free(q);
80166a4: 69f8 ldr r0, [r7, #28]
80166a6: f7f9 ff81 bl 80105ac <pbuf_free>
q = NULL;
80166aa: 2300 movs r3, #0
80166ac: 61fb str r3, [r7, #28]
/* p is still referenced by the caller, and will live on */
}
UDP_STATS_INC(udp.xmit);
return err;
80166ae: f997 301b ldrsb.w r3, [r7, #27]
}
80166b2: 4618 mov r0, r3
80166b4: 3720 adds r7, #32
80166b6: 46bd mov sp, r7
80166b8: bd80 pop {r7, pc}
80166ba: bf00 nop
80166bc: 0801e208 .word 0x0801e208
80166c0: 0801e3f4 .word 0x0801e3f4
80166c4: 0801e25c .word 0x0801e25c
80166c8: 0801e414 .word 0x0801e414
80166cc: 0801e434 .word 0x0801e434
80166d0: 0801e458 .word 0x0801e458
80166d4: 0801e47c .word 0x0801e47c
80166d8: 0801e4a0 .word 0x0801e4a0
080166dc <udp_bind>:
*
* @see udp_disconnect()
*/
err_t
udp_bind(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
{
80166dc: b580 push {r7, lr}
80166de: b086 sub sp, #24
80166e0: af00 add r7, sp, #0
80166e2: 60f8 str r0, [r7, #12]
80166e4: 60b9 str r1, [r7, #8]
80166e6: 4613 mov r3, r2
80166e8: 80fb strh r3, [r7, #6]
LWIP_ASSERT_CORE_LOCKED();
#if LWIP_IPV4
/* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
if (ipaddr == NULL) {
80166ea: 68bb ldr r3, [r7, #8]
80166ec: 2b00 cmp r3, #0
80166ee: d101 bne.n 80166f4 <udp_bind+0x18>
ipaddr = IP4_ADDR_ANY;
80166f0: 4b39 ldr r3, [pc, #228] ; (80167d8 <udp_bind+0xfc>)
80166f2: 60bb str r3, [r7, #8]
}
#else /* LWIP_IPV4 */
LWIP_ERROR("udp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
#endif /* LWIP_IPV4 */
LWIP_ERROR("udp_bind: invalid pcb", pcb != NULL, return ERR_ARG);
80166f4: 68fb ldr r3, [r7, #12]
80166f6: 2b00 cmp r3, #0
80166f8: d109 bne.n 801670e <udp_bind+0x32>
80166fa: 4b38 ldr r3, [pc, #224] ; (80167dc <udp_bind+0x100>)
80166fc: f240 32b7 movw r2, #951 ; 0x3b7
8016700: 4937 ldr r1, [pc, #220] ; (80167e0 <udp_bind+0x104>)
8016702: 4838 ldr r0, [pc, #224] ; (80167e4 <udp_bind+0x108>)
8016704: f004 fc5e bl 801afc4 <iprintf>
8016708: f06f 030f mvn.w r3, #15
801670c: e060 b.n 80167d0 <udp_bind+0xf4>
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = "));
ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_TRACE, ipaddr);
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port));
rebind = 0;
801670e: 2300 movs r3, #0
8016710: 74fb strb r3, [r7, #19]
/* Check for double bind and rebind of the same pcb */
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
8016712: 4b35 ldr r3, [pc, #212] ; (80167e8 <udp_bind+0x10c>)
8016714: 681b ldr r3, [r3, #0]
8016716: 617b str r3, [r7, #20]
8016718: e009 b.n 801672e <udp_bind+0x52>
/* is this UDP PCB already on active list? */
if (pcb == ipcb) {
801671a: 68fa ldr r2, [r7, #12]
801671c: 697b ldr r3, [r7, #20]
801671e: 429a cmp r2, r3
8016720: d102 bne.n 8016728 <udp_bind+0x4c>
rebind = 1;
8016722: 2301 movs r3, #1
8016724: 74fb strb r3, [r7, #19]
break;
8016726: e005 b.n 8016734 <udp_bind+0x58>
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
8016728: 697b ldr r3, [r7, #20]
801672a: 68db ldr r3, [r3, #12]
801672c: 617b str r3, [r7, #20]
801672e: 697b ldr r3, [r7, #20]
8016730: 2b00 cmp r3, #0
8016732: d1f2 bne.n 801671a <udp_bind+0x3e>
ipaddr = &zoned_ipaddr;
}
#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
/* no port specified? */
if (port == 0) {
8016734: 88fb ldrh r3, [r7, #6]
8016736: 2b00 cmp r3, #0
8016738: d109 bne.n 801674e <udp_bind+0x72>
port = udp_new_port();
801673a: f7ff fcc5 bl 80160c8 <udp_new_port>
801673e: 4603 mov r3, r0
8016740: 80fb strh r3, [r7, #6]
if (port == 0) {
8016742: 88fb ldrh r3, [r7, #6]
8016744: 2b00 cmp r3, #0
8016746: d12c bne.n 80167a2 <udp_bind+0xc6>
/* no more ports available in local range */
LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
return ERR_USE;
8016748: f06f 0307 mvn.w r3, #7
801674c: e040 b.n 80167d0 <udp_bind+0xf4>
}
} else {
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
801674e: 4b26 ldr r3, [pc, #152] ; (80167e8 <udp_bind+0x10c>)
8016750: 681b ldr r3, [r3, #0]
8016752: 617b str r3, [r7, #20]
8016754: e022 b.n 801679c <udp_bind+0xc0>
if (pcb != ipcb) {
8016756: 68fa ldr r2, [r7, #12]
8016758: 697b ldr r3, [r7, #20]
801675a: 429a cmp r2, r3
801675c: d01b beq.n 8016796 <udp_bind+0xba>
if (!ip_get_option(pcb, SOF_REUSEADDR) ||
!ip_get_option(ipcb, SOF_REUSEADDR))
#endif /* SO_REUSE */
{
/* port matches that of PCB in list and REUSEADDR not set -> reject */
if ((ipcb->local_port == port) &&
801675e: 697b ldr r3, [r7, #20]
8016760: 8a5b ldrh r3, [r3, #18]
8016762: 88fa ldrh r2, [r7, #6]
8016764: 429a cmp r2, r3
8016766: d116 bne.n 8016796 <udp_bind+0xba>
/* IP address matches or any IP used? */
(ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
8016768: 697b ldr r3, [r7, #20]
801676a: 681a ldr r2, [r3, #0]
801676c: 68bb ldr r3, [r7, #8]
801676e: 681b ldr r3, [r3, #0]
if ((ipcb->local_port == port) &&
8016770: 429a cmp r2, r3
8016772: d00d beq.n 8016790 <udp_bind+0xb4>
(ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
8016774: 68bb ldr r3, [r7, #8]
8016776: 2b00 cmp r3, #0
8016778: d00a beq.n 8016790 <udp_bind+0xb4>
801677a: 68bb ldr r3, [r7, #8]
801677c: 681b ldr r3, [r3, #0]
801677e: 2b00 cmp r3, #0
8016780: d006 beq.n 8016790 <udp_bind+0xb4>
ip_addr_isany(&ipcb->local_ip))) {
8016782: 697b ldr r3, [r7, #20]
(ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
8016784: 2b00 cmp r3, #0
8016786: d003 beq.n 8016790 <udp_bind+0xb4>
ip_addr_isany(&ipcb->local_ip))) {
8016788: 697b ldr r3, [r7, #20]
801678a: 681b ldr r3, [r3, #0]
801678c: 2b00 cmp r3, #0
801678e: d102 bne.n 8016796 <udp_bind+0xba>
/* other PCB already binds to this local IP and port */
LWIP_DEBUGF(UDP_DEBUG,
("udp_bind: local port %"U16_F" already bound by another pcb\n", port));
return ERR_USE;
8016790: f06f 0307 mvn.w r3, #7
8016794: e01c b.n 80167d0 <udp_bind+0xf4>
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
8016796: 697b ldr r3, [r7, #20]
8016798: 68db ldr r3, [r3, #12]
801679a: 617b str r3, [r7, #20]
801679c: 697b ldr r3, [r7, #20]
801679e: 2b00 cmp r3, #0
80167a0: d1d9 bne.n 8016756 <udp_bind+0x7a>
}
}
}
}
ip_addr_set_ipaddr(&pcb->local_ip, ipaddr);
80167a2: 68bb ldr r3, [r7, #8]
80167a4: 2b00 cmp r3, #0
80167a6: d002 beq.n 80167ae <udp_bind+0xd2>
80167a8: 68bb ldr r3, [r7, #8]
80167aa: 681b ldr r3, [r3, #0]
80167ac: e000 b.n 80167b0 <udp_bind+0xd4>
80167ae: 2300 movs r3, #0
80167b0: 68fa ldr r2, [r7, #12]
80167b2: 6013 str r3, [r2, #0]
pcb->local_port = port;
80167b4: 68fb ldr r3, [r7, #12]
80167b6: 88fa ldrh r2, [r7, #6]
80167b8: 825a strh r2, [r3, #18]
mib2_udp_bind(pcb);
/* pcb not active yet? */
if (rebind == 0) {
80167ba: 7cfb ldrb r3, [r7, #19]
80167bc: 2b00 cmp r3, #0
80167be: d106 bne.n 80167ce <udp_bind+0xf2>
/* place the PCB on the active list if not already there */
pcb->next = udp_pcbs;
80167c0: 4b09 ldr r3, [pc, #36] ; (80167e8 <udp_bind+0x10c>)
80167c2: 681a ldr r2, [r3, #0]
80167c4: 68fb ldr r3, [r7, #12]
80167c6: 60da str r2, [r3, #12]
udp_pcbs = pcb;
80167c8: 4a07 ldr r2, [pc, #28] ; (80167e8 <udp_bind+0x10c>)
80167ca: 68fb ldr r3, [r7, #12]
80167cc: 6013 str r3, [r2, #0]
}
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_bind: bound to "));
ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, pcb->local_ip);
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->local_port));
return ERR_OK;
80167ce: 2300 movs r3, #0
}
80167d0: 4618 mov r0, r3
80167d2: 3718 adds r7, #24
80167d4: 46bd mov sp, r7
80167d6: bd80 pop {r7, pc}
80167d8: 0802103c .word 0x0802103c
80167dc: 0801e208 .word 0x0801e208
80167e0: 0801e4d0 .word 0x0801e4d0
80167e4: 0801e25c .word 0x0801e25c
80167e8: 2000f854 .word 0x2000f854
080167ec <udp_connect>:
*
* @see udp_disconnect()
*/
err_t
udp_connect(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
{
80167ec: b580 push {r7, lr}
80167ee: b086 sub sp, #24
80167f0: af00 add r7, sp, #0
80167f2: 60f8 str r0, [r7, #12]
80167f4: 60b9 str r1, [r7, #8]
80167f6: 4613 mov r3, r2
80167f8: 80fb strh r3, [r7, #6]
struct udp_pcb *ipcb;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("udp_connect: invalid pcb", pcb != NULL, return ERR_ARG);
80167fa: 68fb ldr r3, [r7, #12]
80167fc: 2b00 cmp r3, #0
80167fe: d109 bne.n 8016814 <udp_connect+0x28>
8016800: 4b2c ldr r3, [pc, #176] ; (80168b4 <udp_connect+0xc8>)
8016802: f240 4235 movw r2, #1077 ; 0x435
8016806: 492c ldr r1, [pc, #176] ; (80168b8 <udp_connect+0xcc>)
8016808: 482c ldr r0, [pc, #176] ; (80168bc <udp_connect+0xd0>)
801680a: f004 fbdb bl 801afc4 <iprintf>
801680e: f06f 030f mvn.w r3, #15
8016812: e04b b.n 80168ac <udp_connect+0xc0>
LWIP_ERROR("udp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
8016814: 68bb ldr r3, [r7, #8]
8016816: 2b00 cmp r3, #0
8016818: d109 bne.n 801682e <udp_connect+0x42>
801681a: 4b26 ldr r3, [pc, #152] ; (80168b4 <udp_connect+0xc8>)
801681c: f240 4236 movw r2, #1078 ; 0x436
8016820: 4927 ldr r1, [pc, #156] ; (80168c0 <udp_connect+0xd4>)
8016822: 4826 ldr r0, [pc, #152] ; (80168bc <udp_connect+0xd0>)
8016824: f004 fbce bl 801afc4 <iprintf>
8016828: f06f 030f mvn.w r3, #15
801682c: e03e b.n 80168ac <udp_connect+0xc0>
if (pcb->local_port == 0) {
801682e: 68fb ldr r3, [r7, #12]
8016830: 8a5b ldrh r3, [r3, #18]
8016832: 2b00 cmp r3, #0
8016834: d10f bne.n 8016856 <udp_connect+0x6a>
err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
8016836: 68f9 ldr r1, [r7, #12]
8016838: 68fb ldr r3, [r7, #12]
801683a: 8a5b ldrh r3, [r3, #18]
801683c: 461a mov r2, r3
801683e: 68f8 ldr r0, [r7, #12]
8016840: f7ff ff4c bl 80166dc <udp_bind>
8016844: 4603 mov r3, r0
8016846: 74fb strb r3, [r7, #19]
if (err != ERR_OK) {
8016848: f997 3013 ldrsb.w r3, [r7, #19]
801684c: 2b00 cmp r3, #0
801684e: d002 beq.n 8016856 <udp_connect+0x6a>
return err;
8016850: f997 3013 ldrsb.w r3, [r7, #19]
8016854: e02a b.n 80168ac <udp_connect+0xc0>
}
}
ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr);
8016856: 68bb ldr r3, [r7, #8]
8016858: 2b00 cmp r3, #0
801685a: d002 beq.n 8016862 <udp_connect+0x76>
801685c: 68bb ldr r3, [r7, #8]
801685e: 681b ldr r3, [r3, #0]
8016860: e000 b.n 8016864 <udp_connect+0x78>
8016862: 2300 movs r3, #0
8016864: 68fa ldr r2, [r7, #12]
8016866: 6053 str r3, [r2, #4]
ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNKNOWN)) {
ip6_addr_select_zone(ip_2_ip6(&pcb->remote_ip), ip_2_ip6(&pcb->local_ip));
}
#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
pcb->remote_port = port;
8016868: 68fb ldr r3, [r7, #12]
801686a: 88fa ldrh r2, [r7, #6]
801686c: 829a strh r2, [r3, #20]
pcb->flags |= UDP_FLAGS_CONNECTED;
801686e: 68fb ldr r3, [r7, #12]
8016870: 7c1b ldrb r3, [r3, #16]
8016872: f043 0304 orr.w r3, r3, #4
8016876: b2da uxtb r2, r3
8016878: 68fb ldr r3, [r7, #12]
801687a: 741a strb r2, [r3, #16]
ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
pcb->remote_ip);
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->remote_port));
/* Insert UDP PCB into the list of active UDP PCBs. */
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
801687c: 4b11 ldr r3, [pc, #68] ; (80168c4 <udp_connect+0xd8>)
801687e: 681b ldr r3, [r3, #0]
8016880: 617b str r3, [r7, #20]
8016882: e008 b.n 8016896 <udp_connect+0xaa>
if (pcb == ipcb) {
8016884: 68fa ldr r2, [r7, #12]
8016886: 697b ldr r3, [r7, #20]
8016888: 429a cmp r2, r3
801688a: d101 bne.n 8016890 <udp_connect+0xa4>
/* already on the list, just return */
return ERR_OK;
801688c: 2300 movs r3, #0
801688e: e00d b.n 80168ac <udp_connect+0xc0>
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
8016890: 697b ldr r3, [r7, #20]
8016892: 68db ldr r3, [r3, #12]
8016894: 617b str r3, [r7, #20]
8016896: 697b ldr r3, [r7, #20]
8016898: 2b00 cmp r3, #0
801689a: d1f3 bne.n 8016884 <udp_connect+0x98>
}
}
/* PCB not yet on the list, add PCB now */
pcb->next = udp_pcbs;
801689c: 4b09 ldr r3, [pc, #36] ; (80168c4 <udp_connect+0xd8>)
801689e: 681a ldr r2, [r3, #0]
80168a0: 68fb ldr r3, [r7, #12]
80168a2: 60da str r2, [r3, #12]
udp_pcbs = pcb;
80168a4: 4a07 ldr r2, [pc, #28] ; (80168c4 <udp_connect+0xd8>)
80168a6: 68fb ldr r3, [r7, #12]
80168a8: 6013 str r3, [r2, #0]
return ERR_OK;
80168aa: 2300 movs r3, #0
}
80168ac: 4618 mov r0, r3
80168ae: 3718 adds r7, #24
80168b0: 46bd mov sp, r7
80168b2: bd80 pop {r7, pc}
80168b4: 0801e208 .word 0x0801e208
80168b8: 0801e4e8 .word 0x0801e4e8
80168bc: 0801e25c .word 0x0801e25c
80168c0: 0801e504 .word 0x0801e504
80168c4: 2000f854 .word 0x2000f854
080168c8 <udp_recv>:
* @param recv function pointer of the callback function
* @param recv_arg additional argument to pass to the callback function
*/
void
udp_recv(struct udp_pcb *pcb, udp_recv_fn recv, void *recv_arg)
{
80168c8: b580 push {r7, lr}
80168ca: b084 sub sp, #16
80168cc: af00 add r7, sp, #0
80168ce: 60f8 str r0, [r7, #12]
80168d0: 60b9 str r1, [r7, #8]
80168d2: 607a str r2, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("udp_recv: invalid pcb", pcb != NULL, return);
80168d4: 68fb ldr r3, [r7, #12]
80168d6: 2b00 cmp r3, #0
80168d8: d107 bne.n 80168ea <udp_recv+0x22>
80168da: 4b08 ldr r3, [pc, #32] ; (80168fc <udp_recv+0x34>)
80168dc: f240 428a movw r2, #1162 ; 0x48a
80168e0: 4907 ldr r1, [pc, #28] ; (8016900 <udp_recv+0x38>)
80168e2: 4808 ldr r0, [pc, #32] ; (8016904 <udp_recv+0x3c>)
80168e4: f004 fb6e bl 801afc4 <iprintf>
80168e8: e005 b.n 80168f6 <udp_recv+0x2e>
/* remember recv() callback and user data */
pcb->recv = recv;
80168ea: 68fb ldr r3, [r7, #12]
80168ec: 68ba ldr r2, [r7, #8]
80168ee: 619a str r2, [r3, #24]
pcb->recv_arg = recv_arg;
80168f0: 68fb ldr r3, [r7, #12]
80168f2: 687a ldr r2, [r7, #4]
80168f4: 61da str r2, [r3, #28]
}
80168f6: 3710 adds r7, #16
80168f8: 46bd mov sp, r7
80168fa: bd80 pop {r7, pc}
80168fc: 0801e208 .word 0x0801e208
8016900: 0801e53c .word 0x0801e53c
8016904: 0801e25c .word 0x0801e25c
08016908 <udp_remove>:
*
* @see udp_new()
*/
void
udp_remove(struct udp_pcb *pcb)
{
8016908: b580 push {r7, lr}
801690a: b084 sub sp, #16
801690c: af00 add r7, sp, #0
801690e: 6078 str r0, [r7, #4]
struct udp_pcb *pcb2;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("udp_remove: invalid pcb", pcb != NULL, return);
8016910: 687b ldr r3, [r7, #4]
8016912: 2b00 cmp r3, #0
8016914: d107 bne.n 8016926 <udp_remove+0x1e>
8016916: 4b19 ldr r3, [pc, #100] ; (801697c <udp_remove+0x74>)
8016918: f240 42a1 movw r2, #1185 ; 0x4a1
801691c: 4918 ldr r1, [pc, #96] ; (8016980 <udp_remove+0x78>)
801691e: 4819 ldr r0, [pc, #100] ; (8016984 <udp_remove+0x7c>)
8016920: f004 fb50 bl 801afc4 <iprintf>
8016924: e026 b.n 8016974 <udp_remove+0x6c>
mib2_udp_unbind(pcb);
/* pcb to be removed is first in list? */
if (udp_pcbs == pcb) {
8016926: 4b18 ldr r3, [pc, #96] ; (8016988 <udp_remove+0x80>)
8016928: 681b ldr r3, [r3, #0]
801692a: 687a ldr r2, [r7, #4]
801692c: 429a cmp r2, r3
801692e: d105 bne.n 801693c <udp_remove+0x34>
/* make list start at 2nd pcb */
udp_pcbs = udp_pcbs->next;
8016930: 4b15 ldr r3, [pc, #84] ; (8016988 <udp_remove+0x80>)
8016932: 681b ldr r3, [r3, #0]
8016934: 68db ldr r3, [r3, #12]
8016936: 4a14 ldr r2, [pc, #80] ; (8016988 <udp_remove+0x80>)
8016938: 6013 str r3, [r2, #0]
801693a: e017 b.n 801696c <udp_remove+0x64>
/* pcb not 1st in list */
} else {
for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
801693c: 4b12 ldr r3, [pc, #72] ; (8016988 <udp_remove+0x80>)
801693e: 681b ldr r3, [r3, #0]
8016940: 60fb str r3, [r7, #12]
8016942: e010 b.n 8016966 <udp_remove+0x5e>
/* find pcb in udp_pcbs list */
if (pcb2->next != NULL && pcb2->next == pcb) {
8016944: 68fb ldr r3, [r7, #12]
8016946: 68db ldr r3, [r3, #12]
8016948: 2b00 cmp r3, #0
801694a: d009 beq.n 8016960 <udp_remove+0x58>
801694c: 68fb ldr r3, [r7, #12]
801694e: 68db ldr r3, [r3, #12]
8016950: 687a ldr r2, [r7, #4]
8016952: 429a cmp r2, r3
8016954: d104 bne.n 8016960 <udp_remove+0x58>
/* remove pcb from list */
pcb2->next = pcb->next;
8016956: 687b ldr r3, [r7, #4]
8016958: 68da ldr r2, [r3, #12]
801695a: 68fb ldr r3, [r7, #12]
801695c: 60da str r2, [r3, #12]
break;
801695e: e005 b.n 801696c <udp_remove+0x64>
for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
8016960: 68fb ldr r3, [r7, #12]
8016962: 68db ldr r3, [r3, #12]
8016964: 60fb str r3, [r7, #12]
8016966: 68fb ldr r3, [r7, #12]
8016968: 2b00 cmp r3, #0
801696a: d1eb bne.n 8016944 <udp_remove+0x3c>
}
}
}
memp_free(MEMP_UDP_PCB, pcb);
801696c: 6879 ldr r1, [r7, #4]
801696e: 2000 movs r0, #0
8016970: f7f8 ff6c bl 800f84c <memp_free>
}
8016974: 3710 adds r7, #16
8016976: 46bd mov sp, r7
8016978: bd80 pop {r7, pc}
801697a: bf00 nop
801697c: 0801e208 .word 0x0801e208
8016980: 0801e554 .word 0x0801e554
8016984: 0801e25c .word 0x0801e25c
8016988: 2000f854 .word 0x2000f854
0801698c <udp_new>:
*
* @see udp_remove()
*/
struct udp_pcb *
udp_new(void)
{
801698c: b580 push {r7, lr}
801698e: b082 sub sp, #8
8016990: af00 add r7, sp, #0
struct udp_pcb *pcb;
LWIP_ASSERT_CORE_LOCKED();
pcb = (struct udp_pcb *)memp_malloc(MEMP_UDP_PCB);
8016992: 2000 movs r0, #0
8016994: f7f8 ff08 bl 800f7a8 <memp_malloc>
8016998: 6078 str r0, [r7, #4]
/* could allocate UDP PCB? */
if (pcb != NULL) {
801699a: 687b ldr r3, [r7, #4]
801699c: 2b00 cmp r3, #0
801699e: d007 beq.n 80169b0 <udp_new+0x24>
/* UDP Lite: by initializing to all zeroes, chksum_len is set to 0
* which means checksum is generated over the whole datagram per default
* (recommended as default by RFC 3828). */
/* initialize PCB to all zeroes */
memset(pcb, 0, sizeof(struct udp_pcb));
80169a0: 2220 movs r2, #32
80169a2: 2100 movs r1, #0
80169a4: 6878 ldr r0, [r7, #4]
80169a6: f004 fb05 bl 801afb4 <memset>
pcb->ttl = UDP_TTL;
80169aa: 687b ldr r3, [r7, #4]
80169ac: 22ff movs r2, #255 ; 0xff
80169ae: 72da strb r2, [r3, #11]
#if LWIP_MULTICAST_TX_OPTIONS
udp_set_multicast_ttl(pcb, UDP_TTL);
#endif /* LWIP_MULTICAST_TX_OPTIONS */
}
return pcb;
80169b0: 687b ldr r3, [r7, #4]
}
80169b2: 4618 mov r0, r3
80169b4: 3708 adds r7, #8
80169b6: 46bd mov sp, r7
80169b8: bd80 pop {r7, pc}
...
080169bc <udp_netif_ip_addr_changed>:
*
* @param old_addr IP address of the netif before change
* @param new_addr IP address of the netif after change
*/
void udp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
{
80169bc: b480 push {r7}
80169be: b085 sub sp, #20
80169c0: af00 add r7, sp, #0
80169c2: 6078 str r0, [r7, #4]
80169c4: 6039 str r1, [r7, #0]
struct udp_pcb *upcb;
if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) {
80169c6: 687b ldr r3, [r7, #4]
80169c8: 2b00 cmp r3, #0
80169ca: d01e beq.n 8016a0a <udp_netif_ip_addr_changed+0x4e>
80169cc: 687b ldr r3, [r7, #4]
80169ce: 681b ldr r3, [r3, #0]
80169d0: 2b00 cmp r3, #0
80169d2: d01a beq.n 8016a0a <udp_netif_ip_addr_changed+0x4e>
80169d4: 683b ldr r3, [r7, #0]
80169d6: 2b00 cmp r3, #0
80169d8: d017 beq.n 8016a0a <udp_netif_ip_addr_changed+0x4e>
80169da: 683b ldr r3, [r7, #0]
80169dc: 681b ldr r3, [r3, #0]
80169de: 2b00 cmp r3, #0
80169e0: d013 beq.n 8016a0a <udp_netif_ip_addr_changed+0x4e>
for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
80169e2: 4b0d ldr r3, [pc, #52] ; (8016a18 <udp_netif_ip_addr_changed+0x5c>)
80169e4: 681b ldr r3, [r3, #0]
80169e6: 60fb str r3, [r7, #12]
80169e8: e00c b.n 8016a04 <udp_netif_ip_addr_changed+0x48>
/* PCB bound to current local interface address? */
if (ip_addr_cmp(&upcb->local_ip, old_addr)) {
80169ea: 68fb ldr r3, [r7, #12]
80169ec: 681a ldr r2, [r3, #0]
80169ee: 687b ldr r3, [r7, #4]
80169f0: 681b ldr r3, [r3, #0]
80169f2: 429a cmp r2, r3
80169f4: d103 bne.n 80169fe <udp_netif_ip_addr_changed+0x42>
/* The PCB is bound to the old ipaddr and
* is set to bound to the new one instead */
ip_addr_copy(upcb->local_ip, *new_addr);
80169f6: 683b ldr r3, [r7, #0]
80169f8: 681a ldr r2, [r3, #0]
80169fa: 68fb ldr r3, [r7, #12]
80169fc: 601a str r2, [r3, #0]
for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
80169fe: 68fb ldr r3, [r7, #12]
8016a00: 68db ldr r3, [r3, #12]
8016a02: 60fb str r3, [r7, #12]
8016a04: 68fb ldr r3, [r7, #12]
8016a06: 2b00 cmp r3, #0
8016a08: d1ef bne.n 80169ea <udp_netif_ip_addr_changed+0x2e>
}
}
}
}
8016a0a: bf00 nop
8016a0c: 3714 adds r7, #20
8016a0e: 46bd mov sp, r7
8016a10: f85d 7b04 ldr.w r7, [sp], #4
8016a14: 4770 bx lr
8016a16: bf00 nop
8016a18: 2000f854 .word 0x2000f854
08016a1c <dhcp_inc_pcb_refcount>:
static void dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out);
/** Ensure DHCP PCB is allocated and bound */
static err_t
dhcp_inc_pcb_refcount(void)
{
8016a1c: b580 push {r7, lr}
8016a1e: af00 add r7, sp, #0
if (dhcp_pcb_refcount == 0) {
8016a20: 4b20 ldr r3, [pc, #128] ; (8016aa4 <dhcp_inc_pcb_refcount+0x88>)
8016a22: 781b ldrb r3, [r3, #0]
8016a24: 2b00 cmp r3, #0
8016a26: d133 bne.n 8016a90 <dhcp_inc_pcb_refcount+0x74>
LWIP_ASSERT("dhcp_inc_pcb_refcount(): memory leak", dhcp_pcb == NULL);
8016a28: 4b1f ldr r3, [pc, #124] ; (8016aa8 <dhcp_inc_pcb_refcount+0x8c>)
8016a2a: 681b ldr r3, [r3, #0]
8016a2c: 2b00 cmp r3, #0
8016a2e: d005 beq.n 8016a3c <dhcp_inc_pcb_refcount+0x20>
8016a30: 4b1e ldr r3, [pc, #120] ; (8016aac <dhcp_inc_pcb_refcount+0x90>)
8016a32: 22e5 movs r2, #229 ; 0xe5
8016a34: 491e ldr r1, [pc, #120] ; (8016ab0 <dhcp_inc_pcb_refcount+0x94>)
8016a36: 481f ldr r0, [pc, #124] ; (8016ab4 <dhcp_inc_pcb_refcount+0x98>)
8016a38: f004 fac4 bl 801afc4 <iprintf>
/* allocate UDP PCB */
dhcp_pcb = udp_new();
8016a3c: f7ff ffa6 bl 801698c <udp_new>
8016a40: 4603 mov r3, r0
8016a42: 4a19 ldr r2, [pc, #100] ; (8016aa8 <dhcp_inc_pcb_refcount+0x8c>)
8016a44: 6013 str r3, [r2, #0]
if (dhcp_pcb == NULL) {
8016a46: 4b18 ldr r3, [pc, #96] ; (8016aa8 <dhcp_inc_pcb_refcount+0x8c>)
8016a48: 681b ldr r3, [r3, #0]
8016a4a: 2b00 cmp r3, #0
8016a4c: d102 bne.n 8016a54 <dhcp_inc_pcb_refcount+0x38>
return ERR_MEM;
8016a4e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8016a52: e024 b.n 8016a9e <dhcp_inc_pcb_refcount+0x82>
}
ip_set_option(dhcp_pcb, SOF_BROADCAST);
8016a54: 4b14 ldr r3, [pc, #80] ; (8016aa8 <dhcp_inc_pcb_refcount+0x8c>)
8016a56: 681b ldr r3, [r3, #0]
8016a58: 7a5a ldrb r2, [r3, #9]
8016a5a: 4b13 ldr r3, [pc, #76] ; (8016aa8 <dhcp_inc_pcb_refcount+0x8c>)
8016a5c: 681b ldr r3, [r3, #0]
8016a5e: f042 0220 orr.w r2, r2, #32
8016a62: b2d2 uxtb r2, r2
8016a64: 725a strb r2, [r3, #9]
/* set up local and remote port for the pcb -> listen on all interfaces on all src/dest IPs */
udp_bind(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_CLIENT);
8016a66: 4b10 ldr r3, [pc, #64] ; (8016aa8 <dhcp_inc_pcb_refcount+0x8c>)
8016a68: 681b ldr r3, [r3, #0]
8016a6a: 2244 movs r2, #68 ; 0x44
8016a6c: 4912 ldr r1, [pc, #72] ; (8016ab8 <dhcp_inc_pcb_refcount+0x9c>)
8016a6e: 4618 mov r0, r3
8016a70: f7ff fe34 bl 80166dc <udp_bind>
udp_connect(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_SERVER);
8016a74: 4b0c ldr r3, [pc, #48] ; (8016aa8 <dhcp_inc_pcb_refcount+0x8c>)
8016a76: 681b ldr r3, [r3, #0]
8016a78: 2243 movs r2, #67 ; 0x43
8016a7a: 490f ldr r1, [pc, #60] ; (8016ab8 <dhcp_inc_pcb_refcount+0x9c>)
8016a7c: 4618 mov r0, r3
8016a7e: f7ff feb5 bl 80167ec <udp_connect>
udp_recv(dhcp_pcb, dhcp_recv, NULL);
8016a82: 4b09 ldr r3, [pc, #36] ; (8016aa8 <dhcp_inc_pcb_refcount+0x8c>)
8016a84: 681b ldr r3, [r3, #0]
8016a86: 2200 movs r2, #0
8016a88: 490c ldr r1, [pc, #48] ; (8016abc <dhcp_inc_pcb_refcount+0xa0>)
8016a8a: 4618 mov r0, r3
8016a8c: f7ff ff1c bl 80168c8 <udp_recv>
}
dhcp_pcb_refcount++;
8016a90: 4b04 ldr r3, [pc, #16] ; (8016aa4 <dhcp_inc_pcb_refcount+0x88>)
8016a92: 781b ldrb r3, [r3, #0]
8016a94: 3301 adds r3, #1
8016a96: b2da uxtb r2, r3
8016a98: 4b02 ldr r3, [pc, #8] ; (8016aa4 <dhcp_inc_pcb_refcount+0x88>)
8016a9a: 701a strb r2, [r3, #0]
return ERR_OK;
8016a9c: 2300 movs r3, #0
}
8016a9e: 4618 mov r0, r3
8016aa0: bd80 pop {r7, pc}
8016aa2: bf00 nop
8016aa4: 20008764 .word 0x20008764
8016aa8: 20008760 .word 0x20008760
8016aac: 0801e56c .word 0x0801e56c
8016ab0: 0801e5a4 .word 0x0801e5a4
8016ab4: 0801e5cc .word 0x0801e5cc
8016ab8: 0802103c .word 0x0802103c
8016abc: 08018355 .word 0x08018355
08016ac0 <dhcp_dec_pcb_refcount>:
/** Free DHCP PCB if the last netif stops using it */
static void
dhcp_dec_pcb_refcount(void)
{
8016ac0: b580 push {r7, lr}
8016ac2: af00 add r7, sp, #0
LWIP_ASSERT("dhcp_pcb_refcount(): refcount error", (dhcp_pcb_refcount > 0));
8016ac4: 4b0e ldr r3, [pc, #56] ; (8016b00 <dhcp_dec_pcb_refcount+0x40>)
8016ac6: 781b ldrb r3, [r3, #0]
8016ac8: 2b00 cmp r3, #0
8016aca: d105 bne.n 8016ad8 <dhcp_dec_pcb_refcount+0x18>
8016acc: 4b0d ldr r3, [pc, #52] ; (8016b04 <dhcp_dec_pcb_refcount+0x44>)
8016ace: 22ff movs r2, #255 ; 0xff
8016ad0: 490d ldr r1, [pc, #52] ; (8016b08 <dhcp_dec_pcb_refcount+0x48>)
8016ad2: 480e ldr r0, [pc, #56] ; (8016b0c <dhcp_dec_pcb_refcount+0x4c>)
8016ad4: f004 fa76 bl 801afc4 <iprintf>
dhcp_pcb_refcount--;
8016ad8: 4b09 ldr r3, [pc, #36] ; (8016b00 <dhcp_dec_pcb_refcount+0x40>)
8016ada: 781b ldrb r3, [r3, #0]
8016adc: 3b01 subs r3, #1
8016ade: b2da uxtb r2, r3
8016ae0: 4b07 ldr r3, [pc, #28] ; (8016b00 <dhcp_dec_pcb_refcount+0x40>)
8016ae2: 701a strb r2, [r3, #0]
if (dhcp_pcb_refcount == 0) {
8016ae4: 4b06 ldr r3, [pc, #24] ; (8016b00 <dhcp_dec_pcb_refcount+0x40>)
8016ae6: 781b ldrb r3, [r3, #0]
8016ae8: 2b00 cmp r3, #0
8016aea: d107 bne.n 8016afc <dhcp_dec_pcb_refcount+0x3c>
udp_remove(dhcp_pcb);
8016aec: 4b08 ldr r3, [pc, #32] ; (8016b10 <dhcp_dec_pcb_refcount+0x50>)
8016aee: 681b ldr r3, [r3, #0]
8016af0: 4618 mov r0, r3
8016af2: f7ff ff09 bl 8016908 <udp_remove>
dhcp_pcb = NULL;
8016af6: 4b06 ldr r3, [pc, #24] ; (8016b10 <dhcp_dec_pcb_refcount+0x50>)
8016af8: 2200 movs r2, #0
8016afa: 601a str r2, [r3, #0]
}
}
8016afc: bf00 nop
8016afe: bd80 pop {r7, pc}
8016b00: 20008764 .word 0x20008764
8016b04: 0801e56c .word 0x0801e56c
8016b08: 0801e5f4 .word 0x0801e5f4
8016b0c: 0801e5cc .word 0x0801e5cc
8016b10: 20008760 .word 0x20008760
08016b14 <dhcp_handle_nak>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_handle_nak(struct netif *netif)
{
8016b14: b580 push {r7, lr}
8016b16: b084 sub sp, #16
8016b18: af00 add r7, sp, #0
8016b1a: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016b1c: 687b ldr r3, [r7, #4]
8016b1e: 6a5b ldr r3, [r3, #36] ; 0x24
8016b20: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n",
(void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* Change to a defined state - set this before assigning the address
to ensure the callback can use dhcp_supplied_address() */
dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF);
8016b22: 210c movs r1, #12
8016b24: 68f8 ldr r0, [r7, #12]
8016b26: f001 f857 bl 8017bd8 <dhcp_set_state>
/* remove IP address from interface (must no longer be used, as per RFC2131) */
netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4);
8016b2a: 4b06 ldr r3, [pc, #24] ; (8016b44 <dhcp_handle_nak+0x30>)
8016b2c: 4a05 ldr r2, [pc, #20] ; (8016b44 <dhcp_handle_nak+0x30>)
8016b2e: 4905 ldr r1, [pc, #20] ; (8016b44 <dhcp_handle_nak+0x30>)
8016b30: 6878 ldr r0, [r7, #4]
8016b32: f7f9 f82d bl 800fb90 <netif_set_addr>
/* We can immediately restart discovery */
dhcp_discover(netif);
8016b36: 6878 ldr r0, [r7, #4]
8016b38: f000 fc4a bl 80173d0 <dhcp_discover>
}
8016b3c: bf00 nop
8016b3e: 3710 adds r7, #16
8016b40: 46bd mov sp, r7
8016b42: bd80 pop {r7, pc}
8016b44: 0802103c .word 0x0802103c
08016b48 <dhcp_check>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_check(struct netif *netif)
{
8016b48: b580 push {r7, lr}
8016b4a: b084 sub sp, #16
8016b4c: af00 add r7, sp, #0
8016b4e: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016b50: 687b ldr r3, [r7, #4]
8016b52: 6a5b ldr r3, [r3, #36] ; 0x24
8016b54: 60fb str r3, [r7, #12]
err_t result;
u16_t msecs;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0],
(s16_t)netif->name[1]));
dhcp_set_state(dhcp, DHCP_STATE_CHECKING);
8016b56: 2108 movs r1, #8
8016b58: 68f8 ldr r0, [r7, #12]
8016b5a: f001 f83d bl 8017bd8 <dhcp_set_state>
/* create an ARP query for the offered IP address, expecting that no host
responds, as the IP address should not be in use. */
result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
8016b5e: 68fb ldr r3, [r7, #12]
8016b60: 331c adds r3, #28
8016b62: 2200 movs r2, #0
8016b64: 4619 mov r1, r3
8016b66: 6878 ldr r0, [r7, #4]
8016b68: f002 fb3e bl 80191e8 <etharp_query>
8016b6c: 4603 mov r3, r0
8016b6e: 72fb strb r3, [r7, #11]
if (result != ERR_OK) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n"));
}
if (dhcp->tries < 255) {
8016b70: 68fb ldr r3, [r7, #12]
8016b72: 799b ldrb r3, [r3, #6]
8016b74: 2bff cmp r3, #255 ; 0xff
8016b76: d005 beq.n 8016b84 <dhcp_check+0x3c>
dhcp->tries++;
8016b78: 68fb ldr r3, [r7, #12]
8016b7a: 799b ldrb r3, [r3, #6]
8016b7c: 3301 adds r3, #1
8016b7e: b2da uxtb r2, r3
8016b80: 68fb ldr r3, [r7, #12]
8016b82: 719a strb r2, [r3, #6]
}
msecs = 500;
8016b84: f44f 73fa mov.w r3, #500 ; 0x1f4
8016b88: 813b strh r3, [r7, #8]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8016b8a: 893b ldrh r3, [r7, #8]
8016b8c: f203 13f3 addw r3, r3, #499 ; 0x1f3
8016b90: 4a06 ldr r2, [pc, #24] ; (8016bac <dhcp_check+0x64>)
8016b92: fb82 1203 smull r1, r2, r2, r3
8016b96: 1152 asrs r2, r2, #5
8016b98: 17db asrs r3, r3, #31
8016b9a: 1ad3 subs r3, r2, r3
8016b9c: b29a uxth r2, r3
8016b9e: 68fb ldr r3, [r7, #12]
8016ba0: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs));
}
8016ba2: bf00 nop
8016ba4: 3710 adds r7, #16
8016ba6: 46bd mov sp, r7
8016ba8: bd80 pop {r7, pc}
8016baa: bf00 nop
8016bac: 10624dd3 .word 0x10624dd3
08016bb0 <dhcp_handle_offer>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_handle_offer(struct netif *netif, struct dhcp_msg *msg_in)
{
8016bb0: b580 push {r7, lr}
8016bb2: b084 sub sp, #16
8016bb4: af00 add r7, sp, #0
8016bb6: 6078 str r0, [r7, #4]
8016bb8: 6039 str r1, [r7, #0]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016bba: 687b ldr r3, [r7, #4]
8016bbc: 6a5b ldr r3, [r3, #36] ; 0x24
8016bbe: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n",
(void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* obtain the server address */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SERVER_ID)) {
8016bc0: 4b0c ldr r3, [pc, #48] ; (8016bf4 <dhcp_handle_offer+0x44>)
8016bc2: 789b ldrb r3, [r3, #2]
8016bc4: 2b00 cmp r3, #0
8016bc6: d011 beq.n 8016bec <dhcp_handle_offer+0x3c>
dhcp->request_timeout = 0; /* stop timer */
8016bc8: 68fb ldr r3, [r7, #12]
8016bca: 2200 movs r2, #0
8016bcc: 811a strh r2, [r3, #8]
ip_addr_set_ip4_u32(&dhcp->server_ip_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SERVER_ID)));
8016bce: 4b0a ldr r3, [pc, #40] ; (8016bf8 <dhcp_handle_offer+0x48>)
8016bd0: 689b ldr r3, [r3, #8]
8016bd2: 4618 mov r0, r3
8016bd4: f7f8 f947 bl 800ee66 <lwip_htonl>
8016bd8: 4602 mov r2, r0
8016bda: 68fb ldr r3, [r7, #12]
8016bdc: 619a str r2, [r3, #24]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n",
ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr))));
/* remember offered address */
ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr);
8016bde: 683b ldr r3, [r7, #0]
8016be0: 691a ldr r2, [r3, #16]
8016be2: 68fb ldr r3, [r7, #12]
8016be4: 61da str r2, [r3, #28]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n",
ip4_addr_get_u32(&dhcp->offered_ip_addr)));
dhcp_select(netif);
8016be6: 6878 ldr r0, [r7, #4]
8016be8: f000 f808 bl 8016bfc <dhcp_select>
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("dhcp_handle_offer(netif=%p) did not get server ID!\n", (void *)netif));
}
}
8016bec: bf00 nop
8016bee: 3710 adds r7, #16
8016bf0: 46bd mov sp, r7
8016bf2: bd80 pop {r7, pc}
8016bf4: 2000f858 .word 0x2000f858
8016bf8: 2000f860 .word 0x2000f860
08016bfc <dhcp_select>:
* @param netif the netif under DHCP control
* @return lwIP specific error (see error.h)
*/
static err_t
dhcp_select(struct netif *netif)
{
8016bfc: b5b0 push {r4, r5, r7, lr}
8016bfe: b08a sub sp, #40 ; 0x28
8016c00: af02 add r7, sp, #8
8016c02: 6078 str r0, [r7, #4]
u16_t msecs;
u8_t i;
struct pbuf *p_out;
u16_t options_out_len;
LWIP_ERROR("dhcp_select: netif != NULL", (netif != NULL), return ERR_ARG;);
8016c04: 687b ldr r3, [r7, #4]
8016c06: 2b00 cmp r3, #0
8016c08: d109 bne.n 8016c1e <dhcp_select+0x22>
8016c0a: 4b71 ldr r3, [pc, #452] ; (8016dd0 <dhcp_select+0x1d4>)
8016c0c: f240 1277 movw r2, #375 ; 0x177
8016c10: 4970 ldr r1, [pc, #448] ; (8016dd4 <dhcp_select+0x1d8>)
8016c12: 4871 ldr r0, [pc, #452] ; (8016dd8 <dhcp_select+0x1dc>)
8016c14: f004 f9d6 bl 801afc4 <iprintf>
8016c18: f06f 030f mvn.w r3, #15
8016c1c: e0d3 b.n 8016dc6 <dhcp_select+0x1ca>
dhcp = netif_dhcp_data(netif);
8016c1e: 687b ldr r3, [r7, #4]
8016c20: 6a5b ldr r3, [r3, #36] ; 0x24
8016c22: 61bb str r3, [r7, #24]
LWIP_ERROR("dhcp_select: dhcp != NULL", (dhcp != NULL), return ERR_VAL;);
8016c24: 69bb ldr r3, [r7, #24]
8016c26: 2b00 cmp r3, #0
8016c28: d109 bne.n 8016c3e <dhcp_select+0x42>
8016c2a: 4b69 ldr r3, [pc, #420] ; (8016dd0 <dhcp_select+0x1d4>)
8016c2c: f240 1279 movw r2, #377 ; 0x179
8016c30: 496a ldr r1, [pc, #424] ; (8016ddc <dhcp_select+0x1e0>)
8016c32: 4869 ldr r0, [pc, #420] ; (8016dd8 <dhcp_select+0x1dc>)
8016c34: f004 f9c6 bl 801afc4 <iprintf>
8016c38: f06f 0305 mvn.w r3, #5
8016c3c: e0c3 b.n 8016dc6 <dhcp_select+0x1ca>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
dhcp_set_state(dhcp, DHCP_STATE_REQUESTING);
8016c3e: 2101 movs r1, #1
8016c40: 69b8 ldr r0, [r7, #24]
8016c42: f000 ffc9 bl 8017bd8 <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
8016c46: f107 030c add.w r3, r7, #12
8016c4a: 2203 movs r2, #3
8016c4c: 69b9 ldr r1, [r7, #24]
8016c4e: 6878 ldr r0, [r7, #4]
8016c50: f001 fc4e bl 80184f0 <dhcp_create_msg>
8016c54: 6178 str r0, [r7, #20]
if (p_out != NULL) {
8016c56: 697b ldr r3, [r7, #20]
8016c58: 2b00 cmp r3, #0
8016c5a: f000 8085 beq.w 8016d68 <dhcp_select+0x16c>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8016c5e: 697b ldr r3, [r7, #20]
8016c60: 685b ldr r3, [r3, #4]
8016c62: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
8016c64: 89b8 ldrh r0, [r7, #12]
8016c66: 693b ldr r3, [r7, #16]
8016c68: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016c6c: 2302 movs r3, #2
8016c6e: 2239 movs r2, #57 ; 0x39
8016c70: f000 ffcc bl 8017c0c <dhcp_option>
8016c74: 4603 mov r3, r0
8016c76: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
8016c78: 89b8 ldrh r0, [r7, #12]
8016c7a: 693b ldr r3, [r7, #16]
8016c7c: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016c80: 687b ldr r3, [r7, #4]
8016c82: 8d1b ldrh r3, [r3, #40] ; 0x28
8016c84: 461a mov r2, r3
8016c86: f001 f81b bl 8017cc0 <dhcp_option_short>
8016c8a: 4603 mov r3, r0
8016c8c: 81bb strh r3, [r7, #12]
/* MUST request the offered IP address */
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
8016c8e: 89b8 ldrh r0, [r7, #12]
8016c90: 693b ldr r3, [r7, #16]
8016c92: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016c96: 2304 movs r3, #4
8016c98: 2232 movs r2, #50 ; 0x32
8016c9a: f000 ffb7 bl 8017c0c <dhcp_option>
8016c9e: 4603 mov r3, r0
8016ca0: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
8016ca2: 89bc ldrh r4, [r7, #12]
8016ca4: 693b ldr r3, [r7, #16]
8016ca6: f103 05f0 add.w r5, r3, #240 ; 0xf0
8016caa: 69bb ldr r3, [r7, #24]
8016cac: 69db ldr r3, [r3, #28]
8016cae: 4618 mov r0, r3
8016cb0: f7f8 f8d9 bl 800ee66 <lwip_htonl>
8016cb4: 4603 mov r3, r0
8016cb6: 461a mov r2, r3
8016cb8: 4629 mov r1, r5
8016cba: 4620 mov r0, r4
8016cbc: f001 f832 bl 8017d24 <dhcp_option_long>
8016cc0: 4603 mov r3, r0
8016cc2: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4);
8016cc4: 89b8 ldrh r0, [r7, #12]
8016cc6: 693b ldr r3, [r7, #16]
8016cc8: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016ccc: 2304 movs r3, #4
8016cce: 2236 movs r2, #54 ; 0x36
8016cd0: f000 ff9c bl 8017c0c <dhcp_option>
8016cd4: 4603 mov r3, r0
8016cd6: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr))));
8016cd8: 89bc ldrh r4, [r7, #12]
8016cda: 693b ldr r3, [r7, #16]
8016cdc: f103 05f0 add.w r5, r3, #240 ; 0xf0
8016ce0: 69bb ldr r3, [r7, #24]
8016ce2: 699b ldr r3, [r3, #24]
8016ce4: 4618 mov r0, r3
8016ce6: f7f8 f8be bl 800ee66 <lwip_htonl>
8016cea: 4603 mov r3, r0
8016cec: 461a mov r2, r3
8016cee: 4629 mov r1, r5
8016cf0: 4620 mov r0, r4
8016cf2: f001 f817 bl 8017d24 <dhcp_option_long>
8016cf6: 4603 mov r3, r0
8016cf8: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
8016cfa: 89b8 ldrh r0, [r7, #12]
8016cfc: 693b ldr r3, [r7, #16]
8016cfe: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016d02: 2303 movs r3, #3
8016d04: 2237 movs r2, #55 ; 0x37
8016d06: f000 ff81 bl 8017c0c <dhcp_option>
8016d0a: 4603 mov r3, r0
8016d0c: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8016d0e: 2300 movs r3, #0
8016d10: 77bb strb r3, [r7, #30]
8016d12: e00e b.n 8016d32 <dhcp_select+0x136>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
8016d14: 89b8 ldrh r0, [r7, #12]
8016d16: 693b ldr r3, [r7, #16]
8016d18: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016d1c: 7fbb ldrb r3, [r7, #30]
8016d1e: 4a30 ldr r2, [pc, #192] ; (8016de0 <dhcp_select+0x1e4>)
8016d20: 5cd3 ldrb r3, [r2, r3]
8016d22: 461a mov r2, r3
8016d24: f000 ffa6 bl 8017c74 <dhcp_option_byte>
8016d28: 4603 mov r3, r0
8016d2a: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8016d2c: 7fbb ldrb r3, [r7, #30]
8016d2e: 3301 adds r3, #1
8016d30: 77bb strb r3, [r7, #30]
8016d32: 7fbb ldrb r3, [r7, #30]
8016d34: 2b02 cmp r3, #2
8016d36: d9ed bls.n 8016d14 <dhcp_select+0x118>
#if LWIP_NETIF_HOSTNAME
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
#endif /* LWIP_NETIF_HOSTNAME */
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REQUESTING, msg_out, DHCP_REQUEST, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
8016d38: 89b8 ldrh r0, [r7, #12]
8016d3a: 693b ldr r3, [r7, #16]
8016d3c: 33f0 adds r3, #240 ; 0xf0
8016d3e: 697a ldr r2, [r7, #20]
8016d40: 4619 mov r1, r3
8016d42: f001 fcab bl 801869c <dhcp_option_trailer>
/* send broadcast to any DHCP server */
result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
8016d46: 4b27 ldr r3, [pc, #156] ; (8016de4 <dhcp_select+0x1e8>)
8016d48: 6818 ldr r0, [r3, #0]
8016d4a: 4b27 ldr r3, [pc, #156] ; (8016de8 <dhcp_select+0x1ec>)
8016d4c: 9301 str r3, [sp, #4]
8016d4e: 687b ldr r3, [r7, #4]
8016d50: 9300 str r3, [sp, #0]
8016d52: 2343 movs r3, #67 ; 0x43
8016d54: 4a25 ldr r2, [pc, #148] ; (8016dec <dhcp_select+0x1f0>)
8016d56: 6979 ldr r1, [r7, #20]
8016d58: f7ff fbda bl 8016510 <udp_sendto_if_src>
8016d5c: 4603 mov r3, r0
8016d5e: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
8016d60: 6978 ldr r0, [r7, #20]
8016d62: f7f9 fc23 bl 80105ac <pbuf_free>
8016d66: e001 b.n 8016d6c <dhcp_select+0x170>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n"));
result = ERR_MEM;
8016d68: 23ff movs r3, #255 ; 0xff
8016d6a: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
8016d6c: 69bb ldr r3, [r7, #24]
8016d6e: 799b ldrb r3, [r3, #6]
8016d70: 2bff cmp r3, #255 ; 0xff
8016d72: d005 beq.n 8016d80 <dhcp_select+0x184>
dhcp->tries++;
8016d74: 69bb ldr r3, [r7, #24]
8016d76: 799b ldrb r3, [r3, #6]
8016d78: 3301 adds r3, #1
8016d7a: b2da uxtb r2, r3
8016d7c: 69bb ldr r3, [r7, #24]
8016d7e: 719a strb r2, [r3, #6]
}
msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000);
8016d80: 69bb ldr r3, [r7, #24]
8016d82: 799b ldrb r3, [r3, #6]
8016d84: 2b05 cmp r3, #5
8016d86: d80d bhi.n 8016da4 <dhcp_select+0x1a8>
8016d88: 69bb ldr r3, [r7, #24]
8016d8a: 799b ldrb r3, [r3, #6]
8016d8c: 461a mov r2, r3
8016d8e: 2301 movs r3, #1
8016d90: 4093 lsls r3, r2
8016d92: b29b uxth r3, r3
8016d94: 461a mov r2, r3
8016d96: 0152 lsls r2, r2, #5
8016d98: 1ad2 subs r2, r2, r3
8016d9a: 0092 lsls r2, r2, #2
8016d9c: 4413 add r3, r2
8016d9e: 00db lsls r3, r3, #3
8016da0: b29b uxth r3, r3
8016da2: e001 b.n 8016da8 <dhcp_select+0x1ac>
8016da4: f64e 2360 movw r3, #60000 ; 0xea60
8016da8: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8016daa: 89fb ldrh r3, [r7, #14]
8016dac: f203 13f3 addw r3, r3, #499 ; 0x1f3
8016db0: 4a0f ldr r2, [pc, #60] ; (8016df0 <dhcp_select+0x1f4>)
8016db2: fb82 1203 smull r1, r2, r2, r3
8016db6: 1152 asrs r2, r2, #5
8016db8: 17db asrs r3, r3, #31
8016dba: 1ad3 subs r3, r2, r3
8016dbc: b29a uxth r2, r3
8016dbe: 69bb ldr r3, [r7, #24]
8016dc0: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs));
return result;
8016dc2: f997 301f ldrsb.w r3, [r7, #31]
}
8016dc6: 4618 mov r0, r3
8016dc8: 3720 adds r7, #32
8016dca: 46bd mov sp, r7
8016dcc: bdb0 pop {r4, r5, r7, pc}
8016dce: bf00 nop
8016dd0: 0801e56c .word 0x0801e56c
8016dd4: 0801e618 .word 0x0801e618
8016dd8: 0801e5cc .word 0x0801e5cc
8016ddc: 0801e634 .word 0x0801e634
8016de0: 20000074 .word 0x20000074
8016de4: 20008760 .word 0x20008760
8016de8: 0802103c .word 0x0802103c
8016dec: 08021040 .word 0x08021040
8016df0: 10624dd3 .word 0x10624dd3
08016df4 <dhcp_coarse_tmr>:
* The DHCP timer that checks for lease renewal/rebind timeouts.
* Must be called once a minute (see @ref DHCP_COARSE_TIMER_SECS).
*/
void
dhcp_coarse_tmr(void)
{
8016df4: b580 push {r7, lr}
8016df6: b082 sub sp, #8
8016df8: af00 add r7, sp, #0
struct netif *netif;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n"));
/* iterate through all network interfaces */
NETIF_FOREACH(netif) {
8016dfa: 4b27 ldr r3, [pc, #156] ; (8016e98 <dhcp_coarse_tmr+0xa4>)
8016dfc: 681b ldr r3, [r3, #0]
8016dfe: 607b str r3, [r7, #4]
8016e00: e042 b.n 8016e88 <dhcp_coarse_tmr+0x94>
/* only act on DHCP configured interfaces */
struct dhcp *dhcp = netif_dhcp_data(netif);
8016e02: 687b ldr r3, [r7, #4]
8016e04: 6a5b ldr r3, [r3, #36] ; 0x24
8016e06: 603b str r3, [r7, #0]
if ((dhcp != NULL) && (dhcp->state != DHCP_STATE_OFF)) {
8016e08: 683b ldr r3, [r7, #0]
8016e0a: 2b00 cmp r3, #0
8016e0c: d039 beq.n 8016e82 <dhcp_coarse_tmr+0x8e>
8016e0e: 683b ldr r3, [r7, #0]
8016e10: 795b ldrb r3, [r3, #5]
8016e12: 2b00 cmp r3, #0
8016e14: d035 beq.n 8016e82 <dhcp_coarse_tmr+0x8e>
/* compare lease time to expire timeout */
if (dhcp->t0_timeout && (++dhcp->lease_used == dhcp->t0_timeout)) {
8016e16: 683b ldr r3, [r7, #0]
8016e18: 8a9b ldrh r3, [r3, #20]
8016e1a: 2b00 cmp r3, #0
8016e1c: d012 beq.n 8016e44 <dhcp_coarse_tmr+0x50>
8016e1e: 683b ldr r3, [r7, #0]
8016e20: 8a5b ldrh r3, [r3, #18]
8016e22: 3301 adds r3, #1
8016e24: b29a uxth r2, r3
8016e26: 683b ldr r3, [r7, #0]
8016e28: 825a strh r2, [r3, #18]
8016e2a: 683b ldr r3, [r7, #0]
8016e2c: 8a5a ldrh r2, [r3, #18]
8016e2e: 683b ldr r3, [r7, #0]
8016e30: 8a9b ldrh r3, [r3, #20]
8016e32: 429a cmp r2, r3
8016e34: d106 bne.n 8016e44 <dhcp_coarse_tmr+0x50>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t0 timeout\n"));
/* this clients' lease time has expired */
dhcp_release_and_stop(netif);
8016e36: 6878 ldr r0, [r7, #4]
8016e38: f000 fe34 bl 8017aa4 <dhcp_release_and_stop>
dhcp_start(netif);
8016e3c: 6878 ldr r0, [r7, #4]
8016e3e: f000 f96b bl 8017118 <dhcp_start>
8016e42: e01e b.n 8016e82 <dhcp_coarse_tmr+0x8e>
/* timer is active (non zero), and triggers (zeroes) now? */
} else if (dhcp->t2_rebind_time && (dhcp->t2_rebind_time-- == 1)) {
8016e44: 683b ldr r3, [r7, #0]
8016e46: 8a1b ldrh r3, [r3, #16]
8016e48: 2b00 cmp r3, #0
8016e4a: d00b beq.n 8016e64 <dhcp_coarse_tmr+0x70>
8016e4c: 683b ldr r3, [r7, #0]
8016e4e: 8a1b ldrh r3, [r3, #16]
8016e50: 1e5a subs r2, r3, #1
8016e52: b291 uxth r1, r2
8016e54: 683a ldr r2, [r7, #0]
8016e56: 8211 strh r1, [r2, #16]
8016e58: 2b01 cmp r3, #1
8016e5a: d103 bne.n 8016e64 <dhcp_coarse_tmr+0x70>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
/* this clients' rebind timeout triggered */
dhcp_t2_timeout(netif);
8016e5c: 6878 ldr r0, [r7, #4]
8016e5e: f000 f8c7 bl 8016ff0 <dhcp_t2_timeout>
8016e62: e00e b.n 8016e82 <dhcp_coarse_tmr+0x8e>
/* timer is active (non zero), and triggers (zeroes) now */
} else if (dhcp->t1_renew_time && (dhcp->t1_renew_time-- == 1)) {
8016e64: 683b ldr r3, [r7, #0]
8016e66: 89db ldrh r3, [r3, #14]
8016e68: 2b00 cmp r3, #0
8016e6a: d00a beq.n 8016e82 <dhcp_coarse_tmr+0x8e>
8016e6c: 683b ldr r3, [r7, #0]
8016e6e: 89db ldrh r3, [r3, #14]
8016e70: 1e5a subs r2, r3, #1
8016e72: b291 uxth r1, r2
8016e74: 683a ldr r2, [r7, #0]
8016e76: 81d1 strh r1, [r2, #14]
8016e78: 2b01 cmp r3, #1
8016e7a: d102 bne.n 8016e82 <dhcp_coarse_tmr+0x8e>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
/* this clients' renewal timeout triggered */
dhcp_t1_timeout(netif);
8016e7c: 6878 ldr r0, [r7, #4]
8016e7e: f000 f888 bl 8016f92 <dhcp_t1_timeout>
NETIF_FOREACH(netif) {
8016e82: 687b ldr r3, [r7, #4]
8016e84: 681b ldr r3, [r3, #0]
8016e86: 607b str r3, [r7, #4]
8016e88: 687b ldr r3, [r7, #4]
8016e8a: 2b00 cmp r3, #0
8016e8c: d1b9 bne.n 8016e02 <dhcp_coarse_tmr+0xe>
}
}
}
}
8016e8e: bf00 nop
8016e90: bf00 nop
8016e92: 3708 adds r7, #8
8016e94: 46bd mov sp, r7
8016e96: bd80 pop {r7, pc}
8016e98: 2000f82c .word 0x2000f82c
08016e9c <dhcp_fine_tmr>:
* A DHCP server is expected to respond within a short period of time.
* This timer checks whether an outstanding DHCP request is timed out.
*/
void
dhcp_fine_tmr(void)
{
8016e9c: b580 push {r7, lr}
8016e9e: b082 sub sp, #8
8016ea0: af00 add r7, sp, #0
struct netif *netif;
/* loop through netif's */
NETIF_FOREACH(netif) {
8016ea2: 4b16 ldr r3, [pc, #88] ; (8016efc <dhcp_fine_tmr+0x60>)
8016ea4: 681b ldr r3, [r3, #0]
8016ea6: 607b str r3, [r7, #4]
8016ea8: e020 b.n 8016eec <dhcp_fine_tmr+0x50>
struct dhcp *dhcp = netif_dhcp_data(netif);
8016eaa: 687b ldr r3, [r7, #4]
8016eac: 6a5b ldr r3, [r3, #36] ; 0x24
8016eae: 603b str r3, [r7, #0]
/* only act on DHCP configured interfaces */
if (dhcp != NULL) {
8016eb0: 683b ldr r3, [r7, #0]
8016eb2: 2b00 cmp r3, #0
8016eb4: d017 beq.n 8016ee6 <dhcp_fine_tmr+0x4a>
/* timer is active (non zero), and is about to trigger now */
if (dhcp->request_timeout > 1) {
8016eb6: 683b ldr r3, [r7, #0]
8016eb8: 891b ldrh r3, [r3, #8]
8016eba: 2b01 cmp r3, #1
8016ebc: d906 bls.n 8016ecc <dhcp_fine_tmr+0x30>
dhcp->request_timeout--;
8016ebe: 683b ldr r3, [r7, #0]
8016ec0: 891b ldrh r3, [r3, #8]
8016ec2: 3b01 subs r3, #1
8016ec4: b29a uxth r2, r3
8016ec6: 683b ldr r3, [r7, #0]
8016ec8: 811a strh r2, [r3, #8]
8016eca: e00c b.n 8016ee6 <dhcp_fine_tmr+0x4a>
} else if (dhcp->request_timeout == 1) {
8016ecc: 683b ldr r3, [r7, #0]
8016ece: 891b ldrh r3, [r3, #8]
8016ed0: 2b01 cmp r3, #1
8016ed2: d108 bne.n 8016ee6 <dhcp_fine_tmr+0x4a>
dhcp->request_timeout--;
8016ed4: 683b ldr r3, [r7, #0]
8016ed6: 891b ldrh r3, [r3, #8]
8016ed8: 3b01 subs r3, #1
8016eda: b29a uxth r2, r3
8016edc: 683b ldr r3, [r7, #0]
8016ede: 811a strh r2, [r3, #8]
/* { dhcp->request_timeout == 0 } */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
/* this client's request timeout triggered */
dhcp_timeout(netif);
8016ee0: 6878 ldr r0, [r7, #4]
8016ee2: f000 f80d bl 8016f00 <dhcp_timeout>
NETIF_FOREACH(netif) {
8016ee6: 687b ldr r3, [r7, #4]
8016ee8: 681b ldr r3, [r3, #0]
8016eea: 607b str r3, [r7, #4]
8016eec: 687b ldr r3, [r7, #4]
8016eee: 2b00 cmp r3, #0
8016ef0: d1db bne.n 8016eaa <dhcp_fine_tmr+0xe>
}
}
}
}
8016ef2: bf00 nop
8016ef4: bf00 nop
8016ef6: 3708 adds r7, #8
8016ef8: 46bd mov sp, r7
8016efa: bd80 pop {r7, pc}
8016efc: 2000f82c .word 0x2000f82c
08016f00 <dhcp_timeout>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_timeout(struct netif *netif)
{
8016f00: b580 push {r7, lr}
8016f02: b084 sub sp, #16
8016f04: af00 add r7, sp, #0
8016f06: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016f08: 687b ldr r3, [r7, #4]
8016f0a: 6a5b ldr r3, [r3, #36] ; 0x24
8016f0c: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n"));
/* back-off period has passed, or server selection timed out */
if ((dhcp->state == DHCP_STATE_BACKING_OFF) || (dhcp->state == DHCP_STATE_SELECTING)) {
8016f0e: 68fb ldr r3, [r7, #12]
8016f10: 795b ldrb r3, [r3, #5]
8016f12: 2b0c cmp r3, #12
8016f14: d003 beq.n 8016f1e <dhcp_timeout+0x1e>
8016f16: 68fb ldr r3, [r7, #12]
8016f18: 795b ldrb r3, [r3, #5]
8016f1a: 2b06 cmp r3, #6
8016f1c: d103 bne.n 8016f26 <dhcp_timeout+0x26>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
dhcp_discover(netif);
8016f1e: 6878 ldr r0, [r7, #4]
8016f20: f000 fa56 bl 80173d0 <dhcp_discover>
dhcp_reboot(netif);
} else {
dhcp_discover(netif);
}
}
}
8016f24: e031 b.n 8016f8a <dhcp_timeout+0x8a>
} else if (dhcp->state == DHCP_STATE_REQUESTING) {
8016f26: 68fb ldr r3, [r7, #12]
8016f28: 795b ldrb r3, [r3, #5]
8016f2a: 2b01 cmp r3, #1
8016f2c: d10e bne.n 8016f4c <dhcp_timeout+0x4c>
if (dhcp->tries <= 5) {
8016f2e: 68fb ldr r3, [r7, #12]
8016f30: 799b ldrb r3, [r3, #6]
8016f32: 2b05 cmp r3, #5
8016f34: d803 bhi.n 8016f3e <dhcp_timeout+0x3e>
dhcp_select(netif);
8016f36: 6878 ldr r0, [r7, #4]
8016f38: f7ff fe60 bl 8016bfc <dhcp_select>
}
8016f3c: e025 b.n 8016f8a <dhcp_timeout+0x8a>
dhcp_release_and_stop(netif);
8016f3e: 6878 ldr r0, [r7, #4]
8016f40: f000 fdb0 bl 8017aa4 <dhcp_release_and_stop>
dhcp_start(netif);
8016f44: 6878 ldr r0, [r7, #4]
8016f46: f000 f8e7 bl 8017118 <dhcp_start>
}
8016f4a: e01e b.n 8016f8a <dhcp_timeout+0x8a>
} else if (dhcp->state == DHCP_STATE_CHECKING) {
8016f4c: 68fb ldr r3, [r7, #12]
8016f4e: 795b ldrb r3, [r3, #5]
8016f50: 2b08 cmp r3, #8
8016f52: d10b bne.n 8016f6c <dhcp_timeout+0x6c>
if (dhcp->tries <= 1) {
8016f54: 68fb ldr r3, [r7, #12]
8016f56: 799b ldrb r3, [r3, #6]
8016f58: 2b01 cmp r3, #1
8016f5a: d803 bhi.n 8016f64 <dhcp_timeout+0x64>
dhcp_check(netif);
8016f5c: 6878 ldr r0, [r7, #4]
8016f5e: f7ff fdf3 bl 8016b48 <dhcp_check>
}
8016f62: e012 b.n 8016f8a <dhcp_timeout+0x8a>
dhcp_bind(netif);
8016f64: 6878 ldr r0, [r7, #4]
8016f66: f000 fad5 bl 8017514 <dhcp_bind>
}
8016f6a: e00e b.n 8016f8a <dhcp_timeout+0x8a>
} else if (dhcp->state == DHCP_STATE_REBOOTING) {
8016f6c: 68fb ldr r3, [r7, #12]
8016f6e: 795b ldrb r3, [r3, #5]
8016f70: 2b03 cmp r3, #3
8016f72: d10a bne.n 8016f8a <dhcp_timeout+0x8a>
if (dhcp->tries < REBOOT_TRIES) {
8016f74: 68fb ldr r3, [r7, #12]
8016f76: 799b ldrb r3, [r3, #6]
8016f78: 2b01 cmp r3, #1
8016f7a: d803 bhi.n 8016f84 <dhcp_timeout+0x84>
dhcp_reboot(netif);
8016f7c: 6878 ldr r0, [r7, #4]
8016f7e: f000 fcdb bl 8017938 <dhcp_reboot>
}
8016f82: e002 b.n 8016f8a <dhcp_timeout+0x8a>
dhcp_discover(netif);
8016f84: 6878 ldr r0, [r7, #4]
8016f86: f000 fa23 bl 80173d0 <dhcp_discover>
}
8016f8a: bf00 nop
8016f8c: 3710 adds r7, #16
8016f8e: 46bd mov sp, r7
8016f90: bd80 pop {r7, pc}
08016f92 <dhcp_t1_timeout>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_t1_timeout(struct netif *netif)
{
8016f92: b580 push {r7, lr}
8016f94: b084 sub sp, #16
8016f96: af00 add r7, sp, #0
8016f98: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016f9a: 687b ldr r3, [r7, #4]
8016f9c: 6a5b ldr r3, [r3, #36] ; 0x24
8016f9e: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n"));
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
8016fa0: 68fb ldr r3, [r7, #12]
8016fa2: 795b ldrb r3, [r3, #5]
8016fa4: 2b01 cmp r3, #1
8016fa6: d007 beq.n 8016fb8 <dhcp_t1_timeout+0x26>
8016fa8: 68fb ldr r3, [r7, #12]
8016faa: 795b ldrb r3, [r3, #5]
8016fac: 2b0a cmp r3, #10
8016fae: d003 beq.n 8016fb8 <dhcp_t1_timeout+0x26>
(dhcp->state == DHCP_STATE_RENEWING)) {
8016fb0: 68fb ldr r3, [r7, #12]
8016fb2: 795b ldrb r3, [r3, #5]
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
8016fb4: 2b05 cmp r3, #5
8016fb6: d117 bne.n 8016fe8 <dhcp_t1_timeout+0x56>
* eventually time-out if renew tries fail. */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
("dhcp_t1_timeout(): must renew\n"));
/* This slightly different to RFC2131: DHCPREQUEST will be sent from state
DHCP_STATE_RENEWING, not DHCP_STATE_BOUND */
dhcp_renew(netif);
8016fb8: 6878 ldr r0, [r7, #4]
8016fba: f000 fb85 bl 80176c8 <dhcp_renew>
/* Calculate next timeout */
if (((dhcp->t2_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) {
8016fbe: 68fb ldr r3, [r7, #12]
8016fc0: 899b ldrh r3, [r3, #12]
8016fc2: 461a mov r2, r3
8016fc4: 68fb ldr r3, [r7, #12]
8016fc6: 8a5b ldrh r3, [r3, #18]
8016fc8: 1ad3 subs r3, r2, r3
8016fca: 2b01 cmp r3, #1
8016fcc: dd0c ble.n 8016fe8 <dhcp_t1_timeout+0x56>
dhcp->t1_renew_time = (u16_t)((dhcp->t2_timeout - dhcp->lease_used) / 2);
8016fce: 68fb ldr r3, [r7, #12]
8016fd0: 899b ldrh r3, [r3, #12]
8016fd2: 461a mov r2, r3
8016fd4: 68fb ldr r3, [r7, #12]
8016fd6: 8a5b ldrh r3, [r3, #18]
8016fd8: 1ad3 subs r3, r2, r3
8016fda: 2b00 cmp r3, #0
8016fdc: da00 bge.n 8016fe0 <dhcp_t1_timeout+0x4e>
8016fde: 3301 adds r3, #1
8016fe0: 105b asrs r3, r3, #1
8016fe2: b29a uxth r2, r3
8016fe4: 68fb ldr r3, [r7, #12]
8016fe6: 81da strh r2, [r3, #14]
}
}
}
8016fe8: bf00 nop
8016fea: 3710 adds r7, #16
8016fec: 46bd mov sp, r7
8016fee: bd80 pop {r7, pc}
08016ff0 <dhcp_t2_timeout>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_t2_timeout(struct netif *netif)
{
8016ff0: b580 push {r7, lr}
8016ff2: b084 sub sp, #16
8016ff4: af00 add r7, sp, #0
8016ff6: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016ff8: 687b ldr r3, [r7, #4]
8016ffa: 6a5b ldr r3, [r3, #36] ; 0x24
8016ffc: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n"));
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
8016ffe: 68fb ldr r3, [r7, #12]
8017000: 795b ldrb r3, [r3, #5]
8017002: 2b01 cmp r3, #1
8017004: d00b beq.n 801701e <dhcp_t2_timeout+0x2e>
8017006: 68fb ldr r3, [r7, #12]
8017008: 795b ldrb r3, [r3, #5]
801700a: 2b0a cmp r3, #10
801700c: d007 beq.n 801701e <dhcp_t2_timeout+0x2e>
(dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) {
801700e: 68fb ldr r3, [r7, #12]
8017010: 795b ldrb r3, [r3, #5]
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
8017012: 2b05 cmp r3, #5
8017014: d003 beq.n 801701e <dhcp_t2_timeout+0x2e>
(dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) {
8017016: 68fb ldr r3, [r7, #12]
8017018: 795b ldrb r3, [r3, #5]
801701a: 2b04 cmp r3, #4
801701c: d117 bne.n 801704e <dhcp_t2_timeout+0x5e>
/* just retry to rebind */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
("dhcp_t2_timeout(): must rebind\n"));
/* This slightly different to RFC2131: DHCPREQUEST will be sent from state
DHCP_STATE_REBINDING, not DHCP_STATE_BOUND */
dhcp_rebind(netif);
801701e: 6878 ldr r0, [r7, #4]
8017020: f000 fbee bl 8017800 <dhcp_rebind>
/* Calculate next timeout */
if (((dhcp->t0_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) {
8017024: 68fb ldr r3, [r7, #12]
8017026: 8a9b ldrh r3, [r3, #20]
8017028: 461a mov r2, r3
801702a: 68fb ldr r3, [r7, #12]
801702c: 8a5b ldrh r3, [r3, #18]
801702e: 1ad3 subs r3, r2, r3
8017030: 2b01 cmp r3, #1
8017032: dd0c ble.n 801704e <dhcp_t2_timeout+0x5e>
dhcp->t2_rebind_time = (u16_t)((dhcp->t0_timeout - dhcp->lease_used) / 2);
8017034: 68fb ldr r3, [r7, #12]
8017036: 8a9b ldrh r3, [r3, #20]
8017038: 461a mov r2, r3
801703a: 68fb ldr r3, [r7, #12]
801703c: 8a5b ldrh r3, [r3, #18]
801703e: 1ad3 subs r3, r2, r3
8017040: 2b00 cmp r3, #0
8017042: da00 bge.n 8017046 <dhcp_t2_timeout+0x56>
8017044: 3301 adds r3, #1
8017046: 105b asrs r3, r3, #1
8017048: b29a uxth r2, r3
801704a: 68fb ldr r3, [r7, #12]
801704c: 821a strh r2, [r3, #16]
}
}
}
801704e: bf00 nop
8017050: 3710 adds r7, #16
8017052: 46bd mov sp, r7
8017054: bd80 pop {r7, pc}
...
08017058 <dhcp_handle_ack>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_handle_ack(struct netif *netif, struct dhcp_msg *msg_in)
{
8017058: b580 push {r7, lr}
801705a: b084 sub sp, #16
801705c: af00 add r7, sp, #0
801705e: 6078 str r0, [r7, #4]
8017060: 6039 str r1, [r7, #0]
struct dhcp *dhcp = netif_dhcp_data(netif);
8017062: 687b ldr r3, [r7, #4]
8017064: 6a5b ldr r3, [r3, #36] ; 0x24
8017066: 60fb str r3, [r7, #12]
#if LWIP_DHCP_GET_NTP_SRV
ip4_addr_t ntp_server_addrs[LWIP_DHCP_MAX_NTP_SERVERS];
#endif
/* clear options we might not get from the ACK */
ip4_addr_set_zero(&dhcp->offered_sn_mask);
8017068: 68fb ldr r3, [r7, #12]
801706a: 2200 movs r2, #0
801706c: 621a str r2, [r3, #32]
ip4_addr_set_zero(&dhcp->offered_gw_addr);
801706e: 68fb ldr r3, [r7, #12]
8017070: 2200 movs r2, #0
8017072: 625a str r2, [r3, #36] ; 0x24
#if LWIP_DHCP_BOOTP_FILE
ip4_addr_set_zero(&dhcp->offered_si_addr);
#endif /* LWIP_DHCP_BOOTP_FILE */
/* lease time given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_LEASE_TIME)) {
8017074: 4b26 ldr r3, [pc, #152] ; (8017110 <dhcp_handle_ack+0xb8>)
8017076: 78db ldrb r3, [r3, #3]
8017078: 2b00 cmp r3, #0
801707a: d003 beq.n 8017084 <dhcp_handle_ack+0x2c>
/* remember offered lease time */
dhcp->offered_t0_lease = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_LEASE_TIME);
801707c: 4b25 ldr r3, [pc, #148] ; (8017114 <dhcp_handle_ack+0xbc>)
801707e: 68da ldr r2, [r3, #12]
8017080: 68fb ldr r3, [r7, #12]
8017082: 629a str r2, [r3, #40] ; 0x28
}
/* renewal period given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T1)) {
8017084: 4b22 ldr r3, [pc, #136] ; (8017110 <dhcp_handle_ack+0xb8>)
8017086: 791b ldrb r3, [r3, #4]
8017088: 2b00 cmp r3, #0
801708a: d004 beq.n 8017096 <dhcp_handle_ack+0x3e>
/* remember given renewal period */
dhcp->offered_t1_renew = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T1);
801708c: 4b21 ldr r3, [pc, #132] ; (8017114 <dhcp_handle_ack+0xbc>)
801708e: 691a ldr r2, [r3, #16]
8017090: 68fb ldr r3, [r7, #12]
8017092: 62da str r2, [r3, #44] ; 0x2c
8017094: e004 b.n 80170a0 <dhcp_handle_ack+0x48>
} else {
/* calculate safe periods for renewal */
dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
8017096: 68fb ldr r3, [r7, #12]
8017098: 6a9b ldr r3, [r3, #40] ; 0x28
801709a: 085a lsrs r2, r3, #1
801709c: 68fb ldr r3, [r7, #12]
801709e: 62da str r2, [r3, #44] ; 0x2c
}
/* renewal period given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T2)) {
80170a0: 4b1b ldr r3, [pc, #108] ; (8017110 <dhcp_handle_ack+0xb8>)
80170a2: 795b ldrb r3, [r3, #5]
80170a4: 2b00 cmp r3, #0
80170a6: d004 beq.n 80170b2 <dhcp_handle_ack+0x5a>
/* remember given rebind period */
dhcp->offered_t2_rebind = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T2);
80170a8: 4b1a ldr r3, [pc, #104] ; (8017114 <dhcp_handle_ack+0xbc>)
80170aa: 695a ldr r2, [r3, #20]
80170ac: 68fb ldr r3, [r7, #12]
80170ae: 631a str r2, [r3, #48] ; 0x30
80170b0: e007 b.n 80170c2 <dhcp_handle_ack+0x6a>
} else {
/* calculate safe periods for rebinding (offered_t0_lease * 0.875 -> 87.5%)*/
dhcp->offered_t2_rebind = (dhcp->offered_t0_lease * 7U) / 8U;
80170b2: 68fb ldr r3, [r7, #12]
80170b4: 6a9a ldr r2, [r3, #40] ; 0x28
80170b6: 4613 mov r3, r2
80170b8: 00db lsls r3, r3, #3
80170ba: 1a9b subs r3, r3, r2
80170bc: 08da lsrs r2, r3, #3
80170be: 68fb ldr r3, [r7, #12]
80170c0: 631a str r2, [r3, #48] ; 0x30
}
/* (y)our internet address */
ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr);
80170c2: 683b ldr r3, [r7, #0]
80170c4: 691a ldr r2, [r3, #16]
80170c6: 68fb ldr r3, [r7, #12]
80170c8: 61da str r2, [r3, #28]
boot file name copied in dhcp_parse_reply if not overloaded */
ip4_addr_copy(dhcp->offered_si_addr, msg_in->siaddr);
#endif /* LWIP_DHCP_BOOTP_FILE */
/* subnet mask given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)) {
80170ca: 4b11 ldr r3, [pc, #68] ; (8017110 <dhcp_handle_ack+0xb8>)
80170cc: 799b ldrb r3, [r3, #6]
80170ce: 2b00 cmp r3, #0
80170d0: d00b beq.n 80170ea <dhcp_handle_ack+0x92>
/* remember given subnet mask */
ip4_addr_set_u32(&dhcp->offered_sn_mask, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)));
80170d2: 4b10 ldr r3, [pc, #64] ; (8017114 <dhcp_handle_ack+0xbc>)
80170d4: 699b ldr r3, [r3, #24]
80170d6: 4618 mov r0, r3
80170d8: f7f7 fec5 bl 800ee66 <lwip_htonl>
80170dc: 4602 mov r2, r0
80170de: 68fb ldr r3, [r7, #12]
80170e0: 621a str r2, [r3, #32]
dhcp->subnet_mask_given = 1;
80170e2: 68fb ldr r3, [r7, #12]
80170e4: 2201 movs r2, #1
80170e6: 71da strb r2, [r3, #7]
80170e8: e002 b.n 80170f0 <dhcp_handle_ack+0x98>
} else {
dhcp->subnet_mask_given = 0;
80170ea: 68fb ldr r3, [r7, #12]
80170ec: 2200 movs r2, #0
80170ee: 71da strb r2, [r3, #7]
}
/* gateway router */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_ROUTER)) {
80170f0: 4b07 ldr r3, [pc, #28] ; (8017110 <dhcp_handle_ack+0xb8>)
80170f2: 79db ldrb r3, [r3, #7]
80170f4: 2b00 cmp r3, #0
80170f6: d007 beq.n 8017108 <dhcp_handle_ack+0xb0>
ip4_addr_set_u32(&dhcp->offered_gw_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_ROUTER)));
80170f8: 4b06 ldr r3, [pc, #24] ; (8017114 <dhcp_handle_ack+0xbc>)
80170fa: 69db ldr r3, [r3, #28]
80170fc: 4618 mov r0, r3
80170fe: f7f7 feb2 bl 800ee66 <lwip_htonl>
8017102: 4602 mov r2, r0
8017104: 68fb ldr r3, [r7, #12]
8017106: 625a str r2, [r3, #36] ; 0x24
ip_addr_t dns_addr;
ip_addr_set_ip4_u32_val(dns_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n)));
dns_setserver(n, &dns_addr);
}
#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
}
8017108: bf00 nop
801710a: 3710 adds r7, #16
801710c: 46bd mov sp, r7
801710e: bd80 pop {r7, pc}
8017110: 2000f858 .word 0x2000f858
8017114: 2000f860 .word 0x2000f860
08017118 <dhcp_start>:
* - ERR_OK - No error
* - ERR_MEM - Out of memory
*/
err_t
dhcp_start(struct netif *netif)
{
8017118: b580 push {r7, lr}
801711a: b084 sub sp, #16
801711c: af00 add r7, sp, #0
801711e: 6078 str r0, [r7, #4]
struct dhcp *dhcp;
err_t result;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;);
8017120: 687b ldr r3, [r7, #4]
8017122: 2b00 cmp r3, #0
8017124: d109 bne.n 801713a <dhcp_start+0x22>
8017126: 4b37 ldr r3, [pc, #220] ; (8017204 <dhcp_start+0xec>)
8017128: f240 22e7 movw r2, #743 ; 0x2e7
801712c: 4936 ldr r1, [pc, #216] ; (8017208 <dhcp_start+0xf0>)
801712e: 4837 ldr r0, [pc, #220] ; (801720c <dhcp_start+0xf4>)
8017130: f003 ff48 bl 801afc4 <iprintf>
8017134: f06f 030f mvn.w r3, #15
8017138: e060 b.n 80171fc <dhcp_start+0xe4>
LWIP_ERROR("netif is not up, old style port?", netif_is_up(netif), return ERR_ARG;);
801713a: 687b ldr r3, [r7, #4]
801713c: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8017140: f003 0301 and.w r3, r3, #1
8017144: 2b00 cmp r3, #0
8017146: d109 bne.n 801715c <dhcp_start+0x44>
8017148: 4b2e ldr r3, [pc, #184] ; (8017204 <dhcp_start+0xec>)
801714a: f44f 723a mov.w r2, #744 ; 0x2e8
801714e: 4930 ldr r1, [pc, #192] ; (8017210 <dhcp_start+0xf8>)
8017150: 482e ldr r0, [pc, #184] ; (801720c <dhcp_start+0xf4>)
8017152: f003 ff37 bl 801afc4 <iprintf>
8017156: f06f 030f mvn.w r3, #15
801715a: e04f b.n 80171fc <dhcp_start+0xe4>
dhcp = netif_dhcp_data(netif);
801715c: 687b ldr r3, [r7, #4]
801715e: 6a5b ldr r3, [r3, #36] ; 0x24
8017160: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* check MTU of the netif */
if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) {
8017162: 687b ldr r3, [r7, #4]
8017164: 8d1b ldrh r3, [r3, #40] ; 0x28
8017166: f5b3 7f10 cmp.w r3, #576 ; 0x240
801716a: d202 bcs.n 8017172 <dhcp_start+0x5a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n"));
return ERR_MEM;
801716c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8017170: e044 b.n 80171fc <dhcp_start+0xe4>
}
/* no DHCP client attached yet? */
if (dhcp == NULL) {
8017172: 68fb ldr r3, [r7, #12]
8017174: 2b00 cmp r3, #0
8017176: d10d bne.n 8017194 <dhcp_start+0x7c>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): mallocing new DHCP client\n"));
dhcp = (struct dhcp *)mem_malloc(sizeof(struct dhcp));
8017178: 2034 movs r0, #52 ; 0x34
801717a: f7f8 f993 bl 800f4a4 <mem_malloc>
801717e: 60f8 str r0, [r7, #12]
if (dhcp == NULL) {
8017180: 68fb ldr r3, [r7, #12]
8017182: 2b00 cmp r3, #0
8017184: d102 bne.n 801718c <dhcp_start+0x74>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
return ERR_MEM;
8017186: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
801718a: e037 b.n 80171fc <dhcp_start+0xe4>
}
/* store this dhcp client in the netif */
netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, dhcp);
801718c: 687b ldr r3, [r7, #4]
801718e: 68fa ldr r2, [r7, #12]
8017190: 625a str r2, [r3, #36] ; 0x24
8017192: e005 b.n 80171a0 <dhcp_start+0x88>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp"));
/* already has DHCP client attached */
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n"));
if (dhcp->pcb_allocated != 0) {
8017194: 68fb ldr r3, [r7, #12]
8017196: 791b ldrb r3, [r3, #4]
8017198: 2b00 cmp r3, #0
801719a: d001 beq.n 80171a0 <dhcp_start+0x88>
dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */
801719c: f7ff fc90 bl 8016ac0 <dhcp_dec_pcb_refcount>
}
/* dhcp is cleared below, no need to reset flag*/
}
/* clear data structure */
memset(dhcp, 0, sizeof(struct dhcp));
80171a0: 2234 movs r2, #52 ; 0x34
80171a2: 2100 movs r1, #0
80171a4: 68f8 ldr r0, [r7, #12]
80171a6: f003 ff05 bl 801afb4 <memset>
/* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
if (dhcp_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP PCB is allocated */
80171aa: f7ff fc37 bl 8016a1c <dhcp_inc_pcb_refcount>
80171ae: 4603 mov r3, r0
80171b0: 2b00 cmp r3, #0
80171b2: d002 beq.n 80171ba <dhcp_start+0xa2>
return ERR_MEM;
80171b4: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
80171b8: e020 b.n 80171fc <dhcp_start+0xe4>
}
dhcp->pcb_allocated = 1;
80171ba: 68fb ldr r3, [r7, #12]
80171bc: 2201 movs r2, #1
80171be: 711a strb r2, [r3, #4]
if (!netif_is_link_up(netif)) {
80171c0: 687b ldr r3, [r7, #4]
80171c2: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
80171c6: f003 0304 and.w r3, r3, #4
80171ca: 2b00 cmp r3, #0
80171cc: d105 bne.n 80171da <dhcp_start+0xc2>
/* set state INIT and wait for dhcp_network_changed() to call dhcp_discover() */
dhcp_set_state(dhcp, DHCP_STATE_INIT);
80171ce: 2102 movs r1, #2
80171d0: 68f8 ldr r0, [r7, #12]
80171d2: f000 fd01 bl 8017bd8 <dhcp_set_state>
return ERR_OK;
80171d6: 2300 movs r3, #0
80171d8: e010 b.n 80171fc <dhcp_start+0xe4>
}
/* (re)start the DHCP negotiation */
result = dhcp_discover(netif);
80171da: 6878 ldr r0, [r7, #4]
80171dc: f000 f8f8 bl 80173d0 <dhcp_discover>
80171e0: 4603 mov r3, r0
80171e2: 72fb strb r3, [r7, #11]
if (result != ERR_OK) {
80171e4: f997 300b ldrsb.w r3, [r7, #11]
80171e8: 2b00 cmp r3, #0
80171ea: d005 beq.n 80171f8 <dhcp_start+0xe0>
/* free resources allocated above */
dhcp_release_and_stop(netif);
80171ec: 6878 ldr r0, [r7, #4]
80171ee: f000 fc59 bl 8017aa4 <dhcp_release_and_stop>
return ERR_MEM;
80171f2: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
80171f6: e001 b.n 80171fc <dhcp_start+0xe4>
}
return result;
80171f8: f997 300b ldrsb.w r3, [r7, #11]
}
80171fc: 4618 mov r0, r3
80171fe: 3710 adds r7, #16
8017200: 46bd mov sp, r7
8017202: bd80 pop {r7, pc}
8017204: 0801e56c .word 0x0801e56c
8017208: 0801e650 .word 0x0801e650
801720c: 0801e5cc .word 0x0801e5cc
8017210: 0801e694 .word 0x0801e694
08017214 <dhcp_network_changed>:
* This enters the REBOOTING state to verify that the currently bound
* address is still valid.
*/
void
dhcp_network_changed(struct netif *netif)
{
8017214: b580 push {r7, lr}
8017216: b084 sub sp, #16
8017218: af00 add r7, sp, #0
801721a: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
801721c: 687b ldr r3, [r7, #4]
801721e: 6a5b ldr r3, [r3, #36] ; 0x24
8017220: 60fb str r3, [r7, #12]
if (!dhcp) {
8017222: 68fb ldr r3, [r7, #12]
8017224: 2b00 cmp r3, #0
8017226: d025 beq.n 8017274 <dhcp_network_changed+0x60>
return;
}
switch (dhcp->state) {
8017228: 68fb ldr r3, [r7, #12]
801722a: 795b ldrb r3, [r3, #5]
801722c: 2b0a cmp r3, #10
801722e: d008 beq.n 8017242 <dhcp_network_changed+0x2e>
8017230: 2b0a cmp r3, #10
8017232: dc0d bgt.n 8017250 <dhcp_network_changed+0x3c>
8017234: 2b00 cmp r3, #0
8017236: d01f beq.n 8017278 <dhcp_network_changed+0x64>
8017238: 2b00 cmp r3, #0
801723a: db09 blt.n 8017250 <dhcp_network_changed+0x3c>
801723c: 3b03 subs r3, #3
801723e: 2b02 cmp r3, #2
8017240: d806 bhi.n 8017250 <dhcp_network_changed+0x3c>
case DHCP_STATE_REBINDING:
case DHCP_STATE_RENEWING:
case DHCP_STATE_BOUND:
case DHCP_STATE_REBOOTING:
dhcp->tries = 0;
8017242: 68fb ldr r3, [r7, #12]
8017244: 2200 movs r2, #0
8017246: 719a strb r2, [r3, #6]
dhcp_reboot(netif);
8017248: 6878 ldr r0, [r7, #4]
801724a: f000 fb75 bl 8017938 <dhcp_reboot>
break;
801724e: e014 b.n 801727a <dhcp_network_changed+0x66>
case DHCP_STATE_OFF:
/* stay off */
break;
default:
LWIP_ASSERT("invalid dhcp->state", dhcp->state <= DHCP_STATE_BACKING_OFF);
8017250: 68fb ldr r3, [r7, #12]
8017252: 795b ldrb r3, [r3, #5]
8017254: 2b0c cmp r3, #12
8017256: d906 bls.n 8017266 <dhcp_network_changed+0x52>
8017258: 4b09 ldr r3, [pc, #36] ; (8017280 <dhcp_network_changed+0x6c>)
801725a: f240 326d movw r2, #877 ; 0x36d
801725e: 4909 ldr r1, [pc, #36] ; (8017284 <dhcp_network_changed+0x70>)
8017260: 4809 ldr r0, [pc, #36] ; (8017288 <dhcp_network_changed+0x74>)
8017262: f003 feaf bl 801afc4 <iprintf>
autoip_stop(netif);
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
/* ensure we start with short timeouts, even if already discovering */
dhcp->tries = 0;
8017266: 68fb ldr r3, [r7, #12]
8017268: 2200 movs r2, #0
801726a: 719a strb r2, [r3, #6]
dhcp_discover(netif);
801726c: 6878 ldr r0, [r7, #4]
801726e: f000 f8af bl 80173d0 <dhcp_discover>
break;
8017272: e002 b.n 801727a <dhcp_network_changed+0x66>
return;
8017274: bf00 nop
8017276: e000 b.n 801727a <dhcp_network_changed+0x66>
break;
8017278: bf00 nop
}
}
801727a: 3710 adds r7, #16
801727c: 46bd mov sp, r7
801727e: bd80 pop {r7, pc}
8017280: 0801e56c .word 0x0801e56c
8017284: 0801e6b8 .word 0x0801e6b8
8017288: 0801e5cc .word 0x0801e5cc
0801728c <dhcp_arp_reply>:
* @param netif the network interface on which the reply was received
* @param addr The IP address we received a reply from
*/
void
dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr)
{
801728c: b580 push {r7, lr}
801728e: b084 sub sp, #16
8017290: af00 add r7, sp, #0
8017292: 6078 str r0, [r7, #4]
8017294: 6039 str r1, [r7, #0]
struct dhcp *dhcp;
LWIP_ERROR("netif != NULL", (netif != NULL), return;);
8017296: 687b ldr r3, [r7, #4]
8017298: 2b00 cmp r3, #0
801729a: d107 bne.n 80172ac <dhcp_arp_reply+0x20>
801729c: 4b0e ldr r3, [pc, #56] ; (80172d8 <dhcp_arp_reply+0x4c>)
801729e: f240 328b movw r2, #907 ; 0x38b
80172a2: 490e ldr r1, [pc, #56] ; (80172dc <dhcp_arp_reply+0x50>)
80172a4: 480e ldr r0, [pc, #56] ; (80172e0 <dhcp_arp_reply+0x54>)
80172a6: f003 fe8d bl 801afc4 <iprintf>
80172aa: e012 b.n 80172d2 <dhcp_arp_reply+0x46>
dhcp = netif_dhcp_data(netif);
80172ac: 687b ldr r3, [r7, #4]
80172ae: 6a5b ldr r3, [r3, #36] ; 0x24
80172b0: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n"));
/* is a DHCP client doing an ARP check? */
if ((dhcp != NULL) && (dhcp->state == DHCP_STATE_CHECKING)) {
80172b2: 68fb ldr r3, [r7, #12]
80172b4: 2b00 cmp r3, #0
80172b6: d00c beq.n 80172d2 <dhcp_arp_reply+0x46>
80172b8: 68fb ldr r3, [r7, #12]
80172ba: 795b ldrb r3, [r3, #5]
80172bc: 2b08 cmp r3, #8
80172be: d108 bne.n 80172d2 <dhcp_arp_reply+0x46>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n",
ip4_addr_get_u32(addr)));
/* did a host respond with the address we
were offered by the DHCP server? */
if (ip4_addr_cmp(addr, &dhcp->offered_ip_addr)) {
80172c0: 683b ldr r3, [r7, #0]
80172c2: 681a ldr r2, [r3, #0]
80172c4: 68fb ldr r3, [r7, #12]
80172c6: 69db ldr r3, [r3, #28]
80172c8: 429a cmp r2, r3
80172ca: d102 bne.n 80172d2 <dhcp_arp_reply+0x46>
/* we will not accept the offered address */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
dhcp_decline(netif);
80172cc: 6878 ldr r0, [r7, #4]
80172ce: f000 f809 bl 80172e4 <dhcp_decline>
}
}
}
80172d2: 3710 adds r7, #16
80172d4: 46bd mov sp, r7
80172d6: bd80 pop {r7, pc}
80172d8: 0801e56c .word 0x0801e56c
80172dc: 0801e650 .word 0x0801e650
80172e0: 0801e5cc .word 0x0801e5cc
080172e4 <dhcp_decline>:
*
* @param netif the netif under DHCP control
*/
static err_t
dhcp_decline(struct netif *netif)
{
80172e4: b5b0 push {r4, r5, r7, lr}
80172e6: b08a sub sp, #40 ; 0x28
80172e8: af02 add r7, sp, #8
80172ea: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
80172ec: 687b ldr r3, [r7, #4]
80172ee: 6a5b ldr r3, [r3, #36] ; 0x24
80172f0: 61bb str r3, [r7, #24]
u16_t msecs;
struct pbuf *p_out;
u16_t options_out_len;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n"));
dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF);
80172f2: 210c movs r1, #12
80172f4: 69b8 ldr r0, [r7, #24]
80172f6: f000 fc6f bl 8017bd8 <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_DECLINE, &options_out_len);
80172fa: f107 030c add.w r3, r7, #12
80172fe: 2204 movs r2, #4
8017300: 69b9 ldr r1, [r7, #24]
8017302: 6878 ldr r0, [r7, #4]
8017304: f001 f8f4 bl 80184f0 <dhcp_create_msg>
8017308: 6178 str r0, [r7, #20]
if (p_out != NULL) {
801730a: 697b ldr r3, [r7, #20]
801730c: 2b00 cmp r3, #0
801730e: d035 beq.n 801737c <dhcp_decline+0x98>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8017310: 697b ldr r3, [r7, #20]
8017312: 685b ldr r3, [r3, #4]
8017314: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
8017316: 89b8 ldrh r0, [r7, #12]
8017318: 693b ldr r3, [r7, #16]
801731a: f103 01f0 add.w r1, r3, #240 ; 0xf0
801731e: 2304 movs r3, #4
8017320: 2232 movs r2, #50 ; 0x32
8017322: f000 fc73 bl 8017c0c <dhcp_option>
8017326: 4603 mov r3, r0
8017328: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
801732a: 89bc ldrh r4, [r7, #12]
801732c: 693b ldr r3, [r7, #16]
801732e: f103 05f0 add.w r5, r3, #240 ; 0xf0
8017332: 69bb ldr r3, [r7, #24]
8017334: 69db ldr r3, [r3, #28]
8017336: 4618 mov r0, r3
8017338: f7f7 fd95 bl 800ee66 <lwip_htonl>
801733c: 4603 mov r3, r0
801733e: 461a mov r2, r3
8017340: 4629 mov r1, r5
8017342: 4620 mov r0, r4
8017344: f000 fcee bl 8017d24 <dhcp_option_long>
8017348: 4603 mov r3, r0
801734a: 81bb strh r3, [r7, #12]
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_BACKING_OFF, msg_out, DHCP_DECLINE, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
801734c: 89b8 ldrh r0, [r7, #12]
801734e: 693b ldr r3, [r7, #16]
8017350: 33f0 adds r3, #240 ; 0xf0
8017352: 697a ldr r2, [r7, #20]
8017354: 4619 mov r1, r3
8017356: f001 f9a1 bl 801869c <dhcp_option_trailer>
/* per section 4.4.4, broadcast DECLINE messages */
result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
801735a: 4b19 ldr r3, [pc, #100] ; (80173c0 <dhcp_decline+0xdc>)
801735c: 6818 ldr r0, [r3, #0]
801735e: 4b19 ldr r3, [pc, #100] ; (80173c4 <dhcp_decline+0xe0>)
8017360: 9301 str r3, [sp, #4]
8017362: 687b ldr r3, [r7, #4]
8017364: 9300 str r3, [sp, #0]
8017366: 2343 movs r3, #67 ; 0x43
8017368: 4a17 ldr r2, [pc, #92] ; (80173c8 <dhcp_decline+0xe4>)
801736a: 6979 ldr r1, [r7, #20]
801736c: f7ff f8d0 bl 8016510 <udp_sendto_if_src>
8017370: 4603 mov r3, r0
8017372: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
8017374: 6978 ldr r0, [r7, #20]
8017376: f7f9 f919 bl 80105ac <pbuf_free>
801737a: e001 b.n 8017380 <dhcp_decline+0x9c>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("dhcp_decline: could not allocate DHCP request\n"));
result = ERR_MEM;
801737c: 23ff movs r3, #255 ; 0xff
801737e: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
8017380: 69bb ldr r3, [r7, #24]
8017382: 799b ldrb r3, [r3, #6]
8017384: 2bff cmp r3, #255 ; 0xff
8017386: d005 beq.n 8017394 <dhcp_decline+0xb0>
dhcp->tries++;
8017388: 69bb ldr r3, [r7, #24]
801738a: 799b ldrb r3, [r3, #6]
801738c: 3301 adds r3, #1
801738e: b2da uxtb r2, r3
8017390: 69bb ldr r3, [r7, #24]
8017392: 719a strb r2, [r3, #6]
}
msecs = 10 * 1000;
8017394: f242 7310 movw r3, #10000 ; 0x2710
8017398: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
801739a: 89fb ldrh r3, [r7, #14]
801739c: f203 13f3 addw r3, r3, #499 ; 0x1f3
80173a0: 4a0a ldr r2, [pc, #40] ; (80173cc <dhcp_decline+0xe8>)
80173a2: fb82 1203 smull r1, r2, r2, r3
80173a6: 1152 asrs r2, r2, #5
80173a8: 17db asrs r3, r3, #31
80173aa: 1ad3 subs r3, r2, r3
80173ac: b29a uxth r2, r3
80173ae: 69bb ldr r3, [r7, #24]
80173b0: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs));
return result;
80173b2: f997 301f ldrsb.w r3, [r7, #31]
}
80173b6: 4618 mov r0, r3
80173b8: 3720 adds r7, #32
80173ba: 46bd mov sp, r7
80173bc: bdb0 pop {r4, r5, r7, pc}
80173be: bf00 nop
80173c0: 20008760 .word 0x20008760
80173c4: 0802103c .word 0x0802103c
80173c8: 08021040 .word 0x08021040
80173cc: 10624dd3 .word 0x10624dd3
080173d0 <dhcp_discover>:
*
* @param netif the netif under DHCP control
*/
static err_t
dhcp_discover(struct netif *netif)
{
80173d0: b580 push {r7, lr}
80173d2: b08a sub sp, #40 ; 0x28
80173d4: af02 add r7, sp, #8
80173d6: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
80173d8: 687b ldr r3, [r7, #4]
80173da: 6a5b ldr r3, [r3, #36] ; 0x24
80173dc: 61bb str r3, [r7, #24]
err_t result = ERR_OK;
80173de: 2300 movs r3, #0
80173e0: 75fb strb r3, [r7, #23]
struct pbuf *p_out;
u16_t options_out_len;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n"));
ip4_addr_set_any(&dhcp->offered_ip_addr);
80173e2: 69bb ldr r3, [r7, #24]
80173e4: 2200 movs r2, #0
80173e6: 61da str r2, [r3, #28]
dhcp_set_state(dhcp, DHCP_STATE_SELECTING);
80173e8: 2106 movs r1, #6
80173ea: 69b8 ldr r0, [r7, #24]
80173ec: f000 fbf4 bl 8017bd8 <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_DISCOVER, &options_out_len);
80173f0: f107 0308 add.w r3, r7, #8
80173f4: 2201 movs r2, #1
80173f6: 69b9 ldr r1, [r7, #24]
80173f8: 6878 ldr r0, [r7, #4]
80173fa: f001 f879 bl 80184f0 <dhcp_create_msg>
80173fe: 6138 str r0, [r7, #16]
if (p_out != NULL) {
8017400: 693b ldr r3, [r7, #16]
8017402: 2b00 cmp r3, #0
8017404: d04b beq.n 801749e <dhcp_discover+0xce>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8017406: 693b ldr r3, [r7, #16]
8017408: 685b ldr r3, [r3, #4]
801740a: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n"));
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
801740c: 8938 ldrh r0, [r7, #8]
801740e: 68fb ldr r3, [r7, #12]
8017410: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017414: 2302 movs r3, #2
8017416: 2239 movs r2, #57 ; 0x39
8017418: f000 fbf8 bl 8017c0c <dhcp_option>
801741c: 4603 mov r3, r0
801741e: 813b strh r3, [r7, #8]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
8017420: 8938 ldrh r0, [r7, #8]
8017422: 68fb ldr r3, [r7, #12]
8017424: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017428: 687b ldr r3, [r7, #4]
801742a: 8d1b ldrh r3, [r3, #40] ; 0x28
801742c: 461a mov r2, r3
801742e: f000 fc47 bl 8017cc0 <dhcp_option_short>
8017432: 4603 mov r3, r0
8017434: 813b strh r3, [r7, #8]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
8017436: 8938 ldrh r0, [r7, #8]
8017438: 68fb ldr r3, [r7, #12]
801743a: f103 01f0 add.w r1, r3, #240 ; 0xf0
801743e: 2303 movs r3, #3
8017440: 2237 movs r2, #55 ; 0x37
8017442: f000 fbe3 bl 8017c0c <dhcp_option>
8017446: 4603 mov r3, r0
8017448: 813b strh r3, [r7, #8]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
801744a: 2300 movs r3, #0
801744c: 77fb strb r3, [r7, #31]
801744e: e00e b.n 801746e <dhcp_discover+0x9e>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
8017450: 8938 ldrh r0, [r7, #8]
8017452: 68fb ldr r3, [r7, #12]
8017454: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017458: 7ffb ldrb r3, [r7, #31]
801745a: 4a29 ldr r2, [pc, #164] ; (8017500 <dhcp_discover+0x130>)
801745c: 5cd3 ldrb r3, [r2, r3]
801745e: 461a mov r2, r3
8017460: f000 fc08 bl 8017c74 <dhcp_option_byte>
8017464: 4603 mov r3, r0
8017466: 813b strh r3, [r7, #8]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8017468: 7ffb ldrb r3, [r7, #31]
801746a: 3301 adds r3, #1
801746c: 77fb strb r3, [r7, #31]
801746e: 7ffb ldrb r3, [r7, #31]
8017470: 2b02 cmp r3, #2
8017472: d9ed bls.n 8017450 <dhcp_discover+0x80>
}
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_SELECTING, msg_out, DHCP_DISCOVER, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
8017474: 8938 ldrh r0, [r7, #8]
8017476: 68fb ldr r3, [r7, #12]
8017478: 33f0 adds r3, #240 ; 0xf0
801747a: 693a ldr r2, [r7, #16]
801747c: 4619 mov r1, r3
801747e: f001 f90d bl 801869c <dhcp_option_trailer>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER)\n"));
udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
8017482: 4b20 ldr r3, [pc, #128] ; (8017504 <dhcp_discover+0x134>)
8017484: 6818 ldr r0, [r3, #0]
8017486: 4b20 ldr r3, [pc, #128] ; (8017508 <dhcp_discover+0x138>)
8017488: 9301 str r3, [sp, #4]
801748a: 687b ldr r3, [r7, #4]
801748c: 9300 str r3, [sp, #0]
801748e: 2343 movs r3, #67 ; 0x43
8017490: 4a1e ldr r2, [pc, #120] ; (801750c <dhcp_discover+0x13c>)
8017492: 6939 ldr r1, [r7, #16]
8017494: f7ff f83c bl 8016510 <udp_sendto_if_src>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
pbuf_free(p_out);
8017498: 6938 ldr r0, [r7, #16]
801749a: f7f9 f887 bl 80105ac <pbuf_free>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n"));
}
if (dhcp->tries < 255) {
801749e: 69bb ldr r3, [r7, #24]
80174a0: 799b ldrb r3, [r3, #6]
80174a2: 2bff cmp r3, #255 ; 0xff
80174a4: d005 beq.n 80174b2 <dhcp_discover+0xe2>
dhcp->tries++;
80174a6: 69bb ldr r3, [r7, #24]
80174a8: 799b ldrb r3, [r3, #6]
80174aa: 3301 adds r3, #1
80174ac: b2da uxtb r2, r3
80174ae: 69bb ldr r3, [r7, #24]
80174b0: 719a strb r2, [r3, #6]
if (dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) {
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON;
autoip_start(netif);
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000);
80174b2: 69bb ldr r3, [r7, #24]
80174b4: 799b ldrb r3, [r3, #6]
80174b6: 2b05 cmp r3, #5
80174b8: d80d bhi.n 80174d6 <dhcp_discover+0x106>
80174ba: 69bb ldr r3, [r7, #24]
80174bc: 799b ldrb r3, [r3, #6]
80174be: 461a mov r2, r3
80174c0: 2301 movs r3, #1
80174c2: 4093 lsls r3, r2
80174c4: b29b uxth r3, r3
80174c6: 461a mov r2, r3
80174c8: 0152 lsls r2, r2, #5
80174ca: 1ad2 subs r2, r2, r3
80174cc: 0092 lsls r2, r2, #2
80174ce: 4413 add r3, r2
80174d0: 00db lsls r3, r3, #3
80174d2: b29b uxth r3, r3
80174d4: e001 b.n 80174da <dhcp_discover+0x10a>
80174d6: f64e 2360 movw r3, #60000 ; 0xea60
80174da: 817b strh r3, [r7, #10]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
80174dc: 897b ldrh r3, [r7, #10]
80174de: f203 13f3 addw r3, r3, #499 ; 0x1f3
80174e2: 4a0b ldr r2, [pc, #44] ; (8017510 <dhcp_discover+0x140>)
80174e4: fb82 1203 smull r1, r2, r2, r3
80174e8: 1152 asrs r2, r2, #5
80174ea: 17db asrs r3, r3, #31
80174ec: 1ad3 subs r3, r2, r3
80174ee: b29a uxth r2, r3
80174f0: 69bb ldr r3, [r7, #24]
80174f2: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs));
return result;
80174f4: f997 3017 ldrsb.w r3, [r7, #23]
}
80174f8: 4618 mov r0, r3
80174fa: 3720 adds r7, #32
80174fc: 46bd mov sp, r7
80174fe: bd80 pop {r7, pc}
8017500: 20000074 .word 0x20000074
8017504: 20008760 .word 0x20008760
8017508: 0802103c .word 0x0802103c
801750c: 08021040 .word 0x08021040
8017510: 10624dd3 .word 0x10624dd3
08017514 <dhcp_bind>:
*
* @param netif network interface to bind to the offered address
*/
static void
dhcp_bind(struct netif *netif)
{
8017514: b580 push {r7, lr}
8017516: b088 sub sp, #32
8017518: af00 add r7, sp, #0
801751a: 6078 str r0, [r7, #4]
u32_t timeout;
struct dhcp *dhcp;
ip4_addr_t sn_mask, gw_addr;
LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;);
801751c: 687b ldr r3, [r7, #4]
801751e: 2b00 cmp r3, #0
8017520: d107 bne.n 8017532 <dhcp_bind+0x1e>
8017522: 4b64 ldr r3, [pc, #400] ; (80176b4 <dhcp_bind+0x1a0>)
8017524: f240 4215 movw r2, #1045 ; 0x415
8017528: 4963 ldr r1, [pc, #396] ; (80176b8 <dhcp_bind+0x1a4>)
801752a: 4864 ldr r0, [pc, #400] ; (80176bc <dhcp_bind+0x1a8>)
801752c: f003 fd4a bl 801afc4 <iprintf>
8017530: e0bc b.n 80176ac <dhcp_bind+0x198>
dhcp = netif_dhcp_data(netif);
8017532: 687b ldr r3, [r7, #4]
8017534: 6a5b ldr r3, [r3, #36] ; 0x24
8017536: 61bb str r3, [r7, #24]
LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;);
8017538: 69bb ldr r3, [r7, #24]
801753a: 2b00 cmp r3, #0
801753c: d107 bne.n 801754e <dhcp_bind+0x3a>
801753e: 4b5d ldr r3, [pc, #372] ; (80176b4 <dhcp_bind+0x1a0>)
8017540: f240 4217 movw r2, #1047 ; 0x417
8017544: 495e ldr r1, [pc, #376] ; (80176c0 <dhcp_bind+0x1ac>)
8017546: 485d ldr r0, [pc, #372] ; (80176bc <dhcp_bind+0x1a8>)
8017548: f003 fd3c bl 801afc4 <iprintf>
801754c: e0ae b.n 80176ac <dhcp_bind+0x198>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* reset time used of lease */
dhcp->lease_used = 0;
801754e: 69bb ldr r3, [r7, #24]
8017550: 2200 movs r2, #0
8017552: 825a strh r2, [r3, #18]
if (dhcp->offered_t0_lease != 0xffffffffUL) {
8017554: 69bb ldr r3, [r7, #24]
8017556: 6a9b ldr r3, [r3, #40] ; 0x28
8017558: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
801755c: d019 beq.n 8017592 <dhcp_bind+0x7e>
/* set renewal period timer */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t0 renewal timer %"U32_F" secs\n", dhcp->offered_t0_lease));
timeout = (dhcp->offered_t0_lease + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
801755e: 69bb ldr r3, [r7, #24]
8017560: 6a9b ldr r3, [r3, #40] ; 0x28
8017562: 331e adds r3, #30
8017564: 4a57 ldr r2, [pc, #348] ; (80176c4 <dhcp_bind+0x1b0>)
8017566: fba2 2303 umull r2, r3, r2, r3
801756a: 095b lsrs r3, r3, #5
801756c: 61fb str r3, [r7, #28]
if (timeout > 0xffff) {
801756e: 69fb ldr r3, [r7, #28]
8017570: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8017574: d302 bcc.n 801757c <dhcp_bind+0x68>
timeout = 0xffff;
8017576: f64f 73ff movw r3, #65535 ; 0xffff
801757a: 61fb str r3, [r7, #28]
}
dhcp->t0_timeout = (u16_t)timeout;
801757c: 69fb ldr r3, [r7, #28]
801757e: b29a uxth r2, r3
8017580: 69bb ldr r3, [r7, #24]
8017582: 829a strh r2, [r3, #20]
if (dhcp->t0_timeout == 0) {
8017584: 69bb ldr r3, [r7, #24]
8017586: 8a9b ldrh r3, [r3, #20]
8017588: 2b00 cmp r3, #0
801758a: d102 bne.n 8017592 <dhcp_bind+0x7e>
dhcp->t0_timeout = 1;
801758c: 69bb ldr r3, [r7, #24]
801758e: 2201 movs r2, #1
8017590: 829a strh r2, [r3, #20]
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t0_lease * 1000));
}
/* temporary DHCP lease? */
if (dhcp->offered_t1_renew != 0xffffffffUL) {
8017592: 69bb ldr r3, [r7, #24]
8017594: 6adb ldr r3, [r3, #44] ; 0x2c
8017596: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
801759a: d01d beq.n 80175d8 <dhcp_bind+0xc4>
/* set renewal period timer */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew));
timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
801759c: 69bb ldr r3, [r7, #24]
801759e: 6adb ldr r3, [r3, #44] ; 0x2c
80175a0: 331e adds r3, #30
80175a2: 4a48 ldr r2, [pc, #288] ; (80176c4 <dhcp_bind+0x1b0>)
80175a4: fba2 2303 umull r2, r3, r2, r3
80175a8: 095b lsrs r3, r3, #5
80175aa: 61fb str r3, [r7, #28]
if (timeout > 0xffff) {
80175ac: 69fb ldr r3, [r7, #28]
80175ae: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80175b2: d302 bcc.n 80175ba <dhcp_bind+0xa6>
timeout = 0xffff;
80175b4: f64f 73ff movw r3, #65535 ; 0xffff
80175b8: 61fb str r3, [r7, #28]
}
dhcp->t1_timeout = (u16_t)timeout;
80175ba: 69fb ldr r3, [r7, #28]
80175bc: b29a uxth r2, r3
80175be: 69bb ldr r3, [r7, #24]
80175c0: 815a strh r2, [r3, #10]
if (dhcp->t1_timeout == 0) {
80175c2: 69bb ldr r3, [r7, #24]
80175c4: 895b ldrh r3, [r3, #10]
80175c6: 2b00 cmp r3, #0
80175c8: d102 bne.n 80175d0 <dhcp_bind+0xbc>
dhcp->t1_timeout = 1;
80175ca: 69bb ldr r3, [r7, #24]
80175cc: 2201 movs r2, #1
80175ce: 815a strh r2, [r3, #10]
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew * 1000));
dhcp->t1_renew_time = dhcp->t1_timeout;
80175d0: 69bb ldr r3, [r7, #24]
80175d2: 895a ldrh r2, [r3, #10]
80175d4: 69bb ldr r3, [r7, #24]
80175d6: 81da strh r2, [r3, #14]
}
/* set renewal period timer */
if (dhcp->offered_t2_rebind != 0xffffffffUL) {
80175d8: 69bb ldr r3, [r7, #24]
80175da: 6b1b ldr r3, [r3, #48] ; 0x30
80175dc: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
80175e0: d01d beq.n 801761e <dhcp_bind+0x10a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind));
timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
80175e2: 69bb ldr r3, [r7, #24]
80175e4: 6b1b ldr r3, [r3, #48] ; 0x30
80175e6: 331e adds r3, #30
80175e8: 4a36 ldr r2, [pc, #216] ; (80176c4 <dhcp_bind+0x1b0>)
80175ea: fba2 2303 umull r2, r3, r2, r3
80175ee: 095b lsrs r3, r3, #5
80175f0: 61fb str r3, [r7, #28]
if (timeout > 0xffff) {
80175f2: 69fb ldr r3, [r7, #28]
80175f4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80175f8: d302 bcc.n 8017600 <dhcp_bind+0xec>
timeout = 0xffff;
80175fa: f64f 73ff movw r3, #65535 ; 0xffff
80175fe: 61fb str r3, [r7, #28]
}
dhcp->t2_timeout = (u16_t)timeout;
8017600: 69fb ldr r3, [r7, #28]
8017602: b29a uxth r2, r3
8017604: 69bb ldr r3, [r7, #24]
8017606: 819a strh r2, [r3, #12]
if (dhcp->t2_timeout == 0) {
8017608: 69bb ldr r3, [r7, #24]
801760a: 899b ldrh r3, [r3, #12]
801760c: 2b00 cmp r3, #0
801760e: d102 bne.n 8017616 <dhcp_bind+0x102>
dhcp->t2_timeout = 1;
8017610: 69bb ldr r3, [r7, #24]
8017612: 2201 movs r2, #1
8017614: 819a strh r2, [r3, #12]
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind * 1000));
dhcp->t2_rebind_time = dhcp->t2_timeout;
8017616: 69bb ldr r3, [r7, #24]
8017618: 899a ldrh r2, [r3, #12]
801761a: 69bb ldr r3, [r7, #24]
801761c: 821a strh r2, [r3, #16]
}
/* If we have sub 1 minute lease, t2 and t1 will kick in at the same time. */
if ((dhcp->t1_timeout >= dhcp->t2_timeout) && (dhcp->t2_timeout > 0)) {
801761e: 69bb ldr r3, [r7, #24]
8017620: 895a ldrh r2, [r3, #10]
8017622: 69bb ldr r3, [r7, #24]
8017624: 899b ldrh r3, [r3, #12]
8017626: 429a cmp r2, r3
8017628: d306 bcc.n 8017638 <dhcp_bind+0x124>
801762a: 69bb ldr r3, [r7, #24]
801762c: 899b ldrh r3, [r3, #12]
801762e: 2b00 cmp r3, #0
8017630: d002 beq.n 8017638 <dhcp_bind+0x124>
dhcp->t1_timeout = 0;
8017632: 69bb ldr r3, [r7, #24]
8017634: 2200 movs r2, #0
8017636: 815a strh r2, [r3, #10]
}
if (dhcp->subnet_mask_given) {
8017638: 69bb ldr r3, [r7, #24]
801763a: 79db ldrb r3, [r3, #7]
801763c: 2b00 cmp r3, #0
801763e: d003 beq.n 8017648 <dhcp_bind+0x134>
/* copy offered network mask */
ip4_addr_copy(sn_mask, dhcp->offered_sn_mask);
8017640: 69bb ldr r3, [r7, #24]
8017642: 6a1b ldr r3, [r3, #32]
8017644: 613b str r3, [r7, #16]
8017646: e014 b.n 8017672 <dhcp_bind+0x15e>
} else {
/* subnet mask not given, choose a safe subnet mask given the network class */
u8_t first_octet = ip4_addr1(&dhcp->offered_ip_addr);
8017648: 69bb ldr r3, [r7, #24]
801764a: 331c adds r3, #28
801764c: 781b ldrb r3, [r3, #0]
801764e: 75fb strb r3, [r7, #23]
if (first_octet <= 127) {
8017650: f997 3017 ldrsb.w r3, [r7, #23]
8017654: 2b00 cmp r3, #0
8017656: db02 blt.n 801765e <dhcp_bind+0x14a>
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xff000000UL));
8017658: 23ff movs r3, #255 ; 0xff
801765a: 613b str r3, [r7, #16]
801765c: e009 b.n 8017672 <dhcp_bind+0x15e>
} else if (first_octet >= 192) {
801765e: 7dfb ldrb r3, [r7, #23]
8017660: 2bbf cmp r3, #191 ; 0xbf
8017662: d903 bls.n 801766c <dhcp_bind+0x158>
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffffff00UL));
8017664: f06f 437f mvn.w r3, #4278190080 ; 0xff000000
8017668: 613b str r3, [r7, #16]
801766a: e002 b.n 8017672 <dhcp_bind+0x15e>
} else {
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffff0000UL));
801766c: f64f 73ff movw r3, #65535 ; 0xffff
8017670: 613b str r3, [r7, #16]
}
}
ip4_addr_copy(gw_addr, dhcp->offered_gw_addr);
8017672: 69bb ldr r3, [r7, #24]
8017674: 6a5b ldr r3, [r3, #36] ; 0x24
8017676: 60fb str r3, [r7, #12]
/* gateway address not given? */
if (ip4_addr_isany_val(gw_addr)) {
8017678: 68fb ldr r3, [r7, #12]
801767a: 2b00 cmp r3, #0
801767c: d108 bne.n 8017690 <dhcp_bind+0x17c>
/* copy network address */
ip4_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask);
801767e: 69bb ldr r3, [r7, #24]
8017680: 69da ldr r2, [r3, #28]
8017682: 693b ldr r3, [r7, #16]
8017684: 4013 ands r3, r2
8017686: 60fb str r3, [r7, #12]
/* use first host address on network as gateway */
ip4_addr_set_u32(&gw_addr, ip4_addr_get_u32(&gw_addr) | PP_HTONL(0x00000001UL));
8017688: 68fb ldr r3, [r7, #12]
801768a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
801768e: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F" SN: 0x%08"X32_F" GW: 0x%08"X32_F"\n",
ip4_addr_get_u32(&dhcp->offered_ip_addr), ip4_addr_get_u32(&sn_mask), ip4_addr_get_u32(&gw_addr)));
/* netif is now bound to DHCP leased address - set this before assigning the address
to ensure the callback can use dhcp_supplied_address() */
dhcp_set_state(dhcp, DHCP_STATE_BOUND);
8017690: 210a movs r1, #10
8017692: 69b8 ldr r0, [r7, #24]
8017694: f000 faa0 bl 8017bd8 <dhcp_set_state>
netif_set_addr(netif, &dhcp->offered_ip_addr, &sn_mask, &gw_addr);
8017698: 69bb ldr r3, [r7, #24]
801769a: f103 011c add.w r1, r3, #28
801769e: f107 030c add.w r3, r7, #12
80176a2: f107 0210 add.w r2, r7, #16
80176a6: 6878 ldr r0, [r7, #4]
80176a8: f7f8 fa72 bl 800fb90 <netif_set_addr>
/* interface is used by routing now that an address is set */
}
80176ac: 3720 adds r7, #32
80176ae: 46bd mov sp, r7
80176b0: bd80 pop {r7, pc}
80176b2: bf00 nop
80176b4: 0801e56c .word 0x0801e56c
80176b8: 0801e6cc .word 0x0801e6cc
80176bc: 0801e5cc .word 0x0801e5cc
80176c0: 0801e6e8 .word 0x0801e6e8
80176c4: 88888889 .word 0x88888889
080176c8 <dhcp_renew>:
*
* @param netif network interface which must renew its lease
*/
err_t
dhcp_renew(struct netif *netif)
{
80176c8: b580 push {r7, lr}
80176ca: b08a sub sp, #40 ; 0x28
80176cc: af02 add r7, sp, #8
80176ce: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
80176d0: 687b ldr r3, [r7, #4]
80176d2: 6a5b ldr r3, [r3, #36] ; 0x24
80176d4: 61bb str r3, [r7, #24]
struct pbuf *p_out;
u16_t options_out_len;
LWIP_ASSERT_CORE_LOCKED();
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n"));
dhcp_set_state(dhcp, DHCP_STATE_RENEWING);
80176d6: 2105 movs r1, #5
80176d8: 69b8 ldr r0, [r7, #24]
80176da: f000 fa7d bl 8017bd8 <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
80176de: f107 030c add.w r3, r7, #12
80176e2: 2203 movs r2, #3
80176e4: 69b9 ldr r1, [r7, #24]
80176e6: 6878 ldr r0, [r7, #4]
80176e8: f000 ff02 bl 80184f0 <dhcp_create_msg>
80176ec: 6178 str r0, [r7, #20]
if (p_out != NULL) {
80176ee: 697b ldr r3, [r7, #20]
80176f0: 2b00 cmp r3, #0
80176f2: d04e beq.n 8017792 <dhcp_renew+0xca>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
80176f4: 697b ldr r3, [r7, #20]
80176f6: 685b ldr r3, [r3, #4]
80176f8: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
80176fa: 89b8 ldrh r0, [r7, #12]
80176fc: 693b ldr r3, [r7, #16]
80176fe: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017702: 2302 movs r3, #2
8017704: 2239 movs r2, #57 ; 0x39
8017706: f000 fa81 bl 8017c0c <dhcp_option>
801770a: 4603 mov r3, r0
801770c: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
801770e: 89b8 ldrh r0, [r7, #12]
8017710: 693b ldr r3, [r7, #16]
8017712: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017716: 687b ldr r3, [r7, #4]
8017718: 8d1b ldrh r3, [r3, #40] ; 0x28
801771a: 461a mov r2, r3
801771c: f000 fad0 bl 8017cc0 <dhcp_option_short>
8017720: 4603 mov r3, r0
8017722: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
8017724: 89b8 ldrh r0, [r7, #12]
8017726: 693b ldr r3, [r7, #16]
8017728: f103 01f0 add.w r1, r3, #240 ; 0xf0
801772c: 2303 movs r3, #3
801772e: 2237 movs r2, #55 ; 0x37
8017730: f000 fa6c bl 8017c0c <dhcp_option>
8017734: 4603 mov r3, r0
8017736: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8017738: 2300 movs r3, #0
801773a: 77bb strb r3, [r7, #30]
801773c: e00e b.n 801775c <dhcp_renew+0x94>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
801773e: 89b8 ldrh r0, [r7, #12]
8017740: 693b ldr r3, [r7, #16]
8017742: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017746: 7fbb ldrb r3, [r7, #30]
8017748: 4a2a ldr r2, [pc, #168] ; (80177f4 <dhcp_renew+0x12c>)
801774a: 5cd3 ldrb r3, [r2, r3]
801774c: 461a mov r2, r3
801774e: f000 fa91 bl 8017c74 <dhcp_option_byte>
8017752: 4603 mov r3, r0
8017754: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8017756: 7fbb ldrb r3, [r7, #30]
8017758: 3301 adds r3, #1
801775a: 77bb strb r3, [r7, #30]
801775c: 7fbb ldrb r3, [r7, #30]
801775e: 2b02 cmp r3, #2
8017760: d9ed bls.n 801773e <dhcp_renew+0x76>
#if LWIP_NETIF_HOSTNAME
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
#endif /* LWIP_NETIF_HOSTNAME */
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_RENEWING, msg_out, DHCP_REQUEST, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
8017762: 89b8 ldrh r0, [r7, #12]
8017764: 693b ldr r3, [r7, #16]
8017766: 33f0 adds r3, #240 ; 0xf0
8017768: 697a ldr r2, [r7, #20]
801776a: 4619 mov r1, r3
801776c: f000 ff96 bl 801869c <dhcp_option_trailer>
result = udp_sendto_if(dhcp_pcb, p_out, &dhcp->server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif);
8017770: 4b21 ldr r3, [pc, #132] ; (80177f8 <dhcp_renew+0x130>)
8017772: 6818 ldr r0, [r3, #0]
8017774: 69bb ldr r3, [r7, #24]
8017776: f103 0218 add.w r2, r3, #24
801777a: 687b ldr r3, [r7, #4]
801777c: 9300 str r3, [sp, #0]
801777e: 2343 movs r3, #67 ; 0x43
8017780: 6979 ldr r1, [r7, #20]
8017782: f7fe fe51 bl 8016428 <udp_sendto_if>
8017786: 4603 mov r3, r0
8017788: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
801778a: 6978 ldr r0, [r7, #20]
801778c: f7f8 ff0e bl 80105ac <pbuf_free>
8017790: e001 b.n 8017796 <dhcp_renew+0xce>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n"));
result = ERR_MEM;
8017792: 23ff movs r3, #255 ; 0xff
8017794: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
8017796: 69bb ldr r3, [r7, #24]
8017798: 799b ldrb r3, [r3, #6]
801779a: 2bff cmp r3, #255 ; 0xff
801779c: d005 beq.n 80177aa <dhcp_renew+0xe2>
dhcp->tries++;
801779e: 69bb ldr r3, [r7, #24]
80177a0: 799b ldrb r3, [r3, #6]
80177a2: 3301 adds r3, #1
80177a4: b2da uxtb r2, r3
80177a6: 69bb ldr r3, [r7, #24]
80177a8: 719a strb r2, [r3, #6]
}
/* back-off on retries, but to a maximum of 20 seconds */
msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000);
80177aa: 69bb ldr r3, [r7, #24]
80177ac: 799b ldrb r3, [r3, #6]
80177ae: 2b09 cmp r3, #9
80177b0: d80a bhi.n 80177c8 <dhcp_renew+0x100>
80177b2: 69bb ldr r3, [r7, #24]
80177b4: 799b ldrb r3, [r3, #6]
80177b6: b29b uxth r3, r3
80177b8: 461a mov r2, r3
80177ba: 0152 lsls r2, r2, #5
80177bc: 1ad2 subs r2, r2, r3
80177be: 0092 lsls r2, r2, #2
80177c0: 4413 add r3, r2
80177c2: 011b lsls r3, r3, #4
80177c4: b29b uxth r3, r3
80177c6: e001 b.n 80177cc <dhcp_renew+0x104>
80177c8: f644 6320 movw r3, #20000 ; 0x4e20
80177cc: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
80177ce: 89fb ldrh r3, [r7, #14]
80177d0: f203 13f3 addw r3, r3, #499 ; 0x1f3
80177d4: 4a09 ldr r2, [pc, #36] ; (80177fc <dhcp_renew+0x134>)
80177d6: fb82 1203 smull r1, r2, r2, r3
80177da: 1152 asrs r2, r2, #5
80177dc: 17db asrs r3, r3, #31
80177de: 1ad3 subs r3, r2, r3
80177e0: b29a uxth r2, r3
80177e2: 69bb ldr r3, [r7, #24]
80177e4: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs));
return result;
80177e6: f997 301f ldrsb.w r3, [r7, #31]
}
80177ea: 4618 mov r0, r3
80177ec: 3720 adds r7, #32
80177ee: 46bd mov sp, r7
80177f0: bd80 pop {r7, pc}
80177f2: bf00 nop
80177f4: 20000074 .word 0x20000074
80177f8: 20008760 .word 0x20008760
80177fc: 10624dd3 .word 0x10624dd3
08017800 <dhcp_rebind>:
*
* @param netif network interface which must rebind with a DHCP server
*/
static err_t
dhcp_rebind(struct netif *netif)
{
8017800: b580 push {r7, lr}
8017802: b08a sub sp, #40 ; 0x28
8017804: af02 add r7, sp, #8
8017806: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8017808: 687b ldr r3, [r7, #4]
801780a: 6a5b ldr r3, [r3, #36] ; 0x24
801780c: 61bb str r3, [r7, #24]
u8_t i;
struct pbuf *p_out;
u16_t options_out_len;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n"));
dhcp_set_state(dhcp, DHCP_STATE_REBINDING);
801780e: 2104 movs r1, #4
8017810: 69b8 ldr r0, [r7, #24]
8017812: f000 f9e1 bl 8017bd8 <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
8017816: f107 030c add.w r3, r7, #12
801781a: 2203 movs r2, #3
801781c: 69b9 ldr r1, [r7, #24]
801781e: 6878 ldr r0, [r7, #4]
8017820: f000 fe66 bl 80184f0 <dhcp_create_msg>
8017824: 6178 str r0, [r7, #20]
if (p_out != NULL) {
8017826: 697b ldr r3, [r7, #20]
8017828: 2b00 cmp r3, #0
801782a: d04c beq.n 80178c6 <dhcp_rebind+0xc6>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
801782c: 697b ldr r3, [r7, #20]
801782e: 685b ldr r3, [r3, #4]
8017830: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
8017832: 89b8 ldrh r0, [r7, #12]
8017834: 693b ldr r3, [r7, #16]
8017836: f103 01f0 add.w r1, r3, #240 ; 0xf0
801783a: 2302 movs r3, #2
801783c: 2239 movs r2, #57 ; 0x39
801783e: f000 f9e5 bl 8017c0c <dhcp_option>
8017842: 4603 mov r3, r0
8017844: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
8017846: 89b8 ldrh r0, [r7, #12]
8017848: 693b ldr r3, [r7, #16]
801784a: f103 01f0 add.w r1, r3, #240 ; 0xf0
801784e: 687b ldr r3, [r7, #4]
8017850: 8d1b ldrh r3, [r3, #40] ; 0x28
8017852: 461a mov r2, r3
8017854: f000 fa34 bl 8017cc0 <dhcp_option_short>
8017858: 4603 mov r3, r0
801785a: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
801785c: 89b8 ldrh r0, [r7, #12]
801785e: 693b ldr r3, [r7, #16]
8017860: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017864: 2303 movs r3, #3
8017866: 2237 movs r2, #55 ; 0x37
8017868: f000 f9d0 bl 8017c0c <dhcp_option>
801786c: 4603 mov r3, r0
801786e: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8017870: 2300 movs r3, #0
8017872: 77bb strb r3, [r7, #30]
8017874: e00e b.n 8017894 <dhcp_rebind+0x94>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
8017876: 89b8 ldrh r0, [r7, #12]
8017878: 693b ldr r3, [r7, #16]
801787a: f103 01f0 add.w r1, r3, #240 ; 0xf0
801787e: 7fbb ldrb r3, [r7, #30]
8017880: 4a29 ldr r2, [pc, #164] ; (8017928 <dhcp_rebind+0x128>)
8017882: 5cd3 ldrb r3, [r2, r3]
8017884: 461a mov r2, r3
8017886: f000 f9f5 bl 8017c74 <dhcp_option_byte>
801788a: 4603 mov r3, r0
801788c: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
801788e: 7fbb ldrb r3, [r7, #30]
8017890: 3301 adds r3, #1
8017892: 77bb strb r3, [r7, #30]
8017894: 7fbb ldrb r3, [r7, #30]
8017896: 2b02 cmp r3, #2
8017898: d9ed bls.n 8017876 <dhcp_rebind+0x76>
#if LWIP_NETIF_HOSTNAME
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
#endif /* LWIP_NETIF_HOSTNAME */
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBINDING, msg_out, DHCP_DISCOVER, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
801789a: 89b8 ldrh r0, [r7, #12]
801789c: 693b ldr r3, [r7, #16]
801789e: 33f0 adds r3, #240 ; 0xf0
80178a0: 697a ldr r2, [r7, #20]
80178a2: 4619 mov r1, r3
80178a4: f000 fefa bl 801869c <dhcp_option_trailer>
/* broadcast to server */
result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif);
80178a8: 4b20 ldr r3, [pc, #128] ; (801792c <dhcp_rebind+0x12c>)
80178aa: 6818 ldr r0, [r3, #0]
80178ac: 687b ldr r3, [r7, #4]
80178ae: 9300 str r3, [sp, #0]
80178b0: 2343 movs r3, #67 ; 0x43
80178b2: 4a1f ldr r2, [pc, #124] ; (8017930 <dhcp_rebind+0x130>)
80178b4: 6979 ldr r1, [r7, #20]
80178b6: f7fe fdb7 bl 8016428 <udp_sendto_if>
80178ba: 4603 mov r3, r0
80178bc: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
80178be: 6978 ldr r0, [r7, #20]
80178c0: f7f8 fe74 bl 80105ac <pbuf_free>
80178c4: e001 b.n 80178ca <dhcp_rebind+0xca>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n"));
result = ERR_MEM;
80178c6: 23ff movs r3, #255 ; 0xff
80178c8: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
80178ca: 69bb ldr r3, [r7, #24]
80178cc: 799b ldrb r3, [r3, #6]
80178ce: 2bff cmp r3, #255 ; 0xff
80178d0: d005 beq.n 80178de <dhcp_rebind+0xde>
dhcp->tries++;
80178d2: 69bb ldr r3, [r7, #24]
80178d4: 799b ldrb r3, [r3, #6]
80178d6: 3301 adds r3, #1
80178d8: b2da uxtb r2, r3
80178da: 69bb ldr r3, [r7, #24]
80178dc: 719a strb r2, [r3, #6]
}
msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000);
80178de: 69bb ldr r3, [r7, #24]
80178e0: 799b ldrb r3, [r3, #6]
80178e2: 2b09 cmp r3, #9
80178e4: d80a bhi.n 80178fc <dhcp_rebind+0xfc>
80178e6: 69bb ldr r3, [r7, #24]
80178e8: 799b ldrb r3, [r3, #6]
80178ea: b29b uxth r3, r3
80178ec: 461a mov r2, r3
80178ee: 0152 lsls r2, r2, #5
80178f0: 1ad2 subs r2, r2, r3
80178f2: 0092 lsls r2, r2, #2
80178f4: 4413 add r3, r2
80178f6: 00db lsls r3, r3, #3
80178f8: b29b uxth r3, r3
80178fa: e001 b.n 8017900 <dhcp_rebind+0x100>
80178fc: f242 7310 movw r3, #10000 ; 0x2710
8017900: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8017902: 89fb ldrh r3, [r7, #14]
8017904: f203 13f3 addw r3, r3, #499 ; 0x1f3
8017908: 4a0a ldr r2, [pc, #40] ; (8017934 <dhcp_rebind+0x134>)
801790a: fb82 1203 smull r1, r2, r2, r3
801790e: 1152 asrs r2, r2, #5
8017910: 17db asrs r3, r3, #31
8017912: 1ad3 subs r3, r2, r3
8017914: b29a uxth r2, r3
8017916: 69bb ldr r3, [r7, #24]
8017918: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs));
return result;
801791a: f997 301f ldrsb.w r3, [r7, #31]
}
801791e: 4618 mov r0, r3
8017920: 3720 adds r7, #32
8017922: 46bd mov sp, r7
8017924: bd80 pop {r7, pc}
8017926: bf00 nop
8017928: 20000074 .word 0x20000074
801792c: 20008760 .word 0x20008760
8017930: 08021040 .word 0x08021040
8017934: 10624dd3 .word 0x10624dd3
08017938 <dhcp_reboot>:
*
* @param netif network interface which must reboot
*/
static err_t
dhcp_reboot(struct netif *netif)
{
8017938: b5b0 push {r4, r5, r7, lr}
801793a: b08a sub sp, #40 ; 0x28
801793c: af02 add r7, sp, #8
801793e: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8017940: 687b ldr r3, [r7, #4]
8017942: 6a5b ldr r3, [r3, #36] ; 0x24
8017944: 61bb str r3, [r7, #24]
u8_t i;
struct pbuf *p_out;
u16_t options_out_len;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n"));
dhcp_set_state(dhcp, DHCP_STATE_REBOOTING);
8017946: 2103 movs r1, #3
8017948: 69b8 ldr r0, [r7, #24]
801794a: f000 f945 bl 8017bd8 <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
801794e: f107 030c add.w r3, r7, #12
8017952: 2203 movs r2, #3
8017954: 69b9 ldr r1, [r7, #24]
8017956: 6878 ldr r0, [r7, #4]
8017958: f000 fdca bl 80184f0 <dhcp_create_msg>
801795c: 6178 str r0, [r7, #20]
if (p_out != NULL) {
801795e: 697b ldr r3, [r7, #20]
8017960: 2b00 cmp r3, #0
8017962: d066 beq.n 8017a32 <dhcp_reboot+0xfa>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8017964: 697b ldr r3, [r7, #20]
8017966: 685b ldr r3, [r3, #4]
8017968: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
801796a: 89b8 ldrh r0, [r7, #12]
801796c: 693b ldr r3, [r7, #16]
801796e: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017972: 2302 movs r3, #2
8017974: 2239 movs r2, #57 ; 0x39
8017976: f000 f949 bl 8017c0c <dhcp_option>
801797a: 4603 mov r3, r0
801797c: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN_MIN_REQUIRED);
801797e: 89b8 ldrh r0, [r7, #12]
8017980: 693b ldr r3, [r7, #16]
8017982: 33f0 adds r3, #240 ; 0xf0
8017984: f44f 7210 mov.w r2, #576 ; 0x240
8017988: 4619 mov r1, r3
801798a: f000 f999 bl 8017cc0 <dhcp_option_short>
801798e: 4603 mov r3, r0
8017990: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
8017992: 89b8 ldrh r0, [r7, #12]
8017994: 693b ldr r3, [r7, #16]
8017996: f103 01f0 add.w r1, r3, #240 ; 0xf0
801799a: 2304 movs r3, #4
801799c: 2232 movs r2, #50 ; 0x32
801799e: f000 f935 bl 8017c0c <dhcp_option>
80179a2: 4603 mov r3, r0
80179a4: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
80179a6: 89bc ldrh r4, [r7, #12]
80179a8: 693b ldr r3, [r7, #16]
80179aa: f103 05f0 add.w r5, r3, #240 ; 0xf0
80179ae: 69bb ldr r3, [r7, #24]
80179b0: 69db ldr r3, [r3, #28]
80179b2: 4618 mov r0, r3
80179b4: f7f7 fa57 bl 800ee66 <lwip_htonl>
80179b8: 4603 mov r3, r0
80179ba: 461a mov r2, r3
80179bc: 4629 mov r1, r5
80179be: 4620 mov r0, r4
80179c0: f000 f9b0 bl 8017d24 <dhcp_option_long>
80179c4: 4603 mov r3, r0
80179c6: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
80179c8: 89b8 ldrh r0, [r7, #12]
80179ca: 693b ldr r3, [r7, #16]
80179cc: f103 01f0 add.w r1, r3, #240 ; 0xf0
80179d0: 2303 movs r3, #3
80179d2: 2237 movs r2, #55 ; 0x37
80179d4: f000 f91a bl 8017c0c <dhcp_option>
80179d8: 4603 mov r3, r0
80179da: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
80179dc: 2300 movs r3, #0
80179de: 77bb strb r3, [r7, #30]
80179e0: e00e b.n 8017a00 <dhcp_reboot+0xc8>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
80179e2: 89b8 ldrh r0, [r7, #12]
80179e4: 693b ldr r3, [r7, #16]
80179e6: f103 01f0 add.w r1, r3, #240 ; 0xf0
80179ea: 7fbb ldrb r3, [r7, #30]
80179ec: 4a29 ldr r2, [pc, #164] ; (8017a94 <dhcp_reboot+0x15c>)
80179ee: 5cd3 ldrb r3, [r2, r3]
80179f0: 461a mov r2, r3
80179f2: f000 f93f bl 8017c74 <dhcp_option_byte>
80179f6: 4603 mov r3, r0
80179f8: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
80179fa: 7fbb ldrb r3, [r7, #30]
80179fc: 3301 adds r3, #1
80179fe: 77bb strb r3, [r7, #30]
8017a00: 7fbb ldrb r3, [r7, #30]
8017a02: 2b02 cmp r3, #2
8017a04: d9ed bls.n 80179e2 <dhcp_reboot+0xaa>
#if LWIP_NETIF_HOSTNAME
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
#endif /* LWIP_NETIF_HOSTNAME */
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBOOTING, msg_out, DHCP_REQUEST, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
8017a06: 89b8 ldrh r0, [r7, #12]
8017a08: 693b ldr r3, [r7, #16]
8017a0a: 33f0 adds r3, #240 ; 0xf0
8017a0c: 697a ldr r2, [r7, #20]
8017a0e: 4619 mov r1, r3
8017a10: f000 fe44 bl 801869c <dhcp_option_trailer>
/* broadcast to server */
result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif);
8017a14: 4b20 ldr r3, [pc, #128] ; (8017a98 <dhcp_reboot+0x160>)
8017a16: 6818 ldr r0, [r3, #0]
8017a18: 687b ldr r3, [r7, #4]
8017a1a: 9300 str r3, [sp, #0]
8017a1c: 2343 movs r3, #67 ; 0x43
8017a1e: 4a1f ldr r2, [pc, #124] ; (8017a9c <dhcp_reboot+0x164>)
8017a20: 6979 ldr r1, [r7, #20]
8017a22: f7fe fd01 bl 8016428 <udp_sendto_if>
8017a26: 4603 mov r3, r0
8017a28: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
8017a2a: 6978 ldr r0, [r7, #20]
8017a2c: f7f8 fdbe bl 80105ac <pbuf_free>
8017a30: e001 b.n 8017a36 <dhcp_reboot+0xfe>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n"));
result = ERR_MEM;
8017a32: 23ff movs r3, #255 ; 0xff
8017a34: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
8017a36: 69bb ldr r3, [r7, #24]
8017a38: 799b ldrb r3, [r3, #6]
8017a3a: 2bff cmp r3, #255 ; 0xff
8017a3c: d005 beq.n 8017a4a <dhcp_reboot+0x112>
dhcp->tries++;
8017a3e: 69bb ldr r3, [r7, #24]
8017a40: 799b ldrb r3, [r3, #6]
8017a42: 3301 adds r3, #1
8017a44: b2da uxtb r2, r3
8017a46: 69bb ldr r3, [r7, #24]
8017a48: 719a strb r2, [r3, #6]
}
msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000);
8017a4a: 69bb ldr r3, [r7, #24]
8017a4c: 799b ldrb r3, [r3, #6]
8017a4e: 2b09 cmp r3, #9
8017a50: d80a bhi.n 8017a68 <dhcp_reboot+0x130>
8017a52: 69bb ldr r3, [r7, #24]
8017a54: 799b ldrb r3, [r3, #6]
8017a56: b29b uxth r3, r3
8017a58: 461a mov r2, r3
8017a5a: 0152 lsls r2, r2, #5
8017a5c: 1ad2 subs r2, r2, r3
8017a5e: 0092 lsls r2, r2, #2
8017a60: 4413 add r3, r2
8017a62: 00db lsls r3, r3, #3
8017a64: b29b uxth r3, r3
8017a66: e001 b.n 8017a6c <dhcp_reboot+0x134>
8017a68: f242 7310 movw r3, #10000 ; 0x2710
8017a6c: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8017a6e: 89fb ldrh r3, [r7, #14]
8017a70: f203 13f3 addw r3, r3, #499 ; 0x1f3
8017a74: 4a0a ldr r2, [pc, #40] ; (8017aa0 <dhcp_reboot+0x168>)
8017a76: fb82 1203 smull r1, r2, r2, r3
8017a7a: 1152 asrs r2, r2, #5
8017a7c: 17db asrs r3, r3, #31
8017a7e: 1ad3 subs r3, r2, r3
8017a80: b29a uxth r2, r3
8017a82: 69bb ldr r3, [r7, #24]
8017a84: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs));
return result;
8017a86: f997 301f ldrsb.w r3, [r7, #31]
}
8017a8a: 4618 mov r0, r3
8017a8c: 3720 adds r7, #32
8017a8e: 46bd mov sp, r7
8017a90: bdb0 pop {r4, r5, r7, pc}
8017a92: bf00 nop
8017a94: 20000074 .word 0x20000074
8017a98: 20008760 .word 0x20008760
8017a9c: 08021040 .word 0x08021040
8017aa0: 10624dd3 .word 0x10624dd3
08017aa4 <dhcp_release_and_stop>:
*
* @param netif network interface
*/
void
dhcp_release_and_stop(struct netif *netif)
{
8017aa4: b5b0 push {r4, r5, r7, lr}
8017aa6: b08a sub sp, #40 ; 0x28
8017aa8: af02 add r7, sp, #8
8017aaa: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8017aac: 687b ldr r3, [r7, #4]
8017aae: 6a5b ldr r3, [r3, #36] ; 0x24
8017ab0: 61fb str r3, [r7, #28]
ip_addr_t server_ip_addr;
LWIP_ASSERT_CORE_LOCKED();
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release_and_stop()\n"));
if (dhcp == NULL) {
8017ab2: 69fb ldr r3, [r7, #28]
8017ab4: 2b00 cmp r3, #0
8017ab6: f000 8084 beq.w 8017bc2 <dhcp_release_and_stop+0x11e>
return;
}
/* already off? -> nothing to do */
if (dhcp->state == DHCP_STATE_OFF) {
8017aba: 69fb ldr r3, [r7, #28]
8017abc: 795b ldrb r3, [r3, #5]
8017abe: 2b00 cmp r3, #0
8017ac0: f000 8081 beq.w 8017bc6 <dhcp_release_and_stop+0x122>
return;
}
ip_addr_copy(server_ip_addr, dhcp->server_ip_addr);
8017ac4: 69fb ldr r3, [r7, #28]
8017ac6: 699b ldr r3, [r3, #24]
8017ac8: 613b str r3, [r7, #16]
/* clean old DHCP offer */
ip_addr_set_zero_ip4(&dhcp->server_ip_addr);
8017aca: 69fb ldr r3, [r7, #28]
8017acc: 2200 movs r2, #0
8017ace: 619a str r2, [r3, #24]
ip4_addr_set_zero(&dhcp->offered_ip_addr);
8017ad0: 69fb ldr r3, [r7, #28]
8017ad2: 2200 movs r2, #0
8017ad4: 61da str r2, [r3, #28]
ip4_addr_set_zero(&dhcp->offered_sn_mask);
8017ad6: 69fb ldr r3, [r7, #28]
8017ad8: 2200 movs r2, #0
8017ada: 621a str r2, [r3, #32]
ip4_addr_set_zero(&dhcp->offered_gw_addr);
8017adc: 69fb ldr r3, [r7, #28]
8017ade: 2200 movs r2, #0
8017ae0: 625a str r2, [r3, #36] ; 0x24
#if LWIP_DHCP_BOOTP_FILE
ip4_addr_set_zero(&dhcp->offered_si_addr);
#endif /* LWIP_DHCP_BOOTP_FILE */
dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
8017ae2: 69fb ldr r3, [r7, #28]
8017ae4: 2200 movs r2, #0
8017ae6: 631a str r2, [r3, #48] ; 0x30
8017ae8: 69fb ldr r3, [r7, #28]
8017aea: 6b1a ldr r2, [r3, #48] ; 0x30
8017aec: 69fb ldr r3, [r7, #28]
8017aee: 62da str r2, [r3, #44] ; 0x2c
8017af0: 69fb ldr r3, [r7, #28]
8017af2: 6ada ldr r2, [r3, #44] ; 0x2c
8017af4: 69fb ldr r3, [r7, #28]
8017af6: 629a str r2, [r3, #40] ; 0x28
dhcp->t1_renew_time = dhcp->t2_rebind_time = dhcp->lease_used = dhcp->t0_timeout = 0;
8017af8: 69fb ldr r3, [r7, #28]
8017afa: 2200 movs r2, #0
8017afc: 829a strh r2, [r3, #20]
8017afe: 69fb ldr r3, [r7, #28]
8017b00: 8a9a ldrh r2, [r3, #20]
8017b02: 69fb ldr r3, [r7, #28]
8017b04: 825a strh r2, [r3, #18]
8017b06: 69fb ldr r3, [r7, #28]
8017b08: 8a5a ldrh r2, [r3, #18]
8017b0a: 69fb ldr r3, [r7, #28]
8017b0c: 821a strh r2, [r3, #16]
8017b0e: 69fb ldr r3, [r7, #28]
8017b10: 8a1a ldrh r2, [r3, #16]
8017b12: 69fb ldr r3, [r7, #28]
8017b14: 81da strh r2, [r3, #14]
/* send release message when current IP was assigned via DHCP */
if (dhcp_supplied_address(netif)) {
8017b16: 6878 ldr r0, [r7, #4]
8017b18: f000 fdee bl 80186f8 <dhcp_supplied_address>
8017b1c: 4603 mov r3, r0
8017b1e: 2b00 cmp r3, #0
8017b20: d03b beq.n 8017b9a <dhcp_release_and_stop+0xf6>
/* create and initialize the DHCP message header */
struct pbuf *p_out;
u16_t options_out_len;
p_out = dhcp_create_msg(netif, dhcp, DHCP_RELEASE, &options_out_len);
8017b22: f107 030e add.w r3, r7, #14
8017b26: 2207 movs r2, #7
8017b28: 69f9 ldr r1, [r7, #28]
8017b2a: 6878 ldr r0, [r7, #4]
8017b2c: f000 fce0 bl 80184f0 <dhcp_create_msg>
8017b30: 61b8 str r0, [r7, #24]
if (p_out != NULL) {
8017b32: 69bb ldr r3, [r7, #24]
8017b34: 2b00 cmp r3, #0
8017b36: d030 beq.n 8017b9a <dhcp_release_and_stop+0xf6>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8017b38: 69bb ldr r3, [r7, #24]
8017b3a: 685b ldr r3, [r3, #4]
8017b3c: 617b str r3, [r7, #20]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4);
8017b3e: 89f8 ldrh r0, [r7, #14]
8017b40: 697b ldr r3, [r7, #20]
8017b42: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017b46: 2304 movs r3, #4
8017b48: 2236 movs r2, #54 ; 0x36
8017b4a: f000 f85f bl 8017c0c <dhcp_option>
8017b4e: 4603 mov r3, r0
8017b50: 81fb strh r3, [r7, #14]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&server_ip_addr))));
8017b52: 89fc ldrh r4, [r7, #14]
8017b54: 697b ldr r3, [r7, #20]
8017b56: f103 05f0 add.w r5, r3, #240 ; 0xf0
8017b5a: 693b ldr r3, [r7, #16]
8017b5c: 4618 mov r0, r3
8017b5e: f7f7 f982 bl 800ee66 <lwip_htonl>
8017b62: 4603 mov r3, r0
8017b64: 461a mov r2, r3
8017b66: 4629 mov r1, r5
8017b68: 4620 mov r0, r4
8017b6a: f000 f8db bl 8017d24 <dhcp_option_long>
8017b6e: 4603 mov r3, r0
8017b70: 81fb strh r3, [r7, #14]
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, dhcp->state, msg_out, DHCP_RELEASE, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
8017b72: 89f8 ldrh r0, [r7, #14]
8017b74: 697b ldr r3, [r7, #20]
8017b76: 33f0 adds r3, #240 ; 0xf0
8017b78: 69ba ldr r2, [r7, #24]
8017b7a: 4619 mov r1, r3
8017b7c: f000 fd8e bl 801869c <dhcp_option_trailer>
udp_sendto_if(dhcp_pcb, p_out, &server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif);
8017b80: 4b13 ldr r3, [pc, #76] ; (8017bd0 <dhcp_release_and_stop+0x12c>)
8017b82: 6818 ldr r0, [r3, #0]
8017b84: f107 0210 add.w r2, r7, #16
8017b88: 687b ldr r3, [r7, #4]
8017b8a: 9300 str r3, [sp, #0]
8017b8c: 2343 movs r3, #67 ; 0x43
8017b8e: 69b9 ldr r1, [r7, #24]
8017b90: f7fe fc4a bl 8016428 <udp_sendto_if>
pbuf_free(p_out);
8017b94: 69b8 ldr r0, [r7, #24]
8017b96: f7f8 fd09 bl 80105ac <pbuf_free>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n"));
}
}
/* remove IP address from interface (prevents routing from selecting this interface) */
netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4);
8017b9a: 4b0e ldr r3, [pc, #56] ; (8017bd4 <dhcp_release_and_stop+0x130>)
8017b9c: 4a0d ldr r2, [pc, #52] ; (8017bd4 <dhcp_release_and_stop+0x130>)
8017b9e: 490d ldr r1, [pc, #52] ; (8017bd4 <dhcp_release_and_stop+0x130>)
8017ba0: 6878 ldr r0, [r7, #4]
8017ba2: f7f7 fff5 bl 800fb90 <netif_set_addr>
autoip_stop(netif);
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
dhcp_set_state(dhcp, DHCP_STATE_OFF);
8017ba6: 2100 movs r1, #0
8017ba8: 69f8 ldr r0, [r7, #28]
8017baa: f000 f815 bl 8017bd8 <dhcp_set_state>
if (dhcp->pcb_allocated != 0) {
8017bae: 69fb ldr r3, [r7, #28]
8017bb0: 791b ldrb r3, [r3, #4]
8017bb2: 2b00 cmp r3, #0
8017bb4: d008 beq.n 8017bc8 <dhcp_release_and_stop+0x124>
dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */
8017bb6: f7fe ff83 bl 8016ac0 <dhcp_dec_pcb_refcount>
dhcp->pcb_allocated = 0;
8017bba: 69fb ldr r3, [r7, #28]
8017bbc: 2200 movs r2, #0
8017bbe: 711a strb r2, [r3, #4]
8017bc0: e002 b.n 8017bc8 <dhcp_release_and_stop+0x124>
return;
8017bc2: bf00 nop
8017bc4: e000 b.n 8017bc8 <dhcp_release_and_stop+0x124>
return;
8017bc6: bf00 nop
}
}
8017bc8: 3720 adds r7, #32
8017bca: 46bd mov sp, r7
8017bcc: bdb0 pop {r4, r5, r7, pc}
8017bce: bf00 nop
8017bd0: 20008760 .word 0x20008760
8017bd4: 0802103c .word 0x0802103c
08017bd8 <dhcp_set_state>:
*
* If the state changed, reset the number of tries.
*/
static void
dhcp_set_state(struct dhcp *dhcp, u8_t new_state)
{
8017bd8: b480 push {r7}
8017bda: b083 sub sp, #12
8017bdc: af00 add r7, sp, #0
8017bde: 6078 str r0, [r7, #4]
8017be0: 460b mov r3, r1
8017be2: 70fb strb r3, [r7, #3]
if (new_state != dhcp->state) {
8017be4: 687b ldr r3, [r7, #4]
8017be6: 795b ldrb r3, [r3, #5]
8017be8: 78fa ldrb r2, [r7, #3]
8017bea: 429a cmp r2, r3
8017bec: d008 beq.n 8017c00 <dhcp_set_state+0x28>
dhcp->state = new_state;
8017bee: 687b ldr r3, [r7, #4]
8017bf0: 78fa ldrb r2, [r7, #3]
8017bf2: 715a strb r2, [r3, #5]
dhcp->tries = 0;
8017bf4: 687b ldr r3, [r7, #4]
8017bf6: 2200 movs r2, #0
8017bf8: 719a strb r2, [r3, #6]
dhcp->request_timeout = 0;
8017bfa: 687b ldr r3, [r7, #4]
8017bfc: 2200 movs r2, #0
8017bfe: 811a strh r2, [r3, #8]
}
}
8017c00: bf00 nop
8017c02: 370c adds r7, #12
8017c04: 46bd mov sp, r7
8017c06: f85d 7b04 ldr.w r7, [sp], #4
8017c0a: 4770 bx lr
08017c0c <dhcp_option>:
* DHCP message.
*
*/
static u16_t
dhcp_option(u16_t options_out_len, u8_t *options, u8_t option_type, u8_t option_len)
{
8017c0c: b580 push {r7, lr}
8017c0e: b082 sub sp, #8
8017c10: af00 add r7, sp, #0
8017c12: 6039 str r1, [r7, #0]
8017c14: 4611 mov r1, r2
8017c16: 461a mov r2, r3
8017c18: 4603 mov r3, r0
8017c1a: 80fb strh r3, [r7, #6]
8017c1c: 460b mov r3, r1
8017c1e: 717b strb r3, [r7, #5]
8017c20: 4613 mov r3, r2
8017c22: 713b strb r3, [r7, #4]
LWIP_ASSERT("dhcp_option: options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN);
8017c24: 88fa ldrh r2, [r7, #6]
8017c26: 793b ldrb r3, [r7, #4]
8017c28: 4413 add r3, r2
8017c2a: 3302 adds r3, #2
8017c2c: 2b44 cmp r3, #68 ; 0x44
8017c2e: d906 bls.n 8017c3e <dhcp_option+0x32>
8017c30: 4b0d ldr r3, [pc, #52] ; (8017c68 <dhcp_option+0x5c>)
8017c32: f240 529a movw r2, #1434 ; 0x59a
8017c36: 490d ldr r1, [pc, #52] ; (8017c6c <dhcp_option+0x60>)
8017c38: 480d ldr r0, [pc, #52] ; (8017c70 <dhcp_option+0x64>)
8017c3a: f003 f9c3 bl 801afc4 <iprintf>
options[options_out_len++] = option_type;
8017c3e: 88fb ldrh r3, [r7, #6]
8017c40: 1c5a adds r2, r3, #1
8017c42: 80fa strh r2, [r7, #6]
8017c44: 461a mov r2, r3
8017c46: 683b ldr r3, [r7, #0]
8017c48: 4413 add r3, r2
8017c4a: 797a ldrb r2, [r7, #5]
8017c4c: 701a strb r2, [r3, #0]
options[options_out_len++] = option_len;
8017c4e: 88fb ldrh r3, [r7, #6]
8017c50: 1c5a adds r2, r3, #1
8017c52: 80fa strh r2, [r7, #6]
8017c54: 461a mov r2, r3
8017c56: 683b ldr r3, [r7, #0]
8017c58: 4413 add r3, r2
8017c5a: 793a ldrb r2, [r7, #4]
8017c5c: 701a strb r2, [r3, #0]
return options_out_len;
8017c5e: 88fb ldrh r3, [r7, #6]
}
8017c60: 4618 mov r0, r3
8017c62: 3708 adds r7, #8
8017c64: 46bd mov sp, r7
8017c66: bd80 pop {r7, pc}
8017c68: 0801e56c .word 0x0801e56c
8017c6c: 0801e700 .word 0x0801e700
8017c70: 0801e5cc .word 0x0801e5cc
08017c74 <dhcp_option_byte>:
* Concatenate a single byte to the outgoing DHCP message.
*
*/
static u16_t
dhcp_option_byte(u16_t options_out_len, u8_t *options, u8_t value)
{
8017c74: b580 push {r7, lr}
8017c76: b082 sub sp, #8
8017c78: af00 add r7, sp, #0
8017c7a: 4603 mov r3, r0
8017c7c: 6039 str r1, [r7, #0]
8017c7e: 80fb strh r3, [r7, #6]
8017c80: 4613 mov r3, r2
8017c82: 717b strb r3, [r7, #5]
LWIP_ASSERT("dhcp_option_byte: options_out_len < DHCP_OPTIONS_LEN", options_out_len < DHCP_OPTIONS_LEN);
8017c84: 88fb ldrh r3, [r7, #6]
8017c86: 2b43 cmp r3, #67 ; 0x43
8017c88: d906 bls.n 8017c98 <dhcp_option_byte+0x24>
8017c8a: 4b0a ldr r3, [pc, #40] ; (8017cb4 <dhcp_option_byte+0x40>)
8017c8c: f240 52a6 movw r2, #1446 ; 0x5a6
8017c90: 4909 ldr r1, [pc, #36] ; (8017cb8 <dhcp_option_byte+0x44>)
8017c92: 480a ldr r0, [pc, #40] ; (8017cbc <dhcp_option_byte+0x48>)
8017c94: f003 f996 bl 801afc4 <iprintf>
options[options_out_len++] = value;
8017c98: 88fb ldrh r3, [r7, #6]
8017c9a: 1c5a adds r2, r3, #1
8017c9c: 80fa strh r2, [r7, #6]
8017c9e: 461a mov r2, r3
8017ca0: 683b ldr r3, [r7, #0]
8017ca2: 4413 add r3, r2
8017ca4: 797a ldrb r2, [r7, #5]
8017ca6: 701a strb r2, [r3, #0]
return options_out_len;
8017ca8: 88fb ldrh r3, [r7, #6]
}
8017caa: 4618 mov r0, r3
8017cac: 3708 adds r7, #8
8017cae: 46bd mov sp, r7
8017cb0: bd80 pop {r7, pc}
8017cb2: bf00 nop
8017cb4: 0801e56c .word 0x0801e56c
8017cb8: 0801e744 .word 0x0801e744
8017cbc: 0801e5cc .word 0x0801e5cc
08017cc0 <dhcp_option_short>:
static u16_t
dhcp_option_short(u16_t options_out_len, u8_t *options, u16_t value)
{
8017cc0: b580 push {r7, lr}
8017cc2: b082 sub sp, #8
8017cc4: af00 add r7, sp, #0
8017cc6: 4603 mov r3, r0
8017cc8: 6039 str r1, [r7, #0]
8017cca: 80fb strh r3, [r7, #6]
8017ccc: 4613 mov r3, r2
8017cce: 80bb strh r3, [r7, #4]
LWIP_ASSERT("dhcp_option_short: options_out_len + 2 <= DHCP_OPTIONS_LEN", options_out_len + 2U <= DHCP_OPTIONS_LEN);
8017cd0: 88fb ldrh r3, [r7, #6]
8017cd2: 3302 adds r3, #2
8017cd4: 2b44 cmp r3, #68 ; 0x44
8017cd6: d906 bls.n 8017ce6 <dhcp_option_short+0x26>
8017cd8: 4b0f ldr r3, [pc, #60] ; (8017d18 <dhcp_option_short+0x58>)
8017cda: f240 52ae movw r2, #1454 ; 0x5ae
8017cde: 490f ldr r1, [pc, #60] ; (8017d1c <dhcp_option_short+0x5c>)
8017ce0: 480f ldr r0, [pc, #60] ; (8017d20 <dhcp_option_short+0x60>)
8017ce2: f003 f96f bl 801afc4 <iprintf>
options[options_out_len++] = (u8_t)((value & 0xff00U) >> 8);
8017ce6: 88bb ldrh r3, [r7, #4]
8017ce8: 0a1b lsrs r3, r3, #8
8017cea: b29a uxth r2, r3
8017cec: 88fb ldrh r3, [r7, #6]
8017cee: 1c59 adds r1, r3, #1
8017cf0: 80f9 strh r1, [r7, #6]
8017cf2: 4619 mov r1, r3
8017cf4: 683b ldr r3, [r7, #0]
8017cf6: 440b add r3, r1
8017cf8: b2d2 uxtb r2, r2
8017cfa: 701a strb r2, [r3, #0]
options[options_out_len++] = (u8_t) (value & 0x00ffU);
8017cfc: 88fb ldrh r3, [r7, #6]
8017cfe: 1c5a adds r2, r3, #1
8017d00: 80fa strh r2, [r7, #6]
8017d02: 461a mov r2, r3
8017d04: 683b ldr r3, [r7, #0]
8017d06: 4413 add r3, r2
8017d08: 88ba ldrh r2, [r7, #4]
8017d0a: b2d2 uxtb r2, r2
8017d0c: 701a strb r2, [r3, #0]
return options_out_len;
8017d0e: 88fb ldrh r3, [r7, #6]
}
8017d10: 4618 mov r0, r3
8017d12: 3708 adds r7, #8
8017d14: 46bd mov sp, r7
8017d16: bd80 pop {r7, pc}
8017d18: 0801e56c .word 0x0801e56c
8017d1c: 0801e77c .word 0x0801e77c
8017d20: 0801e5cc .word 0x0801e5cc
08017d24 <dhcp_option_long>:
static u16_t
dhcp_option_long(u16_t options_out_len, u8_t *options, u32_t value)
{
8017d24: b580 push {r7, lr}
8017d26: b084 sub sp, #16
8017d28: af00 add r7, sp, #0
8017d2a: 4603 mov r3, r0
8017d2c: 60b9 str r1, [r7, #8]
8017d2e: 607a str r2, [r7, #4]
8017d30: 81fb strh r3, [r7, #14]
LWIP_ASSERT("dhcp_option_long: options_out_len + 4 <= DHCP_OPTIONS_LEN", options_out_len + 4U <= DHCP_OPTIONS_LEN);
8017d32: 89fb ldrh r3, [r7, #14]
8017d34: 3304 adds r3, #4
8017d36: 2b44 cmp r3, #68 ; 0x44
8017d38: d906 bls.n 8017d48 <dhcp_option_long+0x24>
8017d3a: 4b19 ldr r3, [pc, #100] ; (8017da0 <dhcp_option_long+0x7c>)
8017d3c: f240 52b7 movw r2, #1463 ; 0x5b7
8017d40: 4918 ldr r1, [pc, #96] ; (8017da4 <dhcp_option_long+0x80>)
8017d42: 4819 ldr r0, [pc, #100] ; (8017da8 <dhcp_option_long+0x84>)
8017d44: f003 f93e bl 801afc4 <iprintf>
options[options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24);
8017d48: 687b ldr r3, [r7, #4]
8017d4a: 0e1a lsrs r2, r3, #24
8017d4c: 89fb ldrh r3, [r7, #14]
8017d4e: 1c59 adds r1, r3, #1
8017d50: 81f9 strh r1, [r7, #14]
8017d52: 4619 mov r1, r3
8017d54: 68bb ldr r3, [r7, #8]
8017d56: 440b add r3, r1
8017d58: b2d2 uxtb r2, r2
8017d5a: 701a strb r2, [r3, #0]
options[options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16);
8017d5c: 687b ldr r3, [r7, #4]
8017d5e: 0c1a lsrs r2, r3, #16
8017d60: 89fb ldrh r3, [r7, #14]
8017d62: 1c59 adds r1, r3, #1
8017d64: 81f9 strh r1, [r7, #14]
8017d66: 4619 mov r1, r3
8017d68: 68bb ldr r3, [r7, #8]
8017d6a: 440b add r3, r1
8017d6c: b2d2 uxtb r2, r2
8017d6e: 701a strb r2, [r3, #0]
options[options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8);
8017d70: 687b ldr r3, [r7, #4]
8017d72: 0a1a lsrs r2, r3, #8
8017d74: 89fb ldrh r3, [r7, #14]
8017d76: 1c59 adds r1, r3, #1
8017d78: 81f9 strh r1, [r7, #14]
8017d7a: 4619 mov r1, r3
8017d7c: 68bb ldr r3, [r7, #8]
8017d7e: 440b add r3, r1
8017d80: b2d2 uxtb r2, r2
8017d82: 701a strb r2, [r3, #0]
options[options_out_len++] = (u8_t)((value & 0x000000ffUL));
8017d84: 89fb ldrh r3, [r7, #14]
8017d86: 1c5a adds r2, r3, #1
8017d88: 81fa strh r2, [r7, #14]
8017d8a: 461a mov r2, r3
8017d8c: 68bb ldr r3, [r7, #8]
8017d8e: 4413 add r3, r2
8017d90: 687a ldr r2, [r7, #4]
8017d92: b2d2 uxtb r2, r2
8017d94: 701a strb r2, [r3, #0]
return options_out_len;
8017d96: 89fb ldrh r3, [r7, #14]
}
8017d98: 4618 mov r0, r3
8017d9a: 3710 adds r7, #16
8017d9c: 46bd mov sp, r7
8017d9e: bd80 pop {r7, pc}
8017da0: 0801e56c .word 0x0801e56c
8017da4: 0801e7b8 .word 0x0801e7b8
8017da8: 0801e5cc .word 0x0801e5cc
08017dac <dhcp_parse_reply>:
* use that further on.
*
*/
static err_t
dhcp_parse_reply(struct pbuf *p, struct dhcp *dhcp)
{
8017dac: b580 push {r7, lr}
8017dae: b090 sub sp, #64 ; 0x40
8017db0: af00 add r7, sp, #0
8017db2: 6078 str r0, [r7, #4]
8017db4: 6039 str r1, [r7, #0]
u16_t offset;
u16_t offset_max;
u16_t options_idx;
u16_t options_idx_max;
struct pbuf *q;
int parse_file_as_options = 0;
8017db6: 2300 movs r3, #0
8017db8: 62fb str r3, [r7, #44] ; 0x2c
int parse_sname_as_options = 0;
8017dba: 2300 movs r3, #0
8017dbc: 62bb str r3, [r7, #40] ; 0x28
#endif
LWIP_UNUSED_ARG(dhcp);
/* clear received options */
dhcp_clear_all_options(dhcp);
8017dbe: 2208 movs r2, #8
8017dc0: 2100 movs r1, #0
8017dc2: 48be ldr r0, [pc, #760] ; (80180bc <dhcp_parse_reply+0x310>)
8017dc4: f003 f8f6 bl 801afb4 <memset>
/* check that beginning of dhcp_msg (up to and including chaddr) is in first pbuf */
if (p->len < DHCP_SNAME_OFS) {
8017dc8: 687b ldr r3, [r7, #4]
8017dca: 895b ldrh r3, [r3, #10]
8017dcc: 2b2b cmp r3, #43 ; 0x2b
8017dce: d802 bhi.n 8017dd6 <dhcp_parse_reply+0x2a>
return ERR_BUF;
8017dd0: f06f 0301 mvn.w r3, #1
8017dd4: e2a8 b.n 8018328 <dhcp_parse_reply+0x57c>
}
msg_in = (struct dhcp_msg *)p->payload;
8017dd6: 687b ldr r3, [r7, #4]
8017dd8: 685b ldr r3, [r3, #4]
8017dda: 61bb str r3, [r7, #24]
#endif /* LWIP_DHCP_BOOTP_FILE */
/* parse options */
/* start with options field */
options_idx = DHCP_OPTIONS_OFS;
8017ddc: 23f0 movs r3, #240 ; 0xf0
8017dde: 86fb strh r3, [r7, #54] ; 0x36
/* parse options to the end of the received packet */
options_idx_max = p->tot_len;
8017de0: 687b ldr r3, [r7, #4]
8017de2: 891b ldrh r3, [r3, #8]
8017de4: 86bb strh r3, [r7, #52] ; 0x34
again:
q = p;
8017de6: 687b ldr r3, [r7, #4]
8017de8: 633b str r3, [r7, #48] ; 0x30
while ((q != NULL) && (options_idx >= q->len)) {
8017dea: e00c b.n 8017e06 <dhcp_parse_reply+0x5a>
options_idx = (u16_t)(options_idx - q->len);
8017dec: 6b3b ldr r3, [r7, #48] ; 0x30
8017dee: 895b ldrh r3, [r3, #10]
8017df0: 8efa ldrh r2, [r7, #54] ; 0x36
8017df2: 1ad3 subs r3, r2, r3
8017df4: 86fb strh r3, [r7, #54] ; 0x36
options_idx_max = (u16_t)(options_idx_max - q->len);
8017df6: 6b3b ldr r3, [r7, #48] ; 0x30
8017df8: 895b ldrh r3, [r3, #10]
8017dfa: 8eba ldrh r2, [r7, #52] ; 0x34
8017dfc: 1ad3 subs r3, r2, r3
8017dfe: 86bb strh r3, [r7, #52] ; 0x34
q = q->next;
8017e00: 6b3b ldr r3, [r7, #48] ; 0x30
8017e02: 681b ldr r3, [r3, #0]
8017e04: 633b str r3, [r7, #48] ; 0x30
while ((q != NULL) && (options_idx >= q->len)) {
8017e06: 6b3b ldr r3, [r7, #48] ; 0x30
8017e08: 2b00 cmp r3, #0
8017e0a: d004 beq.n 8017e16 <dhcp_parse_reply+0x6a>
8017e0c: 6b3b ldr r3, [r7, #48] ; 0x30
8017e0e: 895b ldrh r3, [r3, #10]
8017e10: 8efa ldrh r2, [r7, #54] ; 0x36
8017e12: 429a cmp r2, r3
8017e14: d2ea bcs.n 8017dec <dhcp_parse_reply+0x40>
}
if (q == NULL) {
8017e16: 6b3b ldr r3, [r7, #48] ; 0x30
8017e18: 2b00 cmp r3, #0
8017e1a: d102 bne.n 8017e22 <dhcp_parse_reply+0x76>
return ERR_BUF;
8017e1c: f06f 0301 mvn.w r3, #1
8017e20: e282 b.n 8018328 <dhcp_parse_reply+0x57c>
}
offset = options_idx;
8017e22: 8efb ldrh r3, [r7, #54] ; 0x36
8017e24: 877b strh r3, [r7, #58] ; 0x3a
offset_max = options_idx_max;
8017e26: 8ebb ldrh r3, [r7, #52] ; 0x34
8017e28: 873b strh r3, [r7, #56] ; 0x38
options = (u8_t *)q->payload;
8017e2a: 6b3b ldr r3, [r7, #48] ; 0x30
8017e2c: 685b ldr r3, [r3, #4]
8017e2e: 63fb str r3, [r7, #60] ; 0x3c
/* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
while ((q != NULL) && (offset < offset_max) && (options[offset] != DHCP_OPTION_END)) {
8017e30: e23a b.n 80182a8 <dhcp_parse_reply+0x4fc>
u8_t op = options[offset];
8017e32: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017e34: 6bfa ldr r2, [r7, #60] ; 0x3c
8017e36: 4413 add r3, r2
8017e38: 781b ldrb r3, [r3, #0]
8017e3a: 75fb strb r3, [r7, #23]
u8_t len;
u8_t decode_len = 0;
8017e3c: 2300 movs r3, #0
8017e3e: f887 3026 strb.w r3, [r7, #38] ; 0x26
int decode_idx = -1;
8017e42: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8017e46: 623b str r3, [r7, #32]
u16_t val_offset = (u16_t)(offset + 2);
8017e48: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017e4a: 3302 adds r3, #2
8017e4c: 83fb strh r3, [r7, #30]
if (val_offset < offset) {
8017e4e: 8bfa ldrh r2, [r7, #30]
8017e50: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017e52: 429a cmp r2, r3
8017e54: d202 bcs.n 8017e5c <dhcp_parse_reply+0xb0>
/* overflow */
return ERR_BUF;
8017e56: f06f 0301 mvn.w r3, #1
8017e5a: e265 b.n 8018328 <dhcp_parse_reply+0x57c>
}
/* len byte might be in the next pbuf */
if ((offset + 1) < q->len) {
8017e5c: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017e5e: 3301 adds r3, #1
8017e60: 6b3a ldr r2, [r7, #48] ; 0x30
8017e62: 8952 ldrh r2, [r2, #10]
8017e64: 4293 cmp r3, r2
8017e66: da07 bge.n 8017e78 <dhcp_parse_reply+0xcc>
len = options[offset + 1];
8017e68: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017e6a: 3301 adds r3, #1
8017e6c: 6bfa ldr r2, [r7, #60] ; 0x3c
8017e6e: 4413 add r3, r2
8017e70: 781b ldrb r3, [r3, #0]
8017e72: f887 3027 strb.w r3, [r7, #39] ; 0x27
8017e76: e00b b.n 8017e90 <dhcp_parse_reply+0xe4>
} else {
len = (q->next != NULL ? ((u8_t *)q->next->payload)[0] : 0);
8017e78: 6b3b ldr r3, [r7, #48] ; 0x30
8017e7a: 681b ldr r3, [r3, #0]
8017e7c: 2b00 cmp r3, #0
8017e7e: d004 beq.n 8017e8a <dhcp_parse_reply+0xde>
8017e80: 6b3b ldr r3, [r7, #48] ; 0x30
8017e82: 681b ldr r3, [r3, #0]
8017e84: 685b ldr r3, [r3, #4]
8017e86: 781b ldrb r3, [r3, #0]
8017e88: e000 b.n 8017e8c <dhcp_parse_reply+0xe0>
8017e8a: 2300 movs r3, #0
8017e8c: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
/* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */
decode_len = len;
8017e90: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8017e94: f887 3026 strb.w r3, [r7, #38] ; 0x26
switch (op) {
8017e98: 7dfb ldrb r3, [r7, #23]
8017e9a: 2b3b cmp r3, #59 ; 0x3b
8017e9c: f200 812d bhi.w 80180fa <dhcp_parse_reply+0x34e>
8017ea0: a201 add r2, pc, #4 ; (adr r2, 8017ea8 <dhcp_parse_reply+0xfc>)
8017ea2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8017ea6: bf00 nop
8017ea8: 08017f99 .word 0x08017f99
8017eac: 08017fa9 .word 0x08017fa9
8017eb0: 080180fb .word 0x080180fb
8017eb4: 08017fcb .word 0x08017fcb
8017eb8: 080180fb .word 0x080180fb
8017ebc: 080180fb .word 0x080180fb
8017ec0: 080180fb .word 0x080180fb
8017ec4: 080180fb .word 0x080180fb
8017ec8: 080180fb .word 0x080180fb
8017ecc: 080180fb .word 0x080180fb
8017ed0: 080180fb .word 0x080180fb
8017ed4: 080180fb .word 0x080180fb
8017ed8: 080180fb .word 0x080180fb
8017edc: 080180fb .word 0x080180fb
8017ee0: 080180fb .word 0x080180fb
8017ee4: 080180fb .word 0x080180fb
8017ee8: 080180fb .word 0x080180fb
8017eec: 080180fb .word 0x080180fb
8017ef0: 080180fb .word 0x080180fb
8017ef4: 080180fb .word 0x080180fb
8017ef8: 080180fb .word 0x080180fb
8017efc: 080180fb .word 0x080180fb
8017f00: 080180fb .word 0x080180fb
8017f04: 080180fb .word 0x080180fb
8017f08: 080180fb .word 0x080180fb
8017f0c: 080180fb .word 0x080180fb
8017f10: 080180fb .word 0x080180fb
8017f14: 080180fb .word 0x080180fb
8017f18: 080180fb .word 0x080180fb
8017f1c: 080180fb .word 0x080180fb
8017f20: 080180fb .word 0x080180fb
8017f24: 080180fb .word 0x080180fb
8017f28: 080180fb .word 0x080180fb
8017f2c: 080180fb .word 0x080180fb
8017f30: 080180fb .word 0x080180fb
8017f34: 080180fb .word 0x080180fb
8017f38: 080180fb .word 0x080180fb
8017f3c: 080180fb .word 0x080180fb
8017f40: 080180fb .word 0x080180fb
8017f44: 080180fb .word 0x080180fb
8017f48: 080180fb .word 0x080180fb
8017f4c: 080180fb .word 0x080180fb
8017f50: 080180fb .word 0x080180fb
8017f54: 080180fb .word 0x080180fb
8017f58: 080180fb .word 0x080180fb
8017f5c: 080180fb .word 0x080180fb
8017f60: 080180fb .word 0x080180fb
8017f64: 080180fb .word 0x080180fb
8017f68: 080180fb .word 0x080180fb
8017f6c: 080180fb .word 0x080180fb
8017f70: 080180fb .word 0x080180fb
8017f74: 08017ff7 .word 0x08017ff7
8017f78: 08018019 .word 0x08018019
8017f7c: 08018055 .word 0x08018055
8017f80: 08018077 .word 0x08018077
8017f84: 080180fb .word 0x080180fb
8017f88: 080180fb .word 0x080180fb
8017f8c: 080180fb .word 0x080180fb
8017f90: 08018099 .word 0x08018099
8017f94: 080180d9 .word 0x080180d9
/* case(DHCP_OPTION_END): handled above */
case (DHCP_OPTION_PAD):
/* special option: no len encoded */
decode_len = len = 0;
8017f98: 2300 movs r3, #0
8017f9a: f887 3027 strb.w r3, [r7, #39] ; 0x27
8017f9e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8017fa2: f887 3026 strb.w r3, [r7, #38] ; 0x26
/* will be increased below */
break;
8017fa6: e0ac b.n 8018102 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_SUBNET_MASK):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
8017fa8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8017fac: 2b04 cmp r3, #4
8017fae: d009 beq.n 8017fc4 <dhcp_parse_reply+0x218>
8017fb0: 4b43 ldr r3, [pc, #268] ; (80180c0 <dhcp_parse_reply+0x314>)
8017fb2: f240 622e movw r2, #1582 ; 0x62e
8017fb6: 4943 ldr r1, [pc, #268] ; (80180c4 <dhcp_parse_reply+0x318>)
8017fb8: 4843 ldr r0, [pc, #268] ; (80180c8 <dhcp_parse_reply+0x31c>)
8017fba: f003 f803 bl 801afc4 <iprintf>
8017fbe: f06f 0305 mvn.w r3, #5
8017fc2: e1b1 b.n 8018328 <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_SUBNET_MASK;
8017fc4: 2306 movs r3, #6
8017fc6: 623b str r3, [r7, #32]
break;
8017fc8: e09b b.n 8018102 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_ROUTER):
decode_len = 4; /* only copy the first given router */
8017fca: 2304 movs r3, #4
8017fcc: f887 3026 strb.w r3, [r7, #38] ; 0x26
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
8017fd0: f897 2027 ldrb.w r2, [r7, #39] ; 0x27
8017fd4: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8017fd8: 429a cmp r2, r3
8017fda: d209 bcs.n 8017ff0 <dhcp_parse_reply+0x244>
8017fdc: 4b38 ldr r3, [pc, #224] ; (80180c0 <dhcp_parse_reply+0x314>)
8017fde: f240 6233 movw r2, #1587 ; 0x633
8017fe2: 493a ldr r1, [pc, #232] ; (80180cc <dhcp_parse_reply+0x320>)
8017fe4: 4838 ldr r0, [pc, #224] ; (80180c8 <dhcp_parse_reply+0x31c>)
8017fe6: f002 ffed bl 801afc4 <iprintf>
8017fea: f06f 0305 mvn.w r3, #5
8017fee: e19b b.n 8018328 <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_ROUTER;
8017ff0: 2307 movs r3, #7
8017ff2: 623b str r3, [r7, #32]
break;
8017ff4: e085 b.n 8018102 <dhcp_parse_reply+0x356>
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_DNS_SERVER;
break;
#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
case (DHCP_OPTION_LEASE_TIME):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
8017ff6: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8017ffa: 2b04 cmp r3, #4
8017ffc: d009 beq.n 8018012 <dhcp_parse_reply+0x266>
8017ffe: 4b30 ldr r3, [pc, #192] ; (80180c0 <dhcp_parse_reply+0x314>)
8018000: f240 6241 movw r2, #1601 ; 0x641
8018004: 492f ldr r1, [pc, #188] ; (80180c4 <dhcp_parse_reply+0x318>)
8018006: 4830 ldr r0, [pc, #192] ; (80180c8 <dhcp_parse_reply+0x31c>)
8018008: f002 ffdc bl 801afc4 <iprintf>
801800c: f06f 0305 mvn.w r3, #5
8018010: e18a b.n 8018328 <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_LEASE_TIME;
8018012: 2303 movs r3, #3
8018014: 623b str r3, [r7, #32]
break;
8018016: e074 b.n 8018102 <dhcp_parse_reply+0x356>
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_NTP_SERVER;
break;
#endif /* LWIP_DHCP_GET_NTP_SRV*/
case (DHCP_OPTION_OVERLOAD):
LWIP_ERROR("len == 1", len == 1, return ERR_VAL;);
8018018: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801801c: 2b01 cmp r3, #1
801801e: d009 beq.n 8018034 <dhcp_parse_reply+0x288>
8018020: 4b27 ldr r3, [pc, #156] ; (80180c0 <dhcp_parse_reply+0x314>)
8018022: f240 624f movw r2, #1615 ; 0x64f
8018026: 492a ldr r1, [pc, #168] ; (80180d0 <dhcp_parse_reply+0x324>)
8018028: 4827 ldr r0, [pc, #156] ; (80180c8 <dhcp_parse_reply+0x31c>)
801802a: f002 ffcb bl 801afc4 <iprintf>
801802e: f06f 0305 mvn.w r3, #5
8018032: e179 b.n 8018328 <dhcp_parse_reply+0x57c>
/* decode overload only in options, not in file/sname: invalid packet */
LWIP_ERROR("overload in file/sname", options_idx == DHCP_OPTIONS_OFS, return ERR_VAL;);
8018034: 8efb ldrh r3, [r7, #54] ; 0x36
8018036: 2bf0 cmp r3, #240 ; 0xf0
8018038: d009 beq.n 801804e <dhcp_parse_reply+0x2a2>
801803a: 4b21 ldr r3, [pc, #132] ; (80180c0 <dhcp_parse_reply+0x314>)
801803c: f240 6251 movw r2, #1617 ; 0x651
8018040: 4924 ldr r1, [pc, #144] ; (80180d4 <dhcp_parse_reply+0x328>)
8018042: 4821 ldr r0, [pc, #132] ; (80180c8 <dhcp_parse_reply+0x31c>)
8018044: f002 ffbe bl 801afc4 <iprintf>
8018048: f06f 0305 mvn.w r3, #5
801804c: e16c b.n 8018328 <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_OVERLOAD;
801804e: 2300 movs r3, #0
8018050: 623b str r3, [r7, #32]
break;
8018052: e056 b.n 8018102 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_MESSAGE_TYPE):
LWIP_ERROR("len == 1", len == 1, return ERR_VAL;);
8018054: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018058: 2b01 cmp r3, #1
801805a: d009 beq.n 8018070 <dhcp_parse_reply+0x2c4>
801805c: 4b18 ldr r3, [pc, #96] ; (80180c0 <dhcp_parse_reply+0x314>)
801805e: f240 6255 movw r2, #1621 ; 0x655
8018062: 491b ldr r1, [pc, #108] ; (80180d0 <dhcp_parse_reply+0x324>)
8018064: 4818 ldr r0, [pc, #96] ; (80180c8 <dhcp_parse_reply+0x31c>)
8018066: f002 ffad bl 801afc4 <iprintf>
801806a: f06f 0305 mvn.w r3, #5
801806e: e15b b.n 8018328 <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_MSG_TYPE;
8018070: 2301 movs r3, #1
8018072: 623b str r3, [r7, #32]
break;
8018074: e045 b.n 8018102 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_SERVER_ID):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
8018076: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801807a: 2b04 cmp r3, #4
801807c: d009 beq.n 8018092 <dhcp_parse_reply+0x2e6>
801807e: 4b10 ldr r3, [pc, #64] ; (80180c0 <dhcp_parse_reply+0x314>)
8018080: f240 6259 movw r2, #1625 ; 0x659
8018084: 490f ldr r1, [pc, #60] ; (80180c4 <dhcp_parse_reply+0x318>)
8018086: 4810 ldr r0, [pc, #64] ; (80180c8 <dhcp_parse_reply+0x31c>)
8018088: f002 ff9c bl 801afc4 <iprintf>
801808c: f06f 0305 mvn.w r3, #5
8018090: e14a b.n 8018328 <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_SERVER_ID;
8018092: 2302 movs r3, #2
8018094: 623b str r3, [r7, #32]
break;
8018096: e034 b.n 8018102 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_T1):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
8018098: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801809c: 2b04 cmp r3, #4
801809e: d009 beq.n 80180b4 <dhcp_parse_reply+0x308>
80180a0: 4b07 ldr r3, [pc, #28] ; (80180c0 <dhcp_parse_reply+0x314>)
80180a2: f240 625d movw r2, #1629 ; 0x65d
80180a6: 4907 ldr r1, [pc, #28] ; (80180c4 <dhcp_parse_reply+0x318>)
80180a8: 4807 ldr r0, [pc, #28] ; (80180c8 <dhcp_parse_reply+0x31c>)
80180aa: f002 ff8b bl 801afc4 <iprintf>
80180ae: f06f 0305 mvn.w r3, #5
80180b2: e139 b.n 8018328 <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_T1;
80180b4: 2304 movs r3, #4
80180b6: 623b str r3, [r7, #32]
break;
80180b8: e023 b.n 8018102 <dhcp_parse_reply+0x356>
80180ba: bf00 nop
80180bc: 2000f858 .word 0x2000f858
80180c0: 0801e56c .word 0x0801e56c
80180c4: 0801e7f4 .word 0x0801e7f4
80180c8: 0801e5cc .word 0x0801e5cc
80180cc: 0801e800 .word 0x0801e800
80180d0: 0801e814 .word 0x0801e814
80180d4: 0801e820 .word 0x0801e820
case (DHCP_OPTION_T2):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
80180d8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80180dc: 2b04 cmp r3, #4
80180de: d009 beq.n 80180f4 <dhcp_parse_reply+0x348>
80180e0: 4b93 ldr r3, [pc, #588] ; (8018330 <dhcp_parse_reply+0x584>)
80180e2: f240 6261 movw r2, #1633 ; 0x661
80180e6: 4993 ldr r1, [pc, #588] ; (8018334 <dhcp_parse_reply+0x588>)
80180e8: 4893 ldr r0, [pc, #588] ; (8018338 <dhcp_parse_reply+0x58c>)
80180ea: f002 ff6b bl 801afc4 <iprintf>
80180ee: f06f 0305 mvn.w r3, #5
80180f2: e119 b.n 8018328 <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_T2;
80180f4: 2305 movs r3, #5
80180f6: 623b str r3, [r7, #32]
break;
80180f8: e003 b.n 8018102 <dhcp_parse_reply+0x356>
default:
decode_len = 0;
80180fa: 2300 movs r3, #0
80180fc: f887 3026 strb.w r3, [r7, #38] ; 0x26
LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", (u16_t)op));
LWIP_HOOK_DHCP_PARSE_OPTION(ip_current_netif(), dhcp, dhcp->state, msg_in,
dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) ? (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) : 0,
op, len, q, val_offset);
break;
8018100: bf00 nop
}
if (op == DHCP_OPTION_PAD) {
8018102: 7dfb ldrb r3, [r7, #23]
8018104: 2b00 cmp r3, #0
8018106: d103 bne.n 8018110 <dhcp_parse_reply+0x364>
offset++;
8018108: 8f7b ldrh r3, [r7, #58] ; 0x3a
801810a: 3301 adds r3, #1
801810c: 877b strh r3, [r7, #58] ; 0x3a
801810e: e0a1 b.n 8018254 <dhcp_parse_reply+0x4a8>
} else {
if (offset + len + 2 > 0xFFFF) {
8018110: 8f7a ldrh r2, [r7, #58] ; 0x3a
8018112: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018116: 4413 add r3, r2
8018118: f64f 72fd movw r2, #65533 ; 0xfffd
801811c: 4293 cmp r3, r2
801811e: dd02 ble.n 8018126 <dhcp_parse_reply+0x37a>
/* overflow */
return ERR_BUF;
8018120: f06f 0301 mvn.w r3, #1
8018124: e100 b.n 8018328 <dhcp_parse_reply+0x57c>
}
offset = (u16_t)(offset + len + 2);
8018126: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801812a: b29a uxth r2, r3
801812c: 8f7b ldrh r3, [r7, #58] ; 0x3a
801812e: 4413 add r3, r2
8018130: b29b uxth r3, r3
8018132: 3302 adds r3, #2
8018134: 877b strh r3, [r7, #58] ; 0x3a
if (decode_len > 0) {
8018136: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
801813a: 2b00 cmp r3, #0
801813c: f000 808a beq.w 8018254 <dhcp_parse_reply+0x4a8>
u32_t value = 0;
8018140: 2300 movs r3, #0
8018142: 60bb str r3, [r7, #8]
u16_t copy_len;
decode_next:
LWIP_ASSERT("check decode_idx", decode_idx >= 0 && decode_idx < DHCP_OPTION_IDX_MAX);
8018144: 6a3b ldr r3, [r7, #32]
8018146: 2b00 cmp r3, #0
8018148: db02 blt.n 8018150 <dhcp_parse_reply+0x3a4>
801814a: 6a3b ldr r3, [r7, #32]
801814c: 2b07 cmp r3, #7
801814e: dd06 ble.n 801815e <dhcp_parse_reply+0x3b2>
8018150: 4b77 ldr r3, [pc, #476] ; (8018330 <dhcp_parse_reply+0x584>)
8018152: f44f 62cf mov.w r2, #1656 ; 0x678
8018156: 4979 ldr r1, [pc, #484] ; (801833c <dhcp_parse_reply+0x590>)
8018158: 4877 ldr r0, [pc, #476] ; (8018338 <dhcp_parse_reply+0x58c>)
801815a: f002 ff33 bl 801afc4 <iprintf>
if (!dhcp_option_given(dhcp, decode_idx)) {
801815e: 4a78 ldr r2, [pc, #480] ; (8018340 <dhcp_parse_reply+0x594>)
8018160: 6a3b ldr r3, [r7, #32]
8018162: 4413 add r3, r2
8018164: 781b ldrb r3, [r3, #0]
8018166: 2b00 cmp r3, #0
8018168: d174 bne.n 8018254 <dhcp_parse_reply+0x4a8>
copy_len = LWIP_MIN(decode_len, 4);
801816a: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
801816e: 2b04 cmp r3, #4
8018170: bf28 it cs
8018172: 2304 movcs r3, #4
8018174: b2db uxtb r3, r3
8018176: 82bb strh r3, [r7, #20]
if (pbuf_copy_partial(q, &value, copy_len, val_offset) != copy_len) {
8018178: 8bfb ldrh r3, [r7, #30]
801817a: 8aba ldrh r2, [r7, #20]
801817c: f107 0108 add.w r1, r7, #8
8018180: 6b38 ldr r0, [r7, #48] ; 0x30
8018182: f7f8 fc19 bl 80109b8 <pbuf_copy_partial>
8018186: 4603 mov r3, r0
8018188: 461a mov r2, r3
801818a: 8abb ldrh r3, [r7, #20]
801818c: 4293 cmp r3, r2
801818e: d002 beq.n 8018196 <dhcp_parse_reply+0x3ea>
return ERR_BUF;
8018190: f06f 0301 mvn.w r3, #1
8018194: e0c8 b.n 8018328 <dhcp_parse_reply+0x57c>
}
if (decode_len > 4) {
8018196: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
801819a: 2b04 cmp r3, #4
801819c: d933 bls.n 8018206 <dhcp_parse_reply+0x45a>
/* decode more than one u32_t */
u16_t next_val_offset;
LWIP_ERROR("decode_len %% 4 == 0", decode_len % 4 == 0, return ERR_VAL;);
801819e: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
80181a2: f003 0303 and.w r3, r3, #3
80181a6: b2db uxtb r3, r3
80181a8: 2b00 cmp r3, #0
80181aa: d009 beq.n 80181c0 <dhcp_parse_reply+0x414>
80181ac: 4b60 ldr r3, [pc, #384] ; (8018330 <dhcp_parse_reply+0x584>)
80181ae: f240 6281 movw r2, #1665 ; 0x681
80181b2: 4964 ldr r1, [pc, #400] ; (8018344 <dhcp_parse_reply+0x598>)
80181b4: 4860 ldr r0, [pc, #384] ; (8018338 <dhcp_parse_reply+0x58c>)
80181b6: f002 ff05 bl 801afc4 <iprintf>
80181ba: f06f 0305 mvn.w r3, #5
80181be: e0b3 b.n 8018328 <dhcp_parse_reply+0x57c>
dhcp_got_option(dhcp, decode_idx);
80181c0: 4a5f ldr r2, [pc, #380] ; (8018340 <dhcp_parse_reply+0x594>)
80181c2: 6a3b ldr r3, [r7, #32]
80181c4: 4413 add r3, r2
80181c6: 2201 movs r2, #1
80181c8: 701a strb r2, [r3, #0]
dhcp_set_option_value(dhcp, decode_idx, lwip_htonl(value));
80181ca: 68bb ldr r3, [r7, #8]
80181cc: 4618 mov r0, r3
80181ce: f7f6 fe4a bl 800ee66 <lwip_htonl>
80181d2: 4602 mov r2, r0
80181d4: 495c ldr r1, [pc, #368] ; (8018348 <dhcp_parse_reply+0x59c>)
80181d6: 6a3b ldr r3, [r7, #32]
80181d8: f841 2023 str.w r2, [r1, r3, lsl #2]
decode_len = (u8_t)(decode_len - 4);
80181dc: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
80181e0: 3b04 subs r3, #4
80181e2: f887 3026 strb.w r3, [r7, #38] ; 0x26
next_val_offset = (u16_t)(val_offset + 4);
80181e6: 8bfb ldrh r3, [r7, #30]
80181e8: 3304 adds r3, #4
80181ea: 827b strh r3, [r7, #18]
if (next_val_offset < val_offset) {
80181ec: 8a7a ldrh r2, [r7, #18]
80181ee: 8bfb ldrh r3, [r7, #30]
80181f0: 429a cmp r2, r3
80181f2: d202 bcs.n 80181fa <dhcp_parse_reply+0x44e>
/* overflow */
return ERR_BUF;
80181f4: f06f 0301 mvn.w r3, #1
80181f8: e096 b.n 8018328 <dhcp_parse_reply+0x57c>
}
val_offset = next_val_offset;
80181fa: 8a7b ldrh r3, [r7, #18]
80181fc: 83fb strh r3, [r7, #30]
decode_idx++;
80181fe: 6a3b ldr r3, [r7, #32]
8018200: 3301 adds r3, #1
8018202: 623b str r3, [r7, #32]
goto decode_next;
8018204: e79e b.n 8018144 <dhcp_parse_reply+0x398>
} else if (decode_len == 4) {
8018206: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
801820a: 2b04 cmp r3, #4
801820c: d106 bne.n 801821c <dhcp_parse_reply+0x470>
value = lwip_ntohl(value);
801820e: 68bb ldr r3, [r7, #8]
8018210: 4618 mov r0, r3
8018212: f7f6 fe28 bl 800ee66 <lwip_htonl>
8018216: 4603 mov r3, r0
8018218: 60bb str r3, [r7, #8]
801821a: e011 b.n 8018240 <dhcp_parse_reply+0x494>
} else {
LWIP_ERROR("invalid decode_len", decode_len == 1, return ERR_VAL;);
801821c: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8018220: 2b01 cmp r3, #1
8018222: d009 beq.n 8018238 <dhcp_parse_reply+0x48c>
8018224: 4b42 ldr r3, [pc, #264] ; (8018330 <dhcp_parse_reply+0x584>)
8018226: f44f 62d2 mov.w r2, #1680 ; 0x690
801822a: 4948 ldr r1, [pc, #288] ; (801834c <dhcp_parse_reply+0x5a0>)
801822c: 4842 ldr r0, [pc, #264] ; (8018338 <dhcp_parse_reply+0x58c>)
801822e: f002 fec9 bl 801afc4 <iprintf>
8018232: f06f 0305 mvn.w r3, #5
8018236: e077 b.n 8018328 <dhcp_parse_reply+0x57c>
value = ((u8_t *)&value)[0];
8018238: f107 0308 add.w r3, r7, #8
801823c: 781b ldrb r3, [r3, #0]
801823e: 60bb str r3, [r7, #8]
}
dhcp_got_option(dhcp, decode_idx);
8018240: 4a3f ldr r2, [pc, #252] ; (8018340 <dhcp_parse_reply+0x594>)
8018242: 6a3b ldr r3, [r7, #32]
8018244: 4413 add r3, r2
8018246: 2201 movs r2, #1
8018248: 701a strb r2, [r3, #0]
dhcp_set_option_value(dhcp, decode_idx, value);
801824a: 68ba ldr r2, [r7, #8]
801824c: 493e ldr r1, [pc, #248] ; (8018348 <dhcp_parse_reply+0x59c>)
801824e: 6a3b ldr r3, [r7, #32]
8018250: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
}
if (offset >= q->len) {
8018254: 6b3b ldr r3, [r7, #48] ; 0x30
8018256: 895b ldrh r3, [r3, #10]
8018258: 8f7a ldrh r2, [r7, #58] ; 0x3a
801825a: 429a cmp r2, r3
801825c: d324 bcc.n 80182a8 <dhcp_parse_reply+0x4fc>
offset = (u16_t)(offset - q->len);
801825e: 6b3b ldr r3, [r7, #48] ; 0x30
8018260: 895b ldrh r3, [r3, #10]
8018262: 8f7a ldrh r2, [r7, #58] ; 0x3a
8018264: 1ad3 subs r3, r2, r3
8018266: 877b strh r3, [r7, #58] ; 0x3a
offset_max = (u16_t)(offset_max - q->len);
8018268: 6b3b ldr r3, [r7, #48] ; 0x30
801826a: 895b ldrh r3, [r3, #10]
801826c: 8f3a ldrh r2, [r7, #56] ; 0x38
801826e: 1ad3 subs r3, r2, r3
8018270: 873b strh r3, [r7, #56] ; 0x38
if (offset < offset_max) {
8018272: 8f7a ldrh r2, [r7, #58] ; 0x3a
8018274: 8f3b ldrh r3, [r7, #56] ; 0x38
8018276: 429a cmp r2, r3
8018278: d213 bcs.n 80182a2 <dhcp_parse_reply+0x4f6>
q = q->next;
801827a: 6b3b ldr r3, [r7, #48] ; 0x30
801827c: 681b ldr r3, [r3, #0]
801827e: 633b str r3, [r7, #48] ; 0x30
LWIP_ERROR("next pbuf was null", q != NULL, return ERR_VAL;);
8018280: 6b3b ldr r3, [r7, #48] ; 0x30
8018282: 2b00 cmp r3, #0
8018284: d109 bne.n 801829a <dhcp_parse_reply+0x4ee>
8018286: 4b2a ldr r3, [pc, #168] ; (8018330 <dhcp_parse_reply+0x584>)
8018288: f240 629d movw r2, #1693 ; 0x69d
801828c: 4930 ldr r1, [pc, #192] ; (8018350 <dhcp_parse_reply+0x5a4>)
801828e: 482a ldr r0, [pc, #168] ; (8018338 <dhcp_parse_reply+0x58c>)
8018290: f002 fe98 bl 801afc4 <iprintf>
8018294: f06f 0305 mvn.w r3, #5
8018298: e046 b.n 8018328 <dhcp_parse_reply+0x57c>
options = (u8_t *)q->payload;
801829a: 6b3b ldr r3, [r7, #48] ; 0x30
801829c: 685b ldr r3, [r3, #4]
801829e: 63fb str r3, [r7, #60] ; 0x3c
80182a0: e002 b.n 80182a8 <dhcp_parse_reply+0x4fc>
} else {
/* We've run out of bytes, probably no end marker. Don't proceed. */
return ERR_BUF;
80182a2: f06f 0301 mvn.w r3, #1
80182a6: e03f b.n 8018328 <dhcp_parse_reply+0x57c>
while ((q != NULL) && (offset < offset_max) && (options[offset] != DHCP_OPTION_END)) {
80182a8: 6b3b ldr r3, [r7, #48] ; 0x30
80182aa: 2b00 cmp r3, #0
80182ac: d00a beq.n 80182c4 <dhcp_parse_reply+0x518>
80182ae: 8f7a ldrh r2, [r7, #58] ; 0x3a
80182b0: 8f3b ldrh r3, [r7, #56] ; 0x38
80182b2: 429a cmp r2, r3
80182b4: d206 bcs.n 80182c4 <dhcp_parse_reply+0x518>
80182b6: 8f7b ldrh r3, [r7, #58] ; 0x3a
80182b8: 6bfa ldr r2, [r7, #60] ; 0x3c
80182ba: 4413 add r3, r2
80182bc: 781b ldrb r3, [r3, #0]
80182be: 2bff cmp r3, #255 ; 0xff
80182c0: f47f adb7 bne.w 8017e32 <dhcp_parse_reply+0x86>
}
}
}
/* is this an overloaded message? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_OVERLOAD)) {
80182c4: 4b1e ldr r3, [pc, #120] ; (8018340 <dhcp_parse_reply+0x594>)
80182c6: 781b ldrb r3, [r3, #0]
80182c8: 2b00 cmp r3, #0
80182ca: d018 beq.n 80182fe <dhcp_parse_reply+0x552>
u32_t overload = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_OVERLOAD);
80182cc: 4b1e ldr r3, [pc, #120] ; (8018348 <dhcp_parse_reply+0x59c>)
80182ce: 681b ldr r3, [r3, #0]
80182d0: 60fb str r3, [r7, #12]
dhcp_clear_option(dhcp, DHCP_OPTION_IDX_OVERLOAD);
80182d2: 4b1b ldr r3, [pc, #108] ; (8018340 <dhcp_parse_reply+0x594>)
80182d4: 2200 movs r2, #0
80182d6: 701a strb r2, [r3, #0]
if (overload == DHCP_OVERLOAD_FILE) {
80182d8: 68fb ldr r3, [r7, #12]
80182da: 2b01 cmp r3, #1
80182dc: d102 bne.n 80182e4 <dhcp_parse_reply+0x538>
parse_file_as_options = 1;
80182de: 2301 movs r3, #1
80182e0: 62fb str r3, [r7, #44] ; 0x2c
80182e2: e00c b.n 80182fe <dhcp_parse_reply+0x552>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n"));
} else if (overload == DHCP_OVERLOAD_SNAME) {
80182e4: 68fb ldr r3, [r7, #12]
80182e6: 2b02 cmp r3, #2
80182e8: d102 bne.n 80182f0 <dhcp_parse_reply+0x544>
parse_sname_as_options = 1;
80182ea: 2301 movs r3, #1
80182ec: 62bb str r3, [r7, #40] ; 0x28
80182ee: e006 b.n 80182fe <dhcp_parse_reply+0x552>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n"));
} else if (overload == DHCP_OVERLOAD_SNAME_FILE) {
80182f0: 68fb ldr r3, [r7, #12]
80182f2: 2b03 cmp r3, #3
80182f4: d103 bne.n 80182fe <dhcp_parse_reply+0x552>
parse_sname_as_options = 1;
80182f6: 2301 movs r3, #1
80182f8: 62bb str r3, [r7, #40] ; 0x28
parse_file_as_options = 1;
80182fa: 2301 movs r3, #1
80182fc: 62fb str r3, [r7, #44] ; 0x2c
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("invalid overload option: %d\n", (int)overload));
}
}
if (parse_file_as_options) {
80182fe: 6afb ldr r3, [r7, #44] ; 0x2c
8018300: 2b00 cmp r3, #0
8018302: d006 beq.n 8018312 <dhcp_parse_reply+0x566>
/* if both are overloaded, parse file first and then sname (RFC 2131 ch. 4.1) */
parse_file_as_options = 0;
8018304: 2300 movs r3, #0
8018306: 62fb str r3, [r7, #44] ; 0x2c
options_idx = DHCP_FILE_OFS;
8018308: 236c movs r3, #108 ; 0x6c
801830a: 86fb strh r3, [r7, #54] ; 0x36
options_idx_max = DHCP_FILE_OFS + DHCP_FILE_LEN;
801830c: 23ec movs r3, #236 ; 0xec
801830e: 86bb strh r3, [r7, #52] ; 0x34
#if LWIP_DHCP_BOOTP_FILE
file_overloaded = 1;
#endif
goto again;
8018310: e569 b.n 8017de6 <dhcp_parse_reply+0x3a>
} else if (parse_sname_as_options) {
8018312: 6abb ldr r3, [r7, #40] ; 0x28
8018314: 2b00 cmp r3, #0
8018316: d006 beq.n 8018326 <dhcp_parse_reply+0x57a>
parse_sname_as_options = 0;
8018318: 2300 movs r3, #0
801831a: 62bb str r3, [r7, #40] ; 0x28
options_idx = DHCP_SNAME_OFS;
801831c: 232c movs r3, #44 ; 0x2c
801831e: 86fb strh r3, [r7, #54] ; 0x36
options_idx_max = DHCP_SNAME_OFS + DHCP_SNAME_LEN;
8018320: 236c movs r3, #108 ; 0x6c
8018322: 86bb strh r3, [r7, #52] ; 0x34
goto again;
8018324: e55f b.n 8017de6 <dhcp_parse_reply+0x3a>
}
/* make sure the string is really NULL-terminated */
dhcp->boot_file_name[DHCP_FILE_LEN-1] = 0;
}
#endif /* LWIP_DHCP_BOOTP_FILE */
return ERR_OK;
8018326: 2300 movs r3, #0
}
8018328: 4618 mov r0, r3
801832a: 3740 adds r7, #64 ; 0x40
801832c: 46bd mov sp, r7
801832e: bd80 pop {r7, pc}
8018330: 0801e56c .word 0x0801e56c
8018334: 0801e7f4 .word 0x0801e7f4
8018338: 0801e5cc .word 0x0801e5cc
801833c: 0801e838 .word 0x0801e838
8018340: 2000f858 .word 0x2000f858
8018344: 0801e84c .word 0x0801e84c
8018348: 2000f860 .word 0x2000f860
801834c: 0801e864 .word 0x0801e864
8018350: 0801e878 .word 0x0801e878
08018354 <dhcp_recv>:
/**
* If an incoming DHCP message is in response to us, then trigger the state machine
*/
static void
dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port)
{
8018354: b580 push {r7, lr}
8018356: b08a sub sp, #40 ; 0x28
8018358: af00 add r7, sp, #0
801835a: 60f8 str r0, [r7, #12]
801835c: 60b9 str r1, [r7, #8]
801835e: 607a str r2, [r7, #4]
8018360: 603b str r3, [r7, #0]
struct netif *netif = ip_current_input_netif();
8018362: 4b60 ldr r3, [pc, #384] ; (80184e4 <dhcp_recv+0x190>)
8018364: 685b ldr r3, [r3, #4]
8018366: 623b str r3, [r7, #32]
struct dhcp *dhcp = netif_dhcp_data(netif);
8018368: 6a3b ldr r3, [r7, #32]
801836a: 6a5b ldr r3, [r3, #36] ; 0x24
801836c: 61fb str r3, [r7, #28]
struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
801836e: 687b ldr r3, [r7, #4]
8018370: 685b ldr r3, [r3, #4]
8018372: 61bb str r3, [r7, #24]
struct dhcp_msg *msg_in;
LWIP_UNUSED_ARG(arg);
/* Caught DHCP message from netif that does not have DHCP enabled? -> not interested */
if ((dhcp == NULL) || (dhcp->pcb_allocated == 0)) {
8018374: 69fb ldr r3, [r7, #28]
8018376: 2b00 cmp r3, #0
8018378: f000 809d beq.w 80184b6 <dhcp_recv+0x162>
801837c: 69fb ldr r3, [r7, #28]
801837e: 791b ldrb r3, [r3, #4]
8018380: 2b00 cmp r3, #0
8018382: f000 8098 beq.w 80184b6 <dhcp_recv+0x162>
/* prevent warnings about unused arguments */
LWIP_UNUSED_ARG(pcb);
LWIP_UNUSED_ARG(addr);
LWIP_UNUSED_ARG(port);
if (p->len < DHCP_MIN_REPLY_LEN) {
8018386: 687b ldr r3, [r7, #4]
8018388: 895b ldrh r3, [r3, #10]
801838a: 2b2b cmp r3, #43 ; 0x2b
801838c: f240 8095 bls.w 80184ba <dhcp_recv+0x166>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message or pbuf too short\n"));
goto free_pbuf_and_return;
}
if (reply_msg->op != DHCP_BOOTREPLY) {
8018390: 69bb ldr r3, [r7, #24]
8018392: 781b ldrb r3, [r3, #0]
8018394: 2b02 cmp r3, #2
8018396: f040 8092 bne.w 80184be <dhcp_recv+0x16a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op));
goto free_pbuf_and_return;
}
/* iterate through hardware address and match against DHCP message */
for (i = 0; i < netif->hwaddr_len && i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
801839a: 2300 movs r3, #0
801839c: f887 3027 strb.w r3, [r7, #39] ; 0x27
80183a0: e012 b.n 80183c8 <dhcp_recv+0x74>
if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
80183a2: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80183a6: 6a3a ldr r2, [r7, #32]
80183a8: 4413 add r3, r2
80183aa: f893 202a ldrb.w r2, [r3, #42] ; 0x2a
80183ae: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80183b2: 69b9 ldr r1, [r7, #24]
80183b4: 440b add r3, r1
80183b6: 7f1b ldrb r3, [r3, #28]
80183b8: 429a cmp r2, r3
80183ba: f040 8082 bne.w 80184c2 <dhcp_recv+0x16e>
for (i = 0; i < netif->hwaddr_len && i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
80183be: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80183c2: 3301 adds r3, #1
80183c4: f887 3027 strb.w r3, [r7, #39] ; 0x27
80183c8: 6a3b ldr r3, [r7, #32]
80183ca: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
80183ce: f897 2027 ldrb.w r2, [r7, #39] ; 0x27
80183d2: 429a cmp r2, r3
80183d4: d203 bcs.n 80183de <dhcp_recv+0x8a>
80183d6: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80183da: 2b05 cmp r3, #5
80183dc: d9e1 bls.n 80183a2 <dhcp_recv+0x4e>
(u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i]));
goto free_pbuf_and_return;
}
}
/* match transaction ID against what we expected */
if (lwip_ntohl(reply_msg->xid) != dhcp->xid) {
80183de: 69bb ldr r3, [r7, #24]
80183e0: 685b ldr r3, [r3, #4]
80183e2: 4618 mov r0, r3
80183e4: f7f6 fd3f bl 800ee66 <lwip_htonl>
80183e8: 4602 mov r2, r0
80183ea: 69fb ldr r3, [r7, #28]
80183ec: 681b ldr r3, [r3, #0]
80183ee: 429a cmp r2, r3
80183f0: d169 bne.n 80184c6 <dhcp_recv+0x172>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n", lwip_ntohl(reply_msg->xid), dhcp->xid));
goto free_pbuf_and_return;
}
/* option fields could be unfold? */
if (dhcp_parse_reply(p, dhcp) != ERR_OK) {
80183f2: 69f9 ldr r1, [r7, #28]
80183f4: 6878 ldr r0, [r7, #4]
80183f6: f7ff fcd9 bl 8017dac <dhcp_parse_reply>
80183fa: 4603 mov r3, r0
80183fc: 2b00 cmp r3, #0
80183fe: d164 bne.n 80184ca <dhcp_recv+0x176>
goto free_pbuf_and_return;
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
/* obtain pointer to DHCP message type */
if (!dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE)) {
8018400: 4b39 ldr r3, [pc, #228] ; (80184e8 <dhcp_recv+0x194>)
8018402: 785b ldrb r3, [r3, #1]
8018404: 2b00 cmp r3, #0
8018406: d062 beq.n 80184ce <dhcp_recv+0x17a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
goto free_pbuf_and_return;
}
msg_in = (struct dhcp_msg *)p->payload;
8018408: 687b ldr r3, [r7, #4]
801840a: 685b ldr r3, [r3, #4]
801840c: 617b str r3, [r7, #20]
/* read DHCP message type */
msg_type = (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE);
801840e: 4b37 ldr r3, [pc, #220] ; (80184ec <dhcp_recv+0x198>)
8018410: 685b ldr r3, [r3, #4]
8018412: 74fb strb r3, [r7, #19]
/* message type is DHCP ACK? */
if (msg_type == DHCP_ACK) {
8018414: 7cfb ldrb r3, [r7, #19]
8018416: 2b05 cmp r3, #5
8018418: d12a bne.n 8018470 <dhcp_recv+0x11c>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n"));
/* in requesting state? */
if (dhcp->state == DHCP_STATE_REQUESTING) {
801841a: 69fb ldr r3, [r7, #28]
801841c: 795b ldrb r3, [r3, #5]
801841e: 2b01 cmp r3, #1
8018420: d112 bne.n 8018448 <dhcp_recv+0xf4>
dhcp_handle_ack(netif, msg_in);
8018422: 6979 ldr r1, [r7, #20]
8018424: 6a38 ldr r0, [r7, #32]
8018426: f7fe fe17 bl 8017058 <dhcp_handle_ack>
#if DHCP_DOES_ARP_CHECK
if ((netif->flags & NETIF_FLAG_ETHARP) != 0) {
801842a: 6a3b ldr r3, [r7, #32]
801842c: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8018430: f003 0308 and.w r3, r3, #8
8018434: 2b00 cmp r3, #0
8018436: d003 beq.n 8018440 <dhcp_recv+0xec>
/* check if the acknowledged lease address is already in use */
dhcp_check(netif);
8018438: 6a38 ldr r0, [r7, #32]
801843a: f7fe fb85 bl 8016b48 <dhcp_check>
801843e: e049 b.n 80184d4 <dhcp_recv+0x180>
} else {
/* bind interface to the acknowledged lease address */
dhcp_bind(netif);
8018440: 6a38 ldr r0, [r7, #32]
8018442: f7ff f867 bl 8017514 <dhcp_bind>
8018446: e045 b.n 80184d4 <dhcp_recv+0x180>
/* bind interface to the acknowledged lease address */
dhcp_bind(netif);
#endif
}
/* already bound to the given lease address? */
else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) ||
8018448: 69fb ldr r3, [r7, #28]
801844a: 795b ldrb r3, [r3, #5]
801844c: 2b03 cmp r3, #3
801844e: d007 beq.n 8018460 <dhcp_recv+0x10c>
8018450: 69fb ldr r3, [r7, #28]
8018452: 795b ldrb r3, [r3, #5]
8018454: 2b04 cmp r3, #4
8018456: d003 beq.n 8018460 <dhcp_recv+0x10c>
(dhcp->state == DHCP_STATE_RENEWING)) {
8018458: 69fb ldr r3, [r7, #28]
801845a: 795b ldrb r3, [r3, #5]
else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) ||
801845c: 2b05 cmp r3, #5
801845e: d139 bne.n 80184d4 <dhcp_recv+0x180>
dhcp_handle_ack(netif, msg_in);
8018460: 6979 ldr r1, [r7, #20]
8018462: 6a38 ldr r0, [r7, #32]
8018464: f7fe fdf8 bl 8017058 <dhcp_handle_ack>
dhcp_bind(netif);
8018468: 6a38 ldr r0, [r7, #32]
801846a: f7ff f853 bl 8017514 <dhcp_bind>
801846e: e031 b.n 80184d4 <dhcp_recv+0x180>
}
}
/* received a DHCP_NAK in appropriate state? */
else if ((msg_type == DHCP_NAK) &&
8018470: 7cfb ldrb r3, [r7, #19]
8018472: 2b06 cmp r3, #6
8018474: d113 bne.n 801849e <dhcp_recv+0x14a>
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
8018476: 69fb ldr r3, [r7, #28]
8018478: 795b ldrb r3, [r3, #5]
else if ((msg_type == DHCP_NAK) &&
801847a: 2b03 cmp r3, #3
801847c: d00b beq.n 8018496 <dhcp_recv+0x142>
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
801847e: 69fb ldr r3, [r7, #28]
8018480: 795b ldrb r3, [r3, #5]
8018482: 2b01 cmp r3, #1
8018484: d007 beq.n 8018496 <dhcp_recv+0x142>
(dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) {
8018486: 69fb ldr r3, [r7, #28]
8018488: 795b ldrb r3, [r3, #5]
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
801848a: 2b04 cmp r3, #4
801848c: d003 beq.n 8018496 <dhcp_recv+0x142>
(dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) {
801848e: 69fb ldr r3, [r7, #28]
8018490: 795b ldrb r3, [r3, #5]
8018492: 2b05 cmp r3, #5
8018494: d103 bne.n 801849e <dhcp_recv+0x14a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n"));
dhcp_handle_nak(netif);
8018496: 6a38 ldr r0, [r7, #32]
8018498: f7fe fb3c bl 8016b14 <dhcp_handle_nak>
801849c: e01a b.n 80184d4 <dhcp_recv+0x180>
}
/* received a DHCP_OFFER in DHCP_STATE_SELECTING state? */
else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_STATE_SELECTING)) {
801849e: 7cfb ldrb r3, [r7, #19]
80184a0: 2b02 cmp r3, #2
80184a2: d116 bne.n 80184d2 <dhcp_recv+0x17e>
80184a4: 69fb ldr r3, [r7, #28]
80184a6: 795b ldrb r3, [r3, #5]
80184a8: 2b06 cmp r3, #6
80184aa: d112 bne.n 80184d2 <dhcp_recv+0x17e>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_STATE_SELECTING state\n"));
/* remember offered lease */
dhcp_handle_offer(netif, msg_in);
80184ac: 6979 ldr r1, [r7, #20]
80184ae: 6a38 ldr r0, [r7, #32]
80184b0: f7fe fb7e bl 8016bb0 <dhcp_handle_offer>
80184b4: e00e b.n 80184d4 <dhcp_recv+0x180>
goto free_pbuf_and_return;
80184b6: bf00 nop
80184b8: e00c b.n 80184d4 <dhcp_recv+0x180>
goto free_pbuf_and_return;
80184ba: bf00 nop
80184bc: e00a b.n 80184d4 <dhcp_recv+0x180>
goto free_pbuf_and_return;
80184be: bf00 nop
80184c0: e008 b.n 80184d4 <dhcp_recv+0x180>
goto free_pbuf_and_return;
80184c2: bf00 nop
80184c4: e006 b.n 80184d4 <dhcp_recv+0x180>
goto free_pbuf_and_return;
80184c6: bf00 nop
80184c8: e004 b.n 80184d4 <dhcp_recv+0x180>
goto free_pbuf_and_return;
80184ca: bf00 nop
80184cc: e002 b.n 80184d4 <dhcp_recv+0x180>
goto free_pbuf_and_return;
80184ce: bf00 nop
80184d0: e000 b.n 80184d4 <dhcp_recv+0x180>
}
free_pbuf_and_return:
80184d2: bf00 nop
pbuf_free(p);
80184d4: 6878 ldr r0, [r7, #4]
80184d6: f7f8 f869 bl 80105ac <pbuf_free>
}
80184da: bf00 nop
80184dc: 3728 adds r7, #40 ; 0x28
80184de: 46bd mov sp, r7
80184e0: bd80 pop {r7, pc}
80184e2: bf00 nop
80184e4: 2000c108 .word 0x2000c108
80184e8: 2000f858 .word 0x2000f858
80184ec: 2000f860 .word 0x2000f860
080184f0 <dhcp_create_msg>:
* @param dhcp dhcp control struct
* @param message_type message type of the request
*/
static struct pbuf *
dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type, u16_t *options_out_len)
{
80184f0: b580 push {r7, lr}
80184f2: b088 sub sp, #32
80184f4: af00 add r7, sp, #0
80184f6: 60f8 str r0, [r7, #12]
80184f8: 60b9 str r1, [r7, #8]
80184fa: 603b str r3, [r7, #0]
80184fc: 4613 mov r3, r2
80184fe: 71fb strb r3, [r7, #7]
if (!xid_initialised) {
xid = DHCP_GLOBAL_XID;
xid_initialised = !xid_initialised;
}
#endif
LWIP_ERROR("dhcp_create_msg: netif != NULL", (netif != NULL), return NULL;);
8018500: 68fb ldr r3, [r7, #12]
8018502: 2b00 cmp r3, #0
8018504: d108 bne.n 8018518 <dhcp_create_msg+0x28>
8018506: 4b5f ldr r3, [pc, #380] ; (8018684 <dhcp_create_msg+0x194>)
8018508: f240 7269 movw r2, #1897 ; 0x769
801850c: 495e ldr r1, [pc, #376] ; (8018688 <dhcp_create_msg+0x198>)
801850e: 485f ldr r0, [pc, #380] ; (801868c <dhcp_create_msg+0x19c>)
8018510: f002 fd58 bl 801afc4 <iprintf>
8018514: 2300 movs r3, #0
8018516: e0b1 b.n 801867c <dhcp_create_msg+0x18c>
LWIP_ERROR("dhcp_create_msg: dhcp != NULL", (dhcp != NULL), return NULL;);
8018518: 68bb ldr r3, [r7, #8]
801851a: 2b00 cmp r3, #0
801851c: d108 bne.n 8018530 <dhcp_create_msg+0x40>
801851e: 4b59 ldr r3, [pc, #356] ; (8018684 <dhcp_create_msg+0x194>)
8018520: f240 726a movw r2, #1898 ; 0x76a
8018524: 495a ldr r1, [pc, #360] ; (8018690 <dhcp_create_msg+0x1a0>)
8018526: 4859 ldr r0, [pc, #356] ; (801868c <dhcp_create_msg+0x19c>)
8018528: f002 fd4c bl 801afc4 <iprintf>
801852c: 2300 movs r3, #0
801852e: e0a5 b.n 801867c <dhcp_create_msg+0x18c>
p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
8018530: f44f 7220 mov.w r2, #640 ; 0x280
8018534: f44f 719a mov.w r1, #308 ; 0x134
8018538: 2036 movs r0, #54 ; 0x36
801853a: f7f7 fd53 bl 800ffe4 <pbuf_alloc>
801853e: 61b8 str r0, [r7, #24]
if (p_out == NULL) {
8018540: 69bb ldr r3, [r7, #24]
8018542: 2b00 cmp r3, #0
8018544: d101 bne.n 801854a <dhcp_create_msg+0x5a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("dhcp_create_msg(): could not allocate pbuf\n"));
return NULL;
8018546: 2300 movs r3, #0
8018548: e098 b.n 801867c <dhcp_create_msg+0x18c>
}
LWIP_ASSERT("dhcp_create_msg: check that first pbuf can hold struct dhcp_msg",
801854a: 69bb ldr r3, [r7, #24]
801854c: 895b ldrh r3, [r3, #10]
801854e: f5b3 7f9a cmp.w r3, #308 ; 0x134
8018552: d206 bcs.n 8018562 <dhcp_create_msg+0x72>
8018554: 4b4b ldr r3, [pc, #300] ; (8018684 <dhcp_create_msg+0x194>)
8018556: f240 7271 movw r2, #1905 ; 0x771
801855a: 494e ldr r1, [pc, #312] ; (8018694 <dhcp_create_msg+0x1a4>)
801855c: 484b ldr r0, [pc, #300] ; (801868c <dhcp_create_msg+0x19c>)
801855e: f002 fd31 bl 801afc4 <iprintf>
(p_out->len >= sizeof(struct dhcp_msg)));
/* DHCP_REQUEST should reuse 'xid' from DHCPOFFER */
if ((message_type != DHCP_REQUEST) || (dhcp->state == DHCP_STATE_REBOOTING)) {
8018562: 79fb ldrb r3, [r7, #7]
8018564: 2b03 cmp r3, #3
8018566: d103 bne.n 8018570 <dhcp_create_msg+0x80>
8018568: 68bb ldr r3, [r7, #8]
801856a: 795b ldrb r3, [r3, #5]
801856c: 2b03 cmp r3, #3
801856e: d10d bne.n 801858c <dhcp_create_msg+0x9c>
/* reuse transaction identifier in retransmissions */
if (dhcp->tries == 0) {
8018570: 68bb ldr r3, [r7, #8]
8018572: 799b ldrb r3, [r3, #6]
8018574: 2b00 cmp r3, #0
8018576: d105 bne.n 8018584 <dhcp_create_msg+0x94>
#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND)
xid = LWIP_RAND();
8018578: f002 fd3c bl 801aff4 <rand>
801857c: 4603 mov r3, r0
801857e: 461a mov r2, r3
8018580: 4b45 ldr r3, [pc, #276] ; (8018698 <dhcp_create_msg+0x1a8>)
8018582: 601a str r2, [r3, #0]
#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
xid++;
#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
}
dhcp->xid = xid;
8018584: 4b44 ldr r3, [pc, #272] ; (8018698 <dhcp_create_msg+0x1a8>)
8018586: 681a ldr r2, [r3, #0]
8018588: 68bb ldr r3, [r7, #8]
801858a: 601a str r2, [r3, #0]
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE,
("transaction id xid(%"X32_F")\n", xid));
msg_out = (struct dhcp_msg *)p_out->payload;
801858c: 69bb ldr r3, [r7, #24]
801858e: 685b ldr r3, [r3, #4]
8018590: 617b str r3, [r7, #20]
memset(msg_out, 0, sizeof(struct dhcp_msg));
8018592: f44f 729a mov.w r2, #308 ; 0x134
8018596: 2100 movs r1, #0
8018598: 6978 ldr r0, [r7, #20]
801859a: f002 fd0b bl 801afb4 <memset>
msg_out->op = DHCP_BOOTREQUEST;
801859e: 697b ldr r3, [r7, #20]
80185a0: 2201 movs r2, #1
80185a2: 701a strb r2, [r3, #0]
/* @todo: make link layer independent */
msg_out->htype = LWIP_IANA_HWTYPE_ETHERNET;
80185a4: 697b ldr r3, [r7, #20]
80185a6: 2201 movs r2, #1
80185a8: 705a strb r2, [r3, #1]
msg_out->hlen = netif->hwaddr_len;
80185aa: 68fb ldr r3, [r7, #12]
80185ac: f893 2030 ldrb.w r2, [r3, #48] ; 0x30
80185b0: 697b ldr r3, [r7, #20]
80185b2: 709a strb r2, [r3, #2]
msg_out->xid = lwip_htonl(dhcp->xid);
80185b4: 68bb ldr r3, [r7, #8]
80185b6: 681b ldr r3, [r3, #0]
80185b8: 4618 mov r0, r3
80185ba: f7f6 fc54 bl 800ee66 <lwip_htonl>
80185be: 4602 mov r2, r0
80185c0: 697b ldr r3, [r7, #20]
80185c2: 605a str r2, [r3, #4]
/* we don't need the broadcast flag since we can receive unicast traffic
before being fully configured! */
/* set ciaddr to netif->ip_addr based on message_type and state */
if ((message_type == DHCP_INFORM) || (message_type == DHCP_DECLINE) || (message_type == DHCP_RELEASE) ||
80185c4: 79fb ldrb r3, [r7, #7]
80185c6: 2b08 cmp r3, #8
80185c8: d010 beq.n 80185ec <dhcp_create_msg+0xfc>
80185ca: 79fb ldrb r3, [r7, #7]
80185cc: 2b04 cmp r3, #4
80185ce: d00d beq.n 80185ec <dhcp_create_msg+0xfc>
80185d0: 79fb ldrb r3, [r7, #7]
80185d2: 2b07 cmp r3, #7
80185d4: d00a beq.n 80185ec <dhcp_create_msg+0xfc>
80185d6: 79fb ldrb r3, [r7, #7]
80185d8: 2b03 cmp r3, #3
80185da: d10c bne.n 80185f6 <dhcp_create_msg+0x106>
((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */
((dhcp->state == DHCP_STATE_RENEWING) || dhcp->state == DHCP_STATE_REBINDING))) {
80185dc: 68bb ldr r3, [r7, #8]
80185de: 795b ldrb r3, [r3, #5]
((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */
80185e0: 2b05 cmp r3, #5
80185e2: d003 beq.n 80185ec <dhcp_create_msg+0xfc>
((dhcp->state == DHCP_STATE_RENEWING) || dhcp->state == DHCP_STATE_REBINDING))) {
80185e4: 68bb ldr r3, [r7, #8]
80185e6: 795b ldrb r3, [r3, #5]
80185e8: 2b04 cmp r3, #4
80185ea: d104 bne.n 80185f6 <dhcp_create_msg+0x106>
ip4_addr_copy(msg_out->ciaddr, *netif_ip4_addr(netif));
80185ec: 68fb ldr r3, [r7, #12]
80185ee: 3304 adds r3, #4
80185f0: 681a ldr r2, [r3, #0]
80185f2: 697b ldr r3, [r7, #20]
80185f4: 60da str r2, [r3, #12]
}
for (i = 0; i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
80185f6: 2300 movs r3, #0
80185f8: 83fb strh r3, [r7, #30]
80185fa: e00c b.n 8018616 <dhcp_create_msg+0x126>
/* copy netif hardware address (padded with zeroes through memset already) */
msg_out->chaddr[i] = netif->hwaddr[i];
80185fc: 8bfa ldrh r2, [r7, #30]
80185fe: 8bfb ldrh r3, [r7, #30]
8018600: 68f9 ldr r1, [r7, #12]
8018602: 440a add r2, r1
8018604: f892 102a ldrb.w r1, [r2, #42] ; 0x2a
8018608: 697a ldr r2, [r7, #20]
801860a: 4413 add r3, r2
801860c: 460a mov r2, r1
801860e: 771a strb r2, [r3, #28]
for (i = 0; i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
8018610: 8bfb ldrh r3, [r7, #30]
8018612: 3301 adds r3, #1
8018614: 83fb strh r3, [r7, #30]
8018616: 8bfb ldrh r3, [r7, #30]
8018618: 2b05 cmp r3, #5
801861a: d9ef bls.n 80185fc <dhcp_create_msg+0x10c>
}
msg_out->cookie = PP_HTONL(DHCP_MAGIC_COOKIE);
801861c: 697b ldr r3, [r7, #20]
801861e: 2200 movs r2, #0
8018620: f042 0263 orr.w r2, r2, #99 ; 0x63
8018624: f883 20ec strb.w r2, [r3, #236] ; 0xec
8018628: 2200 movs r2, #0
801862a: f062 027d orn r2, r2, #125 ; 0x7d
801862e: f883 20ed strb.w r2, [r3, #237] ; 0xed
8018632: 2200 movs r2, #0
8018634: f042 0253 orr.w r2, r2, #83 ; 0x53
8018638: f883 20ee strb.w r2, [r3, #238] ; 0xee
801863c: 2200 movs r2, #0
801863e: f042 0263 orr.w r2, r2, #99 ; 0x63
8018642: f883 20ef strb.w r2, [r3, #239] ; 0xef
/* Add option MESSAGE_TYPE */
options_out_len_loc = dhcp_option(0, msg_out->options, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
8018646: 697b ldr r3, [r7, #20]
8018648: f103 01f0 add.w r1, r3, #240 ; 0xf0
801864c: 2301 movs r3, #1
801864e: 2235 movs r2, #53 ; 0x35
8018650: 2000 movs r0, #0
8018652: f7ff fadb bl 8017c0c <dhcp_option>
8018656: 4603 mov r3, r0
8018658: 827b strh r3, [r7, #18]
options_out_len_loc = dhcp_option_byte(options_out_len_loc, msg_out->options, message_type);
801865a: 697b ldr r3, [r7, #20]
801865c: f103 01f0 add.w r1, r3, #240 ; 0xf0
8018660: 79fa ldrb r2, [r7, #7]
8018662: 8a7b ldrh r3, [r7, #18]
8018664: 4618 mov r0, r3
8018666: f7ff fb05 bl 8017c74 <dhcp_option_byte>
801866a: 4603 mov r3, r0
801866c: 827b strh r3, [r7, #18]
if (options_out_len) {
801866e: 683b ldr r3, [r7, #0]
8018670: 2b00 cmp r3, #0
8018672: d002 beq.n 801867a <dhcp_create_msg+0x18a>
*options_out_len = options_out_len_loc;
8018674: 683b ldr r3, [r7, #0]
8018676: 8a7a ldrh r2, [r7, #18]
8018678: 801a strh r2, [r3, #0]
}
return p_out;
801867a: 69bb ldr r3, [r7, #24]
}
801867c: 4618 mov r0, r3
801867e: 3720 adds r7, #32
8018680: 46bd mov sp, r7
8018682: bd80 pop {r7, pc}
8018684: 0801e56c .word 0x0801e56c
8018688: 0801e88c .word 0x0801e88c
801868c: 0801e5cc .word 0x0801e5cc
8018690: 0801e8ac .word 0x0801e8ac
8018694: 0801e8cc .word 0x0801e8cc
8018698: 20008768 .word 0x20008768
0801869c <dhcp_option_trailer>:
* Adds the END option to the DHCP message, and if
* necessary, up to three padding bytes.
*/
static void
dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out)
{
801869c: b580 push {r7, lr}
801869e: b084 sub sp, #16
80186a0: af00 add r7, sp, #0
80186a2: 4603 mov r3, r0
80186a4: 60b9 str r1, [r7, #8]
80186a6: 607a str r2, [r7, #4]
80186a8: 81fb strh r3, [r7, #14]
options[options_out_len++] = DHCP_OPTION_END;
80186aa: 89fb ldrh r3, [r7, #14]
80186ac: 1c5a adds r2, r3, #1
80186ae: 81fa strh r2, [r7, #14]
80186b0: 461a mov r2, r3
80186b2: 68bb ldr r3, [r7, #8]
80186b4: 4413 add r3, r2
80186b6: 22ff movs r2, #255 ; 0xff
80186b8: 701a strb r2, [r3, #0]
/* packet is too small, or not 4 byte aligned? */
while (((options_out_len < DHCP_MIN_OPTIONS_LEN) || (options_out_len & 3)) &&
80186ba: e007 b.n 80186cc <dhcp_option_trailer+0x30>
(options_out_len < DHCP_OPTIONS_LEN)) {
/* add a fill/padding byte */
options[options_out_len++] = 0;
80186bc: 89fb ldrh r3, [r7, #14]
80186be: 1c5a adds r2, r3, #1
80186c0: 81fa strh r2, [r7, #14]
80186c2: 461a mov r2, r3
80186c4: 68bb ldr r3, [r7, #8]
80186c6: 4413 add r3, r2
80186c8: 2200 movs r2, #0
80186ca: 701a strb r2, [r3, #0]
while (((options_out_len < DHCP_MIN_OPTIONS_LEN) || (options_out_len & 3)) &&
80186cc: 89fb ldrh r3, [r7, #14]
80186ce: 2b43 cmp r3, #67 ; 0x43
80186d0: d904 bls.n 80186dc <dhcp_option_trailer+0x40>
80186d2: 89fb ldrh r3, [r7, #14]
80186d4: f003 0303 and.w r3, r3, #3
80186d8: 2b00 cmp r3, #0
80186da: d002 beq.n 80186e2 <dhcp_option_trailer+0x46>
80186dc: 89fb ldrh r3, [r7, #14]
80186de: 2b43 cmp r3, #67 ; 0x43
80186e0: d9ec bls.n 80186bc <dhcp_option_trailer+0x20>
}
/* shrink the pbuf to the actual content length */
pbuf_realloc(p_out, (u16_t)(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + options_out_len));
80186e2: 89fb ldrh r3, [r7, #14]
80186e4: 33f0 adds r3, #240 ; 0xf0
80186e6: b29b uxth r3, r3
80186e8: 4619 mov r1, r3
80186ea: 6878 ldr r0, [r7, #4]
80186ec: f7f7 fdd8 bl 80102a0 <pbuf_realloc>
}
80186f0: bf00 nop
80186f2: 3710 adds r7, #16
80186f4: 46bd mov sp, r7
80186f6: bd80 pop {r7, pc}
080186f8 <dhcp_supplied_address>:
* @return 1 if DHCP supplied netif->ip_addr (states BOUND or RENEWING),
* 0 otherwise
*/
u8_t
dhcp_supplied_address(const struct netif *netif)
{
80186f8: b480 push {r7}
80186fa: b085 sub sp, #20
80186fc: af00 add r7, sp, #0
80186fe: 6078 str r0, [r7, #4]
if ((netif != NULL) && (netif_dhcp_data(netif) != NULL)) {
8018700: 687b ldr r3, [r7, #4]
8018702: 2b00 cmp r3, #0
8018704: d017 beq.n 8018736 <dhcp_supplied_address+0x3e>
8018706: 687b ldr r3, [r7, #4]
8018708: 6a5b ldr r3, [r3, #36] ; 0x24
801870a: 2b00 cmp r3, #0
801870c: d013 beq.n 8018736 <dhcp_supplied_address+0x3e>
struct dhcp *dhcp = netif_dhcp_data(netif);
801870e: 687b ldr r3, [r7, #4]
8018710: 6a5b ldr r3, [r3, #36] ; 0x24
8018712: 60fb str r3, [r7, #12]
return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING) ||
8018714: 68fb ldr r3, [r7, #12]
8018716: 795b ldrb r3, [r3, #5]
8018718: 2b0a cmp r3, #10
801871a: d007 beq.n 801872c <dhcp_supplied_address+0x34>
801871c: 68fb ldr r3, [r7, #12]
801871e: 795b ldrb r3, [r3, #5]
8018720: 2b05 cmp r3, #5
8018722: d003 beq.n 801872c <dhcp_supplied_address+0x34>
(dhcp->state == DHCP_STATE_REBINDING);
8018724: 68fb ldr r3, [r7, #12]
8018726: 795b ldrb r3, [r3, #5]
return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING) ||
8018728: 2b04 cmp r3, #4
801872a: d101 bne.n 8018730 <dhcp_supplied_address+0x38>
801872c: 2301 movs r3, #1
801872e: e000 b.n 8018732 <dhcp_supplied_address+0x3a>
8018730: 2300 movs r3, #0
8018732: b2db uxtb r3, r3
8018734: e000 b.n 8018738 <dhcp_supplied_address+0x40>
}
return 0;
8018736: 2300 movs r3, #0
}
8018738: 4618 mov r0, r3
801873a: 3714 adds r7, #20
801873c: 46bd mov sp, r7
801873e: f85d 7b04 ldr.w r7, [sp], #4
8018742: 4770 bx lr
08018744 <etharp_free_entry>:
#endif /* ARP_QUEUEING */
/** Clean up ARP table entries */
static void
etharp_free_entry(int i)
{
8018744: b580 push {r7, lr}
8018746: b082 sub sp, #8
8018748: af00 add r7, sp, #0
801874a: 6078 str r0, [r7, #4]
/* remove from SNMP ARP index tree */
mib2_remove_arp_entry(arp_table[i].netif, &arp_table[i].ipaddr);
/* and empty packet queue */
if (arp_table[i].q != NULL) {
801874c: 4915 ldr r1, [pc, #84] ; (80187a4 <etharp_free_entry+0x60>)
801874e: 687a ldr r2, [r7, #4]
8018750: 4613 mov r3, r2
8018752: 005b lsls r3, r3, #1
8018754: 4413 add r3, r2
8018756: 00db lsls r3, r3, #3
8018758: 440b add r3, r1
801875a: 681b ldr r3, [r3, #0]
801875c: 2b00 cmp r3, #0
801875e: d013 beq.n 8018788 <etharp_free_entry+0x44>
/* remove all queued packets */
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_free_entry: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q)));
free_etharp_q(arp_table[i].q);
8018760: 4910 ldr r1, [pc, #64] ; (80187a4 <etharp_free_entry+0x60>)
8018762: 687a ldr r2, [r7, #4]
8018764: 4613 mov r3, r2
8018766: 005b lsls r3, r3, #1
8018768: 4413 add r3, r2
801876a: 00db lsls r3, r3, #3
801876c: 440b add r3, r1
801876e: 681b ldr r3, [r3, #0]
8018770: 4618 mov r0, r3
8018772: f7f7 ff1b bl 80105ac <pbuf_free>
arp_table[i].q = NULL;
8018776: 490b ldr r1, [pc, #44] ; (80187a4 <etharp_free_entry+0x60>)
8018778: 687a ldr r2, [r7, #4]
801877a: 4613 mov r3, r2
801877c: 005b lsls r3, r3, #1
801877e: 4413 add r3, r2
8018780: 00db lsls r3, r3, #3
8018782: 440b add r3, r1
8018784: 2200 movs r2, #0
8018786: 601a str r2, [r3, #0]
}
/* recycle entry for re-use */
arp_table[i].state = ETHARP_STATE_EMPTY;
8018788: 4906 ldr r1, [pc, #24] ; (80187a4 <etharp_free_entry+0x60>)
801878a: 687a ldr r2, [r7, #4]
801878c: 4613 mov r3, r2
801878e: 005b lsls r3, r3, #1
8018790: 4413 add r3, r2
8018792: 00db lsls r3, r3, #3
8018794: 440b add r3, r1
8018796: 3314 adds r3, #20
8018798: 2200 movs r2, #0
801879a: 701a strb r2, [r3, #0]
arp_table[i].ctime = 0;
arp_table[i].netif = NULL;
ip4_addr_set_zero(&arp_table[i].ipaddr);
arp_table[i].ethaddr = ethzero;
#endif /* LWIP_DEBUG */
}
801879c: bf00 nop
801879e: 3708 adds r7, #8
80187a0: 46bd mov sp, r7
80187a2: bd80 pop {r7, pc}
80187a4: 2000876c .word 0x2000876c
080187a8 <etharp_tmr>:
* This function should be called every ARP_TMR_INTERVAL milliseconds (1 second),
* in order to expire entries in the ARP table.
*/
void
etharp_tmr(void)
{
80187a8: b580 push {r7, lr}
80187aa: b082 sub sp, #8
80187ac: af00 add r7, sp, #0
int i;
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
/* remove expired entries from the ARP table */
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
80187ae: 2300 movs r3, #0
80187b0: 607b str r3, [r7, #4]
80187b2: e096 b.n 80188e2 <etharp_tmr+0x13a>
u8_t state = arp_table[i].state;
80187b4: 494f ldr r1, [pc, #316] ; (80188f4 <etharp_tmr+0x14c>)
80187b6: 687a ldr r2, [r7, #4]
80187b8: 4613 mov r3, r2
80187ba: 005b lsls r3, r3, #1
80187bc: 4413 add r3, r2
80187be: 00db lsls r3, r3, #3
80187c0: 440b add r3, r1
80187c2: 3314 adds r3, #20
80187c4: 781b ldrb r3, [r3, #0]
80187c6: 70fb strb r3, [r7, #3]
if (state != ETHARP_STATE_EMPTY
80187c8: 78fb ldrb r3, [r7, #3]
80187ca: 2b00 cmp r3, #0
80187cc: f000 8086 beq.w 80188dc <etharp_tmr+0x134>
#if ETHARP_SUPPORT_STATIC_ENTRIES
&& (state != ETHARP_STATE_STATIC)
#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
) {
arp_table[i].ctime++;
80187d0: 4948 ldr r1, [pc, #288] ; (80188f4 <etharp_tmr+0x14c>)
80187d2: 687a ldr r2, [r7, #4]
80187d4: 4613 mov r3, r2
80187d6: 005b lsls r3, r3, #1
80187d8: 4413 add r3, r2
80187da: 00db lsls r3, r3, #3
80187dc: 440b add r3, r1
80187de: 3312 adds r3, #18
80187e0: 881b ldrh r3, [r3, #0]
80187e2: 3301 adds r3, #1
80187e4: b298 uxth r0, r3
80187e6: 4943 ldr r1, [pc, #268] ; (80188f4 <etharp_tmr+0x14c>)
80187e8: 687a ldr r2, [r7, #4]
80187ea: 4613 mov r3, r2
80187ec: 005b lsls r3, r3, #1
80187ee: 4413 add r3, r2
80187f0: 00db lsls r3, r3, #3
80187f2: 440b add r3, r1
80187f4: 3312 adds r3, #18
80187f6: 4602 mov r2, r0
80187f8: 801a strh r2, [r3, #0]
if ((arp_table[i].ctime >= ARP_MAXAGE) ||
80187fa: 493e ldr r1, [pc, #248] ; (80188f4 <etharp_tmr+0x14c>)
80187fc: 687a ldr r2, [r7, #4]
80187fe: 4613 mov r3, r2
8018800: 005b lsls r3, r3, #1
8018802: 4413 add r3, r2
8018804: 00db lsls r3, r3, #3
8018806: 440b add r3, r1
8018808: 3312 adds r3, #18
801880a: 881b ldrh r3, [r3, #0]
801880c: f5b3 7f96 cmp.w r3, #300 ; 0x12c
8018810: d215 bcs.n 801883e <etharp_tmr+0x96>
((arp_table[i].state == ETHARP_STATE_PENDING) &&
8018812: 4938 ldr r1, [pc, #224] ; (80188f4 <etharp_tmr+0x14c>)
8018814: 687a ldr r2, [r7, #4]
8018816: 4613 mov r3, r2
8018818: 005b lsls r3, r3, #1
801881a: 4413 add r3, r2
801881c: 00db lsls r3, r3, #3
801881e: 440b add r3, r1
8018820: 3314 adds r3, #20
8018822: 781b ldrb r3, [r3, #0]
if ((arp_table[i].ctime >= ARP_MAXAGE) ||
8018824: 2b01 cmp r3, #1
8018826: d10e bne.n 8018846 <etharp_tmr+0x9e>
(arp_table[i].ctime >= ARP_MAXPENDING))) {
8018828: 4932 ldr r1, [pc, #200] ; (80188f4 <etharp_tmr+0x14c>)
801882a: 687a ldr r2, [r7, #4]
801882c: 4613 mov r3, r2
801882e: 005b lsls r3, r3, #1
8018830: 4413 add r3, r2
8018832: 00db lsls r3, r3, #3
8018834: 440b add r3, r1
8018836: 3312 adds r3, #18
8018838: 881b ldrh r3, [r3, #0]
((arp_table[i].state == ETHARP_STATE_PENDING) &&
801883a: 2b04 cmp r3, #4
801883c: d903 bls.n 8018846 <etharp_tmr+0x9e>
/* pending or stable entry has become old! */
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %d.\n",
arp_table[i].state >= ETHARP_STATE_STABLE ? "stable" : "pending", i));
/* clean up entries that have just been expired */
etharp_free_entry(i);
801883e: 6878 ldr r0, [r7, #4]
8018840: f7ff ff80 bl 8018744 <etharp_free_entry>
8018844: e04a b.n 80188dc <etharp_tmr+0x134>
} else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_1) {
8018846: 492b ldr r1, [pc, #172] ; (80188f4 <etharp_tmr+0x14c>)
8018848: 687a ldr r2, [r7, #4]
801884a: 4613 mov r3, r2
801884c: 005b lsls r3, r3, #1
801884e: 4413 add r3, r2
8018850: 00db lsls r3, r3, #3
8018852: 440b add r3, r1
8018854: 3314 adds r3, #20
8018856: 781b ldrb r3, [r3, #0]
8018858: 2b03 cmp r3, #3
801885a: d10a bne.n 8018872 <etharp_tmr+0xca>
/* Don't send more than one request every 2 seconds. */
arp_table[i].state = ETHARP_STATE_STABLE_REREQUESTING_2;
801885c: 4925 ldr r1, [pc, #148] ; (80188f4 <etharp_tmr+0x14c>)
801885e: 687a ldr r2, [r7, #4]
8018860: 4613 mov r3, r2
8018862: 005b lsls r3, r3, #1
8018864: 4413 add r3, r2
8018866: 00db lsls r3, r3, #3
8018868: 440b add r3, r1
801886a: 3314 adds r3, #20
801886c: 2204 movs r2, #4
801886e: 701a strb r2, [r3, #0]
8018870: e034 b.n 80188dc <etharp_tmr+0x134>
} else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_2) {
8018872: 4920 ldr r1, [pc, #128] ; (80188f4 <etharp_tmr+0x14c>)
8018874: 687a ldr r2, [r7, #4]
8018876: 4613 mov r3, r2
8018878: 005b lsls r3, r3, #1
801887a: 4413 add r3, r2
801887c: 00db lsls r3, r3, #3
801887e: 440b add r3, r1
8018880: 3314 adds r3, #20
8018882: 781b ldrb r3, [r3, #0]
8018884: 2b04 cmp r3, #4
8018886: d10a bne.n 801889e <etharp_tmr+0xf6>
/* Reset state to stable, so that the next transmitted packet will
re-send an ARP request. */
arp_table[i].state = ETHARP_STATE_STABLE;
8018888: 491a ldr r1, [pc, #104] ; (80188f4 <etharp_tmr+0x14c>)
801888a: 687a ldr r2, [r7, #4]
801888c: 4613 mov r3, r2
801888e: 005b lsls r3, r3, #1
8018890: 4413 add r3, r2
8018892: 00db lsls r3, r3, #3
8018894: 440b add r3, r1
8018896: 3314 adds r3, #20
8018898: 2202 movs r2, #2
801889a: 701a strb r2, [r3, #0]
801889c: e01e b.n 80188dc <etharp_tmr+0x134>
} else if (arp_table[i].state == ETHARP_STATE_PENDING) {
801889e: 4915 ldr r1, [pc, #84] ; (80188f4 <etharp_tmr+0x14c>)
80188a0: 687a ldr r2, [r7, #4]
80188a2: 4613 mov r3, r2
80188a4: 005b lsls r3, r3, #1
80188a6: 4413 add r3, r2
80188a8: 00db lsls r3, r3, #3
80188aa: 440b add r3, r1
80188ac: 3314 adds r3, #20
80188ae: 781b ldrb r3, [r3, #0]
80188b0: 2b01 cmp r3, #1
80188b2: d113 bne.n 80188dc <etharp_tmr+0x134>
/* still pending, resend an ARP query */
etharp_request(arp_table[i].netif, &arp_table[i].ipaddr);
80188b4: 490f ldr r1, [pc, #60] ; (80188f4 <etharp_tmr+0x14c>)
80188b6: 687a ldr r2, [r7, #4]
80188b8: 4613 mov r3, r2
80188ba: 005b lsls r3, r3, #1
80188bc: 4413 add r3, r2
80188be: 00db lsls r3, r3, #3
80188c0: 440b add r3, r1
80188c2: 3308 adds r3, #8
80188c4: 6818 ldr r0, [r3, #0]
80188c6: 687a ldr r2, [r7, #4]
80188c8: 4613 mov r3, r2
80188ca: 005b lsls r3, r3, #1
80188cc: 4413 add r3, r2
80188ce: 00db lsls r3, r3, #3
80188d0: 4a08 ldr r2, [pc, #32] ; (80188f4 <etharp_tmr+0x14c>)
80188d2: 4413 add r3, r2
80188d4: 3304 adds r3, #4
80188d6: 4619 mov r1, r3
80188d8: f000 fe72 bl 80195c0 <etharp_request>
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
80188dc: 687b ldr r3, [r7, #4]
80188de: 3301 adds r3, #1
80188e0: 607b str r3, [r7, #4]
80188e2: 687b ldr r3, [r7, #4]
80188e4: 2b09 cmp r3, #9
80188e6: f77f af65 ble.w 80187b4 <etharp_tmr+0xc>
}
}
}
}
80188ea: bf00 nop
80188ec: bf00 nop
80188ee: 3708 adds r7, #8
80188f0: 46bd mov sp, r7
80188f2: bd80 pop {r7, pc}
80188f4: 2000876c .word 0x2000876c
080188f8 <etharp_find_entry>:
* @return The ARP entry index that matched or is created, ERR_MEM if no
* entry is found or could be recycled.
*/
static s16_t
etharp_find_entry(const ip4_addr_t *ipaddr, u8_t flags, struct netif *netif)
{
80188f8: b580 push {r7, lr}
80188fa: b08a sub sp, #40 ; 0x28
80188fc: af00 add r7, sp, #0
80188fe: 60f8 str r0, [r7, #12]
8018900: 460b mov r3, r1
8018902: 607a str r2, [r7, #4]
8018904: 72fb strb r3, [r7, #11]
s16_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
8018906: 230a movs r3, #10
8018908: 84fb strh r3, [r7, #38] ; 0x26
801890a: 230a movs r3, #10
801890c: 84bb strh r3, [r7, #36] ; 0x24
s16_t empty = ARP_TABLE_SIZE;
801890e: 230a movs r3, #10
8018910: 847b strh r3, [r7, #34] ; 0x22
s16_t i = 0;
8018912: 2300 movs r3, #0
8018914: 843b strh r3, [r7, #32]
/* oldest entry with packets on queue */
s16_t old_queue = ARP_TABLE_SIZE;
8018916: 230a movs r3, #10
8018918: 83fb strh r3, [r7, #30]
/* its age */
u16_t age_queue = 0, age_pending = 0, age_stable = 0;
801891a: 2300 movs r3, #0
801891c: 83bb strh r3, [r7, #28]
801891e: 2300 movs r3, #0
8018920: 837b strh r3, [r7, #26]
8018922: 2300 movs r3, #0
8018924: 833b strh r3, [r7, #24]
* 4) remember the oldest pending entry with queued packets (if any)
* 5) search for a matching IP entry, either pending or stable
* until 5 matches, or all entries are searched for.
*/
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
8018926: 2300 movs r3, #0
8018928: 843b strh r3, [r7, #32]
801892a: e0ae b.n 8018a8a <etharp_find_entry+0x192>
u8_t state = arp_table[i].state;
801892c: f9b7 2020 ldrsh.w r2, [r7, #32]
8018930: 49a6 ldr r1, [pc, #664] ; (8018bcc <etharp_find_entry+0x2d4>)
8018932: 4613 mov r3, r2
8018934: 005b lsls r3, r3, #1
8018936: 4413 add r3, r2
8018938: 00db lsls r3, r3, #3
801893a: 440b add r3, r1
801893c: 3314 adds r3, #20
801893e: 781b ldrb r3, [r3, #0]
8018940: 75fb strb r3, [r7, #23]
/* no empty entry found yet and now we do find one? */
if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) {
8018942: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22
8018946: 2b0a cmp r3, #10
8018948: d105 bne.n 8018956 <etharp_find_entry+0x5e>
801894a: 7dfb ldrb r3, [r7, #23]
801894c: 2b00 cmp r3, #0
801894e: d102 bne.n 8018956 <etharp_find_entry+0x5e>
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_find_entry: found empty entry %d\n", (int)i));
/* remember first empty entry */
empty = i;
8018950: 8c3b ldrh r3, [r7, #32]
8018952: 847b strh r3, [r7, #34] ; 0x22
8018954: e095 b.n 8018a82 <etharp_find_entry+0x18a>
} else if (state != ETHARP_STATE_EMPTY) {
8018956: 7dfb ldrb r3, [r7, #23]
8018958: 2b00 cmp r3, #0
801895a: f000 8092 beq.w 8018a82 <etharp_find_entry+0x18a>
LWIP_ASSERT("state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE",
801895e: 7dfb ldrb r3, [r7, #23]
8018960: 2b01 cmp r3, #1
8018962: d009 beq.n 8018978 <etharp_find_entry+0x80>
8018964: 7dfb ldrb r3, [r7, #23]
8018966: 2b01 cmp r3, #1
8018968: d806 bhi.n 8018978 <etharp_find_entry+0x80>
801896a: 4b99 ldr r3, [pc, #612] ; (8018bd0 <etharp_find_entry+0x2d8>)
801896c: f240 1223 movw r2, #291 ; 0x123
8018970: 4998 ldr r1, [pc, #608] ; (8018bd4 <etharp_find_entry+0x2dc>)
8018972: 4899 ldr r0, [pc, #612] ; (8018bd8 <etharp_find_entry+0x2e0>)
8018974: f002 fb26 bl 801afc4 <iprintf>
state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE);
/* if given, does IP address match IP address in ARP entry? */
if (ipaddr && ip4_addr_cmp(ipaddr, &arp_table[i].ipaddr)
8018978: 68fb ldr r3, [r7, #12]
801897a: 2b00 cmp r3, #0
801897c: d020 beq.n 80189c0 <etharp_find_entry+0xc8>
801897e: 68fb ldr r3, [r7, #12]
8018980: 6819 ldr r1, [r3, #0]
8018982: f9b7 2020 ldrsh.w r2, [r7, #32]
8018986: 4891 ldr r0, [pc, #580] ; (8018bcc <etharp_find_entry+0x2d4>)
8018988: 4613 mov r3, r2
801898a: 005b lsls r3, r3, #1
801898c: 4413 add r3, r2
801898e: 00db lsls r3, r3, #3
8018990: 4403 add r3, r0
8018992: 3304 adds r3, #4
8018994: 681b ldr r3, [r3, #0]
8018996: 4299 cmp r1, r3
8018998: d112 bne.n 80189c0 <etharp_find_entry+0xc8>
#if ETHARP_TABLE_MATCH_NETIF
&& ((netif == NULL) || (netif == arp_table[i].netif))
801899a: 687b ldr r3, [r7, #4]
801899c: 2b00 cmp r3, #0
801899e: d00c beq.n 80189ba <etharp_find_entry+0xc2>
80189a0: f9b7 2020 ldrsh.w r2, [r7, #32]
80189a4: 4989 ldr r1, [pc, #548] ; (8018bcc <etharp_find_entry+0x2d4>)
80189a6: 4613 mov r3, r2
80189a8: 005b lsls r3, r3, #1
80189aa: 4413 add r3, r2
80189ac: 00db lsls r3, r3, #3
80189ae: 440b add r3, r1
80189b0: 3308 adds r3, #8
80189b2: 681b ldr r3, [r3, #0]
80189b4: 687a ldr r2, [r7, #4]
80189b6: 429a cmp r2, r3
80189b8: d102 bne.n 80189c0 <etharp_find_entry+0xc8>
#endif /* ETHARP_TABLE_MATCH_NETIF */
) {
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: found matching entry %d\n", (int)i));
/* found exact IP address match, simply bail out */
return i;
80189ba: f9b7 3020 ldrsh.w r3, [r7, #32]
80189be: e100 b.n 8018bc2 <etharp_find_entry+0x2ca>
}
/* pending entry? */
if (state == ETHARP_STATE_PENDING) {
80189c0: 7dfb ldrb r3, [r7, #23]
80189c2: 2b01 cmp r3, #1
80189c4: d140 bne.n 8018a48 <etharp_find_entry+0x150>
/* pending with queued packets? */
if (arp_table[i].q != NULL) {
80189c6: f9b7 2020 ldrsh.w r2, [r7, #32]
80189ca: 4980 ldr r1, [pc, #512] ; (8018bcc <etharp_find_entry+0x2d4>)
80189cc: 4613 mov r3, r2
80189ce: 005b lsls r3, r3, #1
80189d0: 4413 add r3, r2
80189d2: 00db lsls r3, r3, #3
80189d4: 440b add r3, r1
80189d6: 681b ldr r3, [r3, #0]
80189d8: 2b00 cmp r3, #0
80189da: d01a beq.n 8018a12 <etharp_find_entry+0x11a>
if (arp_table[i].ctime >= age_queue) {
80189dc: f9b7 2020 ldrsh.w r2, [r7, #32]
80189e0: 497a ldr r1, [pc, #488] ; (8018bcc <etharp_find_entry+0x2d4>)
80189e2: 4613 mov r3, r2
80189e4: 005b lsls r3, r3, #1
80189e6: 4413 add r3, r2
80189e8: 00db lsls r3, r3, #3
80189ea: 440b add r3, r1
80189ec: 3312 adds r3, #18
80189ee: 881b ldrh r3, [r3, #0]
80189f0: 8bba ldrh r2, [r7, #28]
80189f2: 429a cmp r2, r3
80189f4: d845 bhi.n 8018a82 <etharp_find_entry+0x18a>
old_queue = i;
80189f6: 8c3b ldrh r3, [r7, #32]
80189f8: 83fb strh r3, [r7, #30]
age_queue = arp_table[i].ctime;
80189fa: f9b7 2020 ldrsh.w r2, [r7, #32]
80189fe: 4973 ldr r1, [pc, #460] ; (8018bcc <etharp_find_entry+0x2d4>)
8018a00: 4613 mov r3, r2
8018a02: 005b lsls r3, r3, #1
8018a04: 4413 add r3, r2
8018a06: 00db lsls r3, r3, #3
8018a08: 440b add r3, r1
8018a0a: 3312 adds r3, #18
8018a0c: 881b ldrh r3, [r3, #0]
8018a0e: 83bb strh r3, [r7, #28]
8018a10: e037 b.n 8018a82 <etharp_find_entry+0x18a>
}
} else
/* pending without queued packets? */
{
if (arp_table[i].ctime >= age_pending) {
8018a12: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a16: 496d ldr r1, [pc, #436] ; (8018bcc <etharp_find_entry+0x2d4>)
8018a18: 4613 mov r3, r2
8018a1a: 005b lsls r3, r3, #1
8018a1c: 4413 add r3, r2
8018a1e: 00db lsls r3, r3, #3
8018a20: 440b add r3, r1
8018a22: 3312 adds r3, #18
8018a24: 881b ldrh r3, [r3, #0]
8018a26: 8b7a ldrh r2, [r7, #26]
8018a28: 429a cmp r2, r3
8018a2a: d82a bhi.n 8018a82 <etharp_find_entry+0x18a>
old_pending = i;
8018a2c: 8c3b ldrh r3, [r7, #32]
8018a2e: 84fb strh r3, [r7, #38] ; 0x26
age_pending = arp_table[i].ctime;
8018a30: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a34: 4965 ldr r1, [pc, #404] ; (8018bcc <etharp_find_entry+0x2d4>)
8018a36: 4613 mov r3, r2
8018a38: 005b lsls r3, r3, #1
8018a3a: 4413 add r3, r2
8018a3c: 00db lsls r3, r3, #3
8018a3e: 440b add r3, r1
8018a40: 3312 adds r3, #18
8018a42: 881b ldrh r3, [r3, #0]
8018a44: 837b strh r3, [r7, #26]
8018a46: e01c b.n 8018a82 <etharp_find_entry+0x18a>
}
}
/* stable entry? */
} else if (state >= ETHARP_STATE_STABLE) {
8018a48: 7dfb ldrb r3, [r7, #23]
8018a4a: 2b01 cmp r3, #1
8018a4c: d919 bls.n 8018a82 <etharp_find_entry+0x18a>
/* don't record old_stable for static entries since they never expire */
if (state < ETHARP_STATE_STATIC)
#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
{
/* remember entry with oldest stable entry in oldest, its age in maxtime */
if (arp_table[i].ctime >= age_stable) {
8018a4e: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a52: 495e ldr r1, [pc, #376] ; (8018bcc <etharp_find_entry+0x2d4>)
8018a54: 4613 mov r3, r2
8018a56: 005b lsls r3, r3, #1
8018a58: 4413 add r3, r2
8018a5a: 00db lsls r3, r3, #3
8018a5c: 440b add r3, r1
8018a5e: 3312 adds r3, #18
8018a60: 881b ldrh r3, [r3, #0]
8018a62: 8b3a ldrh r2, [r7, #24]
8018a64: 429a cmp r2, r3
8018a66: d80c bhi.n 8018a82 <etharp_find_entry+0x18a>
old_stable = i;
8018a68: 8c3b ldrh r3, [r7, #32]
8018a6a: 84bb strh r3, [r7, #36] ; 0x24
age_stable = arp_table[i].ctime;
8018a6c: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a70: 4956 ldr r1, [pc, #344] ; (8018bcc <etharp_find_entry+0x2d4>)
8018a72: 4613 mov r3, r2
8018a74: 005b lsls r3, r3, #1
8018a76: 4413 add r3, r2
8018a78: 00db lsls r3, r3, #3
8018a7a: 440b add r3, r1
8018a7c: 3312 adds r3, #18
8018a7e: 881b ldrh r3, [r3, #0]
8018a80: 833b strh r3, [r7, #24]
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
8018a82: 8c3b ldrh r3, [r7, #32]
8018a84: 3301 adds r3, #1
8018a86: b29b uxth r3, r3
8018a88: 843b strh r3, [r7, #32]
8018a8a: f9b7 3020 ldrsh.w r3, [r7, #32]
8018a8e: 2b09 cmp r3, #9
8018a90: f77f af4c ble.w 801892c <etharp_find_entry+0x34>
}
}
/* { we have no match } => try to create a new entry */
/* don't create new entry, only search? */
if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) ||
8018a94: 7afb ldrb r3, [r7, #11]
8018a96: f003 0302 and.w r3, r3, #2
8018a9a: 2b00 cmp r3, #0
8018a9c: d108 bne.n 8018ab0 <etharp_find_entry+0x1b8>
8018a9e: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22
8018aa2: 2b0a cmp r3, #10
8018aa4: d107 bne.n 8018ab6 <etharp_find_entry+0x1be>
/* or no empty entry found and not allowed to recycle? */
((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) {
8018aa6: 7afb ldrb r3, [r7, #11]
8018aa8: f003 0301 and.w r3, r3, #1
8018aac: 2b00 cmp r3, #0
8018aae: d102 bne.n 8018ab6 <etharp_find_entry+0x1be>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty entry found and not allowed to recycle\n"));
return (s16_t)ERR_MEM;
8018ab0: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8018ab4: e085 b.n 8018bc2 <etharp_find_entry+0x2ca>
*
* { ETHARP_FLAG_TRY_HARD is set at this point }
*/
/* 1) empty entry available? */
if (empty < ARP_TABLE_SIZE) {
8018ab6: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22
8018aba: 2b09 cmp r3, #9
8018abc: dc02 bgt.n 8018ac4 <etharp_find_entry+0x1cc>
i = empty;
8018abe: 8c7b ldrh r3, [r7, #34] ; 0x22
8018ac0: 843b strh r3, [r7, #32]
8018ac2: e039 b.n 8018b38 <etharp_find_entry+0x240>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting empty entry %d\n", (int)i));
} else {
/* 2) found recyclable stable entry? */
if (old_stable < ARP_TABLE_SIZE) {
8018ac4: f9b7 3024 ldrsh.w r3, [r7, #36] ; 0x24
8018ac8: 2b09 cmp r3, #9
8018aca: dc14 bgt.n 8018af6 <etharp_find_entry+0x1fe>
/* recycle oldest stable*/
i = old_stable;
8018acc: 8cbb ldrh r3, [r7, #36] ; 0x24
8018ace: 843b strh r3, [r7, #32]
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest stable entry %d\n", (int)i));
/* no queued packets should exist on stable entries */
LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL);
8018ad0: f9b7 2020 ldrsh.w r2, [r7, #32]
8018ad4: 493d ldr r1, [pc, #244] ; (8018bcc <etharp_find_entry+0x2d4>)
8018ad6: 4613 mov r3, r2
8018ad8: 005b lsls r3, r3, #1
8018ada: 4413 add r3, r2
8018adc: 00db lsls r3, r3, #3
8018ade: 440b add r3, r1
8018ae0: 681b ldr r3, [r3, #0]
8018ae2: 2b00 cmp r3, #0
8018ae4: d018 beq.n 8018b18 <etharp_find_entry+0x220>
8018ae6: 4b3a ldr r3, [pc, #232] ; (8018bd0 <etharp_find_entry+0x2d8>)
8018ae8: f240 126d movw r2, #365 ; 0x16d
8018aec: 493b ldr r1, [pc, #236] ; (8018bdc <etharp_find_entry+0x2e4>)
8018aee: 483a ldr r0, [pc, #232] ; (8018bd8 <etharp_find_entry+0x2e0>)
8018af0: f002 fa68 bl 801afc4 <iprintf>
8018af4: e010 b.n 8018b18 <etharp_find_entry+0x220>
/* 3) found recyclable pending entry without queued packets? */
} else if (old_pending < ARP_TABLE_SIZE) {
8018af6: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26
8018afa: 2b09 cmp r3, #9
8018afc: dc02 bgt.n 8018b04 <etharp_find_entry+0x20c>
/* recycle oldest pending */
i = old_pending;
8018afe: 8cfb ldrh r3, [r7, #38] ; 0x26
8018b00: 843b strh r3, [r7, #32]
8018b02: e009 b.n 8018b18 <etharp_find_entry+0x220>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d (without queue)\n", (int)i));
/* 4) found recyclable pending entry with queued packets? */
} else if (old_queue < ARP_TABLE_SIZE) {
8018b04: f9b7 301e ldrsh.w r3, [r7, #30]
8018b08: 2b09 cmp r3, #9
8018b0a: dc02 bgt.n 8018b12 <etharp_find_entry+0x21a>
/* recycle oldest pending (queued packets are free in etharp_free_entry) */
i = old_queue;
8018b0c: 8bfb ldrh r3, [r7, #30]
8018b0e: 843b strh r3, [r7, #32]
8018b10: e002 b.n 8018b18 <etharp_find_entry+0x220>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", (int)i, (void *)(arp_table[i].q)));
/* no empty or recyclable entries found */
} else {
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty or recyclable entries found\n"));
return (s16_t)ERR_MEM;
8018b12: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8018b16: e054 b.n 8018bc2 <etharp_find_entry+0x2ca>
}
/* { empty or recyclable entry found } */
LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
8018b18: f9b7 3020 ldrsh.w r3, [r7, #32]
8018b1c: 2b09 cmp r3, #9
8018b1e: dd06 ble.n 8018b2e <etharp_find_entry+0x236>
8018b20: 4b2b ldr r3, [pc, #172] ; (8018bd0 <etharp_find_entry+0x2d8>)
8018b22: f240 127f movw r2, #383 ; 0x17f
8018b26: 492e ldr r1, [pc, #184] ; (8018be0 <etharp_find_entry+0x2e8>)
8018b28: 482b ldr r0, [pc, #172] ; (8018bd8 <etharp_find_entry+0x2e0>)
8018b2a: f002 fa4b bl 801afc4 <iprintf>
etharp_free_entry(i);
8018b2e: f9b7 3020 ldrsh.w r3, [r7, #32]
8018b32: 4618 mov r0, r3
8018b34: f7ff fe06 bl 8018744 <etharp_free_entry>
}
LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
8018b38: f9b7 3020 ldrsh.w r3, [r7, #32]
8018b3c: 2b09 cmp r3, #9
8018b3e: dd06 ble.n 8018b4e <etharp_find_entry+0x256>
8018b40: 4b23 ldr r3, [pc, #140] ; (8018bd0 <etharp_find_entry+0x2d8>)
8018b42: f240 1283 movw r2, #387 ; 0x183
8018b46: 4926 ldr r1, [pc, #152] ; (8018be0 <etharp_find_entry+0x2e8>)
8018b48: 4823 ldr r0, [pc, #140] ; (8018bd8 <etharp_find_entry+0x2e0>)
8018b4a: f002 fa3b bl 801afc4 <iprintf>
LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY",
8018b4e: f9b7 2020 ldrsh.w r2, [r7, #32]
8018b52: 491e ldr r1, [pc, #120] ; (8018bcc <etharp_find_entry+0x2d4>)
8018b54: 4613 mov r3, r2
8018b56: 005b lsls r3, r3, #1
8018b58: 4413 add r3, r2
8018b5a: 00db lsls r3, r3, #3
8018b5c: 440b add r3, r1
8018b5e: 3314 adds r3, #20
8018b60: 781b ldrb r3, [r3, #0]
8018b62: 2b00 cmp r3, #0
8018b64: d006 beq.n 8018b74 <etharp_find_entry+0x27c>
8018b66: 4b1a ldr r3, [pc, #104] ; (8018bd0 <etharp_find_entry+0x2d8>)
8018b68: f44f 72c2 mov.w r2, #388 ; 0x184
8018b6c: 491d ldr r1, [pc, #116] ; (8018be4 <etharp_find_entry+0x2ec>)
8018b6e: 481a ldr r0, [pc, #104] ; (8018bd8 <etharp_find_entry+0x2e0>)
8018b70: f002 fa28 bl 801afc4 <iprintf>
arp_table[i].state == ETHARP_STATE_EMPTY);
/* IP address given? */
if (ipaddr != NULL) {
8018b74: 68fb ldr r3, [r7, #12]
8018b76: 2b00 cmp r3, #0
8018b78: d00b beq.n 8018b92 <etharp_find_entry+0x29a>
/* set IP address */
ip4_addr_copy(arp_table[i].ipaddr, *ipaddr);
8018b7a: f9b7 2020 ldrsh.w r2, [r7, #32]
8018b7e: 68fb ldr r3, [r7, #12]
8018b80: 6819 ldr r1, [r3, #0]
8018b82: 4812 ldr r0, [pc, #72] ; (8018bcc <etharp_find_entry+0x2d4>)
8018b84: 4613 mov r3, r2
8018b86: 005b lsls r3, r3, #1
8018b88: 4413 add r3, r2
8018b8a: 00db lsls r3, r3, #3
8018b8c: 4403 add r3, r0
8018b8e: 3304 adds r3, #4
8018b90: 6019 str r1, [r3, #0]
}
arp_table[i].ctime = 0;
8018b92: f9b7 2020 ldrsh.w r2, [r7, #32]
8018b96: 490d ldr r1, [pc, #52] ; (8018bcc <etharp_find_entry+0x2d4>)
8018b98: 4613 mov r3, r2
8018b9a: 005b lsls r3, r3, #1
8018b9c: 4413 add r3, r2
8018b9e: 00db lsls r3, r3, #3
8018ba0: 440b add r3, r1
8018ba2: 3312 adds r3, #18
8018ba4: 2200 movs r2, #0
8018ba6: 801a strh r2, [r3, #0]
#if ETHARP_TABLE_MATCH_NETIF
arp_table[i].netif = netif;
8018ba8: f9b7 2020 ldrsh.w r2, [r7, #32]
8018bac: 4907 ldr r1, [pc, #28] ; (8018bcc <etharp_find_entry+0x2d4>)
8018bae: 4613 mov r3, r2
8018bb0: 005b lsls r3, r3, #1
8018bb2: 4413 add r3, r2
8018bb4: 00db lsls r3, r3, #3
8018bb6: 440b add r3, r1
8018bb8: 3308 adds r3, #8
8018bba: 687a ldr r2, [r7, #4]
8018bbc: 601a str r2, [r3, #0]
#endif /* ETHARP_TABLE_MATCH_NETIF */
return (s16_t)i;
8018bbe: f9b7 3020 ldrsh.w r3, [r7, #32]
}
8018bc2: 4618 mov r0, r3
8018bc4: 3728 adds r7, #40 ; 0x28
8018bc6: 46bd mov sp, r7
8018bc8: bd80 pop {r7, pc}
8018bca: bf00 nop
8018bcc: 2000876c .word 0x2000876c
8018bd0: 0801e90c .word 0x0801e90c
8018bd4: 0801e944 .word 0x0801e944
8018bd8: 0801e984 .word 0x0801e984
8018bdc: 0801e9ac .word 0x0801e9ac
8018be0: 0801e9c4 .word 0x0801e9c4
8018be4: 0801e9d8 .word 0x0801e9d8
08018be8 <etharp_update_arp_entry>:
*
* @see pbuf_free()
*/
static err_t
etharp_update_arp_entry(struct netif *netif, const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags)
{
8018be8: b580 push {r7, lr}
8018bea: b088 sub sp, #32
8018bec: af02 add r7, sp, #8
8018bee: 60f8 str r0, [r7, #12]
8018bf0: 60b9 str r1, [r7, #8]
8018bf2: 607a str r2, [r7, #4]
8018bf4: 70fb strb r3, [r7, #3]
s16_t i;
LWIP_ASSERT("netif->hwaddr_len == ETH_HWADDR_LEN", netif->hwaddr_len == ETH_HWADDR_LEN);
8018bf6: 68fb ldr r3, [r7, #12]
8018bf8: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
8018bfc: 2b06 cmp r3, #6
8018bfe: d006 beq.n 8018c0e <etharp_update_arp_entry+0x26>
8018c00: 4b48 ldr r3, [pc, #288] ; (8018d24 <etharp_update_arp_entry+0x13c>)
8018c02: f240 12a9 movw r2, #425 ; 0x1a9
8018c06: 4948 ldr r1, [pc, #288] ; (8018d28 <etharp_update_arp_entry+0x140>)
8018c08: 4848 ldr r0, [pc, #288] ; (8018d2c <etharp_update_arp_entry+0x144>)
8018c0a: f002 f9db bl 801afc4 <iprintf>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr),
(u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2],
(u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5]));
/* non-unicast address? */
if (ip4_addr_isany(ipaddr) ||
8018c0e: 68bb ldr r3, [r7, #8]
8018c10: 2b00 cmp r3, #0
8018c12: d012 beq.n 8018c3a <etharp_update_arp_entry+0x52>
8018c14: 68bb ldr r3, [r7, #8]
8018c16: 681b ldr r3, [r3, #0]
8018c18: 2b00 cmp r3, #0
8018c1a: d00e beq.n 8018c3a <etharp_update_arp_entry+0x52>
ip4_addr_isbroadcast(ipaddr, netif) ||
8018c1c: 68bb ldr r3, [r7, #8]
8018c1e: 681b ldr r3, [r3, #0]
8018c20: 68f9 ldr r1, [r7, #12]
8018c22: 4618 mov r0, r3
8018c24: f001 f920 bl 8019e68 <ip4_addr_isbroadcast_u32>
8018c28: 4603 mov r3, r0
if (ip4_addr_isany(ipaddr) ||
8018c2a: 2b00 cmp r3, #0
8018c2c: d105 bne.n 8018c3a <etharp_update_arp_entry+0x52>
ip4_addr_ismulticast(ipaddr)) {
8018c2e: 68bb ldr r3, [r7, #8]
8018c30: 681b ldr r3, [r3, #0]
8018c32: f003 03f0 and.w r3, r3, #240 ; 0xf0
ip4_addr_isbroadcast(ipaddr, netif) ||
8018c36: 2be0 cmp r3, #224 ; 0xe0
8018c38: d102 bne.n 8018c40 <etharp_update_arp_entry+0x58>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
return ERR_ARG;
8018c3a: f06f 030f mvn.w r3, #15
8018c3e: e06c b.n 8018d1a <etharp_update_arp_entry+0x132>
}
/* find or create ARP entry */
i = etharp_find_entry(ipaddr, flags, netif);
8018c40: 78fb ldrb r3, [r7, #3]
8018c42: 68fa ldr r2, [r7, #12]
8018c44: 4619 mov r1, r3
8018c46: 68b8 ldr r0, [r7, #8]
8018c48: f7ff fe56 bl 80188f8 <etharp_find_entry>
8018c4c: 4603 mov r3, r0
8018c4e: 82fb strh r3, [r7, #22]
/* bail out if no entry could be found */
if (i < 0) {
8018c50: f9b7 3016 ldrsh.w r3, [r7, #22]
8018c54: 2b00 cmp r3, #0
8018c56: da02 bge.n 8018c5e <etharp_update_arp_entry+0x76>
return (err_t)i;
8018c58: 8afb ldrh r3, [r7, #22]
8018c5a: b25b sxtb r3, r3
8018c5c: e05d b.n 8018d1a <etharp_update_arp_entry+0x132>
return ERR_VAL;
} else
#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
{
/* mark it stable */
arp_table[i].state = ETHARP_STATE_STABLE;
8018c5e: f9b7 2016 ldrsh.w r2, [r7, #22]
8018c62: 4933 ldr r1, [pc, #204] ; (8018d30 <etharp_update_arp_entry+0x148>)
8018c64: 4613 mov r3, r2
8018c66: 005b lsls r3, r3, #1
8018c68: 4413 add r3, r2
8018c6a: 00db lsls r3, r3, #3
8018c6c: 440b add r3, r1
8018c6e: 3314 adds r3, #20
8018c70: 2202 movs r2, #2
8018c72: 701a strb r2, [r3, #0]
}
/* record network interface */
arp_table[i].netif = netif;
8018c74: f9b7 2016 ldrsh.w r2, [r7, #22]
8018c78: 492d ldr r1, [pc, #180] ; (8018d30 <etharp_update_arp_entry+0x148>)
8018c7a: 4613 mov r3, r2
8018c7c: 005b lsls r3, r3, #1
8018c7e: 4413 add r3, r2
8018c80: 00db lsls r3, r3, #3
8018c82: 440b add r3, r1
8018c84: 3308 adds r3, #8
8018c86: 68fa ldr r2, [r7, #12]
8018c88: 601a str r2, [r3, #0]
/* insert in SNMP ARP index tree */
mib2_add_arp_entry(netif, &arp_table[i].ipaddr);
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: updating stable entry %"S16_F"\n", i));
/* update address */
SMEMCPY(&arp_table[i].ethaddr, ethaddr, ETH_HWADDR_LEN);
8018c8a: f9b7 2016 ldrsh.w r2, [r7, #22]
8018c8e: 4613 mov r3, r2
8018c90: 005b lsls r3, r3, #1
8018c92: 4413 add r3, r2
8018c94: 00db lsls r3, r3, #3
8018c96: 3308 adds r3, #8
8018c98: 4a25 ldr r2, [pc, #148] ; (8018d30 <etharp_update_arp_entry+0x148>)
8018c9a: 4413 add r3, r2
8018c9c: 3304 adds r3, #4
8018c9e: 2206 movs r2, #6
8018ca0: 6879 ldr r1, [r7, #4]
8018ca2: 4618 mov r0, r3
8018ca4: f002 f978 bl 801af98 <memcpy>
/* reset time stamp */
arp_table[i].ctime = 0;
8018ca8: f9b7 2016 ldrsh.w r2, [r7, #22]
8018cac: 4920 ldr r1, [pc, #128] ; (8018d30 <etharp_update_arp_entry+0x148>)
8018cae: 4613 mov r3, r2
8018cb0: 005b lsls r3, r3, #1
8018cb2: 4413 add r3, r2
8018cb4: 00db lsls r3, r3, #3
8018cb6: 440b add r3, r1
8018cb8: 3312 adds r3, #18
8018cba: 2200 movs r2, #0
8018cbc: 801a strh r2, [r3, #0]
/* get the packet pointer */
p = q->p;
/* now queue entry can be freed */
memp_free(MEMP_ARP_QUEUE, q);
#else /* ARP_QUEUEING */
if (arp_table[i].q != NULL) {
8018cbe: f9b7 2016 ldrsh.w r2, [r7, #22]
8018cc2: 491b ldr r1, [pc, #108] ; (8018d30 <etharp_update_arp_entry+0x148>)
8018cc4: 4613 mov r3, r2
8018cc6: 005b lsls r3, r3, #1
8018cc8: 4413 add r3, r2
8018cca: 00db lsls r3, r3, #3
8018ccc: 440b add r3, r1
8018cce: 681b ldr r3, [r3, #0]
8018cd0: 2b00 cmp r3, #0
8018cd2: d021 beq.n 8018d18 <etharp_update_arp_entry+0x130>
struct pbuf *p = arp_table[i].q;
8018cd4: f9b7 2016 ldrsh.w r2, [r7, #22]
8018cd8: 4915 ldr r1, [pc, #84] ; (8018d30 <etharp_update_arp_entry+0x148>)
8018cda: 4613 mov r3, r2
8018cdc: 005b lsls r3, r3, #1
8018cde: 4413 add r3, r2
8018ce0: 00db lsls r3, r3, #3
8018ce2: 440b add r3, r1
8018ce4: 681b ldr r3, [r3, #0]
8018ce6: 613b str r3, [r7, #16]
arp_table[i].q = NULL;
8018ce8: f9b7 2016 ldrsh.w r2, [r7, #22]
8018cec: 4910 ldr r1, [pc, #64] ; (8018d30 <etharp_update_arp_entry+0x148>)
8018cee: 4613 mov r3, r2
8018cf0: 005b lsls r3, r3, #1
8018cf2: 4413 add r3, r2
8018cf4: 00db lsls r3, r3, #3
8018cf6: 440b add r3, r1
8018cf8: 2200 movs r2, #0
8018cfa: 601a str r2, [r3, #0]
#endif /* ARP_QUEUEING */
/* send the queued IP packet */
ethernet_output(netif, p, (struct eth_addr *)(netif->hwaddr), ethaddr, ETHTYPE_IP);
8018cfc: 68fb ldr r3, [r7, #12]
8018cfe: f103 022a add.w r2, r3, #42 ; 0x2a
8018d02: f44f 6300 mov.w r3, #2048 ; 0x800
8018d06: 9300 str r3, [sp, #0]
8018d08: 687b ldr r3, [r7, #4]
8018d0a: 6939 ldr r1, [r7, #16]
8018d0c: 68f8 ldr r0, [r7, #12]
8018d0e: f001 ffb3 bl 801ac78 <ethernet_output>
/* free the queued IP packet */
pbuf_free(p);
8018d12: 6938 ldr r0, [r7, #16]
8018d14: f7f7 fc4a bl 80105ac <pbuf_free>
}
return ERR_OK;
8018d18: 2300 movs r3, #0
}
8018d1a: 4618 mov r0, r3
8018d1c: 3718 adds r7, #24
8018d1e: 46bd mov sp, r7
8018d20: bd80 pop {r7, pc}
8018d22: bf00 nop
8018d24: 0801e90c .word 0x0801e90c
8018d28: 0801ea04 .word 0x0801ea04
8018d2c: 0801e984 .word 0x0801e984
8018d30: 2000876c .word 0x2000876c
08018d34 <etharp_cleanup_netif>:
*
* @param netif points to a network interface
*/
void
etharp_cleanup_netif(struct netif *netif)
{
8018d34: b580 push {r7, lr}
8018d36: b084 sub sp, #16
8018d38: af00 add r7, sp, #0
8018d3a: 6078 str r0, [r7, #4]
int i;
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
8018d3c: 2300 movs r3, #0
8018d3e: 60fb str r3, [r7, #12]
8018d40: e01e b.n 8018d80 <etharp_cleanup_netif+0x4c>
u8_t state = arp_table[i].state;
8018d42: 4913 ldr r1, [pc, #76] ; (8018d90 <etharp_cleanup_netif+0x5c>)
8018d44: 68fa ldr r2, [r7, #12]
8018d46: 4613 mov r3, r2
8018d48: 005b lsls r3, r3, #1
8018d4a: 4413 add r3, r2
8018d4c: 00db lsls r3, r3, #3
8018d4e: 440b add r3, r1
8018d50: 3314 adds r3, #20
8018d52: 781b ldrb r3, [r3, #0]
8018d54: 72fb strb r3, [r7, #11]
if ((state != ETHARP_STATE_EMPTY) && (arp_table[i].netif == netif)) {
8018d56: 7afb ldrb r3, [r7, #11]
8018d58: 2b00 cmp r3, #0
8018d5a: d00e beq.n 8018d7a <etharp_cleanup_netif+0x46>
8018d5c: 490c ldr r1, [pc, #48] ; (8018d90 <etharp_cleanup_netif+0x5c>)
8018d5e: 68fa ldr r2, [r7, #12]
8018d60: 4613 mov r3, r2
8018d62: 005b lsls r3, r3, #1
8018d64: 4413 add r3, r2
8018d66: 00db lsls r3, r3, #3
8018d68: 440b add r3, r1
8018d6a: 3308 adds r3, #8
8018d6c: 681b ldr r3, [r3, #0]
8018d6e: 687a ldr r2, [r7, #4]
8018d70: 429a cmp r2, r3
8018d72: d102 bne.n 8018d7a <etharp_cleanup_netif+0x46>
etharp_free_entry(i);
8018d74: 68f8 ldr r0, [r7, #12]
8018d76: f7ff fce5 bl 8018744 <etharp_free_entry>
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
8018d7a: 68fb ldr r3, [r7, #12]
8018d7c: 3301 adds r3, #1
8018d7e: 60fb str r3, [r7, #12]
8018d80: 68fb ldr r3, [r7, #12]
8018d82: 2b09 cmp r3, #9
8018d84: dddd ble.n 8018d42 <etharp_cleanup_netif+0xe>
}
}
}
8018d86: bf00 nop
8018d88: bf00 nop
8018d8a: 3710 adds r7, #16
8018d8c: 46bd mov sp, r7
8018d8e: bd80 pop {r7, pc}
8018d90: 2000876c .word 0x2000876c
08018d94 <etharp_input>:
*
* @see pbuf_free()
*/
void
etharp_input(struct pbuf *p, struct netif *netif)
{
8018d94: b5b0 push {r4, r5, r7, lr}
8018d96: b08a sub sp, #40 ; 0x28
8018d98: af04 add r7, sp, #16
8018d9a: 6078 str r0, [r7, #4]
8018d9c: 6039 str r1, [r7, #0]
ip4_addr_t sipaddr, dipaddr;
u8_t for_us;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif != NULL", (netif != NULL), return;);
8018d9e: 683b ldr r3, [r7, #0]
8018da0: 2b00 cmp r3, #0
8018da2: d107 bne.n 8018db4 <etharp_input+0x20>
8018da4: 4b3f ldr r3, [pc, #252] ; (8018ea4 <etharp_input+0x110>)
8018da6: f240 228a movw r2, #650 ; 0x28a
8018daa: 493f ldr r1, [pc, #252] ; (8018ea8 <etharp_input+0x114>)
8018dac: 483f ldr r0, [pc, #252] ; (8018eac <etharp_input+0x118>)
8018dae: f002 f909 bl 801afc4 <iprintf>
8018db2: e074 b.n 8018e9e <etharp_input+0x10a>
hdr = (struct etharp_hdr *)p->payload;
8018db4: 687b ldr r3, [r7, #4]
8018db6: 685b ldr r3, [r3, #4]
8018db8: 613b str r3, [r7, #16]
/* RFC 826 "Packet Reception": */
if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
8018dba: 693b ldr r3, [r7, #16]
8018dbc: 881b ldrh r3, [r3, #0]
8018dbe: b29b uxth r3, r3
8018dc0: f5b3 7f80 cmp.w r3, #256 ; 0x100
8018dc4: d10c bne.n 8018de0 <etharp_input+0x4c>
(hdr->hwlen != ETH_HWADDR_LEN) ||
8018dc6: 693b ldr r3, [r7, #16]
8018dc8: 791b ldrb r3, [r3, #4]
if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
8018dca: 2b06 cmp r3, #6
8018dcc: d108 bne.n 8018de0 <etharp_input+0x4c>
(hdr->protolen != sizeof(ip4_addr_t)) ||
8018dce: 693b ldr r3, [r7, #16]
8018dd0: 795b ldrb r3, [r3, #5]
(hdr->hwlen != ETH_HWADDR_LEN) ||
8018dd2: 2b04 cmp r3, #4
8018dd4: d104 bne.n 8018de0 <etharp_input+0x4c>
(hdr->proto != PP_HTONS(ETHTYPE_IP))) {
8018dd6: 693b ldr r3, [r7, #16]
8018dd8: 885b ldrh r3, [r3, #2]
8018dda: b29b uxth r3, r3
(hdr->protolen != sizeof(ip4_addr_t)) ||
8018ddc: 2b08 cmp r3, #8
8018dde: d003 beq.n 8018de8 <etharp_input+0x54>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
("etharp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n",
hdr->hwtype, (u16_t)hdr->hwlen, hdr->proto, (u16_t)hdr->protolen));
ETHARP_STATS_INC(etharp.proterr);
ETHARP_STATS_INC(etharp.drop);
pbuf_free(p);
8018de0: 6878 ldr r0, [r7, #4]
8018de2: f7f7 fbe3 bl 80105ac <pbuf_free>
return;
8018de6: e05a b.n 8018e9e <etharp_input+0x10a>
autoip_arp_reply(netif, hdr);
#endif /* LWIP_AUTOIP */
/* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
* structure packing (not using structure copy which breaks strict-aliasing rules). */
IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr);
8018de8: 693b ldr r3, [r7, #16]
8018dea: 330e adds r3, #14
8018dec: 681b ldr r3, [r3, #0]
8018dee: 60fb str r3, [r7, #12]
IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr);
8018df0: 693b ldr r3, [r7, #16]
8018df2: 3318 adds r3, #24
8018df4: 681b ldr r3, [r3, #0]
8018df6: 60bb str r3, [r7, #8]
/* this interface is not configured? */
if (ip4_addr_isany_val(*netif_ip4_addr(netif))) {
8018df8: 683b ldr r3, [r7, #0]
8018dfa: 3304 adds r3, #4
8018dfc: 681b ldr r3, [r3, #0]
8018dfe: 2b00 cmp r3, #0
8018e00: d102 bne.n 8018e08 <etharp_input+0x74>
for_us = 0;
8018e02: 2300 movs r3, #0
8018e04: 75fb strb r3, [r7, #23]
8018e06: e009 b.n 8018e1c <etharp_input+0x88>
} else {
/* ARP packet directed to us? */
for_us = (u8_t)ip4_addr_cmp(&dipaddr, netif_ip4_addr(netif));
8018e08: 68ba ldr r2, [r7, #8]
8018e0a: 683b ldr r3, [r7, #0]
8018e0c: 3304 adds r3, #4
8018e0e: 681b ldr r3, [r3, #0]
8018e10: 429a cmp r2, r3
8018e12: bf0c ite eq
8018e14: 2301 moveq r3, #1
8018e16: 2300 movne r3, #0
8018e18: b2db uxtb r3, r3
8018e1a: 75fb strb r3, [r7, #23]
/* ARP message directed to us?
-> add IP address in ARP cache; assume requester wants to talk to us,
can result in directly sending the queued packets for this host.
ARP message not directed to us?
-> update the source IP address in the cache, if present */
etharp_update_arp_entry(netif, &sipaddr, &(hdr->shwaddr),
8018e1c: 693b ldr r3, [r7, #16]
8018e1e: f103 0208 add.w r2, r3, #8
8018e22: 7dfb ldrb r3, [r7, #23]
8018e24: 2b00 cmp r3, #0
8018e26: d001 beq.n 8018e2c <etharp_input+0x98>
8018e28: 2301 movs r3, #1
8018e2a: e000 b.n 8018e2e <etharp_input+0x9a>
8018e2c: 2302 movs r3, #2
8018e2e: f107 010c add.w r1, r7, #12
8018e32: 6838 ldr r0, [r7, #0]
8018e34: f7ff fed8 bl 8018be8 <etharp_update_arp_entry>
for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY);
/* now act on the message itself */
switch (hdr->opcode) {
8018e38: 693b ldr r3, [r7, #16]
8018e3a: 88db ldrh r3, [r3, #6]
8018e3c: b29b uxth r3, r3
8018e3e: f5b3 7f80 cmp.w r3, #256 ; 0x100
8018e42: d003 beq.n 8018e4c <etharp_input+0xb8>
8018e44: f5b3 7f00 cmp.w r3, #512 ; 0x200
8018e48: d01e beq.n 8018e88 <etharp_input+0xf4>
#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */
break;
default:
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP unknown opcode type %"S16_F"\n", lwip_htons(hdr->opcode)));
ETHARP_STATS_INC(etharp.err);
break;
8018e4a: e025 b.n 8018e98 <etharp_input+0x104>
if (for_us) {
8018e4c: 7dfb ldrb r3, [r7, #23]
8018e4e: 2b00 cmp r3, #0
8018e50: d021 beq.n 8018e96 <etharp_input+0x102>
(struct eth_addr *)netif->hwaddr, &hdr->shwaddr,
8018e52: 683b ldr r3, [r7, #0]
8018e54: f103 002a add.w r0, r3, #42 ; 0x2a
8018e58: 693b ldr r3, [r7, #16]
8018e5a: f103 0408 add.w r4, r3, #8
(struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif),
8018e5e: 683b ldr r3, [r7, #0]
8018e60: f103 052a add.w r5, r3, #42 ; 0x2a
8018e64: 683b ldr r3, [r7, #0]
8018e66: 3304 adds r3, #4
&hdr->shwaddr, &sipaddr,
8018e68: 693a ldr r2, [r7, #16]
8018e6a: 3208 adds r2, #8
etharp_raw(netif,
8018e6c: 2102 movs r1, #2
8018e6e: 9103 str r1, [sp, #12]
8018e70: f107 010c add.w r1, r7, #12
8018e74: 9102 str r1, [sp, #8]
8018e76: 9201 str r2, [sp, #4]
8018e78: 9300 str r3, [sp, #0]
8018e7a: 462b mov r3, r5
8018e7c: 4622 mov r2, r4
8018e7e: 4601 mov r1, r0
8018e80: 6838 ldr r0, [r7, #0]
8018e82: f000 faef bl 8019464 <etharp_raw>
break;
8018e86: e006 b.n 8018e96 <etharp_input+0x102>
dhcp_arp_reply(netif, &sipaddr);
8018e88: f107 030c add.w r3, r7, #12
8018e8c: 4619 mov r1, r3
8018e8e: 6838 ldr r0, [r7, #0]
8018e90: f7fe f9fc bl 801728c <dhcp_arp_reply>
break;
8018e94: e000 b.n 8018e98 <etharp_input+0x104>
break;
8018e96: bf00 nop
}
/* free ARP packet */
pbuf_free(p);
8018e98: 6878 ldr r0, [r7, #4]
8018e9a: f7f7 fb87 bl 80105ac <pbuf_free>
}
8018e9e: 3718 adds r7, #24
8018ea0: 46bd mov sp, r7
8018ea2: bdb0 pop {r4, r5, r7, pc}
8018ea4: 0801e90c .word 0x0801e90c
8018ea8: 0801ea5c .word 0x0801ea5c
8018eac: 0801e984 .word 0x0801e984
08018eb0 <etharp_output_to_arp_index>:
/** Just a small helper function that sends a pbuf to an ethernet address
* in the arp_table specified by the index 'arp_idx'.
*/
static err_t
etharp_output_to_arp_index(struct netif *netif, struct pbuf *q, netif_addr_idx_t arp_idx)
{
8018eb0: b580 push {r7, lr}
8018eb2: b086 sub sp, #24
8018eb4: af02 add r7, sp, #8
8018eb6: 60f8 str r0, [r7, #12]
8018eb8: 60b9 str r1, [r7, #8]
8018eba: 4613 mov r3, r2
8018ebc: 71fb strb r3, [r7, #7]
LWIP_ASSERT("arp_table[arp_idx].state >= ETHARP_STATE_STABLE",
8018ebe: 79fa ldrb r2, [r7, #7]
8018ec0: 4944 ldr r1, [pc, #272] ; (8018fd4 <etharp_output_to_arp_index+0x124>)
8018ec2: 4613 mov r3, r2
8018ec4: 005b lsls r3, r3, #1
8018ec6: 4413 add r3, r2
8018ec8: 00db lsls r3, r3, #3
8018eca: 440b add r3, r1
8018ecc: 3314 adds r3, #20
8018ece: 781b ldrb r3, [r3, #0]
8018ed0: 2b01 cmp r3, #1
8018ed2: d806 bhi.n 8018ee2 <etharp_output_to_arp_index+0x32>
8018ed4: 4b40 ldr r3, [pc, #256] ; (8018fd8 <etharp_output_to_arp_index+0x128>)
8018ed6: f240 22ee movw r2, #750 ; 0x2ee
8018eda: 4940 ldr r1, [pc, #256] ; (8018fdc <etharp_output_to_arp_index+0x12c>)
8018edc: 4840 ldr r0, [pc, #256] ; (8018fe0 <etharp_output_to_arp_index+0x130>)
8018ede: f002 f871 bl 801afc4 <iprintf>
arp_table[arp_idx].state >= ETHARP_STATE_STABLE);
/* if arp table entry is about to expire: re-request it,
but only if its state is ETHARP_STATE_STABLE to prevent flooding the
network with ARP requests if this address is used frequently. */
if (arp_table[arp_idx].state == ETHARP_STATE_STABLE) {
8018ee2: 79fa ldrb r2, [r7, #7]
8018ee4: 493b ldr r1, [pc, #236] ; (8018fd4 <etharp_output_to_arp_index+0x124>)
8018ee6: 4613 mov r3, r2
8018ee8: 005b lsls r3, r3, #1
8018eea: 4413 add r3, r2
8018eec: 00db lsls r3, r3, #3
8018eee: 440b add r3, r1
8018ef0: 3314 adds r3, #20
8018ef2: 781b ldrb r3, [r3, #0]
8018ef4: 2b02 cmp r3, #2
8018ef6: d153 bne.n 8018fa0 <etharp_output_to_arp_index+0xf0>
if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_BROADCAST) {
8018ef8: 79fa ldrb r2, [r7, #7]
8018efa: 4936 ldr r1, [pc, #216] ; (8018fd4 <etharp_output_to_arp_index+0x124>)
8018efc: 4613 mov r3, r2
8018efe: 005b lsls r3, r3, #1
8018f00: 4413 add r3, r2
8018f02: 00db lsls r3, r3, #3
8018f04: 440b add r3, r1
8018f06: 3312 adds r3, #18
8018f08: 881b ldrh r3, [r3, #0]
8018f0a: f5b3 7f8e cmp.w r3, #284 ; 0x11c
8018f0e: d919 bls.n 8018f44 <etharp_output_to_arp_index+0x94>
/* issue a standard request using broadcast */
if (etharp_request(netif, &arp_table[arp_idx].ipaddr) == ERR_OK) {
8018f10: 79fa ldrb r2, [r7, #7]
8018f12: 4613 mov r3, r2
8018f14: 005b lsls r3, r3, #1
8018f16: 4413 add r3, r2
8018f18: 00db lsls r3, r3, #3
8018f1a: 4a2e ldr r2, [pc, #184] ; (8018fd4 <etharp_output_to_arp_index+0x124>)
8018f1c: 4413 add r3, r2
8018f1e: 3304 adds r3, #4
8018f20: 4619 mov r1, r3
8018f22: 68f8 ldr r0, [r7, #12]
8018f24: f000 fb4c bl 80195c0 <etharp_request>
8018f28: 4603 mov r3, r0
8018f2a: 2b00 cmp r3, #0
8018f2c: d138 bne.n 8018fa0 <etharp_output_to_arp_index+0xf0>
arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
8018f2e: 79fa ldrb r2, [r7, #7]
8018f30: 4928 ldr r1, [pc, #160] ; (8018fd4 <etharp_output_to_arp_index+0x124>)
8018f32: 4613 mov r3, r2
8018f34: 005b lsls r3, r3, #1
8018f36: 4413 add r3, r2
8018f38: 00db lsls r3, r3, #3
8018f3a: 440b add r3, r1
8018f3c: 3314 adds r3, #20
8018f3e: 2203 movs r2, #3
8018f40: 701a strb r2, [r3, #0]
8018f42: e02d b.n 8018fa0 <etharp_output_to_arp_index+0xf0>
}
} else if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_UNICAST) {
8018f44: 79fa ldrb r2, [r7, #7]
8018f46: 4923 ldr r1, [pc, #140] ; (8018fd4 <etharp_output_to_arp_index+0x124>)
8018f48: 4613 mov r3, r2
8018f4a: 005b lsls r3, r3, #1
8018f4c: 4413 add r3, r2
8018f4e: 00db lsls r3, r3, #3
8018f50: 440b add r3, r1
8018f52: 3312 adds r3, #18
8018f54: 881b ldrh r3, [r3, #0]
8018f56: f5b3 7f87 cmp.w r3, #270 ; 0x10e
8018f5a: d321 bcc.n 8018fa0 <etharp_output_to_arp_index+0xf0>
/* issue a unicast request (for 15 seconds) to prevent unnecessary broadcast */
if (etharp_request_dst(netif, &arp_table[arp_idx].ipaddr, &arp_table[arp_idx].ethaddr) == ERR_OK) {
8018f5c: 79fa ldrb r2, [r7, #7]
8018f5e: 4613 mov r3, r2
8018f60: 005b lsls r3, r3, #1
8018f62: 4413 add r3, r2
8018f64: 00db lsls r3, r3, #3
8018f66: 4a1b ldr r2, [pc, #108] ; (8018fd4 <etharp_output_to_arp_index+0x124>)
8018f68: 4413 add r3, r2
8018f6a: 1d19 adds r1, r3, #4
8018f6c: 79fa ldrb r2, [r7, #7]
8018f6e: 4613 mov r3, r2
8018f70: 005b lsls r3, r3, #1
8018f72: 4413 add r3, r2
8018f74: 00db lsls r3, r3, #3
8018f76: 3308 adds r3, #8
8018f78: 4a16 ldr r2, [pc, #88] ; (8018fd4 <etharp_output_to_arp_index+0x124>)
8018f7a: 4413 add r3, r2
8018f7c: 3304 adds r3, #4
8018f7e: 461a mov r2, r3
8018f80: 68f8 ldr r0, [r7, #12]
8018f82: f000 fafb bl 801957c <etharp_request_dst>
8018f86: 4603 mov r3, r0
8018f88: 2b00 cmp r3, #0
8018f8a: d109 bne.n 8018fa0 <etharp_output_to_arp_index+0xf0>
arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
8018f8c: 79fa ldrb r2, [r7, #7]
8018f8e: 4911 ldr r1, [pc, #68] ; (8018fd4 <etharp_output_to_arp_index+0x124>)
8018f90: 4613 mov r3, r2
8018f92: 005b lsls r3, r3, #1
8018f94: 4413 add r3, r2
8018f96: 00db lsls r3, r3, #3
8018f98: 440b add r3, r1
8018f9a: 3314 adds r3, #20
8018f9c: 2203 movs r2, #3
8018f9e: 701a strb r2, [r3, #0]
}
}
}
return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), &arp_table[arp_idx].ethaddr, ETHTYPE_IP);
8018fa0: 68fb ldr r3, [r7, #12]
8018fa2: f103 012a add.w r1, r3, #42 ; 0x2a
8018fa6: 79fa ldrb r2, [r7, #7]
8018fa8: 4613 mov r3, r2
8018faa: 005b lsls r3, r3, #1
8018fac: 4413 add r3, r2
8018fae: 00db lsls r3, r3, #3
8018fb0: 3308 adds r3, #8
8018fb2: 4a08 ldr r2, [pc, #32] ; (8018fd4 <etharp_output_to_arp_index+0x124>)
8018fb4: 4413 add r3, r2
8018fb6: 3304 adds r3, #4
8018fb8: f44f 6200 mov.w r2, #2048 ; 0x800
8018fbc: 9200 str r2, [sp, #0]
8018fbe: 460a mov r2, r1
8018fc0: 68b9 ldr r1, [r7, #8]
8018fc2: 68f8 ldr r0, [r7, #12]
8018fc4: f001 fe58 bl 801ac78 <ethernet_output>
8018fc8: 4603 mov r3, r0
}
8018fca: 4618 mov r0, r3
8018fcc: 3710 adds r7, #16
8018fce: 46bd mov sp, r7
8018fd0: bd80 pop {r7, pc}
8018fd2: bf00 nop
8018fd4: 2000876c .word 0x2000876c
8018fd8: 0801e90c .word 0x0801e90c
8018fdc: 0801ea7c .word 0x0801ea7c
8018fe0: 0801e984 .word 0x0801e984
08018fe4 <etharp_output>:
* - ERR_RTE No route to destination (no gateway to external networks),
* or the return type of either etharp_query() or ethernet_output().
*/
err_t
etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr)
{
8018fe4: b580 push {r7, lr}
8018fe6: b08a sub sp, #40 ; 0x28
8018fe8: af02 add r7, sp, #8
8018fea: 60f8 str r0, [r7, #12]
8018fec: 60b9 str r1, [r7, #8]
8018fee: 607a str r2, [r7, #4]
const struct eth_addr *dest;
struct eth_addr mcastaddr;
const ip4_addr_t *dst_addr = ipaddr;
8018ff0: 687b ldr r3, [r7, #4]
8018ff2: 61bb str r3, [r7, #24]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("netif != NULL", netif != NULL);
8018ff4: 68fb ldr r3, [r7, #12]
8018ff6: 2b00 cmp r3, #0
8018ff8: d106 bne.n 8019008 <etharp_output+0x24>
8018ffa: 4b73 ldr r3, [pc, #460] ; (80191c8 <etharp_output+0x1e4>)
8018ffc: f240 321e movw r2, #798 ; 0x31e
8019000: 4972 ldr r1, [pc, #456] ; (80191cc <etharp_output+0x1e8>)
8019002: 4873 ldr r0, [pc, #460] ; (80191d0 <etharp_output+0x1ec>)
8019004: f001 ffde bl 801afc4 <iprintf>
LWIP_ASSERT("q != NULL", q != NULL);
8019008: 68bb ldr r3, [r7, #8]
801900a: 2b00 cmp r3, #0
801900c: d106 bne.n 801901c <etharp_output+0x38>
801900e: 4b6e ldr r3, [pc, #440] ; (80191c8 <etharp_output+0x1e4>)
8019010: f240 321f movw r2, #799 ; 0x31f
8019014: 496f ldr r1, [pc, #444] ; (80191d4 <etharp_output+0x1f0>)
8019016: 486e ldr r0, [pc, #440] ; (80191d0 <etharp_output+0x1ec>)
8019018: f001 ffd4 bl 801afc4 <iprintf>
LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL);
801901c: 687b ldr r3, [r7, #4]
801901e: 2b00 cmp r3, #0
8019020: d106 bne.n 8019030 <etharp_output+0x4c>
8019022: 4b69 ldr r3, [pc, #420] ; (80191c8 <etharp_output+0x1e4>)
8019024: f44f 7248 mov.w r2, #800 ; 0x320
8019028: 496b ldr r1, [pc, #428] ; (80191d8 <etharp_output+0x1f4>)
801902a: 4869 ldr r0, [pc, #420] ; (80191d0 <etharp_output+0x1ec>)
801902c: f001 ffca bl 801afc4 <iprintf>
/* Determine on destination hardware address. Broadcasts and multicasts
* are special, other IP addresses are looked up in the ARP table. */
/* broadcast destination IP address? */
if (ip4_addr_isbroadcast(ipaddr, netif)) {
8019030: 687b ldr r3, [r7, #4]
8019032: 681b ldr r3, [r3, #0]
8019034: 68f9 ldr r1, [r7, #12]
8019036: 4618 mov r0, r3
8019038: f000 ff16 bl 8019e68 <ip4_addr_isbroadcast_u32>
801903c: 4603 mov r3, r0
801903e: 2b00 cmp r3, #0
8019040: d002 beq.n 8019048 <etharp_output+0x64>
/* broadcast on Ethernet also */
dest = (const struct eth_addr *)&ethbroadcast;
8019042: 4b66 ldr r3, [pc, #408] ; (80191dc <etharp_output+0x1f8>)
8019044: 61fb str r3, [r7, #28]
8019046: e0af b.n 80191a8 <etharp_output+0x1c4>
/* multicast destination IP address? */
} else if (ip4_addr_ismulticast(ipaddr)) {
8019048: 687b ldr r3, [r7, #4]
801904a: 681b ldr r3, [r3, #0]
801904c: f003 03f0 and.w r3, r3, #240 ; 0xf0
8019050: 2be0 cmp r3, #224 ; 0xe0
8019052: d118 bne.n 8019086 <etharp_output+0xa2>
/* Hash IP multicast address to MAC address.*/
mcastaddr.addr[0] = LL_IP4_MULTICAST_ADDR_0;
8019054: 2301 movs r3, #1
8019056: 743b strb r3, [r7, #16]
mcastaddr.addr[1] = LL_IP4_MULTICAST_ADDR_1;
8019058: 2300 movs r3, #0
801905a: 747b strb r3, [r7, #17]
mcastaddr.addr[2] = LL_IP4_MULTICAST_ADDR_2;
801905c: 235e movs r3, #94 ; 0x5e
801905e: 74bb strb r3, [r7, #18]
mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
8019060: 687b ldr r3, [r7, #4]
8019062: 3301 adds r3, #1
8019064: 781b ldrb r3, [r3, #0]
8019066: f003 037f and.w r3, r3, #127 ; 0x7f
801906a: b2db uxtb r3, r3
801906c: 74fb strb r3, [r7, #19]
mcastaddr.addr[4] = ip4_addr3(ipaddr);
801906e: 687b ldr r3, [r7, #4]
8019070: 3302 adds r3, #2
8019072: 781b ldrb r3, [r3, #0]
8019074: 753b strb r3, [r7, #20]
mcastaddr.addr[5] = ip4_addr4(ipaddr);
8019076: 687b ldr r3, [r7, #4]
8019078: 3303 adds r3, #3
801907a: 781b ldrb r3, [r3, #0]
801907c: 757b strb r3, [r7, #21]
/* destination Ethernet address is multicast */
dest = &mcastaddr;
801907e: f107 0310 add.w r3, r7, #16
8019082: 61fb str r3, [r7, #28]
8019084: e090 b.n 80191a8 <etharp_output+0x1c4>
/* unicast destination IP address? */
} else {
netif_addr_idx_t i;
/* outside local network? if so, this can neither be a global broadcast nor
a subnet broadcast. */
if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
8019086: 687b ldr r3, [r7, #4]
8019088: 681a ldr r2, [r3, #0]
801908a: 68fb ldr r3, [r7, #12]
801908c: 3304 adds r3, #4
801908e: 681b ldr r3, [r3, #0]
8019090: 405a eors r2, r3
8019092: 68fb ldr r3, [r7, #12]
8019094: 3308 adds r3, #8
8019096: 681b ldr r3, [r3, #0]
8019098: 4013 ands r3, r2
801909a: 2b00 cmp r3, #0
801909c: d012 beq.n 80190c4 <etharp_output+0xe0>
!ip4_addr_islinklocal(ipaddr)) {
801909e: 687b ldr r3, [r7, #4]
80190a0: 681b ldr r3, [r3, #0]
80190a2: b29b uxth r3, r3
if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
80190a4: f64f 62a9 movw r2, #65193 ; 0xfea9
80190a8: 4293 cmp r3, r2
80190aa: d00b beq.n 80190c4 <etharp_output+0xe0>
dst_addr = LWIP_HOOK_ETHARP_GET_GW(netif, ipaddr);
if (dst_addr == NULL)
#endif /* LWIP_HOOK_ETHARP_GET_GW */
{
/* interface has default gateway? */
if (!ip4_addr_isany_val(*netif_ip4_gw(netif))) {
80190ac: 68fb ldr r3, [r7, #12]
80190ae: 330c adds r3, #12
80190b0: 681b ldr r3, [r3, #0]
80190b2: 2b00 cmp r3, #0
80190b4: d003 beq.n 80190be <etharp_output+0xda>
/* send to hardware address of default gateway IP address */
dst_addr = netif_ip4_gw(netif);
80190b6: 68fb ldr r3, [r7, #12]
80190b8: 330c adds r3, #12
80190ba: 61bb str r3, [r7, #24]
80190bc: e002 b.n 80190c4 <etharp_output+0xe0>
/* no default gateway available */
} else {
/* no route to destination error (default gateway missing) */
return ERR_RTE;
80190be: f06f 0303 mvn.w r3, #3
80190c2: e07d b.n 80191c0 <etharp_output+0x1dc>
if (netif->hints != NULL) {
/* per-pcb cached entry was given */
netif_addr_idx_t etharp_cached_entry = netif->hints->addr_hint;
if (etharp_cached_entry < ARP_TABLE_SIZE) {
#endif /* LWIP_NETIF_HWADDRHINT */
if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
80190c4: 4b46 ldr r3, [pc, #280] ; (80191e0 <etharp_output+0x1fc>)
80190c6: 781b ldrb r3, [r3, #0]
80190c8: 4619 mov r1, r3
80190ca: 4a46 ldr r2, [pc, #280] ; (80191e4 <etharp_output+0x200>)
80190cc: 460b mov r3, r1
80190ce: 005b lsls r3, r3, #1
80190d0: 440b add r3, r1
80190d2: 00db lsls r3, r3, #3
80190d4: 4413 add r3, r2
80190d6: 3314 adds r3, #20
80190d8: 781b ldrb r3, [r3, #0]
80190da: 2b01 cmp r3, #1
80190dc: d925 bls.n 801912a <etharp_output+0x146>
#if ETHARP_TABLE_MATCH_NETIF
(arp_table[etharp_cached_entry].netif == netif) &&
80190de: 4b40 ldr r3, [pc, #256] ; (80191e0 <etharp_output+0x1fc>)
80190e0: 781b ldrb r3, [r3, #0]
80190e2: 4619 mov r1, r3
80190e4: 4a3f ldr r2, [pc, #252] ; (80191e4 <etharp_output+0x200>)
80190e6: 460b mov r3, r1
80190e8: 005b lsls r3, r3, #1
80190ea: 440b add r3, r1
80190ec: 00db lsls r3, r3, #3
80190ee: 4413 add r3, r2
80190f0: 3308 adds r3, #8
80190f2: 681b ldr r3, [r3, #0]
if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
80190f4: 68fa ldr r2, [r7, #12]
80190f6: 429a cmp r2, r3
80190f8: d117 bne.n 801912a <etharp_output+0x146>
#endif
(ip4_addr_cmp(dst_addr, &arp_table[etharp_cached_entry].ipaddr))) {
80190fa: 69bb ldr r3, [r7, #24]
80190fc: 681a ldr r2, [r3, #0]
80190fe: 4b38 ldr r3, [pc, #224] ; (80191e0 <etharp_output+0x1fc>)
8019100: 781b ldrb r3, [r3, #0]
8019102: 4618 mov r0, r3
8019104: 4937 ldr r1, [pc, #220] ; (80191e4 <etharp_output+0x200>)
8019106: 4603 mov r3, r0
8019108: 005b lsls r3, r3, #1
801910a: 4403 add r3, r0
801910c: 00db lsls r3, r3, #3
801910e: 440b add r3, r1
8019110: 3304 adds r3, #4
8019112: 681b ldr r3, [r3, #0]
(arp_table[etharp_cached_entry].netif == netif) &&
8019114: 429a cmp r2, r3
8019116: d108 bne.n 801912a <etharp_output+0x146>
/* the per-pcb-cached entry is stable and the right one! */
ETHARP_STATS_INC(etharp.cachehit);
return etharp_output_to_arp_index(netif, q, etharp_cached_entry);
8019118: 4b31 ldr r3, [pc, #196] ; (80191e0 <etharp_output+0x1fc>)
801911a: 781b ldrb r3, [r3, #0]
801911c: 461a mov r2, r3
801911e: 68b9 ldr r1, [r7, #8]
8019120: 68f8 ldr r0, [r7, #12]
8019122: f7ff fec5 bl 8018eb0 <etharp_output_to_arp_index>
8019126: 4603 mov r3, r0
8019128: e04a b.n 80191c0 <etharp_output+0x1dc>
}
#endif /* LWIP_NETIF_HWADDRHINT */
/* find stable entry: do this here since this is a critical path for
throughput and etharp_find_entry() is kind of slow */
for (i = 0; i < ARP_TABLE_SIZE; i++) {
801912a: 2300 movs r3, #0
801912c: 75fb strb r3, [r7, #23]
801912e: e031 b.n 8019194 <etharp_output+0x1b0>
if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
8019130: 7dfa ldrb r2, [r7, #23]
8019132: 492c ldr r1, [pc, #176] ; (80191e4 <etharp_output+0x200>)
8019134: 4613 mov r3, r2
8019136: 005b lsls r3, r3, #1
8019138: 4413 add r3, r2
801913a: 00db lsls r3, r3, #3
801913c: 440b add r3, r1
801913e: 3314 adds r3, #20
8019140: 781b ldrb r3, [r3, #0]
8019142: 2b01 cmp r3, #1
8019144: d923 bls.n 801918e <etharp_output+0x1aa>
#if ETHARP_TABLE_MATCH_NETIF
(arp_table[i].netif == netif) &&
8019146: 7dfa ldrb r2, [r7, #23]
8019148: 4926 ldr r1, [pc, #152] ; (80191e4 <etharp_output+0x200>)
801914a: 4613 mov r3, r2
801914c: 005b lsls r3, r3, #1
801914e: 4413 add r3, r2
8019150: 00db lsls r3, r3, #3
8019152: 440b add r3, r1
8019154: 3308 adds r3, #8
8019156: 681b ldr r3, [r3, #0]
if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
8019158: 68fa ldr r2, [r7, #12]
801915a: 429a cmp r2, r3
801915c: d117 bne.n 801918e <etharp_output+0x1aa>
#endif
(ip4_addr_cmp(dst_addr, &arp_table[i].ipaddr))) {
801915e: 69bb ldr r3, [r7, #24]
8019160: 6819 ldr r1, [r3, #0]
8019162: 7dfa ldrb r2, [r7, #23]
8019164: 481f ldr r0, [pc, #124] ; (80191e4 <etharp_output+0x200>)
8019166: 4613 mov r3, r2
8019168: 005b lsls r3, r3, #1
801916a: 4413 add r3, r2
801916c: 00db lsls r3, r3, #3
801916e: 4403 add r3, r0
8019170: 3304 adds r3, #4
8019172: 681b ldr r3, [r3, #0]
(arp_table[i].netif == netif) &&
8019174: 4299 cmp r1, r3
8019176: d10a bne.n 801918e <etharp_output+0x1aa>
/* found an existing, stable entry */
ETHARP_SET_ADDRHINT(netif, i);
8019178: 4a19 ldr r2, [pc, #100] ; (80191e0 <etharp_output+0x1fc>)
801917a: 7dfb ldrb r3, [r7, #23]
801917c: 7013 strb r3, [r2, #0]
return etharp_output_to_arp_index(netif, q, i);
801917e: 7dfb ldrb r3, [r7, #23]
8019180: 461a mov r2, r3
8019182: 68b9 ldr r1, [r7, #8]
8019184: 68f8 ldr r0, [r7, #12]
8019186: f7ff fe93 bl 8018eb0 <etharp_output_to_arp_index>
801918a: 4603 mov r3, r0
801918c: e018 b.n 80191c0 <etharp_output+0x1dc>
for (i = 0; i < ARP_TABLE_SIZE; i++) {
801918e: 7dfb ldrb r3, [r7, #23]
8019190: 3301 adds r3, #1
8019192: 75fb strb r3, [r7, #23]
8019194: 7dfb ldrb r3, [r7, #23]
8019196: 2b09 cmp r3, #9
8019198: d9ca bls.n 8019130 <etharp_output+0x14c>
}
}
/* no stable entry found, use the (slower) query function:
queue on destination Ethernet address belonging to ipaddr */
return etharp_query(netif, dst_addr, q);
801919a: 68ba ldr r2, [r7, #8]
801919c: 69b9 ldr r1, [r7, #24]
801919e: 68f8 ldr r0, [r7, #12]
80191a0: f000 f822 bl 80191e8 <etharp_query>
80191a4: 4603 mov r3, r0
80191a6: e00b b.n 80191c0 <etharp_output+0x1dc>
}
/* continuation for multicast/broadcast destinations */
/* obtain source Ethernet address of the given interface */
/* send packet directly on the link */
return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), dest, ETHTYPE_IP);
80191a8: 68fb ldr r3, [r7, #12]
80191aa: f103 022a add.w r2, r3, #42 ; 0x2a
80191ae: f44f 6300 mov.w r3, #2048 ; 0x800
80191b2: 9300 str r3, [sp, #0]
80191b4: 69fb ldr r3, [r7, #28]
80191b6: 68b9 ldr r1, [r7, #8]
80191b8: 68f8 ldr r0, [r7, #12]
80191ba: f001 fd5d bl 801ac78 <ethernet_output>
80191be: 4603 mov r3, r0
}
80191c0: 4618 mov r0, r3
80191c2: 3720 adds r7, #32
80191c4: 46bd mov sp, r7
80191c6: bd80 pop {r7, pc}
80191c8: 0801e90c .word 0x0801e90c
80191cc: 0801ea5c .word 0x0801ea5c
80191d0: 0801e984 .word 0x0801e984
80191d4: 0801eaac .word 0x0801eaac
80191d8: 0801ea4c .word 0x0801ea4c
80191dc: 08021044 .word 0x08021044
80191e0: 2000885c .word 0x2000885c
80191e4: 2000876c .word 0x2000876c
080191e8 <etharp_query>:
* - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
*
*/
err_t
etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q)
{
80191e8: b580 push {r7, lr}
80191ea: b08c sub sp, #48 ; 0x30
80191ec: af02 add r7, sp, #8
80191ee: 60f8 str r0, [r7, #12]
80191f0: 60b9 str r1, [r7, #8]
80191f2: 607a str r2, [r7, #4]
struct eth_addr *srcaddr = (struct eth_addr *)netif->hwaddr;
80191f4: 68fb ldr r3, [r7, #12]
80191f6: 332a adds r3, #42 ; 0x2a
80191f8: 617b str r3, [r7, #20]
err_t result = ERR_MEM;
80191fa: 23ff movs r3, #255 ; 0xff
80191fc: f887 3027 strb.w r3, [r7, #39] ; 0x27
int is_new_entry = 0;
8019200: 2300 movs r3, #0
8019202: 623b str r3, [r7, #32]
s16_t i_err;
netif_addr_idx_t i;
/* non-unicast address? */
if (ip4_addr_isbroadcast(ipaddr, netif) ||
8019204: 68bb ldr r3, [r7, #8]
8019206: 681b ldr r3, [r3, #0]
8019208: 68f9 ldr r1, [r7, #12]
801920a: 4618 mov r0, r3
801920c: f000 fe2c bl 8019e68 <ip4_addr_isbroadcast_u32>
8019210: 4603 mov r3, r0
8019212: 2b00 cmp r3, #0
8019214: d10c bne.n 8019230 <etharp_query+0x48>
ip4_addr_ismulticast(ipaddr) ||
8019216: 68bb ldr r3, [r7, #8]
8019218: 681b ldr r3, [r3, #0]
801921a: f003 03f0 and.w r3, r3, #240 ; 0xf0
if (ip4_addr_isbroadcast(ipaddr, netif) ||
801921e: 2be0 cmp r3, #224 ; 0xe0
8019220: d006 beq.n 8019230 <etharp_query+0x48>
ip4_addr_ismulticast(ipaddr) ||
8019222: 68bb ldr r3, [r7, #8]
8019224: 2b00 cmp r3, #0
8019226: d003 beq.n 8019230 <etharp_query+0x48>
ip4_addr_isany(ipaddr)) {
8019228: 68bb ldr r3, [r7, #8]
801922a: 681b ldr r3, [r3, #0]
801922c: 2b00 cmp r3, #0
801922e: d102 bne.n 8019236 <etharp_query+0x4e>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
return ERR_ARG;
8019230: f06f 030f mvn.w r3, #15
8019234: e101 b.n 801943a <etharp_query+0x252>
}
/* find entry in ARP cache, ask to create entry if queueing packet */
i_err = etharp_find_entry(ipaddr, ETHARP_FLAG_TRY_HARD, netif);
8019236: 68fa ldr r2, [r7, #12]
8019238: 2101 movs r1, #1
801923a: 68b8 ldr r0, [r7, #8]
801923c: f7ff fb5c bl 80188f8 <etharp_find_entry>
8019240: 4603 mov r3, r0
8019242: 827b strh r3, [r7, #18]
/* could not find or create entry? */
if (i_err < 0) {
8019244: f9b7 3012 ldrsh.w r3, [r7, #18]
8019248: 2b00 cmp r3, #0
801924a: da02 bge.n 8019252 <etharp_query+0x6a>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
if (q) {
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n"));
ETHARP_STATS_INC(etharp.memerr);
}
return (err_t)i_err;
801924c: 8a7b ldrh r3, [r7, #18]
801924e: b25b sxtb r3, r3
8019250: e0f3 b.n 801943a <etharp_query+0x252>
}
LWIP_ASSERT("type overflow", (size_t)i_err < NETIF_ADDR_IDX_MAX);
8019252: 8a7b ldrh r3, [r7, #18]
8019254: 2b7e cmp r3, #126 ; 0x7e
8019256: d906 bls.n 8019266 <etharp_query+0x7e>
8019258: 4b7a ldr r3, [pc, #488] ; (8019444 <etharp_query+0x25c>)
801925a: f240 32c1 movw r2, #961 ; 0x3c1
801925e: 497a ldr r1, [pc, #488] ; (8019448 <etharp_query+0x260>)
8019260: 487a ldr r0, [pc, #488] ; (801944c <etharp_query+0x264>)
8019262: f001 feaf bl 801afc4 <iprintf>
i = (netif_addr_idx_t)i_err;
8019266: 8a7b ldrh r3, [r7, #18]
8019268: 747b strb r3, [r7, #17]
/* mark a fresh entry as pending (we just sent a request) */
if (arp_table[i].state == ETHARP_STATE_EMPTY) {
801926a: 7c7a ldrb r2, [r7, #17]
801926c: 4978 ldr r1, [pc, #480] ; (8019450 <etharp_query+0x268>)
801926e: 4613 mov r3, r2
8019270: 005b lsls r3, r3, #1
8019272: 4413 add r3, r2
8019274: 00db lsls r3, r3, #3
8019276: 440b add r3, r1
8019278: 3314 adds r3, #20
801927a: 781b ldrb r3, [r3, #0]
801927c: 2b00 cmp r3, #0
801927e: d115 bne.n 80192ac <etharp_query+0xc4>
is_new_entry = 1;
8019280: 2301 movs r3, #1
8019282: 623b str r3, [r7, #32]
arp_table[i].state = ETHARP_STATE_PENDING;
8019284: 7c7a ldrb r2, [r7, #17]
8019286: 4972 ldr r1, [pc, #456] ; (8019450 <etharp_query+0x268>)
8019288: 4613 mov r3, r2
801928a: 005b lsls r3, r3, #1
801928c: 4413 add r3, r2
801928e: 00db lsls r3, r3, #3
8019290: 440b add r3, r1
8019292: 3314 adds r3, #20
8019294: 2201 movs r2, #1
8019296: 701a strb r2, [r3, #0]
/* record network interface for re-sending arp request in etharp_tmr */
arp_table[i].netif = netif;
8019298: 7c7a ldrb r2, [r7, #17]
801929a: 496d ldr r1, [pc, #436] ; (8019450 <etharp_query+0x268>)
801929c: 4613 mov r3, r2
801929e: 005b lsls r3, r3, #1
80192a0: 4413 add r3, r2
80192a2: 00db lsls r3, r3, #3
80192a4: 440b add r3, r1
80192a6: 3308 adds r3, #8
80192a8: 68fa ldr r2, [r7, #12]
80192aa: 601a str r2, [r3, #0]
}
/* { i is either a STABLE or (new or existing) PENDING entry } */
LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
80192ac: 7c7a ldrb r2, [r7, #17]
80192ae: 4968 ldr r1, [pc, #416] ; (8019450 <etharp_query+0x268>)
80192b0: 4613 mov r3, r2
80192b2: 005b lsls r3, r3, #1
80192b4: 4413 add r3, r2
80192b6: 00db lsls r3, r3, #3
80192b8: 440b add r3, r1
80192ba: 3314 adds r3, #20
80192bc: 781b ldrb r3, [r3, #0]
80192be: 2b01 cmp r3, #1
80192c0: d011 beq.n 80192e6 <etharp_query+0xfe>
80192c2: 7c7a ldrb r2, [r7, #17]
80192c4: 4962 ldr r1, [pc, #392] ; (8019450 <etharp_query+0x268>)
80192c6: 4613 mov r3, r2
80192c8: 005b lsls r3, r3, #1
80192ca: 4413 add r3, r2
80192cc: 00db lsls r3, r3, #3
80192ce: 440b add r3, r1
80192d0: 3314 adds r3, #20
80192d2: 781b ldrb r3, [r3, #0]
80192d4: 2b01 cmp r3, #1
80192d6: d806 bhi.n 80192e6 <etharp_query+0xfe>
80192d8: 4b5a ldr r3, [pc, #360] ; (8019444 <etharp_query+0x25c>)
80192da: f240 32cd movw r2, #973 ; 0x3cd
80192de: 495d ldr r1, [pc, #372] ; (8019454 <etharp_query+0x26c>)
80192e0: 485a ldr r0, [pc, #360] ; (801944c <etharp_query+0x264>)
80192e2: f001 fe6f bl 801afc4 <iprintf>
((arp_table[i].state == ETHARP_STATE_PENDING) ||
(arp_table[i].state >= ETHARP_STATE_STABLE)));
/* do we have a new entry? or an implicit query request? */
if (is_new_entry || (q == NULL)) {
80192e6: 6a3b ldr r3, [r7, #32]
80192e8: 2b00 cmp r3, #0
80192ea: d102 bne.n 80192f2 <etharp_query+0x10a>
80192ec: 687b ldr r3, [r7, #4]
80192ee: 2b00 cmp r3, #0
80192f0: d10c bne.n 801930c <etharp_query+0x124>
/* try to resolve it; send out ARP request */
result = etharp_request(netif, ipaddr);
80192f2: 68b9 ldr r1, [r7, #8]
80192f4: 68f8 ldr r0, [r7, #12]
80192f6: f000 f963 bl 80195c0 <etharp_request>
80192fa: 4603 mov r3, r0
80192fc: f887 3027 strb.w r3, [r7, #39] ; 0x27
/* ARP request couldn't be sent */
/* We don't re-send arp request in etharp_tmr, but we still queue packets,
since this failure could be temporary, and the next packet calling
etharp_query again could lead to sending the queued packets. */
}
if (q == NULL) {
8019300: 687b ldr r3, [r7, #4]
8019302: 2b00 cmp r3, #0
8019304: d102 bne.n 801930c <etharp_query+0x124>
return result;
8019306: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
801930a: e096 b.n 801943a <etharp_query+0x252>
}
}
/* packet given? */
LWIP_ASSERT("q != NULL", q != NULL);
801930c: 687b ldr r3, [r7, #4]
801930e: 2b00 cmp r3, #0
8019310: d106 bne.n 8019320 <etharp_query+0x138>
8019312: 4b4c ldr r3, [pc, #304] ; (8019444 <etharp_query+0x25c>)
8019314: f240 32e1 movw r2, #993 ; 0x3e1
8019318: 494f ldr r1, [pc, #316] ; (8019458 <etharp_query+0x270>)
801931a: 484c ldr r0, [pc, #304] ; (801944c <etharp_query+0x264>)
801931c: f001 fe52 bl 801afc4 <iprintf>
/* stable entry? */
if (arp_table[i].state >= ETHARP_STATE_STABLE) {
8019320: 7c7a ldrb r2, [r7, #17]
8019322: 494b ldr r1, [pc, #300] ; (8019450 <etharp_query+0x268>)
8019324: 4613 mov r3, r2
8019326: 005b lsls r3, r3, #1
8019328: 4413 add r3, r2
801932a: 00db lsls r3, r3, #3
801932c: 440b add r3, r1
801932e: 3314 adds r3, #20
8019330: 781b ldrb r3, [r3, #0]
8019332: 2b01 cmp r3, #1
8019334: d917 bls.n 8019366 <etharp_query+0x17e>
/* we have a valid IP->Ethernet address mapping */
ETHARP_SET_ADDRHINT(netif, i);
8019336: 4a49 ldr r2, [pc, #292] ; (801945c <etharp_query+0x274>)
8019338: 7c7b ldrb r3, [r7, #17]
801933a: 7013 strb r3, [r2, #0]
/* send the packet */
result = ethernet_output(netif, q, srcaddr, &(arp_table[i].ethaddr), ETHTYPE_IP);
801933c: 7c7a ldrb r2, [r7, #17]
801933e: 4613 mov r3, r2
8019340: 005b lsls r3, r3, #1
8019342: 4413 add r3, r2
8019344: 00db lsls r3, r3, #3
8019346: 3308 adds r3, #8
8019348: 4a41 ldr r2, [pc, #260] ; (8019450 <etharp_query+0x268>)
801934a: 4413 add r3, r2
801934c: 3304 adds r3, #4
801934e: f44f 6200 mov.w r2, #2048 ; 0x800
8019352: 9200 str r2, [sp, #0]
8019354: 697a ldr r2, [r7, #20]
8019356: 6879 ldr r1, [r7, #4]
8019358: 68f8 ldr r0, [r7, #12]
801935a: f001 fc8d bl 801ac78 <ethernet_output>
801935e: 4603 mov r3, r0
8019360: f887 3027 strb.w r3, [r7, #39] ; 0x27
8019364: e067 b.n 8019436 <etharp_query+0x24e>
/* pending entry? (either just created or already pending */
} else if (arp_table[i].state == ETHARP_STATE_PENDING) {
8019366: 7c7a ldrb r2, [r7, #17]
8019368: 4939 ldr r1, [pc, #228] ; (8019450 <etharp_query+0x268>)
801936a: 4613 mov r3, r2
801936c: 005b lsls r3, r3, #1
801936e: 4413 add r3, r2
8019370: 00db lsls r3, r3, #3
8019372: 440b add r3, r1
8019374: 3314 adds r3, #20
8019376: 781b ldrb r3, [r3, #0]
8019378: 2b01 cmp r3, #1
801937a: d15c bne.n 8019436 <etharp_query+0x24e>
/* entry is still pending, queue the given packet 'q' */
struct pbuf *p;
int copy_needed = 0;
801937c: 2300 movs r3, #0
801937e: 61bb str r3, [r7, #24]
/* IF q includes a pbuf that must be copied, copy the whole chain into a
* new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */
p = q;
8019380: 687b ldr r3, [r7, #4]
8019382: 61fb str r3, [r7, #28]
while (p) {
8019384: e01c b.n 80193c0 <etharp_query+0x1d8>
LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0));
8019386: 69fb ldr r3, [r7, #28]
8019388: 895a ldrh r2, [r3, #10]
801938a: 69fb ldr r3, [r7, #28]
801938c: 891b ldrh r3, [r3, #8]
801938e: 429a cmp r2, r3
8019390: d10a bne.n 80193a8 <etharp_query+0x1c0>
8019392: 69fb ldr r3, [r7, #28]
8019394: 681b ldr r3, [r3, #0]
8019396: 2b00 cmp r3, #0
8019398: d006 beq.n 80193a8 <etharp_query+0x1c0>
801939a: 4b2a ldr r3, [pc, #168] ; (8019444 <etharp_query+0x25c>)
801939c: f240 32f1 movw r2, #1009 ; 0x3f1
80193a0: 492f ldr r1, [pc, #188] ; (8019460 <etharp_query+0x278>)
80193a2: 482a ldr r0, [pc, #168] ; (801944c <etharp_query+0x264>)
80193a4: f001 fe0e bl 801afc4 <iprintf>
if (PBUF_NEEDS_COPY(p)) {
80193a8: 69fb ldr r3, [r7, #28]
80193aa: 7b1b ldrb r3, [r3, #12]
80193ac: f003 0340 and.w r3, r3, #64 ; 0x40
80193b0: 2b00 cmp r3, #0
80193b2: d002 beq.n 80193ba <etharp_query+0x1d2>
copy_needed = 1;
80193b4: 2301 movs r3, #1
80193b6: 61bb str r3, [r7, #24]
break;
80193b8: e005 b.n 80193c6 <etharp_query+0x1de>
}
p = p->next;
80193ba: 69fb ldr r3, [r7, #28]
80193bc: 681b ldr r3, [r3, #0]
80193be: 61fb str r3, [r7, #28]
while (p) {
80193c0: 69fb ldr r3, [r7, #28]
80193c2: 2b00 cmp r3, #0
80193c4: d1df bne.n 8019386 <etharp_query+0x19e>
}
if (copy_needed) {
80193c6: 69bb ldr r3, [r7, #24]
80193c8: 2b00 cmp r3, #0
80193ca: d007 beq.n 80193dc <etharp_query+0x1f4>
/* copy the whole packet into new pbufs */
p = pbuf_clone(PBUF_LINK, PBUF_RAM, q);
80193cc: 687a ldr r2, [r7, #4]
80193ce: f44f 7120 mov.w r1, #640 ; 0x280
80193d2: 200e movs r0, #14
80193d4: f7f7 fb62 bl 8010a9c <pbuf_clone>
80193d8: 61f8 str r0, [r7, #28]
80193da: e004 b.n 80193e6 <etharp_query+0x1fe>
} else {
/* referencing the old pbuf is enough */
p = q;
80193dc: 687b ldr r3, [r7, #4]
80193de: 61fb str r3, [r7, #28]
pbuf_ref(p);
80193e0: 69f8 ldr r0, [r7, #28]
80193e2: f7f7 f989 bl 80106f8 <pbuf_ref>
}
/* packet could be taken over? */
if (p != NULL) {
80193e6: 69fb ldr r3, [r7, #28]
80193e8: 2b00 cmp r3, #0
80193ea: d021 beq.n 8019430 <etharp_query+0x248>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
result = ERR_MEM;
}
#else /* ARP_QUEUEING */
/* always queue one packet per ARP request only, freeing a previously queued packet */
if (arp_table[i].q != NULL) {
80193ec: 7c7a ldrb r2, [r7, #17]
80193ee: 4918 ldr r1, [pc, #96] ; (8019450 <etharp_query+0x268>)
80193f0: 4613 mov r3, r2
80193f2: 005b lsls r3, r3, #1
80193f4: 4413 add r3, r2
80193f6: 00db lsls r3, r3, #3
80193f8: 440b add r3, r1
80193fa: 681b ldr r3, [r3, #0]
80193fc: 2b00 cmp r3, #0
80193fe: d00a beq.n 8019416 <etharp_query+0x22e>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
pbuf_free(arp_table[i].q);
8019400: 7c7a ldrb r2, [r7, #17]
8019402: 4913 ldr r1, [pc, #76] ; (8019450 <etharp_query+0x268>)
8019404: 4613 mov r3, r2
8019406: 005b lsls r3, r3, #1
8019408: 4413 add r3, r2
801940a: 00db lsls r3, r3, #3
801940c: 440b add r3, r1
801940e: 681b ldr r3, [r3, #0]
8019410: 4618 mov r0, r3
8019412: f7f7 f8cb bl 80105ac <pbuf_free>
}
arp_table[i].q = p;
8019416: 7c7a ldrb r2, [r7, #17]
8019418: 490d ldr r1, [pc, #52] ; (8019450 <etharp_query+0x268>)
801941a: 4613 mov r3, r2
801941c: 005b lsls r3, r3, #1
801941e: 4413 add r3, r2
8019420: 00db lsls r3, r3, #3
8019422: 440b add r3, r1
8019424: 69fa ldr r2, [r7, #28]
8019426: 601a str r2, [r3, #0]
result = ERR_OK;
8019428: 2300 movs r3, #0
801942a: f887 3027 strb.w r3, [r7, #39] ; 0x27
801942e: e002 b.n 8019436 <etharp_query+0x24e>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
#endif /* ARP_QUEUEING */
} else {
ETHARP_STATS_INC(etharp.memerr);
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
result = ERR_MEM;
8019430: 23ff movs r3, #255 ; 0xff
8019432: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
}
return result;
8019436: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
}
801943a: 4618 mov r0, r3
801943c: 3728 adds r7, #40 ; 0x28
801943e: 46bd mov sp, r7
8019440: bd80 pop {r7, pc}
8019442: bf00 nop
8019444: 0801e90c .word 0x0801e90c
8019448: 0801eab8 .word 0x0801eab8
801944c: 0801e984 .word 0x0801e984
8019450: 2000876c .word 0x2000876c
8019454: 0801eac8 .word 0x0801eac8
8019458: 0801eaac .word 0x0801eaac
801945c: 2000885c .word 0x2000885c
8019460: 0801eaf0 .word 0x0801eaf0
08019464 <etharp_raw>:
etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
const struct eth_addr *ethdst_addr,
const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr,
const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr,
const u16_t opcode)
{
8019464: b580 push {r7, lr}
8019466: b08a sub sp, #40 ; 0x28
8019468: af02 add r7, sp, #8
801946a: 60f8 str r0, [r7, #12]
801946c: 60b9 str r1, [r7, #8]
801946e: 607a str r2, [r7, #4]
8019470: 603b str r3, [r7, #0]
struct pbuf *p;
err_t result = ERR_OK;
8019472: 2300 movs r3, #0
8019474: 77fb strb r3, [r7, #31]
struct etharp_hdr *hdr;
LWIP_ASSERT("netif != NULL", netif != NULL);
8019476: 68fb ldr r3, [r7, #12]
8019478: 2b00 cmp r3, #0
801947a: d106 bne.n 801948a <etharp_raw+0x26>
801947c: 4b3a ldr r3, [pc, #232] ; (8019568 <etharp_raw+0x104>)
801947e: f240 4257 movw r2, #1111 ; 0x457
8019482: 493a ldr r1, [pc, #232] ; (801956c <etharp_raw+0x108>)
8019484: 483a ldr r0, [pc, #232] ; (8019570 <etharp_raw+0x10c>)
8019486: f001 fd9d bl 801afc4 <iprintf>
/* allocate a pbuf for the outgoing ARP request packet */
p = pbuf_alloc(PBUF_LINK, SIZEOF_ETHARP_HDR, PBUF_RAM);
801948a: f44f 7220 mov.w r2, #640 ; 0x280
801948e: 211c movs r1, #28
8019490: 200e movs r0, #14
8019492: f7f6 fda7 bl 800ffe4 <pbuf_alloc>
8019496: 61b8 str r0, [r7, #24]
/* could allocate a pbuf for an ARP request? */
if (p == NULL) {
8019498: 69bb ldr r3, [r7, #24]
801949a: 2b00 cmp r3, #0
801949c: d102 bne.n 80194a4 <etharp_raw+0x40>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("etharp_raw: could not allocate pbuf for ARP request.\n"));
ETHARP_STATS_INC(etharp.memerr);
return ERR_MEM;
801949e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
80194a2: e05d b.n 8019560 <etharp_raw+0xfc>
}
LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr",
80194a4: 69bb ldr r3, [r7, #24]
80194a6: 895b ldrh r3, [r3, #10]
80194a8: 2b1b cmp r3, #27
80194aa: d806 bhi.n 80194ba <etharp_raw+0x56>
80194ac: 4b2e ldr r3, [pc, #184] ; (8019568 <etharp_raw+0x104>)
80194ae: f240 4262 movw r2, #1122 ; 0x462
80194b2: 4930 ldr r1, [pc, #192] ; (8019574 <etharp_raw+0x110>)
80194b4: 482e ldr r0, [pc, #184] ; (8019570 <etharp_raw+0x10c>)
80194b6: f001 fd85 bl 801afc4 <iprintf>
(p->len >= SIZEOF_ETHARP_HDR));
hdr = (struct etharp_hdr *)p->payload;
80194ba: 69bb ldr r3, [r7, #24]
80194bc: 685b ldr r3, [r3, #4]
80194be: 617b str r3, [r7, #20]
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n"));
hdr->opcode = lwip_htons(opcode);
80194c0: 8ebb ldrh r3, [r7, #52] ; 0x34
80194c2: 4618 mov r0, r3
80194c4: f7f5 fcba bl 800ee3c <lwip_htons>
80194c8: 4603 mov r3, r0
80194ca: 461a mov r2, r3
80194cc: 697b ldr r3, [r7, #20]
80194ce: 80da strh r2, [r3, #6]
LWIP_ASSERT("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp!",
80194d0: 68fb ldr r3, [r7, #12]
80194d2: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
80194d6: 2b06 cmp r3, #6
80194d8: d006 beq.n 80194e8 <etharp_raw+0x84>
80194da: 4b23 ldr r3, [pc, #140] ; (8019568 <etharp_raw+0x104>)
80194dc: f240 4269 movw r2, #1129 ; 0x469
80194e0: 4925 ldr r1, [pc, #148] ; (8019578 <etharp_raw+0x114>)
80194e2: 4823 ldr r0, [pc, #140] ; (8019570 <etharp_raw+0x10c>)
80194e4: f001 fd6e bl 801afc4 <iprintf>
(netif->hwaddr_len == ETH_HWADDR_LEN));
/* Write the ARP MAC-Addresses */
SMEMCPY(&hdr->shwaddr, hwsrc_addr, ETH_HWADDR_LEN);
80194e8: 697b ldr r3, [r7, #20]
80194ea: 3308 adds r3, #8
80194ec: 2206 movs r2, #6
80194ee: 6839 ldr r1, [r7, #0]
80194f0: 4618 mov r0, r3
80194f2: f001 fd51 bl 801af98 <memcpy>
SMEMCPY(&hdr->dhwaddr, hwdst_addr, ETH_HWADDR_LEN);
80194f6: 697b ldr r3, [r7, #20]
80194f8: 3312 adds r3, #18
80194fa: 2206 movs r2, #6
80194fc: 6af9 ldr r1, [r7, #44] ; 0x2c
80194fe: 4618 mov r0, r3
8019500: f001 fd4a bl 801af98 <memcpy>
/* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
* structure packing. */
IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->sipaddr, ipsrc_addr);
8019504: 697b ldr r3, [r7, #20]
8019506: 330e adds r3, #14
8019508: 6aba ldr r2, [r7, #40] ; 0x28
801950a: 6812 ldr r2, [r2, #0]
801950c: 601a str r2, [r3, #0]
IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->dipaddr, ipdst_addr);
801950e: 697b ldr r3, [r7, #20]
8019510: 3318 adds r3, #24
8019512: 6b3a ldr r2, [r7, #48] ; 0x30
8019514: 6812 ldr r2, [r2, #0]
8019516: 601a str r2, [r3, #0]
hdr->hwtype = PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET);
8019518: 697b ldr r3, [r7, #20]
801951a: 2200 movs r2, #0
801951c: 701a strb r2, [r3, #0]
801951e: 2200 movs r2, #0
8019520: f042 0201 orr.w r2, r2, #1
8019524: 705a strb r2, [r3, #1]
hdr->proto = PP_HTONS(ETHTYPE_IP);
8019526: 697b ldr r3, [r7, #20]
8019528: 2200 movs r2, #0
801952a: f042 0208 orr.w r2, r2, #8
801952e: 709a strb r2, [r3, #2]
8019530: 2200 movs r2, #0
8019532: 70da strb r2, [r3, #3]
/* set hwlen and protolen */
hdr->hwlen = ETH_HWADDR_LEN;
8019534: 697b ldr r3, [r7, #20]
8019536: 2206 movs r2, #6
8019538: 711a strb r2, [r3, #4]
hdr->protolen = sizeof(ip4_addr_t);
801953a: 697b ldr r3, [r7, #20]
801953c: 2204 movs r2, #4
801953e: 715a strb r2, [r3, #5]
if (ip4_addr_islinklocal(ipsrc_addr)) {
ethernet_output(netif, p, ethsrc_addr, &ethbroadcast, ETHTYPE_ARP);
} else
#endif /* LWIP_AUTOIP */
{
ethernet_output(netif, p, ethsrc_addr, ethdst_addr, ETHTYPE_ARP);
8019540: f640 0306 movw r3, #2054 ; 0x806
8019544: 9300 str r3, [sp, #0]
8019546: 687b ldr r3, [r7, #4]
8019548: 68ba ldr r2, [r7, #8]
801954a: 69b9 ldr r1, [r7, #24]
801954c: 68f8 ldr r0, [r7, #12]
801954e: f001 fb93 bl 801ac78 <ethernet_output>
}
ETHARP_STATS_INC(etharp.xmit);
/* free ARP query packet */
pbuf_free(p);
8019552: 69b8 ldr r0, [r7, #24]
8019554: f7f7 f82a bl 80105ac <pbuf_free>
p = NULL;
8019558: 2300 movs r3, #0
801955a: 61bb str r3, [r7, #24]
/* could not allocate pbuf for ARP request */
return result;
801955c: f997 301f ldrsb.w r3, [r7, #31]
}
8019560: 4618 mov r0, r3
8019562: 3720 adds r7, #32
8019564: 46bd mov sp, r7
8019566: bd80 pop {r7, pc}
8019568: 0801e90c .word 0x0801e90c
801956c: 0801ea5c .word 0x0801ea5c
8019570: 0801e984 .word 0x0801e984
8019574: 0801eb0c .word 0x0801eb0c
8019578: 0801eb40 .word 0x0801eb40
0801957c <etharp_request_dst>:
* ERR_MEM if the ARP packet couldn't be allocated
* any other err_t on failure
*/
static err_t
etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr)
{
801957c: b580 push {r7, lr}
801957e: b088 sub sp, #32
8019580: af04 add r7, sp, #16
8019582: 60f8 str r0, [r7, #12]
8019584: 60b9 str r1, [r7, #8]
8019586: 607a str r2, [r7, #4]
return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
8019588: 68fb ldr r3, [r7, #12]
801958a: f103 012a add.w r1, r3, #42 ; 0x2a
(struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), &ethzero,
801958e: 68fb ldr r3, [r7, #12]
8019590: f103 002a add.w r0, r3, #42 ; 0x2a
8019594: 68fb ldr r3, [r7, #12]
8019596: 3304 adds r3, #4
return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
8019598: 2201 movs r2, #1
801959a: 9203 str r2, [sp, #12]
801959c: 68ba ldr r2, [r7, #8]
801959e: 9202 str r2, [sp, #8]
80195a0: 4a06 ldr r2, [pc, #24] ; (80195bc <etharp_request_dst+0x40>)
80195a2: 9201 str r2, [sp, #4]
80195a4: 9300 str r3, [sp, #0]
80195a6: 4603 mov r3, r0
80195a8: 687a ldr r2, [r7, #4]
80195aa: 68f8 ldr r0, [r7, #12]
80195ac: f7ff ff5a bl 8019464 <etharp_raw>
80195b0: 4603 mov r3, r0
ipaddr, ARP_REQUEST);
}
80195b2: 4618 mov r0, r3
80195b4: 3710 adds r7, #16
80195b6: 46bd mov sp, r7
80195b8: bd80 pop {r7, pc}
80195ba: bf00 nop
80195bc: 0802104c .word 0x0802104c
080195c0 <etharp_request>:
* ERR_MEM if the ARP packet couldn't be allocated
* any other err_t on failure
*/
err_t
etharp_request(struct netif *netif, const ip4_addr_t *ipaddr)
{
80195c0: b580 push {r7, lr}
80195c2: b082 sub sp, #8
80195c4: af00 add r7, sp, #0
80195c6: 6078 str r0, [r7, #4]
80195c8: 6039 str r1, [r7, #0]
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n"));
return etharp_request_dst(netif, ipaddr, &ethbroadcast);
80195ca: 4a05 ldr r2, [pc, #20] ; (80195e0 <etharp_request+0x20>)
80195cc: 6839 ldr r1, [r7, #0]
80195ce: 6878 ldr r0, [r7, #4]
80195d0: f7ff ffd4 bl 801957c <etharp_request_dst>
80195d4: 4603 mov r3, r0
}
80195d6: 4618 mov r0, r3
80195d8: 3708 adds r7, #8
80195da: 46bd mov sp, r7
80195dc: bd80 pop {r7, pc}
80195de: bf00 nop
80195e0: 08021044 .word 0x08021044
080195e4 <icmp_input>:
* @param p the icmp echo request packet, p->payload pointing to the icmp header
* @param inp the netif on which this packet was received
*/
void
icmp_input(struct pbuf *p, struct netif *inp)
{
80195e4: b580 push {r7, lr}
80195e6: b08e sub sp, #56 ; 0x38
80195e8: af04 add r7, sp, #16
80195ea: 6078 str r0, [r7, #4]
80195ec: 6039 str r1, [r7, #0]
const ip4_addr_t *src;
ICMP_STATS_INC(icmp.recv);
MIB2_STATS_INC(mib2.icmpinmsgs);
iphdr_in = ip4_current_header();
80195ee: 4b79 ldr r3, [pc, #484] ; (80197d4 <icmp_input+0x1f0>)
80195f0: 689b ldr r3, [r3, #8]
80195f2: 627b str r3, [r7, #36] ; 0x24
hlen = IPH_HL_BYTES(iphdr_in);
80195f4: 6a7b ldr r3, [r7, #36] ; 0x24
80195f6: 781b ldrb r3, [r3, #0]
80195f8: f003 030f and.w r3, r3, #15
80195fc: b2db uxtb r3, r3
80195fe: 009b lsls r3, r3, #2
8019600: b2db uxtb r3, r3
8019602: 847b strh r3, [r7, #34] ; 0x22
if (hlen < IP_HLEN) {
8019604: 8c7b ldrh r3, [r7, #34] ; 0x22
8019606: 2b13 cmp r3, #19
8019608: f240 80cd bls.w 80197a6 <icmp_input+0x1c2>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short IP header (%"S16_F" bytes) received\n", hlen));
goto lenerr;
}
if (p->len < sizeof(u16_t) * 2) {
801960c: 687b ldr r3, [r7, #4]
801960e: 895b ldrh r3, [r3, #10]
8019610: 2b03 cmp r3, #3
8019612: f240 80ca bls.w 80197aa <icmp_input+0x1c6>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
goto lenerr;
}
type = *((u8_t *)p->payload);
8019616: 687b ldr r3, [r7, #4]
8019618: 685b ldr r3, [r3, #4]
801961a: 781b ldrb r3, [r3, #0]
801961c: f887 3021 strb.w r3, [r7, #33] ; 0x21
#ifdef LWIP_DEBUG
code = *(((u8_t *)p->payload) + 1);
/* if debug is enabled but debug statement below is somehow disabled: */
LWIP_UNUSED_ARG(code);
#endif /* LWIP_DEBUG */
switch (type) {
8019620: f897 3021 ldrb.w r3, [r7, #33] ; 0x21
8019624: 2b00 cmp r3, #0
8019626: f000 80b7 beq.w 8019798 <icmp_input+0x1b4>
801962a: 2b08 cmp r3, #8
801962c: f040 80b7 bne.w 801979e <icmp_input+0x1ba>
(as obviously, an echo request has been sent, too). */
MIB2_STATS_INC(mib2.icmpinechoreps);
break;
case ICMP_ECHO:
MIB2_STATS_INC(mib2.icmpinechos);
src = ip4_current_dest_addr();
8019630: 4b69 ldr r3, [pc, #420] ; (80197d8 <icmp_input+0x1f4>)
8019632: 61fb str r3, [r7, #28]
/* multicast destination address? */
if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
8019634: 4b67 ldr r3, [pc, #412] ; (80197d4 <icmp_input+0x1f0>)
8019636: 695b ldr r3, [r3, #20]
8019638: f003 03f0 and.w r3, r3, #240 ; 0xf0
801963c: 2be0 cmp r3, #224 ; 0xe0
801963e: f000 80bb beq.w 80197b8 <icmp_input+0x1d4>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast pings\n"));
goto icmperr;
#endif /* LWIP_MULTICAST_PING */
}
/* broadcast destination address? */
if (ip4_addr_isbroadcast(ip4_current_dest_addr(), ip_current_netif())) {
8019642: 4b64 ldr r3, [pc, #400] ; (80197d4 <icmp_input+0x1f0>)
8019644: 695b ldr r3, [r3, #20]
8019646: 4a63 ldr r2, [pc, #396] ; (80197d4 <icmp_input+0x1f0>)
8019648: 6812 ldr r2, [r2, #0]
801964a: 4611 mov r1, r2
801964c: 4618 mov r0, r3
801964e: f000 fc0b bl 8019e68 <ip4_addr_isbroadcast_u32>
8019652: 4603 mov r3, r0
8019654: 2b00 cmp r3, #0
8019656: f040 80b1 bne.w 80197bc <icmp_input+0x1d8>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to broadcast pings\n"));
goto icmperr;
#endif /* LWIP_BROADCAST_PING */
}
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
801965a: 687b ldr r3, [r7, #4]
801965c: 891b ldrh r3, [r3, #8]
801965e: 2b07 cmp r3, #7
8019660: f240 80a5 bls.w 80197ae <icmp_input+0x1ca>
return;
}
}
#endif
#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
if (pbuf_add_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
8019664: 8c7b ldrh r3, [r7, #34] ; 0x22
8019666: 330e adds r3, #14
8019668: 4619 mov r1, r3
801966a: 6878 ldr r0, [r7, #4]
801966c: f7f6 ff08 bl 8010480 <pbuf_add_header>
8019670: 4603 mov r3, r0
8019672: 2b00 cmp r3, #0
8019674: d04b beq.n 801970e <icmp_input+0x12a>
/* p is not big enough to contain link headers
* allocate a new one and copy p into it
*/
struct pbuf *r;
u16_t alloc_len = (u16_t)(p->tot_len + hlen);
8019676: 687b ldr r3, [r7, #4]
8019678: 891a ldrh r2, [r3, #8]
801967a: 8c7b ldrh r3, [r7, #34] ; 0x22
801967c: 4413 add r3, r2
801967e: 837b strh r3, [r7, #26]
if (alloc_len < p->tot_len) {
8019680: 687b ldr r3, [r7, #4]
8019682: 891b ldrh r3, [r3, #8]
8019684: 8b7a ldrh r2, [r7, #26]
8019686: 429a cmp r2, r3
8019688: f0c0 809a bcc.w 80197c0 <icmp_input+0x1dc>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed (tot_len overflow)\n"));
goto icmperr;
}
/* allocate new packet buffer with space for link headers */
r = pbuf_alloc(PBUF_LINK, alloc_len, PBUF_RAM);
801968c: 8b7b ldrh r3, [r7, #26]
801968e: f44f 7220 mov.w r2, #640 ; 0x280
8019692: 4619 mov r1, r3
8019694: 200e movs r0, #14
8019696: f7f6 fca5 bl 800ffe4 <pbuf_alloc>
801969a: 6178 str r0, [r7, #20]
if (r == NULL) {
801969c: 697b ldr r3, [r7, #20]
801969e: 2b00 cmp r3, #0
80196a0: f000 8090 beq.w 80197c4 <icmp_input+0x1e0>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n"));
goto icmperr;
}
if (r->len < hlen + sizeof(struct icmp_echo_hdr)) {
80196a4: 697b ldr r3, [r7, #20]
80196a6: 895b ldrh r3, [r3, #10]
80196a8: 461a mov r2, r3
80196aa: 8c7b ldrh r3, [r7, #34] ; 0x22
80196ac: 3308 adds r3, #8
80196ae: 429a cmp r2, r3
80196b0: d203 bcs.n 80196ba <icmp_input+0xd6>
LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("first pbuf cannot hold the ICMP header"));
pbuf_free(r);
80196b2: 6978 ldr r0, [r7, #20]
80196b4: f7f6 ff7a bl 80105ac <pbuf_free>
goto icmperr;
80196b8: e085 b.n 80197c6 <icmp_input+0x1e2>
}
/* copy the ip header */
MEMCPY(r->payload, iphdr_in, hlen);
80196ba: 697b ldr r3, [r7, #20]
80196bc: 685b ldr r3, [r3, #4]
80196be: 8c7a ldrh r2, [r7, #34] ; 0x22
80196c0: 6a79 ldr r1, [r7, #36] ; 0x24
80196c2: 4618 mov r0, r3
80196c4: f001 fc68 bl 801af98 <memcpy>
/* switch r->payload back to icmp header (cannot fail) */
if (pbuf_remove_header(r, hlen)) {
80196c8: 8c7b ldrh r3, [r7, #34] ; 0x22
80196ca: 4619 mov r1, r3
80196cc: 6978 ldr r0, [r7, #20]
80196ce: f7f6 fee7 bl 80104a0 <pbuf_remove_header>
80196d2: 4603 mov r3, r0
80196d4: 2b00 cmp r3, #0
80196d6: d009 beq.n 80196ec <icmp_input+0x108>
LWIP_ASSERT("icmp_input: moving r->payload to icmp header failed\n", 0);
80196d8: 4b40 ldr r3, [pc, #256] ; (80197dc <icmp_input+0x1f8>)
80196da: 22b6 movs r2, #182 ; 0xb6
80196dc: 4940 ldr r1, [pc, #256] ; (80197e0 <icmp_input+0x1fc>)
80196de: 4841 ldr r0, [pc, #260] ; (80197e4 <icmp_input+0x200>)
80196e0: f001 fc70 bl 801afc4 <iprintf>
pbuf_free(r);
80196e4: 6978 ldr r0, [r7, #20]
80196e6: f7f6 ff61 bl 80105ac <pbuf_free>
goto icmperr;
80196ea: e06c b.n 80197c6 <icmp_input+0x1e2>
}
/* copy the rest of the packet without ip header */
if (pbuf_copy(r, p) != ERR_OK) {
80196ec: 6879 ldr r1, [r7, #4]
80196ee: 6978 ldr r0, [r7, #20]
80196f0: f7f7 f890 bl 8010814 <pbuf_copy>
80196f4: 4603 mov r3, r0
80196f6: 2b00 cmp r3, #0
80196f8: d003 beq.n 8019702 <icmp_input+0x11e>
LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("icmp_input: copying to new pbuf failed"));
pbuf_free(r);
80196fa: 6978 ldr r0, [r7, #20]
80196fc: f7f6 ff56 bl 80105ac <pbuf_free>
goto icmperr;
8019700: e061 b.n 80197c6 <icmp_input+0x1e2>
}
/* free the original p */
pbuf_free(p);
8019702: 6878 ldr r0, [r7, #4]
8019704: f7f6 ff52 bl 80105ac <pbuf_free>
/* we now have an identical copy of p that has room for link headers */
p = r;
8019708: 697b ldr r3, [r7, #20]
801970a: 607b str r3, [r7, #4]
801970c: e00f b.n 801972e <icmp_input+0x14a>
} else {
/* restore p->payload to point to icmp header (cannot fail) */
if (pbuf_remove_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
801970e: 8c7b ldrh r3, [r7, #34] ; 0x22
8019710: 330e adds r3, #14
8019712: 4619 mov r1, r3
8019714: 6878 ldr r0, [r7, #4]
8019716: f7f6 fec3 bl 80104a0 <pbuf_remove_header>
801971a: 4603 mov r3, r0
801971c: 2b00 cmp r3, #0
801971e: d006 beq.n 801972e <icmp_input+0x14a>
LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
8019720: 4b2e ldr r3, [pc, #184] ; (80197dc <icmp_input+0x1f8>)
8019722: 22c7 movs r2, #199 ; 0xc7
8019724: 4930 ldr r1, [pc, #192] ; (80197e8 <icmp_input+0x204>)
8019726: 482f ldr r0, [pc, #188] ; (80197e4 <icmp_input+0x200>)
8019728: f001 fc4c bl 801afc4 <iprintf>
goto icmperr;
801972c: e04b b.n 80197c6 <icmp_input+0x1e2>
}
#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
/* At this point, all checks are OK. */
/* We generate an answer by switching the dest and src ip addresses,
* setting the icmp type to ECHO_RESPONSE and updating the checksum. */
iecho = (struct icmp_echo_hdr *)p->payload;
801972e: 687b ldr r3, [r7, #4]
8019730: 685b ldr r3, [r3, #4]
8019732: 613b str r3, [r7, #16]
if (pbuf_add_header(p, hlen)) {
8019734: 8c7b ldrh r3, [r7, #34] ; 0x22
8019736: 4619 mov r1, r3
8019738: 6878 ldr r0, [r7, #4]
801973a: f7f6 fea1 bl 8010480 <pbuf_add_header>
801973e: 4603 mov r3, r0
8019740: 2b00 cmp r3, #0
8019742: d12b bne.n 801979c <icmp_input+0x1b8>
LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Can't move over header in packet"));
} else {
err_t ret;
struct ip_hdr *iphdr = (struct ip_hdr *)p->payload;
8019744: 687b ldr r3, [r7, #4]
8019746: 685b ldr r3, [r3, #4]
8019748: 60fb str r3, [r7, #12]
ip4_addr_copy(iphdr->src, *src);
801974a: 69fb ldr r3, [r7, #28]
801974c: 681a ldr r2, [r3, #0]
801974e: 68fb ldr r3, [r7, #12]
8019750: 60da str r2, [r3, #12]
ip4_addr_copy(iphdr->dest, *ip4_current_src_addr());
8019752: 4b20 ldr r3, [pc, #128] ; (80197d4 <icmp_input+0x1f0>)
8019754: 691a ldr r2, [r3, #16]
8019756: 68fb ldr r3, [r7, #12]
8019758: 611a str r2, [r3, #16]
ICMPH_TYPE_SET(iecho, ICMP_ER);
801975a: 693b ldr r3, [r7, #16]
801975c: 2200 movs r2, #0
801975e: 701a strb r2, [r3, #0]
else {
iecho->chksum = 0;
}
#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
#else /* CHECKSUM_GEN_ICMP */
iecho->chksum = 0;
8019760: 693b ldr r3, [r7, #16]
8019762: 2200 movs r2, #0
8019764: 709a strb r2, [r3, #2]
8019766: 2200 movs r2, #0
8019768: 70da strb r2, [r3, #3]
#endif /* CHECKSUM_GEN_ICMP */
/* Set the correct TTL and recalculate the header checksum. */
IPH_TTL_SET(iphdr, ICMP_TTL);
801976a: 68fb ldr r3, [r7, #12]
801976c: 22ff movs r2, #255 ; 0xff
801976e: 721a strb r2, [r3, #8]
IPH_CHKSUM_SET(iphdr, 0);
8019770: 68fb ldr r3, [r7, #12]
8019772: 2200 movs r2, #0
8019774: 729a strb r2, [r3, #10]
8019776: 2200 movs r2, #0
8019778: 72da strb r2, [r3, #11]
MIB2_STATS_INC(mib2.icmpoutmsgs);
/* increase number of echo replies attempted to send */
MIB2_STATS_INC(mib2.icmpoutechoreps);
/* send an ICMP packet */
ret = ip4_output_if(p, src, LWIP_IP_HDRINCL,
801977a: 683b ldr r3, [r7, #0]
801977c: 9302 str r3, [sp, #8]
801977e: 2301 movs r3, #1
8019780: 9301 str r3, [sp, #4]
8019782: 2300 movs r3, #0
8019784: 9300 str r3, [sp, #0]
8019786: 23ff movs r3, #255 ; 0xff
8019788: 2200 movs r2, #0
801978a: 69f9 ldr r1, [r7, #28]
801978c: 6878 ldr r0, [r7, #4]
801978e: f000 fa93 bl 8019cb8 <ip4_output_if>
8019792: 4603 mov r3, r0
8019794: 72fb strb r3, [r7, #11]
ICMP_TTL, 0, IP_PROTO_ICMP, inp);
if (ret != ERR_OK) {
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret)));
}
}
break;
8019796: e001 b.n 801979c <icmp_input+0x1b8>
break;
8019798: bf00 nop
801979a: e000 b.n 801979e <icmp_input+0x1ba>
break;
801979c: bf00 nop
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n",
(s16_t)type, (s16_t)code));
ICMP_STATS_INC(icmp.proterr);
ICMP_STATS_INC(icmp.drop);
}
pbuf_free(p);
801979e: 6878 ldr r0, [r7, #4]
80197a0: f7f6 ff04 bl 80105ac <pbuf_free>
return;
80197a4: e013 b.n 80197ce <icmp_input+0x1ea>
goto lenerr;
80197a6: bf00 nop
80197a8: e002 b.n 80197b0 <icmp_input+0x1cc>
goto lenerr;
80197aa: bf00 nop
80197ac: e000 b.n 80197b0 <icmp_input+0x1cc>
goto lenerr;
80197ae: bf00 nop
lenerr:
pbuf_free(p);
80197b0: 6878 ldr r0, [r7, #4]
80197b2: f7f6 fefb bl 80105ac <pbuf_free>
ICMP_STATS_INC(icmp.lenerr);
MIB2_STATS_INC(mib2.icmpinerrors);
return;
80197b6: e00a b.n 80197ce <icmp_input+0x1ea>
goto icmperr;
80197b8: bf00 nop
80197ba: e004 b.n 80197c6 <icmp_input+0x1e2>
goto icmperr;
80197bc: bf00 nop
80197be: e002 b.n 80197c6 <icmp_input+0x1e2>
goto icmperr;
80197c0: bf00 nop
80197c2: e000 b.n 80197c6 <icmp_input+0x1e2>
goto icmperr;
80197c4: bf00 nop
#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING
icmperr:
pbuf_free(p);
80197c6: 6878 ldr r0, [r7, #4]
80197c8: f7f6 fef0 bl 80105ac <pbuf_free>
ICMP_STATS_INC(icmp.err);
MIB2_STATS_INC(mib2.icmpinerrors);
return;
80197cc: bf00 nop
#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */
}
80197ce: 3728 adds r7, #40 ; 0x28
80197d0: 46bd mov sp, r7
80197d2: bd80 pop {r7, pc}
80197d4: 2000c108 .word 0x2000c108
80197d8: 2000c11c .word 0x2000c11c
80197dc: 0801eb84 .word 0x0801eb84
80197e0: 0801ebbc .word 0x0801ebbc
80197e4: 0801ebf4 .word 0x0801ebf4
80197e8: 0801ec1c .word 0x0801ec1c
080197ec <icmp_dest_unreach>:
* p->payload pointing to the IP header
* @param t type of the 'unreachable' packet
*/
void
icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
{
80197ec: b580 push {r7, lr}
80197ee: b082 sub sp, #8
80197f0: af00 add r7, sp, #0
80197f2: 6078 str r0, [r7, #4]
80197f4: 460b mov r3, r1
80197f6: 70fb strb r3, [r7, #3]
MIB2_STATS_INC(mib2.icmpoutdestunreachs);
icmp_send_response(p, ICMP_DUR, t);
80197f8: 78fb ldrb r3, [r7, #3]
80197fa: 461a mov r2, r3
80197fc: 2103 movs r1, #3
80197fe: 6878 ldr r0, [r7, #4]
8019800: f000 f814 bl 801982c <icmp_send_response>
}
8019804: bf00 nop
8019806: 3708 adds r7, #8
8019808: 46bd mov sp, r7
801980a: bd80 pop {r7, pc}
0801980c <icmp_time_exceeded>:
* p->payload pointing to the IP header
* @param t type of the 'time exceeded' packet
*/
void
icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
{
801980c: b580 push {r7, lr}
801980e: b082 sub sp, #8
8019810: af00 add r7, sp, #0
8019812: 6078 str r0, [r7, #4]
8019814: 460b mov r3, r1
8019816: 70fb strb r3, [r7, #3]
MIB2_STATS_INC(mib2.icmpouttimeexcds);
icmp_send_response(p, ICMP_TE, t);
8019818: 78fb ldrb r3, [r7, #3]
801981a: 461a mov r2, r3
801981c: 210b movs r1, #11
801981e: 6878 ldr r0, [r7, #4]
8019820: f000 f804 bl 801982c <icmp_send_response>
}
8019824: bf00 nop
8019826: 3708 adds r7, #8
8019828: 46bd mov sp, r7
801982a: bd80 pop {r7, pc}
0801982c <icmp_send_response>:
* @param type Type of the ICMP header
* @param code Code of the ICMP header
*/
static void
icmp_send_response(struct pbuf *p, u8_t type, u8_t code)
{
801982c: b580 push {r7, lr}
801982e: b08c sub sp, #48 ; 0x30
8019830: af04 add r7, sp, #16
8019832: 6078 str r0, [r7, #4]
8019834: 460b mov r3, r1
8019836: 70fb strb r3, [r7, #3]
8019838: 4613 mov r3, r2
801983a: 70bb strb r3, [r7, #2]
/* increase number of messages attempted to send */
MIB2_STATS_INC(mib2.icmpoutmsgs);
/* ICMP header + IP header + 8 bytes of data */
q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE,
801983c: f44f 7220 mov.w r2, #640 ; 0x280
8019840: 2124 movs r1, #36 ; 0x24
8019842: 2022 movs r0, #34 ; 0x22
8019844: f7f6 fbce bl 800ffe4 <pbuf_alloc>
8019848: 61f8 str r0, [r7, #28]
PBUF_RAM);
if (q == NULL) {
801984a: 69fb ldr r3, [r7, #28]
801984c: 2b00 cmp r3, #0
801984e: d04c beq.n 80198ea <icmp_send_response+0xbe>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n"));
MIB2_STATS_INC(mib2.icmpouterrors);
return;
}
LWIP_ASSERT("check that first pbuf can hold icmp message",
8019850: 69fb ldr r3, [r7, #28]
8019852: 895b ldrh r3, [r3, #10]
8019854: 2b23 cmp r3, #35 ; 0x23
8019856: d806 bhi.n 8019866 <icmp_send_response+0x3a>
8019858: 4b26 ldr r3, [pc, #152] ; (80198f4 <icmp_send_response+0xc8>)
801985a: f44f 72b4 mov.w r2, #360 ; 0x168
801985e: 4926 ldr r1, [pc, #152] ; (80198f8 <icmp_send_response+0xcc>)
8019860: 4826 ldr r0, [pc, #152] ; (80198fc <icmp_send_response+0xd0>)
8019862: f001 fbaf bl 801afc4 <iprintf>
(q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE)));
iphdr = (struct ip_hdr *)p->payload;
8019866: 687b ldr r3, [r7, #4]
8019868: 685b ldr r3, [r3, #4]
801986a: 61bb str r3, [r7, #24]
ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->src);
LWIP_DEBUGF(ICMP_DEBUG, (" to "));
ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->dest);
LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
icmphdr = (struct icmp_echo_hdr *)q->payload;
801986c: 69fb ldr r3, [r7, #28]
801986e: 685b ldr r3, [r3, #4]
8019870: 617b str r3, [r7, #20]
icmphdr->type = type;
8019872: 697b ldr r3, [r7, #20]
8019874: 78fa ldrb r2, [r7, #3]
8019876: 701a strb r2, [r3, #0]
icmphdr->code = code;
8019878: 697b ldr r3, [r7, #20]
801987a: 78ba ldrb r2, [r7, #2]
801987c: 705a strb r2, [r3, #1]
icmphdr->id = 0;
801987e: 697b ldr r3, [r7, #20]
8019880: 2200 movs r2, #0
8019882: 711a strb r2, [r3, #4]
8019884: 2200 movs r2, #0
8019886: 715a strb r2, [r3, #5]
icmphdr->seqno = 0;
8019888: 697b ldr r3, [r7, #20]
801988a: 2200 movs r2, #0
801988c: 719a strb r2, [r3, #6]
801988e: 2200 movs r2, #0
8019890: 71da strb r2, [r3, #7]
/* copy fields from original packet */
SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload,
8019892: 69fb ldr r3, [r7, #28]
8019894: 685b ldr r3, [r3, #4]
8019896: f103 0008 add.w r0, r3, #8
801989a: 687b ldr r3, [r7, #4]
801989c: 685b ldr r3, [r3, #4]
801989e: 221c movs r2, #28
80198a0: 4619 mov r1, r3
80198a2: f001 fb79 bl 801af98 <memcpy>
IP_HLEN + ICMP_DEST_UNREACH_DATASIZE);
ip4_addr_copy(iphdr_src, iphdr->src);
80198a6: 69bb ldr r3, [r7, #24]
80198a8: 68db ldr r3, [r3, #12]
80198aa: 60fb str r3, [r7, #12]
ip4_addr_t iphdr_dst;
ip4_addr_copy(iphdr_dst, iphdr->dest);
netif = ip4_route_src(&iphdr_dst, &iphdr_src);
}
#else
netif = ip4_route(&iphdr_src);
80198ac: f107 030c add.w r3, r7, #12
80198b0: 4618 mov r0, r3
80198b2: f000 f825 bl 8019900 <ip4_route>
80198b6: 6138 str r0, [r7, #16]
#endif
if (netif != NULL) {
80198b8: 693b ldr r3, [r7, #16]
80198ba: 2b00 cmp r3, #0
80198bc: d011 beq.n 80198e2 <icmp_send_response+0xb6>
/* calculate checksum */
icmphdr->chksum = 0;
80198be: 697b ldr r3, [r7, #20]
80198c0: 2200 movs r2, #0
80198c2: 709a strb r2, [r3, #2]
80198c4: 2200 movs r2, #0
80198c6: 70da strb r2, [r3, #3]
IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP) {
icmphdr->chksum = inet_chksum(icmphdr, q->len);
}
#endif
ICMP_STATS_INC(icmp.xmit);
ip4_output_if(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP, netif);
80198c8: f107 020c add.w r2, r7, #12
80198cc: 693b ldr r3, [r7, #16]
80198ce: 9302 str r3, [sp, #8]
80198d0: 2301 movs r3, #1
80198d2: 9301 str r3, [sp, #4]
80198d4: 2300 movs r3, #0
80198d6: 9300 str r3, [sp, #0]
80198d8: 23ff movs r3, #255 ; 0xff
80198da: 2100 movs r1, #0
80198dc: 69f8 ldr r0, [r7, #28]
80198de: f000 f9eb bl 8019cb8 <ip4_output_if>
}
pbuf_free(q);
80198e2: 69f8 ldr r0, [r7, #28]
80198e4: f7f6 fe62 bl 80105ac <pbuf_free>
80198e8: e000 b.n 80198ec <icmp_send_response+0xc0>
return;
80198ea: bf00 nop
}
80198ec: 3720 adds r7, #32
80198ee: 46bd mov sp, r7
80198f0: bd80 pop {r7, pc}
80198f2: bf00 nop
80198f4: 0801eb84 .word 0x0801eb84
80198f8: 0801ec50 .word 0x0801ec50
80198fc: 0801ebf4 .word 0x0801ebf4
08019900 <ip4_route>:
* @param dest the destination IP address for which to find the route
* @return the netif on which to send to reach dest
*/
struct netif *
ip4_route(const ip4_addr_t *dest)
{
8019900: b480 push {r7}
8019902: b085 sub sp, #20
8019904: af00 add r7, sp, #0
8019906: 6078 str r0, [r7, #4]
/* bug #54569: in case LWIP_SINGLE_NETIF=1 and LWIP_DEBUGF() disabled, the following loop is optimized away */
LWIP_UNUSED_ARG(dest);
/* iterate through netifs */
NETIF_FOREACH(netif) {
8019908: 4b33 ldr r3, [pc, #204] ; (80199d8 <ip4_route+0xd8>)
801990a: 681b ldr r3, [r3, #0]
801990c: 60fb str r3, [r7, #12]
801990e: e036 b.n 801997e <ip4_route+0x7e>
/* is the netif up, does it have a link and a valid address? */
if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) {
8019910: 68fb ldr r3, [r7, #12]
8019912: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019916: f003 0301 and.w r3, r3, #1
801991a: b2db uxtb r3, r3
801991c: 2b00 cmp r3, #0
801991e: d02b beq.n 8019978 <ip4_route+0x78>
8019920: 68fb ldr r3, [r7, #12]
8019922: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019926: 089b lsrs r3, r3, #2
8019928: f003 0301 and.w r3, r3, #1
801992c: b2db uxtb r3, r3
801992e: 2b00 cmp r3, #0
8019930: d022 beq.n 8019978 <ip4_route+0x78>
8019932: 68fb ldr r3, [r7, #12]
8019934: 3304 adds r3, #4
8019936: 681b ldr r3, [r3, #0]
8019938: 2b00 cmp r3, #0
801993a: d01d beq.n 8019978 <ip4_route+0x78>
/* network mask matches? */
if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) {
801993c: 687b ldr r3, [r7, #4]
801993e: 681a ldr r2, [r3, #0]
8019940: 68fb ldr r3, [r7, #12]
8019942: 3304 adds r3, #4
8019944: 681b ldr r3, [r3, #0]
8019946: 405a eors r2, r3
8019948: 68fb ldr r3, [r7, #12]
801994a: 3308 adds r3, #8
801994c: 681b ldr r3, [r3, #0]
801994e: 4013 ands r3, r2
8019950: 2b00 cmp r3, #0
8019952: d101 bne.n 8019958 <ip4_route+0x58>
/* return netif on which to forward IP packet */
return netif;
8019954: 68fb ldr r3, [r7, #12]
8019956: e038 b.n 80199ca <ip4_route+0xca>
}
/* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */
if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) {
8019958: 68fb ldr r3, [r7, #12]
801995a: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
801995e: f003 0302 and.w r3, r3, #2
8019962: 2b00 cmp r3, #0
8019964: d108 bne.n 8019978 <ip4_route+0x78>
8019966: 687b ldr r3, [r7, #4]
8019968: 681a ldr r2, [r3, #0]
801996a: 68fb ldr r3, [r7, #12]
801996c: 330c adds r3, #12
801996e: 681b ldr r3, [r3, #0]
8019970: 429a cmp r2, r3
8019972: d101 bne.n 8019978 <ip4_route+0x78>
/* return netif on which to forward IP packet */
return netif;
8019974: 68fb ldr r3, [r7, #12]
8019976: e028 b.n 80199ca <ip4_route+0xca>
NETIF_FOREACH(netif) {
8019978: 68fb ldr r3, [r7, #12]
801997a: 681b ldr r3, [r3, #0]
801997c: 60fb str r3, [r7, #12]
801997e: 68fb ldr r3, [r7, #12]
8019980: 2b00 cmp r3, #0
8019982: d1c5 bne.n 8019910 <ip4_route+0x10>
return netif;
}
#endif
#endif /* !LWIP_SINGLE_NETIF */
if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
8019984: 4b15 ldr r3, [pc, #84] ; (80199dc <ip4_route+0xdc>)
8019986: 681b ldr r3, [r3, #0]
8019988: 2b00 cmp r3, #0
801998a: d01a beq.n 80199c2 <ip4_route+0xc2>
801998c: 4b13 ldr r3, [pc, #76] ; (80199dc <ip4_route+0xdc>)
801998e: 681b ldr r3, [r3, #0]
8019990: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019994: f003 0301 and.w r3, r3, #1
8019998: 2b00 cmp r3, #0
801999a: d012 beq.n 80199c2 <ip4_route+0xc2>
801999c: 4b0f ldr r3, [pc, #60] ; (80199dc <ip4_route+0xdc>)
801999e: 681b ldr r3, [r3, #0]
80199a0: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
80199a4: f003 0304 and.w r3, r3, #4
80199a8: 2b00 cmp r3, #0
80199aa: d00a beq.n 80199c2 <ip4_route+0xc2>
ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
80199ac: 4b0b ldr r3, [pc, #44] ; (80199dc <ip4_route+0xdc>)
80199ae: 681b ldr r3, [r3, #0]
80199b0: 3304 adds r3, #4
80199b2: 681b ldr r3, [r3, #0]
if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
80199b4: 2b00 cmp r3, #0
80199b6: d004 beq.n 80199c2 <ip4_route+0xc2>
ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
80199b8: 687b ldr r3, [r7, #4]
80199ba: 681b ldr r3, [r3, #0]
80199bc: b2db uxtb r3, r3
80199be: 2b7f cmp r3, #127 ; 0x7f
80199c0: d101 bne.n 80199c6 <ip4_route+0xc6>
If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
IP_STATS_INC(ip.rterr);
MIB2_STATS_INC(mib2.ipoutnoroutes);
return NULL;
80199c2: 2300 movs r3, #0
80199c4: e001 b.n 80199ca <ip4_route+0xca>
}
return netif_default;
80199c6: 4b05 ldr r3, [pc, #20] ; (80199dc <ip4_route+0xdc>)
80199c8: 681b ldr r3, [r3, #0]
}
80199ca: 4618 mov r0, r3
80199cc: 3714 adds r7, #20
80199ce: 46bd mov sp, r7
80199d0: f85d 7b04 ldr.w r7, [sp], #4
80199d4: 4770 bx lr
80199d6: bf00 nop
80199d8: 2000f82c .word 0x2000f82c
80199dc: 2000f830 .word 0x2000f830
080199e0 <ip4_input_accept>:
#endif /* IP_FORWARD */
/** Return true if the current input packet should be accepted on this netif */
static int
ip4_input_accept(struct netif *netif)
{
80199e0: b580 push {r7, lr}
80199e2: b082 sub sp, #8
80199e4: af00 add r7, sp, #0
80199e6: 6078 str r0, [r7, #4]
ip4_addr_get_u32(ip4_current_dest_addr()) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
ip4_addr_get_u32(ip4_current_dest_addr()) & ~ip4_addr_get_u32(netif_ip4_netmask(netif))));
/* interface is up and configured? */
if ((netif_is_up(netif)) && (!ip4_addr_isany_val(*netif_ip4_addr(netif)))) {
80199e8: 687b ldr r3, [r7, #4]
80199ea: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
80199ee: f003 0301 and.w r3, r3, #1
80199f2: b2db uxtb r3, r3
80199f4: 2b00 cmp r3, #0
80199f6: d016 beq.n 8019a26 <ip4_input_accept+0x46>
80199f8: 687b ldr r3, [r7, #4]
80199fa: 3304 adds r3, #4
80199fc: 681b ldr r3, [r3, #0]
80199fe: 2b00 cmp r3, #0
8019a00: d011 beq.n 8019a26 <ip4_input_accept+0x46>
/* unicast to this interface address? */
if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
8019a02: 4b0b ldr r3, [pc, #44] ; (8019a30 <ip4_input_accept+0x50>)
8019a04: 695a ldr r2, [r3, #20]
8019a06: 687b ldr r3, [r7, #4]
8019a08: 3304 adds r3, #4
8019a0a: 681b ldr r3, [r3, #0]
8019a0c: 429a cmp r2, r3
8019a0e: d008 beq.n 8019a22 <ip4_input_accept+0x42>
/* or broadcast on this interface network address? */
ip4_addr_isbroadcast(ip4_current_dest_addr(), netif)
8019a10: 4b07 ldr r3, [pc, #28] ; (8019a30 <ip4_input_accept+0x50>)
8019a12: 695b ldr r3, [r3, #20]
8019a14: 6879 ldr r1, [r7, #4]
8019a16: 4618 mov r0, r3
8019a18: f000 fa26 bl 8019e68 <ip4_addr_isbroadcast_u32>
8019a1c: 4603 mov r3, r0
if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
8019a1e: 2b00 cmp r3, #0
8019a20: d001 beq.n 8019a26 <ip4_input_accept+0x46>
#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */
) {
LWIP_DEBUGF(IP_DEBUG, ("ip4_input: packet accepted on interface %c%c\n",
netif->name[0], netif->name[1]));
/* accept on this netif */
return 1;
8019a22: 2301 movs r3, #1
8019a24: e000 b.n 8019a28 <ip4_input_accept+0x48>
/* accept on this netif */
return 1;
}
#endif /* LWIP_AUTOIP */
}
return 0;
8019a26: 2300 movs r3, #0
}
8019a28: 4618 mov r0, r3
8019a2a: 3708 adds r7, #8
8019a2c: 46bd mov sp, r7
8019a2e: bd80 pop {r7, pc}
8019a30: 2000c108 .word 0x2000c108
08019a34 <ip4_input>:
* @return ERR_OK if the packet was processed (could return ERR_* if it wasn't
* processed, but currently always returns ERR_OK)
*/
err_t
ip4_input(struct pbuf *p, struct netif *inp)
{
8019a34: b580 push {r7, lr}
8019a36: b088 sub sp, #32
8019a38: af00 add r7, sp, #0
8019a3a: 6078 str r0, [r7, #4]
8019a3c: 6039 str r1, [r7, #0]
const struct ip_hdr *iphdr;
struct netif *netif;
u16_t iphdr_hlen;
u16_t iphdr_len;
#if IP_ACCEPT_LINK_LAYER_ADDRESSING || LWIP_IGMP
int check_ip_src = 1;
8019a3e: 2301 movs r3, #1
8019a40: 617b str r3, [r7, #20]
IP_STATS_INC(ip.recv);
MIB2_STATS_INC(mib2.ipinreceives);
/* identify the IP header */
iphdr = (struct ip_hdr *)p->payload;
8019a42: 687b ldr r3, [r7, #4]
8019a44: 685b ldr r3, [r3, #4]
8019a46: 61fb str r3, [r7, #28]
if (IPH_V(iphdr) != 4) {
8019a48: 69fb ldr r3, [r7, #28]
8019a4a: 781b ldrb r3, [r3, #0]
8019a4c: 091b lsrs r3, r3, #4
8019a4e: b2db uxtb r3, r3
8019a50: 2b04 cmp r3, #4
8019a52: d004 beq.n 8019a5e <ip4_input+0x2a>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", (u16_t)IPH_V(iphdr)));
ip4_debug_print(p);
pbuf_free(p);
8019a54: 6878 ldr r0, [r7, #4]
8019a56: f7f6 fda9 bl 80105ac <pbuf_free>
IP_STATS_INC(ip.err);
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipinhdrerrors);
return ERR_OK;
8019a5a: 2300 movs r3, #0
8019a5c: e123 b.n 8019ca6 <ip4_input+0x272>
return ERR_OK;
}
#endif
/* obtain IP header length in bytes */
iphdr_hlen = IPH_HL_BYTES(iphdr);
8019a5e: 69fb ldr r3, [r7, #28]
8019a60: 781b ldrb r3, [r3, #0]
8019a62: f003 030f and.w r3, r3, #15
8019a66: b2db uxtb r3, r3
8019a68: 009b lsls r3, r3, #2
8019a6a: b2db uxtb r3, r3
8019a6c: 827b strh r3, [r7, #18]
/* obtain ip length in bytes */
iphdr_len = lwip_ntohs(IPH_LEN(iphdr));
8019a6e: 69fb ldr r3, [r7, #28]
8019a70: 885b ldrh r3, [r3, #2]
8019a72: b29b uxth r3, r3
8019a74: 4618 mov r0, r3
8019a76: f7f5 f9e1 bl 800ee3c <lwip_htons>
8019a7a: 4603 mov r3, r0
8019a7c: 823b strh r3, [r7, #16]
/* Trim pbuf. This is especially required for packets < 60 bytes. */
if (iphdr_len < p->tot_len) {
8019a7e: 687b ldr r3, [r7, #4]
8019a80: 891b ldrh r3, [r3, #8]
8019a82: 8a3a ldrh r2, [r7, #16]
8019a84: 429a cmp r2, r3
8019a86: d204 bcs.n 8019a92 <ip4_input+0x5e>
pbuf_realloc(p, iphdr_len);
8019a88: 8a3b ldrh r3, [r7, #16]
8019a8a: 4619 mov r1, r3
8019a8c: 6878 ldr r0, [r7, #4]
8019a8e: f7f6 fc07 bl 80102a0 <pbuf_realloc>
}
/* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */
if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len) || (iphdr_hlen < IP_HLEN)) {
8019a92: 687b ldr r3, [r7, #4]
8019a94: 895b ldrh r3, [r3, #10]
8019a96: 8a7a ldrh r2, [r7, #18]
8019a98: 429a cmp r2, r3
8019a9a: d807 bhi.n 8019aac <ip4_input+0x78>
8019a9c: 687b ldr r3, [r7, #4]
8019a9e: 891b ldrh r3, [r3, #8]
8019aa0: 8a3a ldrh r2, [r7, #16]
8019aa2: 429a cmp r2, r3
8019aa4: d802 bhi.n 8019aac <ip4_input+0x78>
8019aa6: 8a7b ldrh r3, [r7, #18]
8019aa8: 2b13 cmp r3, #19
8019aaa: d804 bhi.n 8019ab6 <ip4_input+0x82>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n",
iphdr_len, p->tot_len));
}
/* free (drop) packet pbufs */
pbuf_free(p);
8019aac: 6878 ldr r0, [r7, #4]
8019aae: f7f6 fd7d bl 80105ac <pbuf_free>
IP_STATS_INC(ip.lenerr);
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipindiscards);
return ERR_OK;
8019ab2: 2300 movs r3, #0
8019ab4: e0f7 b.n 8019ca6 <ip4_input+0x272>
}
}
#endif
/* copy IP addresses to aligned ip_addr_t */
ip_addr_copy_from_ip4(ip_data.current_iphdr_dest, iphdr->dest);
8019ab6: 69fb ldr r3, [r7, #28]
8019ab8: 691b ldr r3, [r3, #16]
8019aba: 4a7d ldr r2, [pc, #500] ; (8019cb0 <ip4_input+0x27c>)
8019abc: 6153 str r3, [r2, #20]
ip_addr_copy_from_ip4(ip_data.current_iphdr_src, iphdr->src);
8019abe: 69fb ldr r3, [r7, #28]
8019ac0: 68db ldr r3, [r3, #12]
8019ac2: 4a7b ldr r2, [pc, #492] ; (8019cb0 <ip4_input+0x27c>)
8019ac4: 6113 str r3, [r2, #16]
/* match packet against an interface, i.e. is this packet for us? */
if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
8019ac6: 4b7a ldr r3, [pc, #488] ; (8019cb0 <ip4_input+0x27c>)
8019ac8: 695b ldr r3, [r3, #20]
8019aca: f003 03f0 and.w r3, r3, #240 ; 0xf0
8019ace: 2be0 cmp r3, #224 ; 0xe0
8019ad0: d112 bne.n 8019af8 <ip4_input+0xc4>
netif = inp;
} else {
netif = NULL;
}
#else /* LWIP_IGMP */
if ((netif_is_up(inp)) && (!ip4_addr_isany_val(*netif_ip4_addr(inp)))) {
8019ad2: 683b ldr r3, [r7, #0]
8019ad4: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019ad8: f003 0301 and.w r3, r3, #1
8019adc: b2db uxtb r3, r3
8019ade: 2b00 cmp r3, #0
8019ae0: d007 beq.n 8019af2 <ip4_input+0xbe>
8019ae2: 683b ldr r3, [r7, #0]
8019ae4: 3304 adds r3, #4
8019ae6: 681b ldr r3, [r3, #0]
8019ae8: 2b00 cmp r3, #0
8019aea: d002 beq.n 8019af2 <ip4_input+0xbe>
netif = inp;
8019aec: 683b ldr r3, [r7, #0]
8019aee: 61bb str r3, [r7, #24]
8019af0: e02a b.n 8019b48 <ip4_input+0x114>
} else {
netif = NULL;
8019af2: 2300 movs r3, #0
8019af4: 61bb str r3, [r7, #24]
8019af6: e027 b.n 8019b48 <ip4_input+0x114>
}
#endif /* LWIP_IGMP */
} else {
/* start trying with inp. if that's not acceptable, start walking the
list of configured netifs. */
if (ip4_input_accept(inp)) {
8019af8: 6838 ldr r0, [r7, #0]
8019afa: f7ff ff71 bl 80199e0 <ip4_input_accept>
8019afe: 4603 mov r3, r0
8019b00: 2b00 cmp r3, #0
8019b02: d002 beq.n 8019b0a <ip4_input+0xd6>
netif = inp;
8019b04: 683b ldr r3, [r7, #0]
8019b06: 61bb str r3, [r7, #24]
8019b08: e01e b.n 8019b48 <ip4_input+0x114>
} else {
netif = NULL;
8019b0a: 2300 movs r3, #0
8019b0c: 61bb str r3, [r7, #24]
#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF
/* Packets sent to the loopback address must not be accepted on an
* interface that does not have the loopback address assigned to it,
* unless a non-loopback interface is used for loopback traffic. */
if (!ip4_addr_isloopback(ip4_current_dest_addr()))
8019b0e: 4b68 ldr r3, [pc, #416] ; (8019cb0 <ip4_input+0x27c>)
8019b10: 695b ldr r3, [r3, #20]
8019b12: b2db uxtb r3, r3
8019b14: 2b7f cmp r3, #127 ; 0x7f
8019b16: d017 beq.n 8019b48 <ip4_input+0x114>
#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */
{
#if !LWIP_SINGLE_NETIF
NETIF_FOREACH(netif) {
8019b18: 4b66 ldr r3, [pc, #408] ; (8019cb4 <ip4_input+0x280>)
8019b1a: 681b ldr r3, [r3, #0]
8019b1c: 61bb str r3, [r7, #24]
8019b1e: e00e b.n 8019b3e <ip4_input+0x10a>
if (netif == inp) {
8019b20: 69ba ldr r2, [r7, #24]
8019b22: 683b ldr r3, [r7, #0]
8019b24: 429a cmp r2, r3
8019b26: d006 beq.n 8019b36 <ip4_input+0x102>
/* we checked that before already */
continue;
}
if (ip4_input_accept(netif)) {
8019b28: 69b8 ldr r0, [r7, #24]
8019b2a: f7ff ff59 bl 80199e0 <ip4_input_accept>
8019b2e: 4603 mov r3, r0
8019b30: 2b00 cmp r3, #0
8019b32: d108 bne.n 8019b46 <ip4_input+0x112>
8019b34: e000 b.n 8019b38 <ip4_input+0x104>
continue;
8019b36: bf00 nop
NETIF_FOREACH(netif) {
8019b38: 69bb ldr r3, [r7, #24]
8019b3a: 681b ldr r3, [r3, #0]
8019b3c: 61bb str r3, [r7, #24]
8019b3e: 69bb ldr r3, [r7, #24]
8019b40: 2b00 cmp r3, #0
8019b42: d1ed bne.n 8019b20 <ip4_input+0xec>
8019b44: e000 b.n 8019b48 <ip4_input+0x114>
break;
8019b46: bf00 nop
* If you want to accept private broadcast communication while a netif is down,
* define LWIP_IP_ACCEPT_UDP_PORT(dst_port), e.g.:
*
* #define LWIP_IP_ACCEPT_UDP_PORT(dst_port) ((dst_port) == PP_NTOHS(12345))
*/
if (netif == NULL) {
8019b48: 69bb ldr r3, [r7, #24]
8019b4a: 2b00 cmp r3, #0
8019b4c: d111 bne.n 8019b72 <ip4_input+0x13e>
/* remote port is DHCP server? */
if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
8019b4e: 69fb ldr r3, [r7, #28]
8019b50: 7a5b ldrb r3, [r3, #9]
8019b52: 2b11 cmp r3, #17
8019b54: d10d bne.n 8019b72 <ip4_input+0x13e>
const struct udp_hdr *udphdr = (const struct udp_hdr *)((const u8_t *)iphdr + iphdr_hlen);
8019b56: 8a7b ldrh r3, [r7, #18]
8019b58: 69fa ldr r2, [r7, #28]
8019b5a: 4413 add r3, r2
8019b5c: 60fb str r3, [r7, #12]
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: UDP packet to DHCP client port %"U16_F"\n",
lwip_ntohs(udphdr->dest)));
if (IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(udphdr->dest)) {
8019b5e: 68fb ldr r3, [r7, #12]
8019b60: 885b ldrh r3, [r3, #2]
8019b62: b29b uxth r3, r3
8019b64: f5b3 4f88 cmp.w r3, #17408 ; 0x4400
8019b68: d103 bne.n 8019b72 <ip4_input+0x13e>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: DHCP packet accepted.\n"));
netif = inp;
8019b6a: 683b ldr r3, [r7, #0]
8019b6c: 61bb str r3, [r7, #24]
check_ip_src = 0;
8019b6e: 2300 movs r3, #0
8019b70: 617b str r3, [r7, #20]
}
#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
/* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */
#if LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING
if (check_ip_src
8019b72: 697b ldr r3, [r7, #20]
8019b74: 2b00 cmp r3, #0
8019b76: d017 beq.n 8019ba8 <ip4_input+0x174>
#if IP_ACCEPT_LINK_LAYER_ADDRESSING
/* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */
&& !ip4_addr_isany_val(*ip4_current_src_addr())
8019b78: 4b4d ldr r3, [pc, #308] ; (8019cb0 <ip4_input+0x27c>)
8019b7a: 691b ldr r3, [r3, #16]
8019b7c: 2b00 cmp r3, #0
8019b7e: d013 beq.n 8019ba8 <ip4_input+0x174>
#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
)
#endif /* LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING */
{
if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
8019b80: 4b4b ldr r3, [pc, #300] ; (8019cb0 <ip4_input+0x27c>)
8019b82: 691b ldr r3, [r3, #16]
8019b84: 6839 ldr r1, [r7, #0]
8019b86: 4618 mov r0, r3
8019b88: f000 f96e bl 8019e68 <ip4_addr_isbroadcast_u32>
8019b8c: 4603 mov r3, r0
8019b8e: 2b00 cmp r3, #0
8019b90: d105 bne.n 8019b9e <ip4_input+0x16a>
(ip4_addr_ismulticast(ip4_current_src_addr()))) {
8019b92: 4b47 ldr r3, [pc, #284] ; (8019cb0 <ip4_input+0x27c>)
8019b94: 691b ldr r3, [r3, #16]
8019b96: f003 03f0 and.w r3, r3, #240 ; 0xf0
if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
8019b9a: 2be0 cmp r3, #224 ; 0xe0
8019b9c: d104 bne.n 8019ba8 <ip4_input+0x174>
/* packet source is not valid */
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip4_input: packet source is not valid.\n"));
/* free (drop) packet pbufs */
pbuf_free(p);
8019b9e: 6878 ldr r0, [r7, #4]
8019ba0: f7f6 fd04 bl 80105ac <pbuf_free>
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipinaddrerrors);
MIB2_STATS_INC(mib2.ipindiscards);
return ERR_OK;
8019ba4: 2300 movs r3, #0
8019ba6: e07e b.n 8019ca6 <ip4_input+0x272>
}
}
/* packet not for us? */
if (netif == NULL) {
8019ba8: 69bb ldr r3, [r7, #24]
8019baa: 2b00 cmp r3, #0
8019bac: d104 bne.n 8019bb8 <ip4_input+0x184>
{
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipinaddrerrors);
MIB2_STATS_INC(mib2.ipindiscards);
}
pbuf_free(p);
8019bae: 6878 ldr r0, [r7, #4]
8019bb0: f7f6 fcfc bl 80105ac <pbuf_free>
return ERR_OK;
8019bb4: 2300 movs r3, #0
8019bb6: e076 b.n 8019ca6 <ip4_input+0x272>
}
/* packet consists of multiple fragments? */
if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) {
8019bb8: 69fb ldr r3, [r7, #28]
8019bba: 88db ldrh r3, [r3, #6]
8019bbc: b29b uxth r3, r3
8019bbe: 461a mov r2, r3
8019bc0: f64f 733f movw r3, #65343 ; 0xff3f
8019bc4: 4013 ands r3, r2
8019bc6: 2b00 cmp r3, #0
8019bc8: d00b beq.n 8019be2 <ip4_input+0x1ae>
#if IP_REASSEMBLY /* packet fragment reassembly code present? */
LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip4_reass()\n",
lwip_ntohs(IPH_ID(iphdr)), p->tot_len, lwip_ntohs(IPH_LEN(iphdr)), (u16_t)!!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (u16_t)((lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK) * 8)));
/* reassemble the packet*/
p = ip4_reass(p);
8019bca: 6878 ldr r0, [r7, #4]
8019bcc: f000 fc92 bl 801a4f4 <ip4_reass>
8019bd0: 6078 str r0, [r7, #4]
/* packet not fully reassembled yet? */
if (p == NULL) {
8019bd2: 687b ldr r3, [r7, #4]
8019bd4: 2b00 cmp r3, #0
8019bd6: d101 bne.n 8019bdc <ip4_input+0x1a8>
return ERR_OK;
8019bd8: 2300 movs r3, #0
8019bda: e064 b.n 8019ca6 <ip4_input+0x272>
}
iphdr = (const struct ip_hdr *)p->payload;
8019bdc: 687b ldr r3, [r7, #4]
8019bde: 685b ldr r3, [r3, #4]
8019be0: 61fb str r3, [r7, #28]
/* send to upper layers */
LWIP_DEBUGF(IP_DEBUG, ("ip4_input: \n"));
ip4_debug_print(p);
LWIP_DEBUGF(IP_DEBUG, ("ip4_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
ip_data.current_netif = netif;
8019be2: 4a33 ldr r2, [pc, #204] ; (8019cb0 <ip4_input+0x27c>)
8019be4: 69bb ldr r3, [r7, #24]
8019be6: 6013 str r3, [r2, #0]
ip_data.current_input_netif = inp;
8019be8: 4a31 ldr r2, [pc, #196] ; (8019cb0 <ip4_input+0x27c>)
8019bea: 683b ldr r3, [r7, #0]
8019bec: 6053 str r3, [r2, #4]
ip_data.current_ip4_header = iphdr;
8019bee: 4a30 ldr r2, [pc, #192] ; (8019cb0 <ip4_input+0x27c>)
8019bf0: 69fb ldr r3, [r7, #28]
8019bf2: 6093 str r3, [r2, #8]
ip_data.current_ip_header_tot_len = IPH_HL_BYTES(iphdr);
8019bf4: 69fb ldr r3, [r7, #28]
8019bf6: 781b ldrb r3, [r3, #0]
8019bf8: f003 030f and.w r3, r3, #15
8019bfc: b2db uxtb r3, r3
8019bfe: 009b lsls r3, r3, #2
8019c00: b2db uxtb r3, r3
8019c02: b29a uxth r2, r3
8019c04: 4b2a ldr r3, [pc, #168] ; (8019cb0 <ip4_input+0x27c>)
8019c06: 819a strh r2, [r3, #12]
/* raw input did not eat the packet? */
raw_status = raw_input(p, inp);
if (raw_status != RAW_INPUT_EATEN)
#endif /* LWIP_RAW */
{
pbuf_remove_header(p, iphdr_hlen); /* Move to payload, no check necessary. */
8019c08: 8a7b ldrh r3, [r7, #18]
8019c0a: 4619 mov r1, r3
8019c0c: 6878 ldr r0, [r7, #4]
8019c0e: f7f6 fc47 bl 80104a0 <pbuf_remove_header>
switch (IPH_PROTO(iphdr)) {
8019c12: 69fb ldr r3, [r7, #28]
8019c14: 7a5b ldrb r3, [r3, #9]
8019c16: 2b11 cmp r3, #17
8019c18: d006 beq.n 8019c28 <ip4_input+0x1f4>
8019c1a: 2b11 cmp r3, #17
8019c1c: dc13 bgt.n 8019c46 <ip4_input+0x212>
8019c1e: 2b01 cmp r3, #1
8019c20: d00c beq.n 8019c3c <ip4_input+0x208>
8019c22: 2b06 cmp r3, #6
8019c24: d005 beq.n 8019c32 <ip4_input+0x1fe>
8019c26: e00e b.n 8019c46 <ip4_input+0x212>
case IP_PROTO_UDP:
#if LWIP_UDPLITE
case IP_PROTO_UDPLITE:
#endif /* LWIP_UDPLITE */
MIB2_STATS_INC(mib2.ipindelivers);
udp_input(p, inp);
8019c28: 6839 ldr r1, [r7, #0]
8019c2a: 6878 ldr r0, [r7, #4]
8019c2c: f7fc fae8 bl 8016200 <udp_input>
break;
8019c30: e026 b.n 8019c80 <ip4_input+0x24c>
#endif /* LWIP_UDP */
#if LWIP_TCP
case IP_PROTO_TCP:
MIB2_STATS_INC(mib2.ipindelivers);
tcp_input(p, inp);
8019c32: 6839 ldr r1, [r7, #0]
8019c34: 6878 ldr r0, [r7, #4]
8019c36: f7f8 fafd bl 8012234 <tcp_input>
break;
8019c3a: e021 b.n 8019c80 <ip4_input+0x24c>
#endif /* LWIP_TCP */
#if LWIP_ICMP
case IP_PROTO_ICMP:
MIB2_STATS_INC(mib2.ipindelivers);
icmp_input(p, inp);
8019c3c: 6839 ldr r1, [r7, #0]
8019c3e: 6878 ldr r0, [r7, #4]
8019c40: f7ff fcd0 bl 80195e4 <icmp_input>
break;
8019c44: e01c b.n 8019c80 <ip4_input+0x24c>
} else
#endif /* LWIP_RAW */
{
#if LWIP_ICMP
/* send ICMP destination protocol unreachable unless is was a broadcast */
if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
8019c46: 4b1a ldr r3, [pc, #104] ; (8019cb0 <ip4_input+0x27c>)
8019c48: 695b ldr r3, [r3, #20]
8019c4a: 69b9 ldr r1, [r7, #24]
8019c4c: 4618 mov r0, r3
8019c4e: f000 f90b bl 8019e68 <ip4_addr_isbroadcast_u32>
8019c52: 4603 mov r3, r0
8019c54: 2b00 cmp r3, #0
8019c56: d10f bne.n 8019c78 <ip4_input+0x244>
!ip4_addr_ismulticast(ip4_current_dest_addr())) {
8019c58: 4b15 ldr r3, [pc, #84] ; (8019cb0 <ip4_input+0x27c>)
8019c5a: 695b ldr r3, [r3, #20]
8019c5c: f003 03f0 and.w r3, r3, #240 ; 0xf0
if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
8019c60: 2be0 cmp r3, #224 ; 0xe0
8019c62: d009 beq.n 8019c78 <ip4_input+0x244>
pbuf_header_force(p, (s16_t)iphdr_hlen); /* Move to ip header, no check necessary. */
8019c64: f9b7 3012 ldrsh.w r3, [r7, #18]
8019c68: 4619 mov r1, r3
8019c6a: 6878 ldr r0, [r7, #4]
8019c6c: f7f6 fc8b bl 8010586 <pbuf_header_force>
icmp_dest_unreach(p, ICMP_DUR_PROTO);
8019c70: 2102 movs r1, #2
8019c72: 6878 ldr r0, [r7, #4]
8019c74: f7ff fdba bl 80197ec <icmp_dest_unreach>
IP_STATS_INC(ip.proterr);
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipinunknownprotos);
}
pbuf_free(p);
8019c78: 6878 ldr r0, [r7, #4]
8019c7a: f7f6 fc97 bl 80105ac <pbuf_free>
break;
8019c7e: bf00 nop
}
}
/* @todo: this is not really necessary... */
ip_data.current_netif = NULL;
8019c80: 4b0b ldr r3, [pc, #44] ; (8019cb0 <ip4_input+0x27c>)
8019c82: 2200 movs r2, #0
8019c84: 601a str r2, [r3, #0]
ip_data.current_input_netif = NULL;
8019c86: 4b0a ldr r3, [pc, #40] ; (8019cb0 <ip4_input+0x27c>)
8019c88: 2200 movs r2, #0
8019c8a: 605a str r2, [r3, #4]
ip_data.current_ip4_header = NULL;
8019c8c: 4b08 ldr r3, [pc, #32] ; (8019cb0 <ip4_input+0x27c>)
8019c8e: 2200 movs r2, #0
8019c90: 609a str r2, [r3, #8]
ip_data.current_ip_header_tot_len = 0;
8019c92: 4b07 ldr r3, [pc, #28] ; (8019cb0 <ip4_input+0x27c>)
8019c94: 2200 movs r2, #0
8019c96: 819a strh r2, [r3, #12]
ip4_addr_set_any(ip4_current_src_addr());
8019c98: 4b05 ldr r3, [pc, #20] ; (8019cb0 <ip4_input+0x27c>)
8019c9a: 2200 movs r2, #0
8019c9c: 611a str r2, [r3, #16]
ip4_addr_set_any(ip4_current_dest_addr());
8019c9e: 4b04 ldr r3, [pc, #16] ; (8019cb0 <ip4_input+0x27c>)
8019ca0: 2200 movs r2, #0
8019ca2: 615a str r2, [r3, #20]
return ERR_OK;
8019ca4: 2300 movs r3, #0
}
8019ca6: 4618 mov r0, r3
8019ca8: 3720 adds r7, #32
8019caa: 46bd mov sp, r7
8019cac: bd80 pop {r7, pc}
8019cae: bf00 nop
8019cb0: 2000c108 .word 0x2000c108
8019cb4: 2000f82c .word 0x2000f82c
08019cb8 <ip4_output_if>:
*/
err_t
ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
u8_t ttl, u8_t tos,
u8_t proto, struct netif *netif)
{
8019cb8: b580 push {r7, lr}
8019cba: b08a sub sp, #40 ; 0x28
8019cbc: af04 add r7, sp, #16
8019cbe: 60f8 str r0, [r7, #12]
8019cc0: 60b9 str r1, [r7, #8]
8019cc2: 607a str r2, [r7, #4]
8019cc4: 70fb strb r3, [r7, #3]
ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
u16_t optlen)
{
#endif /* IP_OPTIONS_SEND */
const ip4_addr_t *src_used = src;
8019cc6: 68bb ldr r3, [r7, #8]
8019cc8: 617b str r3, [r7, #20]
if (dest != LWIP_IP_HDRINCL) {
8019cca: 687b ldr r3, [r7, #4]
8019ccc: 2b00 cmp r3, #0
8019cce: d009 beq.n 8019ce4 <ip4_output_if+0x2c>
if (ip4_addr_isany(src)) {
8019cd0: 68bb ldr r3, [r7, #8]
8019cd2: 2b00 cmp r3, #0
8019cd4: d003 beq.n 8019cde <ip4_output_if+0x26>
8019cd6: 68bb ldr r3, [r7, #8]
8019cd8: 681b ldr r3, [r3, #0]
8019cda: 2b00 cmp r3, #0
8019cdc: d102 bne.n 8019ce4 <ip4_output_if+0x2c>
src_used = netif_ip4_addr(netif);
8019cde: 6abb ldr r3, [r7, #40] ; 0x28
8019ce0: 3304 adds r3, #4
8019ce2: 617b str r3, [r7, #20]
#if IP_OPTIONS_SEND
return ip4_output_if_opt_src(p, src_used, dest, ttl, tos, proto, netif,
ip_options, optlen);
#else /* IP_OPTIONS_SEND */
return ip4_output_if_src(p, src_used, dest, ttl, tos, proto, netif);
8019ce4: 78fa ldrb r2, [r7, #3]
8019ce6: 6abb ldr r3, [r7, #40] ; 0x28
8019ce8: 9302 str r3, [sp, #8]
8019cea: f897 3024 ldrb.w r3, [r7, #36] ; 0x24
8019cee: 9301 str r3, [sp, #4]
8019cf0: f897 3020 ldrb.w r3, [r7, #32]
8019cf4: 9300 str r3, [sp, #0]
8019cf6: 4613 mov r3, r2
8019cf8: 687a ldr r2, [r7, #4]
8019cfa: 6979 ldr r1, [r7, #20]
8019cfc: 68f8 ldr r0, [r7, #12]
8019cfe: f000 f805 bl 8019d0c <ip4_output_if_src>
8019d02: 4603 mov r3, r0
#endif /* IP_OPTIONS_SEND */
}
8019d04: 4618 mov r0, r3
8019d06: 3718 adds r7, #24
8019d08: 46bd mov sp, r7
8019d0a: bd80 pop {r7, pc}
08019d0c <ip4_output_if_src>:
*/
err_t
ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
u8_t ttl, u8_t tos,
u8_t proto, struct netif *netif)
{
8019d0c: b580 push {r7, lr}
8019d0e: b088 sub sp, #32
8019d10: af00 add r7, sp, #0
8019d12: 60f8 str r0, [r7, #12]
8019d14: 60b9 str r1, [r7, #8]
8019d16: 607a str r2, [r7, #4]
8019d18: 70fb strb r3, [r7, #3]
#if CHECKSUM_GEN_IP_INLINE
u32_t chk_sum = 0;
#endif /* CHECKSUM_GEN_IP_INLINE */
LWIP_ASSERT_CORE_LOCKED();
LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p);
8019d1a: 68fb ldr r3, [r7, #12]
8019d1c: 7b9b ldrb r3, [r3, #14]
8019d1e: 2b01 cmp r3, #1
8019d20: d006 beq.n 8019d30 <ip4_output_if_src+0x24>
8019d22: 4b4b ldr r3, [pc, #300] ; (8019e50 <ip4_output_if_src+0x144>)
8019d24: f44f 7255 mov.w r2, #852 ; 0x354
8019d28: 494a ldr r1, [pc, #296] ; (8019e54 <ip4_output_if_src+0x148>)
8019d2a: 484b ldr r0, [pc, #300] ; (8019e58 <ip4_output_if_src+0x14c>)
8019d2c: f001 f94a bl 801afc4 <iprintf>
MIB2_STATS_INC(mib2.ipoutrequests);
/* Should the IP header be generated or is it already included in p? */
if (dest != LWIP_IP_HDRINCL) {
8019d30: 687b ldr r3, [r7, #4]
8019d32: 2b00 cmp r3, #0
8019d34: d060 beq.n 8019df8 <ip4_output_if_src+0xec>
u16_t ip_hlen = IP_HLEN;
8019d36: 2314 movs r3, #20
8019d38: 837b strh r3, [r7, #26]
}
#endif /* CHECKSUM_GEN_IP_INLINE */
}
#endif /* IP_OPTIONS_SEND */
/* generate IP header */
if (pbuf_add_header(p, IP_HLEN)) {
8019d3a: 2114 movs r1, #20
8019d3c: 68f8 ldr r0, [r7, #12]
8019d3e: f7f6 fb9f bl 8010480 <pbuf_add_header>
8019d42: 4603 mov r3, r0
8019d44: 2b00 cmp r3, #0
8019d46: d002 beq.n 8019d4e <ip4_output_if_src+0x42>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: not enough room for IP header in pbuf\n"));
IP_STATS_INC(ip.err);
MIB2_STATS_INC(mib2.ipoutdiscards);
return ERR_BUF;
8019d48: f06f 0301 mvn.w r3, #1
8019d4c: e07c b.n 8019e48 <ip4_output_if_src+0x13c>
}
iphdr = (struct ip_hdr *)p->payload;
8019d4e: 68fb ldr r3, [r7, #12]
8019d50: 685b ldr r3, [r3, #4]
8019d52: 61fb str r3, [r7, #28]
LWIP_ASSERT("check that first pbuf can hold struct ip_hdr",
8019d54: 68fb ldr r3, [r7, #12]
8019d56: 895b ldrh r3, [r3, #10]
8019d58: 2b13 cmp r3, #19
8019d5a: d806 bhi.n 8019d6a <ip4_output_if_src+0x5e>
8019d5c: 4b3c ldr r3, [pc, #240] ; (8019e50 <ip4_output_if_src+0x144>)
8019d5e: f44f 7262 mov.w r2, #904 ; 0x388
8019d62: 493e ldr r1, [pc, #248] ; (8019e5c <ip4_output_if_src+0x150>)
8019d64: 483c ldr r0, [pc, #240] ; (8019e58 <ip4_output_if_src+0x14c>)
8019d66: f001 f92d bl 801afc4 <iprintf>
(p->len >= sizeof(struct ip_hdr)));
IPH_TTL_SET(iphdr, ttl);
8019d6a: 69fb ldr r3, [r7, #28]
8019d6c: 78fa ldrb r2, [r7, #3]
8019d6e: 721a strb r2, [r3, #8]
IPH_PROTO_SET(iphdr, proto);
8019d70: 69fb ldr r3, [r7, #28]
8019d72: f897 202c ldrb.w r2, [r7, #44] ; 0x2c
8019d76: 725a strb r2, [r3, #9]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += PP_NTOHS(proto | (ttl << 8));
#endif /* CHECKSUM_GEN_IP_INLINE */
/* dest cannot be NULL here */
ip4_addr_copy(iphdr->dest, *dest);
8019d78: 687b ldr r3, [r7, #4]
8019d7a: 681a ldr r2, [r3, #0]
8019d7c: 69fb ldr r3, [r7, #28]
8019d7e: 611a str r2, [r3, #16]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF;
chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16;
#endif /* CHECKSUM_GEN_IP_INLINE */
IPH_VHL_SET(iphdr, 4, ip_hlen / 4);
8019d80: 8b7b ldrh r3, [r7, #26]
8019d82: 089b lsrs r3, r3, #2
8019d84: b29b uxth r3, r3
8019d86: b2db uxtb r3, r3
8019d88: f043 0340 orr.w r3, r3, #64 ; 0x40
8019d8c: b2da uxtb r2, r3
8019d8e: 69fb ldr r3, [r7, #28]
8019d90: 701a strb r2, [r3, #0]
IPH_TOS_SET(iphdr, tos);
8019d92: 69fb ldr r3, [r7, #28]
8019d94: f897 2028 ldrb.w r2, [r7, #40] ; 0x28
8019d98: 705a strb r2, [r3, #1]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += PP_NTOHS(tos | (iphdr->_v_hl << 8));
#endif /* CHECKSUM_GEN_IP_INLINE */
IPH_LEN_SET(iphdr, lwip_htons(p->tot_len));
8019d9a: 68fb ldr r3, [r7, #12]
8019d9c: 891b ldrh r3, [r3, #8]
8019d9e: 4618 mov r0, r3
8019da0: f7f5 f84c bl 800ee3c <lwip_htons>
8019da4: 4603 mov r3, r0
8019da6: 461a mov r2, r3
8019da8: 69fb ldr r3, [r7, #28]
8019daa: 805a strh r2, [r3, #2]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += iphdr->_len;
#endif /* CHECKSUM_GEN_IP_INLINE */
IPH_OFFSET_SET(iphdr, 0);
8019dac: 69fb ldr r3, [r7, #28]
8019dae: 2200 movs r2, #0
8019db0: 719a strb r2, [r3, #6]
8019db2: 2200 movs r2, #0
8019db4: 71da strb r2, [r3, #7]
IPH_ID_SET(iphdr, lwip_htons(ip_id));
8019db6: 4b2a ldr r3, [pc, #168] ; (8019e60 <ip4_output_if_src+0x154>)
8019db8: 881b ldrh r3, [r3, #0]
8019dba: 4618 mov r0, r3
8019dbc: f7f5 f83e bl 800ee3c <lwip_htons>
8019dc0: 4603 mov r3, r0
8019dc2: 461a mov r2, r3
8019dc4: 69fb ldr r3, [r7, #28]
8019dc6: 809a strh r2, [r3, #4]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += iphdr->_id;
#endif /* CHECKSUM_GEN_IP_INLINE */
++ip_id;
8019dc8: 4b25 ldr r3, [pc, #148] ; (8019e60 <ip4_output_if_src+0x154>)
8019dca: 881b ldrh r3, [r3, #0]
8019dcc: 3301 adds r3, #1
8019dce: b29a uxth r2, r3
8019dd0: 4b23 ldr r3, [pc, #140] ; (8019e60 <ip4_output_if_src+0x154>)
8019dd2: 801a strh r2, [r3, #0]
if (src == NULL) {
8019dd4: 68bb ldr r3, [r7, #8]
8019dd6: 2b00 cmp r3, #0
8019dd8: d104 bne.n 8019de4 <ip4_output_if_src+0xd8>
ip4_addr_copy(iphdr->src, *IP4_ADDR_ANY4);
8019dda: 4b22 ldr r3, [pc, #136] ; (8019e64 <ip4_output_if_src+0x158>)
8019ddc: 681a ldr r2, [r3, #0]
8019dde: 69fb ldr r3, [r7, #28]
8019de0: 60da str r2, [r3, #12]
8019de2: e003 b.n 8019dec <ip4_output_if_src+0xe0>
} else {
/* src cannot be NULL here */
ip4_addr_copy(iphdr->src, *src);
8019de4: 68bb ldr r3, [r7, #8]
8019de6: 681a ldr r2, [r3, #0]
8019de8: 69fb ldr r3, [r7, #28]
8019dea: 60da str r2, [r3, #12]
else {
IPH_CHKSUM_SET(iphdr, 0);
}
#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/
#else /* CHECKSUM_GEN_IP_INLINE */
IPH_CHKSUM_SET(iphdr, 0);
8019dec: 69fb ldr r3, [r7, #28]
8019dee: 2200 movs r2, #0
8019df0: 729a strb r2, [r3, #10]
8019df2: 2200 movs r2, #0
8019df4: 72da strb r2, [r3, #11]
8019df6: e00f b.n 8019e18 <ip4_output_if_src+0x10c>
}
#endif /* CHECKSUM_GEN_IP */
#endif /* CHECKSUM_GEN_IP_INLINE */
} else {
/* IP header already included in p */
if (p->len < IP_HLEN) {
8019df8: 68fb ldr r3, [r7, #12]
8019dfa: 895b ldrh r3, [r3, #10]
8019dfc: 2b13 cmp r3, #19
8019dfe: d802 bhi.n 8019e06 <ip4_output_if_src+0xfa>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: LWIP_IP_HDRINCL but pbuf is too short\n"));
IP_STATS_INC(ip.err);
MIB2_STATS_INC(mib2.ipoutdiscards);
return ERR_BUF;
8019e00: f06f 0301 mvn.w r3, #1
8019e04: e020 b.n 8019e48 <ip4_output_if_src+0x13c>
}
iphdr = (struct ip_hdr *)p->payload;
8019e06: 68fb ldr r3, [r7, #12]
8019e08: 685b ldr r3, [r3, #4]
8019e0a: 61fb str r3, [r7, #28]
ip4_addr_copy(dest_addr, iphdr->dest);
8019e0c: 69fb ldr r3, [r7, #28]
8019e0e: 691b ldr r3, [r3, #16]
8019e10: 617b str r3, [r7, #20]
dest = &dest_addr;
8019e12: f107 0314 add.w r3, r7, #20
8019e16: 607b str r3, [r7, #4]
}
#endif /* LWIP_MULTICAST_TX_OPTIONS */
#endif /* ENABLE_LOOPBACK */
#if IP_FRAG
/* don't fragment if interface has mtu set to 0 [loopif] */
if (netif->mtu && (p->tot_len > netif->mtu)) {
8019e18: 6b3b ldr r3, [r7, #48] ; 0x30
8019e1a: 8d1b ldrh r3, [r3, #40] ; 0x28
8019e1c: 2b00 cmp r3, #0
8019e1e: d00c beq.n 8019e3a <ip4_output_if_src+0x12e>
8019e20: 68fb ldr r3, [r7, #12]
8019e22: 891a ldrh r2, [r3, #8]
8019e24: 6b3b ldr r3, [r7, #48] ; 0x30
8019e26: 8d1b ldrh r3, [r3, #40] ; 0x28
8019e28: 429a cmp r2, r3
8019e2a: d906 bls.n 8019e3a <ip4_output_if_src+0x12e>
return ip4_frag(p, netif, dest);
8019e2c: 687a ldr r2, [r7, #4]
8019e2e: 6b39 ldr r1, [r7, #48] ; 0x30
8019e30: 68f8 ldr r0, [r7, #12]
8019e32: f000 fd4d bl 801a8d0 <ip4_frag>
8019e36: 4603 mov r3, r0
8019e38: e006 b.n 8019e48 <ip4_output_if_src+0x13c>
}
#endif /* IP_FRAG */
LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: call netif->output()\n"));
return netif->output(netif, p, dest);
8019e3a: 6b3b ldr r3, [r7, #48] ; 0x30
8019e3c: 695b ldr r3, [r3, #20]
8019e3e: 687a ldr r2, [r7, #4]
8019e40: 68f9 ldr r1, [r7, #12]
8019e42: 6b38 ldr r0, [r7, #48] ; 0x30
8019e44: 4798 blx r3
8019e46: 4603 mov r3, r0
}
8019e48: 4618 mov r0, r3
8019e4a: 3720 adds r7, #32
8019e4c: 46bd mov sp, r7
8019e4e: bd80 pop {r7, pc}
8019e50: 0801ec7c .word 0x0801ec7c
8019e54: 0801ecb0 .word 0x0801ecb0
8019e58: 0801ecbc .word 0x0801ecbc
8019e5c: 0801ece4 .word 0x0801ece4
8019e60: 2000885e .word 0x2000885e
8019e64: 0802103c .word 0x0802103c
08019e68 <ip4_addr_isbroadcast_u32>:
* @param netif the network interface against which the address is checked
* @return returns non-zero if the address is a broadcast address
*/
u8_t
ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif)
{
8019e68: b480 push {r7}
8019e6a: b085 sub sp, #20
8019e6c: af00 add r7, sp, #0
8019e6e: 6078 str r0, [r7, #4]
8019e70: 6039 str r1, [r7, #0]
ip4_addr_t ipaddr;
ip4_addr_set_u32(&ipaddr, addr);
8019e72: 687b ldr r3, [r7, #4]
8019e74: 60fb str r3, [r7, #12]
/* all ones (broadcast) or all zeroes (old skool broadcast) */
if ((~addr == IPADDR_ANY) ||
8019e76: 687b ldr r3, [r7, #4]
8019e78: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8019e7c: d002 beq.n 8019e84 <ip4_addr_isbroadcast_u32+0x1c>
8019e7e: 687b ldr r3, [r7, #4]
8019e80: 2b00 cmp r3, #0
8019e82: d101 bne.n 8019e88 <ip4_addr_isbroadcast_u32+0x20>
(addr == IPADDR_ANY)) {
return 1;
8019e84: 2301 movs r3, #1
8019e86: e02a b.n 8019ede <ip4_addr_isbroadcast_u32+0x76>
/* no broadcast support on this network interface? */
} else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) {
8019e88: 683b ldr r3, [r7, #0]
8019e8a: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019e8e: f003 0302 and.w r3, r3, #2
8019e92: 2b00 cmp r3, #0
8019e94: d101 bne.n 8019e9a <ip4_addr_isbroadcast_u32+0x32>
/* the given address cannot be a broadcast address
* nor can we check against any broadcast addresses */
return 0;
8019e96: 2300 movs r3, #0
8019e98: e021 b.n 8019ede <ip4_addr_isbroadcast_u32+0x76>
/* address matches network interface address exactly? => no broadcast */
} else if (addr == ip4_addr_get_u32(netif_ip4_addr(netif))) {
8019e9a: 683b ldr r3, [r7, #0]
8019e9c: 3304 adds r3, #4
8019e9e: 681b ldr r3, [r3, #0]
8019ea0: 687a ldr r2, [r7, #4]
8019ea2: 429a cmp r2, r3
8019ea4: d101 bne.n 8019eaa <ip4_addr_isbroadcast_u32+0x42>
return 0;
8019ea6: 2300 movs r3, #0
8019ea8: e019 b.n 8019ede <ip4_addr_isbroadcast_u32+0x76>
/* on the same (sub) network... */
} else if (ip4_addr_netcmp(&ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif))
8019eaa: 68fa ldr r2, [r7, #12]
8019eac: 683b ldr r3, [r7, #0]
8019eae: 3304 adds r3, #4
8019eb0: 681b ldr r3, [r3, #0]
8019eb2: 405a eors r2, r3
8019eb4: 683b ldr r3, [r7, #0]
8019eb6: 3308 adds r3, #8
8019eb8: 681b ldr r3, [r3, #0]
8019eba: 4013 ands r3, r2
8019ebc: 2b00 cmp r3, #0
8019ebe: d10d bne.n 8019edc <ip4_addr_isbroadcast_u32+0x74>
/* ...and host identifier bits are all ones? =>... */
&& ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
8019ec0: 683b ldr r3, [r7, #0]
8019ec2: 3308 adds r3, #8
8019ec4: 681b ldr r3, [r3, #0]
8019ec6: 43da mvns r2, r3
8019ec8: 687b ldr r3, [r7, #4]
8019eca: 401a ands r2, r3
(IPADDR_BROADCAST & ~ip4_addr_get_u32(netif_ip4_netmask(netif))))) {
8019ecc: 683b ldr r3, [r7, #0]
8019ece: 3308 adds r3, #8
8019ed0: 681b ldr r3, [r3, #0]
8019ed2: 43db mvns r3, r3
&& ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
8019ed4: 429a cmp r2, r3
8019ed6: d101 bne.n 8019edc <ip4_addr_isbroadcast_u32+0x74>
/* => network broadcast address */
return 1;
8019ed8: 2301 movs r3, #1
8019eda: e000 b.n 8019ede <ip4_addr_isbroadcast_u32+0x76>
} else {
return 0;
8019edc: 2300 movs r3, #0
}
}
8019ede: 4618 mov r0, r3
8019ee0: 3714 adds r7, #20
8019ee2: 46bd mov sp, r7
8019ee4: f85d 7b04 ldr.w r7, [sp], #4
8019ee8: 4770 bx lr
...
08019eec <ip_reass_tmr>:
*
* Should be called every 1000 msec (defined by IP_TMR_INTERVAL).
*/
void
ip_reass_tmr(void)
{
8019eec: b580 push {r7, lr}
8019eee: b084 sub sp, #16
8019ef0: af00 add r7, sp, #0
struct ip_reassdata *r, *prev = NULL;
8019ef2: 2300 movs r3, #0
8019ef4: 60bb str r3, [r7, #8]
r = reassdatagrams;
8019ef6: 4b12 ldr r3, [pc, #72] ; (8019f40 <ip_reass_tmr+0x54>)
8019ef8: 681b ldr r3, [r3, #0]
8019efa: 60fb str r3, [r7, #12]
while (r != NULL) {
8019efc: e018 b.n 8019f30 <ip_reass_tmr+0x44>
/* Decrement the timer. Once it reaches 0,
* clean up the incomplete fragment assembly */
if (r->timer > 0) {
8019efe: 68fb ldr r3, [r7, #12]
8019f00: 7fdb ldrb r3, [r3, #31]
8019f02: 2b00 cmp r3, #0
8019f04: d00b beq.n 8019f1e <ip_reass_tmr+0x32>
r->timer--;
8019f06: 68fb ldr r3, [r7, #12]
8019f08: 7fdb ldrb r3, [r3, #31]
8019f0a: 3b01 subs r3, #1
8019f0c: b2da uxtb r2, r3
8019f0e: 68fb ldr r3, [r7, #12]
8019f10: 77da strb r2, [r3, #31]
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n", (u16_t)r->timer));
prev = r;
8019f12: 68fb ldr r3, [r7, #12]
8019f14: 60bb str r3, [r7, #8]
r = r->next;
8019f16: 68fb ldr r3, [r7, #12]
8019f18: 681b ldr r3, [r3, #0]
8019f1a: 60fb str r3, [r7, #12]
8019f1c: e008 b.n 8019f30 <ip_reass_tmr+0x44>
} else {
/* reassembly timed out */
struct ip_reassdata *tmp;
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n"));
tmp = r;
8019f1e: 68fb ldr r3, [r7, #12]
8019f20: 607b str r3, [r7, #4]
/* get the next pointer before freeing */
r = r->next;
8019f22: 68fb ldr r3, [r7, #12]
8019f24: 681b ldr r3, [r3, #0]
8019f26: 60fb str r3, [r7, #12]
/* free the helper struct and all enqueued pbufs */
ip_reass_free_complete_datagram(tmp, prev);
8019f28: 68b9 ldr r1, [r7, #8]
8019f2a: 6878 ldr r0, [r7, #4]
8019f2c: f000 f80a bl 8019f44 <ip_reass_free_complete_datagram>
while (r != NULL) {
8019f30: 68fb ldr r3, [r7, #12]
8019f32: 2b00 cmp r3, #0
8019f34: d1e3 bne.n 8019efe <ip_reass_tmr+0x12>
}
}
}
8019f36: bf00 nop
8019f38: bf00 nop
8019f3a: 3710 adds r7, #16
8019f3c: 46bd mov sp, r7
8019f3e: bd80 pop {r7, pc}
8019f40: 20008860 .word 0x20008860
08019f44 <ip_reass_free_complete_datagram>:
* @param prev the previous datagram in the linked list
* @return the number of pbufs freed
*/
static int
ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
{
8019f44: b580 push {r7, lr}
8019f46: b088 sub sp, #32
8019f48: af00 add r7, sp, #0
8019f4a: 6078 str r0, [r7, #4]
8019f4c: 6039 str r1, [r7, #0]
u16_t pbufs_freed = 0;
8019f4e: 2300 movs r3, #0
8019f50: 83fb strh r3, [r7, #30]
u16_t clen;
struct pbuf *p;
struct ip_reass_helper *iprh;
LWIP_ASSERT("prev != ipr", prev != ipr);
8019f52: 683a ldr r2, [r7, #0]
8019f54: 687b ldr r3, [r7, #4]
8019f56: 429a cmp r2, r3
8019f58: d105 bne.n 8019f66 <ip_reass_free_complete_datagram+0x22>
8019f5a: 4b45 ldr r3, [pc, #276] ; (801a070 <ip_reass_free_complete_datagram+0x12c>)
8019f5c: 22ab movs r2, #171 ; 0xab
8019f5e: 4945 ldr r1, [pc, #276] ; (801a074 <ip_reass_free_complete_datagram+0x130>)
8019f60: 4845 ldr r0, [pc, #276] ; (801a078 <ip_reass_free_complete_datagram+0x134>)
8019f62: f001 f82f bl 801afc4 <iprintf>
if (prev != NULL) {
8019f66: 683b ldr r3, [r7, #0]
8019f68: 2b00 cmp r3, #0
8019f6a: d00a beq.n 8019f82 <ip_reass_free_complete_datagram+0x3e>
LWIP_ASSERT("prev->next == ipr", prev->next == ipr);
8019f6c: 683b ldr r3, [r7, #0]
8019f6e: 681b ldr r3, [r3, #0]
8019f70: 687a ldr r2, [r7, #4]
8019f72: 429a cmp r2, r3
8019f74: d005 beq.n 8019f82 <ip_reass_free_complete_datagram+0x3e>
8019f76: 4b3e ldr r3, [pc, #248] ; (801a070 <ip_reass_free_complete_datagram+0x12c>)
8019f78: 22ad movs r2, #173 ; 0xad
8019f7a: 4940 ldr r1, [pc, #256] ; (801a07c <ip_reass_free_complete_datagram+0x138>)
8019f7c: 483e ldr r0, [pc, #248] ; (801a078 <ip_reass_free_complete_datagram+0x134>)
8019f7e: f001 f821 bl 801afc4 <iprintf>
}
MIB2_STATS_INC(mib2.ipreasmfails);
#if LWIP_ICMP
iprh = (struct ip_reass_helper *)ipr->p->payload;
8019f82: 687b ldr r3, [r7, #4]
8019f84: 685b ldr r3, [r3, #4]
8019f86: 685b ldr r3, [r3, #4]
8019f88: 617b str r3, [r7, #20]
if (iprh->start == 0) {
8019f8a: 697b ldr r3, [r7, #20]
8019f8c: 889b ldrh r3, [r3, #4]
8019f8e: b29b uxth r3, r3
8019f90: 2b00 cmp r3, #0
8019f92: d12a bne.n 8019fea <ip_reass_free_complete_datagram+0xa6>
/* The first fragment was received, send ICMP time exceeded. */
/* First, de-queue the first pbuf from r->p. */
p = ipr->p;
8019f94: 687b ldr r3, [r7, #4]
8019f96: 685b ldr r3, [r3, #4]
8019f98: 61bb str r3, [r7, #24]
ipr->p = iprh->next_pbuf;
8019f9a: 697b ldr r3, [r7, #20]
8019f9c: 681a ldr r2, [r3, #0]
8019f9e: 687b ldr r3, [r7, #4]
8019fa0: 605a str r2, [r3, #4]
/* Then, copy the original header into it. */
SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN);
8019fa2: 69bb ldr r3, [r7, #24]
8019fa4: 6858 ldr r0, [r3, #4]
8019fa6: 687b ldr r3, [r7, #4]
8019fa8: 3308 adds r3, #8
8019faa: 2214 movs r2, #20
8019fac: 4619 mov r1, r3
8019fae: f000 fff3 bl 801af98 <memcpy>
icmp_time_exceeded(p, ICMP_TE_FRAG);
8019fb2: 2101 movs r1, #1
8019fb4: 69b8 ldr r0, [r7, #24]
8019fb6: f7ff fc29 bl 801980c <icmp_time_exceeded>
clen = pbuf_clen(p);
8019fba: 69b8 ldr r0, [r7, #24]
8019fbc: f7f6 fb84 bl 80106c8 <pbuf_clen>
8019fc0: 4603 mov r3, r0
8019fc2: 827b strh r3, [r7, #18]
LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
8019fc4: 8bfa ldrh r2, [r7, #30]
8019fc6: 8a7b ldrh r3, [r7, #18]
8019fc8: 4413 add r3, r2
8019fca: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8019fce: db05 blt.n 8019fdc <ip_reass_free_complete_datagram+0x98>
8019fd0: 4b27 ldr r3, [pc, #156] ; (801a070 <ip_reass_free_complete_datagram+0x12c>)
8019fd2: 22bc movs r2, #188 ; 0xbc
8019fd4: 492a ldr r1, [pc, #168] ; (801a080 <ip_reass_free_complete_datagram+0x13c>)
8019fd6: 4828 ldr r0, [pc, #160] ; (801a078 <ip_reass_free_complete_datagram+0x134>)
8019fd8: f000 fff4 bl 801afc4 <iprintf>
pbufs_freed = (u16_t)(pbufs_freed + clen);
8019fdc: 8bfa ldrh r2, [r7, #30]
8019fde: 8a7b ldrh r3, [r7, #18]
8019fe0: 4413 add r3, r2
8019fe2: 83fb strh r3, [r7, #30]
pbuf_free(p);
8019fe4: 69b8 ldr r0, [r7, #24]
8019fe6: f7f6 fae1 bl 80105ac <pbuf_free>
}
#endif /* LWIP_ICMP */
/* First, free all received pbufs. The individual pbufs need to be released
separately as they have not yet been chained */
p = ipr->p;
8019fea: 687b ldr r3, [r7, #4]
8019fec: 685b ldr r3, [r3, #4]
8019fee: 61bb str r3, [r7, #24]
while (p != NULL) {
8019ff0: e01f b.n 801a032 <ip_reass_free_complete_datagram+0xee>
struct pbuf *pcur;
iprh = (struct ip_reass_helper *)p->payload;
8019ff2: 69bb ldr r3, [r7, #24]
8019ff4: 685b ldr r3, [r3, #4]
8019ff6: 617b str r3, [r7, #20]
pcur = p;
8019ff8: 69bb ldr r3, [r7, #24]
8019ffa: 60fb str r3, [r7, #12]
/* get the next pointer before freeing */
p = iprh->next_pbuf;
8019ffc: 697b ldr r3, [r7, #20]
8019ffe: 681b ldr r3, [r3, #0]
801a000: 61bb str r3, [r7, #24]
clen = pbuf_clen(pcur);
801a002: 68f8 ldr r0, [r7, #12]
801a004: f7f6 fb60 bl 80106c8 <pbuf_clen>
801a008: 4603 mov r3, r0
801a00a: 827b strh r3, [r7, #18]
LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
801a00c: 8bfa ldrh r2, [r7, #30]
801a00e: 8a7b ldrh r3, [r7, #18]
801a010: 4413 add r3, r2
801a012: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
801a016: db05 blt.n 801a024 <ip_reass_free_complete_datagram+0xe0>
801a018: 4b15 ldr r3, [pc, #84] ; (801a070 <ip_reass_free_complete_datagram+0x12c>)
801a01a: 22cc movs r2, #204 ; 0xcc
801a01c: 4918 ldr r1, [pc, #96] ; (801a080 <ip_reass_free_complete_datagram+0x13c>)
801a01e: 4816 ldr r0, [pc, #88] ; (801a078 <ip_reass_free_complete_datagram+0x134>)
801a020: f000 ffd0 bl 801afc4 <iprintf>
pbufs_freed = (u16_t)(pbufs_freed + clen);
801a024: 8bfa ldrh r2, [r7, #30]
801a026: 8a7b ldrh r3, [r7, #18]
801a028: 4413 add r3, r2
801a02a: 83fb strh r3, [r7, #30]
pbuf_free(pcur);
801a02c: 68f8 ldr r0, [r7, #12]
801a02e: f7f6 fabd bl 80105ac <pbuf_free>
while (p != NULL) {
801a032: 69bb ldr r3, [r7, #24]
801a034: 2b00 cmp r3, #0
801a036: d1dc bne.n 8019ff2 <ip_reass_free_complete_datagram+0xae>
}
/* Then, unchain the struct ip_reassdata from the list and free it. */
ip_reass_dequeue_datagram(ipr, prev);
801a038: 6839 ldr r1, [r7, #0]
801a03a: 6878 ldr r0, [r7, #4]
801a03c: f000 f8c2 bl 801a1c4 <ip_reass_dequeue_datagram>
LWIP_ASSERT("ip_reass_pbufcount >= pbufs_freed", ip_reass_pbufcount >= pbufs_freed);
801a040: 4b10 ldr r3, [pc, #64] ; (801a084 <ip_reass_free_complete_datagram+0x140>)
801a042: 881b ldrh r3, [r3, #0]
801a044: 8bfa ldrh r2, [r7, #30]
801a046: 429a cmp r2, r3
801a048: d905 bls.n 801a056 <ip_reass_free_complete_datagram+0x112>
801a04a: 4b09 ldr r3, [pc, #36] ; (801a070 <ip_reass_free_complete_datagram+0x12c>)
801a04c: 22d2 movs r2, #210 ; 0xd2
801a04e: 490e ldr r1, [pc, #56] ; (801a088 <ip_reass_free_complete_datagram+0x144>)
801a050: 4809 ldr r0, [pc, #36] ; (801a078 <ip_reass_free_complete_datagram+0x134>)
801a052: f000 ffb7 bl 801afc4 <iprintf>
ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - pbufs_freed);
801a056: 4b0b ldr r3, [pc, #44] ; (801a084 <ip_reass_free_complete_datagram+0x140>)
801a058: 881a ldrh r2, [r3, #0]
801a05a: 8bfb ldrh r3, [r7, #30]
801a05c: 1ad3 subs r3, r2, r3
801a05e: b29a uxth r2, r3
801a060: 4b08 ldr r3, [pc, #32] ; (801a084 <ip_reass_free_complete_datagram+0x140>)
801a062: 801a strh r2, [r3, #0]
return pbufs_freed;
801a064: 8bfb ldrh r3, [r7, #30]
}
801a066: 4618 mov r0, r3
801a068: 3720 adds r7, #32
801a06a: 46bd mov sp, r7
801a06c: bd80 pop {r7, pc}
801a06e: bf00 nop
801a070: 0801ed14 .word 0x0801ed14
801a074: 0801ed50 .word 0x0801ed50
801a078: 0801ed5c .word 0x0801ed5c
801a07c: 0801ed84 .word 0x0801ed84
801a080: 0801ed98 .word 0x0801ed98
801a084: 20008864 .word 0x20008864
801a088: 0801edb8 .word 0x0801edb8
0801a08c <ip_reass_remove_oldest_datagram>:
* (used for freeing other datagrams if not enough space)
* @return the number of pbufs freed
*/
static int
ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed)
{
801a08c: b580 push {r7, lr}
801a08e: b08a sub sp, #40 ; 0x28
801a090: af00 add r7, sp, #0
801a092: 6078 str r0, [r7, #4]
801a094: 6039 str r1, [r7, #0]
/* @todo Can't we simply remove the last datagram in the
* linked list behind reassdatagrams?
*/
struct ip_reassdata *r, *oldest, *prev, *oldest_prev;
int pbufs_freed = 0, pbufs_freed_current;
801a096: 2300 movs r3, #0
801a098: 617b str r3, [r7, #20]
int other_datagrams;
/* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs,
* but don't free the datagram that 'fraghdr' belongs to! */
do {
oldest = NULL;
801a09a: 2300 movs r3, #0
801a09c: 623b str r3, [r7, #32]
prev = NULL;
801a09e: 2300 movs r3, #0
801a0a0: 61fb str r3, [r7, #28]
oldest_prev = NULL;
801a0a2: 2300 movs r3, #0
801a0a4: 61bb str r3, [r7, #24]
other_datagrams = 0;
801a0a6: 2300 movs r3, #0
801a0a8: 613b str r3, [r7, #16]
r = reassdatagrams;
801a0aa: 4b28 ldr r3, [pc, #160] ; (801a14c <ip_reass_remove_oldest_datagram+0xc0>)
801a0ac: 681b ldr r3, [r3, #0]
801a0ae: 627b str r3, [r7, #36] ; 0x24
while (r != NULL) {
801a0b0: e030 b.n 801a114 <ip_reass_remove_oldest_datagram+0x88>
if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) {
801a0b2: 6a7b ldr r3, [r7, #36] ; 0x24
801a0b4: 695a ldr r2, [r3, #20]
801a0b6: 687b ldr r3, [r7, #4]
801a0b8: 68db ldr r3, [r3, #12]
801a0ba: 429a cmp r2, r3
801a0bc: d10c bne.n 801a0d8 <ip_reass_remove_oldest_datagram+0x4c>
801a0be: 6a7b ldr r3, [r7, #36] ; 0x24
801a0c0: 699a ldr r2, [r3, #24]
801a0c2: 687b ldr r3, [r7, #4]
801a0c4: 691b ldr r3, [r3, #16]
801a0c6: 429a cmp r2, r3
801a0c8: d106 bne.n 801a0d8 <ip_reass_remove_oldest_datagram+0x4c>
801a0ca: 6a7b ldr r3, [r7, #36] ; 0x24
801a0cc: 899a ldrh r2, [r3, #12]
801a0ce: 687b ldr r3, [r7, #4]
801a0d0: 889b ldrh r3, [r3, #4]
801a0d2: b29b uxth r3, r3
801a0d4: 429a cmp r2, r3
801a0d6: d014 beq.n 801a102 <ip_reass_remove_oldest_datagram+0x76>
/* Not the same datagram as fraghdr */
other_datagrams++;
801a0d8: 693b ldr r3, [r7, #16]
801a0da: 3301 adds r3, #1
801a0dc: 613b str r3, [r7, #16]
if (oldest == NULL) {
801a0de: 6a3b ldr r3, [r7, #32]
801a0e0: 2b00 cmp r3, #0
801a0e2: d104 bne.n 801a0ee <ip_reass_remove_oldest_datagram+0x62>
oldest = r;
801a0e4: 6a7b ldr r3, [r7, #36] ; 0x24
801a0e6: 623b str r3, [r7, #32]
oldest_prev = prev;
801a0e8: 69fb ldr r3, [r7, #28]
801a0ea: 61bb str r3, [r7, #24]
801a0ec: e009 b.n 801a102 <ip_reass_remove_oldest_datagram+0x76>
} else if (r->timer <= oldest->timer) {
801a0ee: 6a7b ldr r3, [r7, #36] ; 0x24
801a0f0: 7fda ldrb r2, [r3, #31]
801a0f2: 6a3b ldr r3, [r7, #32]
801a0f4: 7fdb ldrb r3, [r3, #31]
801a0f6: 429a cmp r2, r3
801a0f8: d803 bhi.n 801a102 <ip_reass_remove_oldest_datagram+0x76>
/* older than the previous oldest */
oldest = r;
801a0fa: 6a7b ldr r3, [r7, #36] ; 0x24
801a0fc: 623b str r3, [r7, #32]
oldest_prev = prev;
801a0fe: 69fb ldr r3, [r7, #28]
801a100: 61bb str r3, [r7, #24]
}
}
if (r->next != NULL) {
801a102: 6a7b ldr r3, [r7, #36] ; 0x24
801a104: 681b ldr r3, [r3, #0]
801a106: 2b00 cmp r3, #0
801a108: d001 beq.n 801a10e <ip_reass_remove_oldest_datagram+0x82>
prev = r;
801a10a: 6a7b ldr r3, [r7, #36] ; 0x24
801a10c: 61fb str r3, [r7, #28]
}
r = r->next;
801a10e: 6a7b ldr r3, [r7, #36] ; 0x24
801a110: 681b ldr r3, [r3, #0]
801a112: 627b str r3, [r7, #36] ; 0x24
while (r != NULL) {
801a114: 6a7b ldr r3, [r7, #36] ; 0x24
801a116: 2b00 cmp r3, #0
801a118: d1cb bne.n 801a0b2 <ip_reass_remove_oldest_datagram+0x26>
}
if (oldest != NULL) {
801a11a: 6a3b ldr r3, [r7, #32]
801a11c: 2b00 cmp r3, #0
801a11e: d008 beq.n 801a132 <ip_reass_remove_oldest_datagram+0xa6>
pbufs_freed_current = ip_reass_free_complete_datagram(oldest, oldest_prev);
801a120: 69b9 ldr r1, [r7, #24]
801a122: 6a38 ldr r0, [r7, #32]
801a124: f7ff ff0e bl 8019f44 <ip_reass_free_complete_datagram>
801a128: 60f8 str r0, [r7, #12]
pbufs_freed += pbufs_freed_current;
801a12a: 697a ldr r2, [r7, #20]
801a12c: 68fb ldr r3, [r7, #12]
801a12e: 4413 add r3, r2
801a130: 617b str r3, [r7, #20]
}
} while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1));
801a132: 697a ldr r2, [r7, #20]
801a134: 683b ldr r3, [r7, #0]
801a136: 429a cmp r2, r3
801a138: da02 bge.n 801a140 <ip_reass_remove_oldest_datagram+0xb4>
801a13a: 693b ldr r3, [r7, #16]
801a13c: 2b01 cmp r3, #1
801a13e: dcac bgt.n 801a09a <ip_reass_remove_oldest_datagram+0xe>
return pbufs_freed;
801a140: 697b ldr r3, [r7, #20]
}
801a142: 4618 mov r0, r3
801a144: 3728 adds r7, #40 ; 0x28
801a146: 46bd mov sp, r7
801a148: bd80 pop {r7, pc}
801a14a: bf00 nop
801a14c: 20008860 .word 0x20008860
0801a150 <ip_reass_enqueue_new_datagram>:
* @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space)
* @return A pointer to the queue location into which the fragment was enqueued
*/
static struct ip_reassdata *
ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen)
{
801a150: b580 push {r7, lr}
801a152: b084 sub sp, #16
801a154: af00 add r7, sp, #0
801a156: 6078 str r0, [r7, #4]
801a158: 6039 str r1, [r7, #0]
#if ! IP_REASS_FREE_OLDEST
LWIP_UNUSED_ARG(clen);
#endif
/* No matching previous fragment found, allocate a new reassdata struct */
ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
801a15a: 2004 movs r0, #4
801a15c: f7f5 fb24 bl 800f7a8 <memp_malloc>
801a160: 60f8 str r0, [r7, #12]
if (ipr == NULL) {
801a162: 68fb ldr r3, [r7, #12]
801a164: 2b00 cmp r3, #0
801a166: d110 bne.n 801a18a <ip_reass_enqueue_new_datagram+0x3a>
#if IP_REASS_FREE_OLDEST
if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) {
801a168: 6839 ldr r1, [r7, #0]
801a16a: 6878 ldr r0, [r7, #4]
801a16c: f7ff ff8e bl 801a08c <ip_reass_remove_oldest_datagram>
801a170: 4602 mov r2, r0
801a172: 683b ldr r3, [r7, #0]
801a174: 4293 cmp r3, r2
801a176: dc03 bgt.n 801a180 <ip_reass_enqueue_new_datagram+0x30>
ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
801a178: 2004 movs r0, #4
801a17a: f7f5 fb15 bl 800f7a8 <memp_malloc>
801a17e: 60f8 str r0, [r7, #12]
}
if (ipr == NULL)
801a180: 68fb ldr r3, [r7, #12]
801a182: 2b00 cmp r3, #0
801a184: d101 bne.n 801a18a <ip_reass_enqueue_new_datagram+0x3a>
#endif /* IP_REASS_FREE_OLDEST */
{
IPFRAG_STATS_INC(ip_frag.memerr);
LWIP_DEBUGF(IP_REASS_DEBUG, ("Failed to alloc reassdata struct\n"));
return NULL;
801a186: 2300 movs r3, #0
801a188: e016 b.n 801a1b8 <ip_reass_enqueue_new_datagram+0x68>
}
}
memset(ipr, 0, sizeof(struct ip_reassdata));
801a18a: 2220 movs r2, #32
801a18c: 2100 movs r1, #0
801a18e: 68f8 ldr r0, [r7, #12]
801a190: f000 ff10 bl 801afb4 <memset>
ipr->timer = IP_REASS_MAXAGE;
801a194: 68fb ldr r3, [r7, #12]
801a196: 220f movs r2, #15
801a198: 77da strb r2, [r3, #31]
/* enqueue the new structure to the front of the list */
ipr->next = reassdatagrams;
801a19a: 4b09 ldr r3, [pc, #36] ; (801a1c0 <ip_reass_enqueue_new_datagram+0x70>)
801a19c: 681a ldr r2, [r3, #0]
801a19e: 68fb ldr r3, [r7, #12]
801a1a0: 601a str r2, [r3, #0]
reassdatagrams = ipr;
801a1a2: 4a07 ldr r2, [pc, #28] ; (801a1c0 <ip_reass_enqueue_new_datagram+0x70>)
801a1a4: 68fb ldr r3, [r7, #12]
801a1a6: 6013 str r3, [r2, #0]
/* copy the ip header for later tests and input */
/* @todo: no ip options supported? */
SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN);
801a1a8: 68fb ldr r3, [r7, #12]
801a1aa: 3308 adds r3, #8
801a1ac: 2214 movs r2, #20
801a1ae: 6879 ldr r1, [r7, #4]
801a1b0: 4618 mov r0, r3
801a1b2: f000 fef1 bl 801af98 <memcpy>
return ipr;
801a1b6: 68fb ldr r3, [r7, #12]
}
801a1b8: 4618 mov r0, r3
801a1ba: 3710 adds r7, #16
801a1bc: 46bd mov sp, r7
801a1be: bd80 pop {r7, pc}
801a1c0: 20008860 .word 0x20008860
0801a1c4 <ip_reass_dequeue_datagram>:
* Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs.
* @param ipr points to the queue entry to dequeue
*/
static void
ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
{
801a1c4: b580 push {r7, lr}
801a1c6: b082 sub sp, #8
801a1c8: af00 add r7, sp, #0
801a1ca: 6078 str r0, [r7, #4]
801a1cc: 6039 str r1, [r7, #0]
/* dequeue the reass struct */
if (reassdatagrams == ipr) {
801a1ce: 4b10 ldr r3, [pc, #64] ; (801a210 <ip_reass_dequeue_datagram+0x4c>)
801a1d0: 681b ldr r3, [r3, #0]
801a1d2: 687a ldr r2, [r7, #4]
801a1d4: 429a cmp r2, r3
801a1d6: d104 bne.n 801a1e2 <ip_reass_dequeue_datagram+0x1e>
/* it was the first in the list */
reassdatagrams = ipr->next;
801a1d8: 687b ldr r3, [r7, #4]
801a1da: 681b ldr r3, [r3, #0]
801a1dc: 4a0c ldr r2, [pc, #48] ; (801a210 <ip_reass_dequeue_datagram+0x4c>)
801a1de: 6013 str r3, [r2, #0]
801a1e0: e00d b.n 801a1fe <ip_reass_dequeue_datagram+0x3a>
} else {
/* it wasn't the first, so it must have a valid 'prev' */
LWIP_ASSERT("sanity check linked list", prev != NULL);
801a1e2: 683b ldr r3, [r7, #0]
801a1e4: 2b00 cmp r3, #0
801a1e6: d106 bne.n 801a1f6 <ip_reass_dequeue_datagram+0x32>
801a1e8: 4b0a ldr r3, [pc, #40] ; (801a214 <ip_reass_dequeue_datagram+0x50>)
801a1ea: f240 1245 movw r2, #325 ; 0x145
801a1ee: 490a ldr r1, [pc, #40] ; (801a218 <ip_reass_dequeue_datagram+0x54>)
801a1f0: 480a ldr r0, [pc, #40] ; (801a21c <ip_reass_dequeue_datagram+0x58>)
801a1f2: f000 fee7 bl 801afc4 <iprintf>
prev->next = ipr->next;
801a1f6: 687b ldr r3, [r7, #4]
801a1f8: 681a ldr r2, [r3, #0]
801a1fa: 683b ldr r3, [r7, #0]
801a1fc: 601a str r2, [r3, #0]
}
/* now we can free the ip_reassdata struct */
memp_free(MEMP_REASSDATA, ipr);
801a1fe: 6879 ldr r1, [r7, #4]
801a200: 2004 movs r0, #4
801a202: f7f5 fb23 bl 800f84c <memp_free>
}
801a206: bf00 nop
801a208: 3708 adds r7, #8
801a20a: 46bd mov sp, r7
801a20c: bd80 pop {r7, pc}
801a20e: bf00 nop
801a210: 20008860 .word 0x20008860
801a214: 0801ed14 .word 0x0801ed14
801a218: 0801eddc .word 0x0801eddc
801a21c: 0801ed5c .word 0x0801ed5c
0801a220 <ip_reass_chain_frag_into_datagram_and_validate>:
* @param is_last is 1 if this pbuf has MF==0 (ipr->flags not updated yet)
* @return see IP_REASS_VALIDATE_* defines
*/
static int
ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p, int is_last)
{
801a220: b580 push {r7, lr}
801a222: b08c sub sp, #48 ; 0x30
801a224: af00 add r7, sp, #0
801a226: 60f8 str r0, [r7, #12]
801a228: 60b9 str r1, [r7, #8]
801a22a: 607a str r2, [r7, #4]
struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev = NULL;
801a22c: 2300 movs r3, #0
801a22e: 62bb str r3, [r7, #40] ; 0x28
struct pbuf *q;
u16_t offset, len;
u8_t hlen;
struct ip_hdr *fraghdr;
int valid = 1;
801a230: 2301 movs r3, #1
801a232: 623b str r3, [r7, #32]
/* Extract length and fragment offset from current fragment */
fraghdr = (struct ip_hdr *)new_p->payload;
801a234: 68bb ldr r3, [r7, #8]
801a236: 685b ldr r3, [r3, #4]
801a238: 61fb str r3, [r7, #28]
len = lwip_ntohs(IPH_LEN(fraghdr));
801a23a: 69fb ldr r3, [r7, #28]
801a23c: 885b ldrh r3, [r3, #2]
801a23e: b29b uxth r3, r3
801a240: 4618 mov r0, r3
801a242: f7f4 fdfb bl 800ee3c <lwip_htons>
801a246: 4603 mov r3, r0
801a248: 837b strh r3, [r7, #26]
hlen = IPH_HL_BYTES(fraghdr);
801a24a: 69fb ldr r3, [r7, #28]
801a24c: 781b ldrb r3, [r3, #0]
801a24e: f003 030f and.w r3, r3, #15
801a252: b2db uxtb r3, r3
801a254: 009b lsls r3, r3, #2
801a256: 767b strb r3, [r7, #25]
if (hlen > len) {
801a258: 7e7b ldrb r3, [r7, #25]
801a25a: b29b uxth r3, r3
801a25c: 8b7a ldrh r2, [r7, #26]
801a25e: 429a cmp r2, r3
801a260: d202 bcs.n 801a268 <ip_reass_chain_frag_into_datagram_and_validate+0x48>
/* invalid datagram */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a262: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
801a266: e135 b.n 801a4d4 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
}
len = (u16_t)(len - hlen);
801a268: 7e7b ldrb r3, [r7, #25]
801a26a: b29b uxth r3, r3
801a26c: 8b7a ldrh r2, [r7, #26]
801a26e: 1ad3 subs r3, r2, r3
801a270: 837b strh r3, [r7, #26]
offset = IPH_OFFSET_BYTES(fraghdr);
801a272: 69fb ldr r3, [r7, #28]
801a274: 88db ldrh r3, [r3, #6]
801a276: b29b uxth r3, r3
801a278: 4618 mov r0, r3
801a27a: f7f4 fddf bl 800ee3c <lwip_htons>
801a27e: 4603 mov r3, r0
801a280: f3c3 030c ubfx r3, r3, #0, #13
801a284: b29b uxth r3, r3
801a286: 00db lsls r3, r3, #3
801a288: 82fb strh r3, [r7, #22]
/* overwrite the fragment's ip header from the pbuf with our helper struct,
* and setup the embedded helper structure. */
/* make sure the struct ip_reass_helper fits into the IP header */
LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN",
sizeof(struct ip_reass_helper) <= IP_HLEN);
iprh = (struct ip_reass_helper *)new_p->payload;
801a28a: 68bb ldr r3, [r7, #8]
801a28c: 685b ldr r3, [r3, #4]
801a28e: 62fb str r3, [r7, #44] ; 0x2c
iprh->next_pbuf = NULL;
801a290: 6afb ldr r3, [r7, #44] ; 0x2c
801a292: 2200 movs r2, #0
801a294: 701a strb r2, [r3, #0]
801a296: 2200 movs r2, #0
801a298: 705a strb r2, [r3, #1]
801a29a: 2200 movs r2, #0
801a29c: 709a strb r2, [r3, #2]
801a29e: 2200 movs r2, #0
801a2a0: 70da strb r2, [r3, #3]
iprh->start = offset;
801a2a2: 6afb ldr r3, [r7, #44] ; 0x2c
801a2a4: 8afa ldrh r2, [r7, #22]
801a2a6: 809a strh r2, [r3, #4]
iprh->end = (u16_t)(offset + len);
801a2a8: 8afa ldrh r2, [r7, #22]
801a2aa: 8b7b ldrh r3, [r7, #26]
801a2ac: 4413 add r3, r2
801a2ae: b29a uxth r2, r3
801a2b0: 6afb ldr r3, [r7, #44] ; 0x2c
801a2b2: 80da strh r2, [r3, #6]
if (iprh->end < offset) {
801a2b4: 6afb ldr r3, [r7, #44] ; 0x2c
801a2b6: 88db ldrh r3, [r3, #6]
801a2b8: b29b uxth r3, r3
801a2ba: 8afa ldrh r2, [r7, #22]
801a2bc: 429a cmp r2, r3
801a2be: d902 bls.n 801a2c6 <ip_reass_chain_frag_into_datagram_and_validate+0xa6>
/* u16_t overflow, cannot handle this */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a2c0: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
801a2c4: e106 b.n 801a4d4 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
}
/* Iterate through until we either get to the end of the list (append),
* or we find one with a larger offset (insert). */
for (q = ipr->p; q != NULL;) {
801a2c6: 68fb ldr r3, [r7, #12]
801a2c8: 685b ldr r3, [r3, #4]
801a2ca: 627b str r3, [r7, #36] ; 0x24
801a2cc: e068 b.n 801a3a0 <ip_reass_chain_frag_into_datagram_and_validate+0x180>
iprh_tmp = (struct ip_reass_helper *)q->payload;
801a2ce: 6a7b ldr r3, [r7, #36] ; 0x24
801a2d0: 685b ldr r3, [r3, #4]
801a2d2: 613b str r3, [r7, #16]
if (iprh->start < iprh_tmp->start) {
801a2d4: 6afb ldr r3, [r7, #44] ; 0x2c
801a2d6: 889b ldrh r3, [r3, #4]
801a2d8: b29a uxth r2, r3
801a2da: 693b ldr r3, [r7, #16]
801a2dc: 889b ldrh r3, [r3, #4]
801a2de: b29b uxth r3, r3
801a2e0: 429a cmp r2, r3
801a2e2: d235 bcs.n 801a350 <ip_reass_chain_frag_into_datagram_and_validate+0x130>
/* the new pbuf should be inserted before this */
iprh->next_pbuf = q;
801a2e4: 6afb ldr r3, [r7, #44] ; 0x2c
801a2e6: 6a7a ldr r2, [r7, #36] ; 0x24
801a2e8: 601a str r2, [r3, #0]
if (iprh_prev != NULL) {
801a2ea: 6abb ldr r3, [r7, #40] ; 0x28
801a2ec: 2b00 cmp r3, #0
801a2ee: d020 beq.n 801a332 <ip_reass_chain_frag_into_datagram_and_validate+0x112>
/* not the fragment with the lowest offset */
#if IP_REASS_CHECK_OVERLAP
if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) {
801a2f0: 6afb ldr r3, [r7, #44] ; 0x2c
801a2f2: 889b ldrh r3, [r3, #4]
801a2f4: b29a uxth r2, r3
801a2f6: 6abb ldr r3, [r7, #40] ; 0x28
801a2f8: 88db ldrh r3, [r3, #6]
801a2fa: b29b uxth r3, r3
801a2fc: 429a cmp r2, r3
801a2fe: d307 bcc.n 801a310 <ip_reass_chain_frag_into_datagram_and_validate+0xf0>
801a300: 6afb ldr r3, [r7, #44] ; 0x2c
801a302: 88db ldrh r3, [r3, #6]
801a304: b29a uxth r2, r3
801a306: 693b ldr r3, [r7, #16]
801a308: 889b ldrh r3, [r3, #4]
801a30a: b29b uxth r3, r3
801a30c: 429a cmp r2, r3
801a30e: d902 bls.n 801a316 <ip_reass_chain_frag_into_datagram_and_validate+0xf6>
/* fragment overlaps with previous or following, throw away */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a310: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
801a314: e0de b.n 801a4d4 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
}
#endif /* IP_REASS_CHECK_OVERLAP */
iprh_prev->next_pbuf = new_p;
801a316: 6abb ldr r3, [r7, #40] ; 0x28
801a318: 68ba ldr r2, [r7, #8]
801a31a: 601a str r2, [r3, #0]
if (iprh_prev->end != iprh->start) {
801a31c: 6abb ldr r3, [r7, #40] ; 0x28
801a31e: 88db ldrh r3, [r3, #6]
801a320: b29a uxth r2, r3
801a322: 6afb ldr r3, [r7, #44] ; 0x2c
801a324: 889b ldrh r3, [r3, #4]
801a326: b29b uxth r3, r3
801a328: 429a cmp r2, r3
801a32a: d03d beq.n 801a3a8 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
/* There is a fragment missing between the current
* and the previous fragment */
valid = 0;
801a32c: 2300 movs r3, #0
801a32e: 623b str r3, [r7, #32]
}
#endif /* IP_REASS_CHECK_OVERLAP */
/* fragment with the lowest offset */
ipr->p = new_p;
}
break;
801a330: e03a b.n 801a3a8 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
if (iprh->end > iprh_tmp->start) {
801a332: 6afb ldr r3, [r7, #44] ; 0x2c
801a334: 88db ldrh r3, [r3, #6]
801a336: b29a uxth r2, r3
801a338: 693b ldr r3, [r7, #16]
801a33a: 889b ldrh r3, [r3, #4]
801a33c: b29b uxth r3, r3
801a33e: 429a cmp r2, r3
801a340: d902 bls.n 801a348 <ip_reass_chain_frag_into_datagram_and_validate+0x128>
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a342: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
801a346: e0c5 b.n 801a4d4 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
ipr->p = new_p;
801a348: 68fb ldr r3, [r7, #12]
801a34a: 68ba ldr r2, [r7, #8]
801a34c: 605a str r2, [r3, #4]
break;
801a34e: e02b b.n 801a3a8 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
} else if (iprh->start == iprh_tmp->start) {
801a350: 6afb ldr r3, [r7, #44] ; 0x2c
801a352: 889b ldrh r3, [r3, #4]
801a354: b29a uxth r2, r3
801a356: 693b ldr r3, [r7, #16]
801a358: 889b ldrh r3, [r3, #4]
801a35a: b29b uxth r3, r3
801a35c: 429a cmp r2, r3
801a35e: d102 bne.n 801a366 <ip_reass_chain_frag_into_datagram_and_validate+0x146>
/* received the same datagram twice: no need to keep the datagram */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a360: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
801a364: e0b6 b.n 801a4d4 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
#if IP_REASS_CHECK_OVERLAP
} else if (iprh->start < iprh_tmp->end) {
801a366: 6afb ldr r3, [r7, #44] ; 0x2c
801a368: 889b ldrh r3, [r3, #4]
801a36a: b29a uxth r2, r3
801a36c: 693b ldr r3, [r7, #16]
801a36e: 88db ldrh r3, [r3, #6]
801a370: b29b uxth r3, r3
801a372: 429a cmp r2, r3
801a374: d202 bcs.n 801a37c <ip_reass_chain_frag_into_datagram_and_validate+0x15c>
/* overlap: no need to keep the new datagram */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a376: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
801a37a: e0ab b.n 801a4d4 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
#endif /* IP_REASS_CHECK_OVERLAP */
} else {
/* Check if the fragments received so far have no holes. */
if (iprh_prev != NULL) {
801a37c: 6abb ldr r3, [r7, #40] ; 0x28
801a37e: 2b00 cmp r3, #0
801a380: d009 beq.n 801a396 <ip_reass_chain_frag_into_datagram_and_validate+0x176>
if (iprh_prev->end != iprh_tmp->start) {
801a382: 6abb ldr r3, [r7, #40] ; 0x28
801a384: 88db ldrh r3, [r3, #6]
801a386: b29a uxth r2, r3
801a388: 693b ldr r3, [r7, #16]
801a38a: 889b ldrh r3, [r3, #4]
801a38c: b29b uxth r3, r3
801a38e: 429a cmp r2, r3
801a390: d001 beq.n 801a396 <ip_reass_chain_frag_into_datagram_and_validate+0x176>
/* There is a fragment missing between the current
* and the previous fragment */
valid = 0;
801a392: 2300 movs r3, #0
801a394: 623b str r3, [r7, #32]
}
}
}
q = iprh_tmp->next_pbuf;
801a396: 693b ldr r3, [r7, #16]
801a398: 681b ldr r3, [r3, #0]
801a39a: 627b str r3, [r7, #36] ; 0x24
iprh_prev = iprh_tmp;
801a39c: 693b ldr r3, [r7, #16]
801a39e: 62bb str r3, [r7, #40] ; 0x28
for (q = ipr->p; q != NULL;) {
801a3a0: 6a7b ldr r3, [r7, #36] ; 0x24
801a3a2: 2b00 cmp r3, #0
801a3a4: d193 bne.n 801a2ce <ip_reass_chain_frag_into_datagram_and_validate+0xae>
801a3a6: e000 b.n 801a3aa <ip_reass_chain_frag_into_datagram_and_validate+0x18a>
break;
801a3a8: bf00 nop
}
/* If q is NULL, then we made it to the end of the list. Determine what to do now */
if (q == NULL) {
801a3aa: 6a7b ldr r3, [r7, #36] ; 0x24
801a3ac: 2b00 cmp r3, #0
801a3ae: d12d bne.n 801a40c <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
if (iprh_prev != NULL) {
801a3b0: 6abb ldr r3, [r7, #40] ; 0x28
801a3b2: 2b00 cmp r3, #0
801a3b4: d01c beq.n 801a3f0 <ip_reass_chain_frag_into_datagram_and_validate+0x1d0>
/* this is (for now), the fragment with the highest offset:
* chain it to the last fragment */
#if IP_REASS_CHECK_OVERLAP
LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start);
801a3b6: 6abb ldr r3, [r7, #40] ; 0x28
801a3b8: 88db ldrh r3, [r3, #6]
801a3ba: b29a uxth r2, r3
801a3bc: 6afb ldr r3, [r7, #44] ; 0x2c
801a3be: 889b ldrh r3, [r3, #4]
801a3c0: b29b uxth r3, r3
801a3c2: 429a cmp r2, r3
801a3c4: d906 bls.n 801a3d4 <ip_reass_chain_frag_into_datagram_and_validate+0x1b4>
801a3c6: 4b45 ldr r3, [pc, #276] ; (801a4dc <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a3c8: f44f 72db mov.w r2, #438 ; 0x1b6
801a3cc: 4944 ldr r1, [pc, #272] ; (801a4e0 <ip_reass_chain_frag_into_datagram_and_validate+0x2c0>)
801a3ce: 4845 ldr r0, [pc, #276] ; (801a4e4 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a3d0: f000 fdf8 bl 801afc4 <iprintf>
#endif /* IP_REASS_CHECK_OVERLAP */
iprh_prev->next_pbuf = new_p;
801a3d4: 6abb ldr r3, [r7, #40] ; 0x28
801a3d6: 68ba ldr r2, [r7, #8]
801a3d8: 601a str r2, [r3, #0]
if (iprh_prev->end != iprh->start) {
801a3da: 6abb ldr r3, [r7, #40] ; 0x28
801a3dc: 88db ldrh r3, [r3, #6]
801a3de: b29a uxth r2, r3
801a3e0: 6afb ldr r3, [r7, #44] ; 0x2c
801a3e2: 889b ldrh r3, [r3, #4]
801a3e4: b29b uxth r3, r3
801a3e6: 429a cmp r2, r3
801a3e8: d010 beq.n 801a40c <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
valid = 0;
801a3ea: 2300 movs r3, #0
801a3ec: 623b str r3, [r7, #32]
801a3ee: e00d b.n 801a40c <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
}
} else {
#if IP_REASS_CHECK_OVERLAP
LWIP_ASSERT("no previous fragment, this must be the first fragment!",
801a3f0: 68fb ldr r3, [r7, #12]
801a3f2: 685b ldr r3, [r3, #4]
801a3f4: 2b00 cmp r3, #0
801a3f6: d006 beq.n 801a406 <ip_reass_chain_frag_into_datagram_and_validate+0x1e6>
801a3f8: 4b38 ldr r3, [pc, #224] ; (801a4dc <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a3fa: f44f 72df mov.w r2, #446 ; 0x1be
801a3fe: 493a ldr r1, [pc, #232] ; (801a4e8 <ip_reass_chain_frag_into_datagram_and_validate+0x2c8>)
801a400: 4838 ldr r0, [pc, #224] ; (801a4e4 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a402: f000 fddf bl 801afc4 <iprintf>
ipr->p == NULL);
#endif /* IP_REASS_CHECK_OVERLAP */
/* this is the first fragment we ever received for this ip datagram */
ipr->p = new_p;
801a406: 68fb ldr r3, [r7, #12]
801a408: 68ba ldr r2, [r7, #8]
801a40a: 605a str r2, [r3, #4]
}
}
/* At this point, the validation part begins: */
/* If we already received the last fragment */
if (is_last || ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0)) {
801a40c: 687b ldr r3, [r7, #4]
801a40e: 2b00 cmp r3, #0
801a410: d105 bne.n 801a41e <ip_reass_chain_frag_into_datagram_and_validate+0x1fe>
801a412: 68fb ldr r3, [r7, #12]
801a414: 7f9b ldrb r3, [r3, #30]
801a416: f003 0301 and.w r3, r3, #1
801a41a: 2b00 cmp r3, #0
801a41c: d059 beq.n 801a4d2 <ip_reass_chain_frag_into_datagram_and_validate+0x2b2>
/* and had no holes so far */
if (valid) {
801a41e: 6a3b ldr r3, [r7, #32]
801a420: 2b00 cmp r3, #0
801a422: d04f beq.n 801a4c4 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
/* then check if the rest of the fragments is here */
/* Check if the queue starts with the first datagram */
if ((ipr->p == NULL) || (((struct ip_reass_helper *)ipr->p->payload)->start != 0)) {
801a424: 68fb ldr r3, [r7, #12]
801a426: 685b ldr r3, [r3, #4]
801a428: 2b00 cmp r3, #0
801a42a: d006 beq.n 801a43a <ip_reass_chain_frag_into_datagram_and_validate+0x21a>
801a42c: 68fb ldr r3, [r7, #12]
801a42e: 685b ldr r3, [r3, #4]
801a430: 685b ldr r3, [r3, #4]
801a432: 889b ldrh r3, [r3, #4]
801a434: b29b uxth r3, r3
801a436: 2b00 cmp r3, #0
801a438: d002 beq.n 801a440 <ip_reass_chain_frag_into_datagram_and_validate+0x220>
valid = 0;
801a43a: 2300 movs r3, #0
801a43c: 623b str r3, [r7, #32]
801a43e: e041 b.n 801a4c4 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
} else {
/* and check that there are no holes after this datagram */
iprh_prev = iprh;
801a440: 6afb ldr r3, [r7, #44] ; 0x2c
801a442: 62bb str r3, [r7, #40] ; 0x28
q = iprh->next_pbuf;
801a444: 6afb ldr r3, [r7, #44] ; 0x2c
801a446: 681b ldr r3, [r3, #0]
801a448: 627b str r3, [r7, #36] ; 0x24
while (q != NULL) {
801a44a: e012 b.n 801a472 <ip_reass_chain_frag_into_datagram_and_validate+0x252>
iprh = (struct ip_reass_helper *)q->payload;
801a44c: 6a7b ldr r3, [r7, #36] ; 0x24
801a44e: 685b ldr r3, [r3, #4]
801a450: 62fb str r3, [r7, #44] ; 0x2c
if (iprh_prev->end != iprh->start) {
801a452: 6abb ldr r3, [r7, #40] ; 0x28
801a454: 88db ldrh r3, [r3, #6]
801a456: b29a uxth r2, r3
801a458: 6afb ldr r3, [r7, #44] ; 0x2c
801a45a: 889b ldrh r3, [r3, #4]
801a45c: b29b uxth r3, r3
801a45e: 429a cmp r2, r3
801a460: d002 beq.n 801a468 <ip_reass_chain_frag_into_datagram_and_validate+0x248>
valid = 0;
801a462: 2300 movs r3, #0
801a464: 623b str r3, [r7, #32]
break;
801a466: e007 b.n 801a478 <ip_reass_chain_frag_into_datagram_and_validate+0x258>
}
iprh_prev = iprh;
801a468: 6afb ldr r3, [r7, #44] ; 0x2c
801a46a: 62bb str r3, [r7, #40] ; 0x28
q = iprh->next_pbuf;
801a46c: 6afb ldr r3, [r7, #44] ; 0x2c
801a46e: 681b ldr r3, [r3, #0]
801a470: 627b str r3, [r7, #36] ; 0x24
while (q != NULL) {
801a472: 6a7b ldr r3, [r7, #36] ; 0x24
801a474: 2b00 cmp r3, #0
801a476: d1e9 bne.n 801a44c <ip_reass_chain_frag_into_datagram_and_validate+0x22c>
}
/* if still valid, all fragments are received
* (because to the MF==0 already arrived */
if (valid) {
801a478: 6a3b ldr r3, [r7, #32]
801a47a: 2b00 cmp r3, #0
801a47c: d022 beq.n 801a4c4 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
LWIP_ASSERT("sanity check", ipr->p != NULL);
801a47e: 68fb ldr r3, [r7, #12]
801a480: 685b ldr r3, [r3, #4]
801a482: 2b00 cmp r3, #0
801a484: d106 bne.n 801a494 <ip_reass_chain_frag_into_datagram_and_validate+0x274>
801a486: 4b15 ldr r3, [pc, #84] ; (801a4dc <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a488: f240 12df movw r2, #479 ; 0x1df
801a48c: 4917 ldr r1, [pc, #92] ; (801a4ec <ip_reass_chain_frag_into_datagram_and_validate+0x2cc>)
801a48e: 4815 ldr r0, [pc, #84] ; (801a4e4 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a490: f000 fd98 bl 801afc4 <iprintf>
LWIP_ASSERT("sanity check",
801a494: 68fb ldr r3, [r7, #12]
801a496: 685b ldr r3, [r3, #4]
801a498: 685b ldr r3, [r3, #4]
801a49a: 6afa ldr r2, [r7, #44] ; 0x2c
801a49c: 429a cmp r2, r3
801a49e: d106 bne.n 801a4ae <ip_reass_chain_frag_into_datagram_and_validate+0x28e>
801a4a0: 4b0e ldr r3, [pc, #56] ; (801a4dc <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a4a2: f44f 72f0 mov.w r2, #480 ; 0x1e0
801a4a6: 4911 ldr r1, [pc, #68] ; (801a4ec <ip_reass_chain_frag_into_datagram_and_validate+0x2cc>)
801a4a8: 480e ldr r0, [pc, #56] ; (801a4e4 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a4aa: f000 fd8b bl 801afc4 <iprintf>
((struct ip_reass_helper *)ipr->p->payload) != iprh);
LWIP_ASSERT("validate_datagram:next_pbuf!=NULL",
801a4ae: 6afb ldr r3, [r7, #44] ; 0x2c
801a4b0: 681b ldr r3, [r3, #0]
801a4b2: 2b00 cmp r3, #0
801a4b4: d006 beq.n 801a4c4 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
801a4b6: 4b09 ldr r3, [pc, #36] ; (801a4dc <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a4b8: f44f 72f1 mov.w r2, #482 ; 0x1e2
801a4bc: 490c ldr r1, [pc, #48] ; (801a4f0 <ip_reass_chain_frag_into_datagram_and_validate+0x2d0>)
801a4be: 4809 ldr r0, [pc, #36] ; (801a4e4 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a4c0: f000 fd80 bl 801afc4 <iprintf>
}
}
/* If valid is 0 here, there are some fragments missing in the middle
* (since MF == 0 has already arrived). Such datagrams simply time out if
* no more fragments are received... */
return valid ? IP_REASS_VALIDATE_TELEGRAM_FINISHED : IP_REASS_VALIDATE_PBUF_QUEUED;
801a4c4: 6a3b ldr r3, [r7, #32]
801a4c6: 2b00 cmp r3, #0
801a4c8: bf14 ite ne
801a4ca: 2301 movne r3, #1
801a4cc: 2300 moveq r3, #0
801a4ce: b2db uxtb r3, r3
801a4d0: e000 b.n 801a4d4 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
}
/* If we come here, not all fragments were received, yet! */
return IP_REASS_VALIDATE_PBUF_QUEUED; /* not yet valid! */
801a4d2: 2300 movs r3, #0
}
801a4d4: 4618 mov r0, r3
801a4d6: 3730 adds r7, #48 ; 0x30
801a4d8: 46bd mov sp, r7
801a4da: bd80 pop {r7, pc}
801a4dc: 0801ed14 .word 0x0801ed14
801a4e0: 0801edf8 .word 0x0801edf8
801a4e4: 0801ed5c .word 0x0801ed5c
801a4e8: 0801ee18 .word 0x0801ee18
801a4ec: 0801ee50 .word 0x0801ee50
801a4f0: 0801ee60 .word 0x0801ee60
0801a4f4 <ip4_reass>:
* @param p points to a pbuf chain of the fragment
* @return NULL if reassembly is incomplete, ? otherwise
*/
struct pbuf *
ip4_reass(struct pbuf *p)
{
801a4f4: b580 push {r7, lr}
801a4f6: b08e sub sp, #56 ; 0x38
801a4f8: af00 add r7, sp, #0
801a4fa: 6078 str r0, [r7, #4]
int is_last;
IPFRAG_STATS_INC(ip_frag.recv);
MIB2_STATS_INC(mib2.ipreasmreqds);
fraghdr = (struct ip_hdr *)p->payload;
801a4fc: 687b ldr r3, [r7, #4]
801a4fe: 685b ldr r3, [r3, #4]
801a500: 62bb str r3, [r7, #40] ; 0x28
if (IPH_HL_BYTES(fraghdr) != IP_HLEN) {
801a502: 6abb ldr r3, [r7, #40] ; 0x28
801a504: 781b ldrb r3, [r3, #0]
801a506: f003 030f and.w r3, r3, #15
801a50a: b2db uxtb r3, r3
801a50c: 009b lsls r3, r3, #2
801a50e: b2db uxtb r3, r3
801a510: 2b14 cmp r3, #20
801a512: f040 8167 bne.w 801a7e4 <ip4_reass+0x2f0>
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: IP options currently not supported!\n"));
IPFRAG_STATS_INC(ip_frag.err);
goto nullreturn;
}
offset = IPH_OFFSET_BYTES(fraghdr);
801a516: 6abb ldr r3, [r7, #40] ; 0x28
801a518: 88db ldrh r3, [r3, #6]
801a51a: b29b uxth r3, r3
801a51c: 4618 mov r0, r3
801a51e: f7f4 fc8d bl 800ee3c <lwip_htons>
801a522: 4603 mov r3, r0
801a524: f3c3 030c ubfx r3, r3, #0, #13
801a528: b29b uxth r3, r3
801a52a: 00db lsls r3, r3, #3
801a52c: 84fb strh r3, [r7, #38] ; 0x26
len = lwip_ntohs(IPH_LEN(fraghdr));
801a52e: 6abb ldr r3, [r7, #40] ; 0x28
801a530: 885b ldrh r3, [r3, #2]
801a532: b29b uxth r3, r3
801a534: 4618 mov r0, r3
801a536: f7f4 fc81 bl 800ee3c <lwip_htons>
801a53a: 4603 mov r3, r0
801a53c: 84bb strh r3, [r7, #36] ; 0x24
hlen = IPH_HL_BYTES(fraghdr);
801a53e: 6abb ldr r3, [r7, #40] ; 0x28
801a540: 781b ldrb r3, [r3, #0]
801a542: f003 030f and.w r3, r3, #15
801a546: b2db uxtb r3, r3
801a548: 009b lsls r3, r3, #2
801a54a: f887 3023 strb.w r3, [r7, #35] ; 0x23
if (hlen > len) {
801a54e: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
801a552: b29b uxth r3, r3
801a554: 8cba ldrh r2, [r7, #36] ; 0x24
801a556: 429a cmp r2, r3
801a558: f0c0 8146 bcc.w 801a7e8 <ip4_reass+0x2f4>
/* invalid datagram */
goto nullreturn;
}
len = (u16_t)(len - hlen);
801a55c: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
801a560: b29b uxth r3, r3
801a562: 8cba ldrh r2, [r7, #36] ; 0x24
801a564: 1ad3 subs r3, r2, r3
801a566: 84bb strh r3, [r7, #36] ; 0x24
/* Check if we are allowed to enqueue more datagrams. */
clen = pbuf_clen(p);
801a568: 6878 ldr r0, [r7, #4]
801a56a: f7f6 f8ad bl 80106c8 <pbuf_clen>
801a56e: 4603 mov r3, r0
801a570: 843b strh r3, [r7, #32]
if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) {
801a572: 4b9f ldr r3, [pc, #636] ; (801a7f0 <ip4_reass+0x2fc>)
801a574: 881b ldrh r3, [r3, #0]
801a576: 461a mov r2, r3
801a578: 8c3b ldrh r3, [r7, #32]
801a57a: 4413 add r3, r2
801a57c: 2b0a cmp r3, #10
801a57e: dd10 ble.n 801a5a2 <ip4_reass+0xae>
#if IP_REASS_FREE_OLDEST
if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
801a580: 8c3b ldrh r3, [r7, #32]
801a582: 4619 mov r1, r3
801a584: 6ab8 ldr r0, [r7, #40] ; 0x28
801a586: f7ff fd81 bl 801a08c <ip_reass_remove_oldest_datagram>
801a58a: 4603 mov r3, r0
801a58c: 2b00 cmp r3, #0
801a58e: f000 812d beq.w 801a7ec <ip4_reass+0x2f8>
((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS))
801a592: 4b97 ldr r3, [pc, #604] ; (801a7f0 <ip4_reass+0x2fc>)
801a594: 881b ldrh r3, [r3, #0]
801a596: 461a mov r2, r3
801a598: 8c3b ldrh r3, [r7, #32]
801a59a: 4413 add r3, r2
if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
801a59c: 2b0a cmp r3, #10
801a59e: f300 8125 bgt.w 801a7ec <ip4_reass+0x2f8>
}
}
/* Look for the datagram the fragment belongs to in the current datagram queue,
* remembering the previous in the queue for later dequeueing. */
for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
801a5a2: 4b94 ldr r3, [pc, #592] ; (801a7f4 <ip4_reass+0x300>)
801a5a4: 681b ldr r3, [r3, #0]
801a5a6: 633b str r3, [r7, #48] ; 0x30
801a5a8: e015 b.n 801a5d6 <ip4_reass+0xe2>
/* Check if the incoming fragment matches the one currently present
in the reassembly buffer. If so, we proceed with copying the
fragment into the buffer. */
if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) {
801a5aa: 6b3b ldr r3, [r7, #48] ; 0x30
801a5ac: 695a ldr r2, [r3, #20]
801a5ae: 6abb ldr r3, [r7, #40] ; 0x28
801a5b0: 68db ldr r3, [r3, #12]
801a5b2: 429a cmp r2, r3
801a5b4: d10c bne.n 801a5d0 <ip4_reass+0xdc>
801a5b6: 6b3b ldr r3, [r7, #48] ; 0x30
801a5b8: 699a ldr r2, [r3, #24]
801a5ba: 6abb ldr r3, [r7, #40] ; 0x28
801a5bc: 691b ldr r3, [r3, #16]
801a5be: 429a cmp r2, r3
801a5c0: d106 bne.n 801a5d0 <ip4_reass+0xdc>
801a5c2: 6b3b ldr r3, [r7, #48] ; 0x30
801a5c4: 899a ldrh r2, [r3, #12]
801a5c6: 6abb ldr r3, [r7, #40] ; 0x28
801a5c8: 889b ldrh r3, [r3, #4]
801a5ca: b29b uxth r3, r3
801a5cc: 429a cmp r2, r3
801a5ce: d006 beq.n 801a5de <ip4_reass+0xea>
for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
801a5d0: 6b3b ldr r3, [r7, #48] ; 0x30
801a5d2: 681b ldr r3, [r3, #0]
801a5d4: 633b str r3, [r7, #48] ; 0x30
801a5d6: 6b3b ldr r3, [r7, #48] ; 0x30
801a5d8: 2b00 cmp r3, #0
801a5da: d1e6 bne.n 801a5aa <ip4_reass+0xb6>
801a5dc: e000 b.n 801a5e0 <ip4_reass+0xec>
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: matching previous fragment ID=%"X16_F"\n",
lwip_ntohs(IPH_ID(fraghdr))));
IPFRAG_STATS_INC(ip_frag.cachehit);
break;
801a5de: bf00 nop
}
}
if (ipr == NULL) {
801a5e0: 6b3b ldr r3, [r7, #48] ; 0x30
801a5e2: 2b00 cmp r3, #0
801a5e4: d109 bne.n 801a5fa <ip4_reass+0x106>
/* Enqueue a new datagram into the datagram queue */
ipr = ip_reass_enqueue_new_datagram(fraghdr, clen);
801a5e6: 8c3b ldrh r3, [r7, #32]
801a5e8: 4619 mov r1, r3
801a5ea: 6ab8 ldr r0, [r7, #40] ; 0x28
801a5ec: f7ff fdb0 bl 801a150 <ip_reass_enqueue_new_datagram>
801a5f0: 6338 str r0, [r7, #48] ; 0x30
/* Bail if unable to enqueue */
if (ipr == NULL) {
801a5f2: 6b3b ldr r3, [r7, #48] ; 0x30
801a5f4: 2b00 cmp r3, #0
801a5f6: d11c bne.n 801a632 <ip4_reass+0x13e>
goto nullreturn;
801a5f8: e109 b.n 801a80e <ip4_reass+0x31a>
}
} else {
if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
801a5fa: 6abb ldr r3, [r7, #40] ; 0x28
801a5fc: 88db ldrh r3, [r3, #6]
801a5fe: b29b uxth r3, r3
801a600: 4618 mov r0, r3
801a602: f7f4 fc1b bl 800ee3c <lwip_htons>
801a606: 4603 mov r3, r0
801a608: f3c3 030c ubfx r3, r3, #0, #13
801a60c: 2b00 cmp r3, #0
801a60e: d110 bne.n 801a632 <ip4_reass+0x13e>
((lwip_ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) {
801a610: 6b3b ldr r3, [r7, #48] ; 0x30
801a612: 89db ldrh r3, [r3, #14]
801a614: 4618 mov r0, r3
801a616: f7f4 fc11 bl 800ee3c <lwip_htons>
801a61a: 4603 mov r3, r0
801a61c: f3c3 030c ubfx r3, r3, #0, #13
if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
801a620: 2b00 cmp r3, #0
801a622: d006 beq.n 801a632 <ip4_reass+0x13e>
/* ipr->iphdr is not the header from the first fragment, but fraghdr is
* -> copy fraghdr into ipr->iphdr since we want to have the header
* of the first fragment (for ICMP time exceeded and later, for copying
* all options, if supported)*/
SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN);
801a624: 6b3b ldr r3, [r7, #48] ; 0x30
801a626: 3308 adds r3, #8
801a628: 2214 movs r2, #20
801a62a: 6ab9 ldr r1, [r7, #40] ; 0x28
801a62c: 4618 mov r0, r3
801a62e: f000 fcb3 bl 801af98 <memcpy>
/* At this point, we have either created a new entry or pointing
* to an existing one */
/* check for 'no more fragments', and update queue entry*/
is_last = (IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0;
801a632: 6abb ldr r3, [r7, #40] ; 0x28
801a634: 88db ldrh r3, [r3, #6]
801a636: b29b uxth r3, r3
801a638: f003 0320 and.w r3, r3, #32
801a63c: 2b00 cmp r3, #0
801a63e: bf0c ite eq
801a640: 2301 moveq r3, #1
801a642: 2300 movne r3, #0
801a644: b2db uxtb r3, r3
801a646: 61fb str r3, [r7, #28]
if (is_last) {
801a648: 69fb ldr r3, [r7, #28]
801a64a: 2b00 cmp r3, #0
801a64c: d00e beq.n 801a66c <ip4_reass+0x178>
u16_t datagram_len = (u16_t)(offset + len);
801a64e: 8cfa ldrh r2, [r7, #38] ; 0x26
801a650: 8cbb ldrh r3, [r7, #36] ; 0x24
801a652: 4413 add r3, r2
801a654: 837b strh r3, [r7, #26]
if ((datagram_len < offset) || (datagram_len > (0xFFFF - IP_HLEN))) {
801a656: 8b7a ldrh r2, [r7, #26]
801a658: 8cfb ldrh r3, [r7, #38] ; 0x26
801a65a: 429a cmp r2, r3
801a65c: f0c0 80a0 bcc.w 801a7a0 <ip4_reass+0x2ac>
801a660: 8b7b ldrh r3, [r7, #26]
801a662: f64f 72eb movw r2, #65515 ; 0xffeb
801a666: 4293 cmp r3, r2
801a668: f200 809a bhi.w 801a7a0 <ip4_reass+0x2ac>
goto nullreturn_ipr;
}
}
/* find the right place to insert this pbuf */
/* @todo: trim pbufs if fragments are overlapping */
valid = ip_reass_chain_frag_into_datagram_and_validate(ipr, p, is_last);
801a66c: 69fa ldr r2, [r7, #28]
801a66e: 6879 ldr r1, [r7, #4]
801a670: 6b38 ldr r0, [r7, #48] ; 0x30
801a672: f7ff fdd5 bl 801a220 <ip_reass_chain_frag_into_datagram_and_validate>
801a676: 6178 str r0, [r7, #20]
if (valid == IP_REASS_VALIDATE_PBUF_DROPPED) {
801a678: 697b ldr r3, [r7, #20]
801a67a: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
801a67e: f000 8091 beq.w 801a7a4 <ip4_reass+0x2b0>
/* if we come here, the pbuf has been enqueued */
/* Track the current number of pbufs current 'in-flight', in order to limit
the number of fragments that may be enqueued at any one time
(overflow checked by testing against IP_REASS_MAX_PBUFS) */
ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount + clen);
801a682: 4b5b ldr r3, [pc, #364] ; (801a7f0 <ip4_reass+0x2fc>)
801a684: 881a ldrh r2, [r3, #0]
801a686: 8c3b ldrh r3, [r7, #32]
801a688: 4413 add r3, r2
801a68a: b29a uxth r2, r3
801a68c: 4b58 ldr r3, [pc, #352] ; (801a7f0 <ip4_reass+0x2fc>)
801a68e: 801a strh r2, [r3, #0]
if (is_last) {
801a690: 69fb ldr r3, [r7, #28]
801a692: 2b00 cmp r3, #0
801a694: d00d beq.n 801a6b2 <ip4_reass+0x1be>
u16_t datagram_len = (u16_t)(offset + len);
801a696: 8cfa ldrh r2, [r7, #38] ; 0x26
801a698: 8cbb ldrh r3, [r7, #36] ; 0x24
801a69a: 4413 add r3, r2
801a69c: 827b strh r3, [r7, #18]
ipr->datagram_len = datagram_len;
801a69e: 6b3b ldr r3, [r7, #48] ; 0x30
801a6a0: 8a7a ldrh r2, [r7, #18]
801a6a2: 839a strh r2, [r3, #28]
ipr->flags |= IP_REASS_FLAG_LASTFRAG;
801a6a4: 6b3b ldr r3, [r7, #48] ; 0x30
801a6a6: 7f9b ldrb r3, [r3, #30]
801a6a8: f043 0301 orr.w r3, r3, #1
801a6ac: b2da uxtb r2, r3
801a6ae: 6b3b ldr r3, [r7, #48] ; 0x30
801a6b0: 779a strb r2, [r3, #30]
LWIP_DEBUGF(IP_REASS_DEBUG,
("ip4_reass: last fragment seen, total len %"S16_F"\n",
ipr->datagram_len));
}
if (valid == IP_REASS_VALIDATE_TELEGRAM_FINISHED) {
801a6b2: 697b ldr r3, [r7, #20]
801a6b4: 2b01 cmp r3, #1
801a6b6: d171 bne.n 801a79c <ip4_reass+0x2a8>
struct ip_reassdata *ipr_prev;
/* the totally last fragment (flag more fragments = 0) was received at least
* once AND all fragments are received */
u16_t datagram_len = (u16_t)(ipr->datagram_len + IP_HLEN);
801a6b8: 6b3b ldr r3, [r7, #48] ; 0x30
801a6ba: 8b9b ldrh r3, [r3, #28]
801a6bc: 3314 adds r3, #20
801a6be: 823b strh r3, [r7, #16]
/* save the second pbuf before copying the header over the pointer */
r = ((struct ip_reass_helper *)ipr->p->payload)->next_pbuf;
801a6c0: 6b3b ldr r3, [r7, #48] ; 0x30
801a6c2: 685b ldr r3, [r3, #4]
801a6c4: 685b ldr r3, [r3, #4]
801a6c6: 681b ldr r3, [r3, #0]
801a6c8: 637b str r3, [r7, #52] ; 0x34
/* copy the original ip header back to the first pbuf */
fraghdr = (struct ip_hdr *)(ipr->p->payload);
801a6ca: 6b3b ldr r3, [r7, #48] ; 0x30
801a6cc: 685b ldr r3, [r3, #4]
801a6ce: 685b ldr r3, [r3, #4]
801a6d0: 62bb str r3, [r7, #40] ; 0x28
SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN);
801a6d2: 6b3b ldr r3, [r7, #48] ; 0x30
801a6d4: 3308 adds r3, #8
801a6d6: 2214 movs r2, #20
801a6d8: 4619 mov r1, r3
801a6da: 6ab8 ldr r0, [r7, #40] ; 0x28
801a6dc: f000 fc5c bl 801af98 <memcpy>
IPH_LEN_SET(fraghdr, lwip_htons(datagram_len));
801a6e0: 8a3b ldrh r3, [r7, #16]
801a6e2: 4618 mov r0, r3
801a6e4: f7f4 fbaa bl 800ee3c <lwip_htons>
801a6e8: 4603 mov r3, r0
801a6ea: 461a mov r2, r3
801a6ec: 6abb ldr r3, [r7, #40] ; 0x28
801a6ee: 805a strh r2, [r3, #2]
IPH_OFFSET_SET(fraghdr, 0);
801a6f0: 6abb ldr r3, [r7, #40] ; 0x28
801a6f2: 2200 movs r2, #0
801a6f4: 719a strb r2, [r3, #6]
801a6f6: 2200 movs r2, #0
801a6f8: 71da strb r2, [r3, #7]
IPH_CHKSUM_SET(fraghdr, 0);
801a6fa: 6abb ldr r3, [r7, #40] ; 0x28
801a6fc: 2200 movs r2, #0
801a6fe: 729a strb r2, [r3, #10]
801a700: 2200 movs r2, #0
801a702: 72da strb r2, [r3, #11]
IF__NETIF_CHECKSUM_ENABLED(ip_current_input_netif(), NETIF_CHECKSUM_GEN_IP) {
IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN));
}
#endif /* CHECKSUM_GEN_IP */
p = ipr->p;
801a704: 6b3b ldr r3, [r7, #48] ; 0x30
801a706: 685b ldr r3, [r3, #4]
801a708: 607b str r3, [r7, #4]
/* chain together the pbufs contained within the reass_data list. */
while (r != NULL) {
801a70a: e00d b.n 801a728 <ip4_reass+0x234>
iprh = (struct ip_reass_helper *)r->payload;
801a70c: 6b7b ldr r3, [r7, #52] ; 0x34
801a70e: 685b ldr r3, [r3, #4]
801a710: 60fb str r3, [r7, #12]
/* hide the ip header for every succeeding fragment */
pbuf_remove_header(r, IP_HLEN);
801a712: 2114 movs r1, #20
801a714: 6b78 ldr r0, [r7, #52] ; 0x34
801a716: f7f5 fec3 bl 80104a0 <pbuf_remove_header>
pbuf_cat(p, r);
801a71a: 6b79 ldr r1, [r7, #52] ; 0x34
801a71c: 6878 ldr r0, [r7, #4]
801a71e: f7f6 f813 bl 8010748 <pbuf_cat>
r = iprh->next_pbuf;
801a722: 68fb ldr r3, [r7, #12]
801a724: 681b ldr r3, [r3, #0]
801a726: 637b str r3, [r7, #52] ; 0x34
while (r != NULL) {
801a728: 6b7b ldr r3, [r7, #52] ; 0x34
801a72a: 2b00 cmp r3, #0
801a72c: d1ee bne.n 801a70c <ip4_reass+0x218>
}
/* find the previous entry in the linked list */
if (ipr == reassdatagrams) {
801a72e: 4b31 ldr r3, [pc, #196] ; (801a7f4 <ip4_reass+0x300>)
801a730: 681b ldr r3, [r3, #0]
801a732: 6b3a ldr r2, [r7, #48] ; 0x30
801a734: 429a cmp r2, r3
801a736: d102 bne.n 801a73e <ip4_reass+0x24a>
ipr_prev = NULL;
801a738: 2300 movs r3, #0
801a73a: 62fb str r3, [r7, #44] ; 0x2c
801a73c: e010 b.n 801a760 <ip4_reass+0x26c>
} else {
for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
801a73e: 4b2d ldr r3, [pc, #180] ; (801a7f4 <ip4_reass+0x300>)
801a740: 681b ldr r3, [r3, #0]
801a742: 62fb str r3, [r7, #44] ; 0x2c
801a744: e007 b.n 801a756 <ip4_reass+0x262>
if (ipr_prev->next == ipr) {
801a746: 6afb ldr r3, [r7, #44] ; 0x2c
801a748: 681b ldr r3, [r3, #0]
801a74a: 6b3a ldr r2, [r7, #48] ; 0x30
801a74c: 429a cmp r2, r3
801a74e: d006 beq.n 801a75e <ip4_reass+0x26a>
for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
801a750: 6afb ldr r3, [r7, #44] ; 0x2c
801a752: 681b ldr r3, [r3, #0]
801a754: 62fb str r3, [r7, #44] ; 0x2c
801a756: 6afb ldr r3, [r7, #44] ; 0x2c
801a758: 2b00 cmp r3, #0
801a75a: d1f4 bne.n 801a746 <ip4_reass+0x252>
801a75c: e000 b.n 801a760 <ip4_reass+0x26c>
break;
801a75e: bf00 nop
}
}
}
/* release the sources allocate for the fragment queue entry */
ip_reass_dequeue_datagram(ipr, ipr_prev);
801a760: 6af9 ldr r1, [r7, #44] ; 0x2c
801a762: 6b38 ldr r0, [r7, #48] ; 0x30
801a764: f7ff fd2e bl 801a1c4 <ip_reass_dequeue_datagram>
/* and adjust the number of pbufs currently queued for reassembly. */
clen = pbuf_clen(p);
801a768: 6878 ldr r0, [r7, #4]
801a76a: f7f5 ffad bl 80106c8 <pbuf_clen>
801a76e: 4603 mov r3, r0
801a770: 843b strh r3, [r7, #32]
LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= clen);
801a772: 4b1f ldr r3, [pc, #124] ; (801a7f0 <ip4_reass+0x2fc>)
801a774: 881b ldrh r3, [r3, #0]
801a776: 8c3a ldrh r2, [r7, #32]
801a778: 429a cmp r2, r3
801a77a: d906 bls.n 801a78a <ip4_reass+0x296>
801a77c: 4b1e ldr r3, [pc, #120] ; (801a7f8 <ip4_reass+0x304>)
801a77e: f240 229b movw r2, #667 ; 0x29b
801a782: 491e ldr r1, [pc, #120] ; (801a7fc <ip4_reass+0x308>)
801a784: 481e ldr r0, [pc, #120] ; (801a800 <ip4_reass+0x30c>)
801a786: f000 fc1d bl 801afc4 <iprintf>
ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - clen);
801a78a: 4b19 ldr r3, [pc, #100] ; (801a7f0 <ip4_reass+0x2fc>)
801a78c: 881a ldrh r2, [r3, #0]
801a78e: 8c3b ldrh r3, [r7, #32]
801a790: 1ad3 subs r3, r2, r3
801a792: b29a uxth r2, r3
801a794: 4b16 ldr r3, [pc, #88] ; (801a7f0 <ip4_reass+0x2fc>)
801a796: 801a strh r2, [r3, #0]
MIB2_STATS_INC(mib2.ipreasmoks);
/* Return the pbuf chain */
return p;
801a798: 687b ldr r3, [r7, #4]
801a79a: e03c b.n 801a816 <ip4_reass+0x322>
}
/* the datagram is not (yet?) reassembled completely */
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount));
return NULL;
801a79c: 2300 movs r3, #0
801a79e: e03a b.n 801a816 <ip4_reass+0x322>
goto nullreturn_ipr;
801a7a0: bf00 nop
801a7a2: e000 b.n 801a7a6 <ip4_reass+0x2b2>
goto nullreturn_ipr;
801a7a4: bf00 nop
nullreturn_ipr:
LWIP_ASSERT("ipr != NULL", ipr != NULL);
801a7a6: 6b3b ldr r3, [r7, #48] ; 0x30
801a7a8: 2b00 cmp r3, #0
801a7aa: d106 bne.n 801a7ba <ip4_reass+0x2c6>
801a7ac: 4b12 ldr r3, [pc, #72] ; (801a7f8 <ip4_reass+0x304>)
801a7ae: f44f 722a mov.w r2, #680 ; 0x2a8
801a7b2: 4914 ldr r1, [pc, #80] ; (801a804 <ip4_reass+0x310>)
801a7b4: 4812 ldr r0, [pc, #72] ; (801a800 <ip4_reass+0x30c>)
801a7b6: f000 fc05 bl 801afc4 <iprintf>
if (ipr->p == NULL) {
801a7ba: 6b3b ldr r3, [r7, #48] ; 0x30
801a7bc: 685b ldr r3, [r3, #4]
801a7be: 2b00 cmp r3, #0
801a7c0: d124 bne.n 801a80c <ip4_reass+0x318>
/* dropped pbuf after creating a new datagram entry: remove the entry, too */
LWIP_ASSERT("not firstalthough just enqueued", ipr == reassdatagrams);
801a7c2: 4b0c ldr r3, [pc, #48] ; (801a7f4 <ip4_reass+0x300>)
801a7c4: 681b ldr r3, [r3, #0]
801a7c6: 6b3a ldr r2, [r7, #48] ; 0x30
801a7c8: 429a cmp r2, r3
801a7ca: d006 beq.n 801a7da <ip4_reass+0x2e6>
801a7cc: 4b0a ldr r3, [pc, #40] ; (801a7f8 <ip4_reass+0x304>)
801a7ce: f240 22ab movw r2, #683 ; 0x2ab
801a7d2: 490d ldr r1, [pc, #52] ; (801a808 <ip4_reass+0x314>)
801a7d4: 480a ldr r0, [pc, #40] ; (801a800 <ip4_reass+0x30c>)
801a7d6: f000 fbf5 bl 801afc4 <iprintf>
ip_reass_dequeue_datagram(ipr, NULL);
801a7da: 2100 movs r1, #0
801a7dc: 6b38 ldr r0, [r7, #48] ; 0x30
801a7de: f7ff fcf1 bl 801a1c4 <ip_reass_dequeue_datagram>
801a7e2: e014 b.n 801a80e <ip4_reass+0x31a>
goto nullreturn;
801a7e4: bf00 nop
801a7e6: e012 b.n 801a80e <ip4_reass+0x31a>
goto nullreturn;
801a7e8: bf00 nop
801a7ea: e010 b.n 801a80e <ip4_reass+0x31a>
goto nullreturn;
801a7ec: bf00 nop
801a7ee: e00e b.n 801a80e <ip4_reass+0x31a>
801a7f0: 20008864 .word 0x20008864
801a7f4: 20008860 .word 0x20008860
801a7f8: 0801ed14 .word 0x0801ed14
801a7fc: 0801ee84 .word 0x0801ee84
801a800: 0801ed5c .word 0x0801ed5c
801a804: 0801eea0 .word 0x0801eea0
801a808: 0801eeac .word 0x0801eeac
}
nullreturn:
801a80c: bf00 nop
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: nullreturn\n"));
IPFRAG_STATS_INC(ip_frag.drop);
pbuf_free(p);
801a80e: 6878 ldr r0, [r7, #4]
801a810: f7f5 fecc bl 80105ac <pbuf_free>
return NULL;
801a814: 2300 movs r3, #0
}
801a816: 4618 mov r0, r3
801a818: 3738 adds r7, #56 ; 0x38
801a81a: 46bd mov sp, r7
801a81c: bd80 pop {r7, pc}
801a81e: bf00 nop
0801a820 <ip_frag_alloc_pbuf_custom_ref>:
#if IP_FRAG
#if !LWIP_NETIF_TX_SINGLE_PBUF
/** Allocate a new struct pbuf_custom_ref */
static struct pbuf_custom_ref *
ip_frag_alloc_pbuf_custom_ref(void)
{
801a820: b580 push {r7, lr}
801a822: af00 add r7, sp, #0
return (struct pbuf_custom_ref *)memp_malloc(MEMP_FRAG_PBUF);
801a824: 2005 movs r0, #5
801a826: f7f4 ffbf bl 800f7a8 <memp_malloc>
801a82a: 4603 mov r3, r0
}
801a82c: 4618 mov r0, r3
801a82e: bd80 pop {r7, pc}
0801a830 <ip_frag_free_pbuf_custom_ref>:
/** Free a struct pbuf_custom_ref */
static void
ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref *p)
{
801a830: b580 push {r7, lr}
801a832: b082 sub sp, #8
801a834: af00 add r7, sp, #0
801a836: 6078 str r0, [r7, #4]
LWIP_ASSERT("p != NULL", p != NULL);
801a838: 687b ldr r3, [r7, #4]
801a83a: 2b00 cmp r3, #0
801a83c: d106 bne.n 801a84c <ip_frag_free_pbuf_custom_ref+0x1c>
801a83e: 4b07 ldr r3, [pc, #28] ; (801a85c <ip_frag_free_pbuf_custom_ref+0x2c>)
801a840: f44f 7231 mov.w r2, #708 ; 0x2c4
801a844: 4906 ldr r1, [pc, #24] ; (801a860 <ip_frag_free_pbuf_custom_ref+0x30>)
801a846: 4807 ldr r0, [pc, #28] ; (801a864 <ip_frag_free_pbuf_custom_ref+0x34>)
801a848: f000 fbbc bl 801afc4 <iprintf>
memp_free(MEMP_FRAG_PBUF, p);
801a84c: 6879 ldr r1, [r7, #4]
801a84e: 2005 movs r0, #5
801a850: f7f4 fffc bl 800f84c <memp_free>
}
801a854: bf00 nop
801a856: 3708 adds r7, #8
801a858: 46bd mov sp, r7
801a85a: bd80 pop {r7, pc}
801a85c: 0801ed14 .word 0x0801ed14
801a860: 0801eecc .word 0x0801eecc
801a864: 0801ed5c .word 0x0801ed5c
0801a868 <ipfrag_free_pbuf_custom>:
/** Free-callback function to free a 'struct pbuf_custom_ref', called by
* pbuf_free. */
static void
ipfrag_free_pbuf_custom(struct pbuf *p)
{
801a868: b580 push {r7, lr}
801a86a: b084 sub sp, #16
801a86c: af00 add r7, sp, #0
801a86e: 6078 str r0, [r7, #4]
struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref *)p;
801a870: 687b ldr r3, [r7, #4]
801a872: 60fb str r3, [r7, #12]
LWIP_ASSERT("pcr != NULL", pcr != NULL);
801a874: 68fb ldr r3, [r7, #12]
801a876: 2b00 cmp r3, #0
801a878: d106 bne.n 801a888 <ipfrag_free_pbuf_custom+0x20>
801a87a: 4b11 ldr r3, [pc, #68] ; (801a8c0 <ipfrag_free_pbuf_custom+0x58>)
801a87c: f240 22ce movw r2, #718 ; 0x2ce
801a880: 4910 ldr r1, [pc, #64] ; (801a8c4 <ipfrag_free_pbuf_custom+0x5c>)
801a882: 4811 ldr r0, [pc, #68] ; (801a8c8 <ipfrag_free_pbuf_custom+0x60>)
801a884: f000 fb9e bl 801afc4 <iprintf>
LWIP_ASSERT("pcr == p", (void *)pcr == (void *)p);
801a888: 68fa ldr r2, [r7, #12]
801a88a: 687b ldr r3, [r7, #4]
801a88c: 429a cmp r2, r3
801a88e: d006 beq.n 801a89e <ipfrag_free_pbuf_custom+0x36>
801a890: 4b0b ldr r3, [pc, #44] ; (801a8c0 <ipfrag_free_pbuf_custom+0x58>)
801a892: f240 22cf movw r2, #719 ; 0x2cf
801a896: 490d ldr r1, [pc, #52] ; (801a8cc <ipfrag_free_pbuf_custom+0x64>)
801a898: 480b ldr r0, [pc, #44] ; (801a8c8 <ipfrag_free_pbuf_custom+0x60>)
801a89a: f000 fb93 bl 801afc4 <iprintf>
if (pcr->original != NULL) {
801a89e: 68fb ldr r3, [r7, #12]
801a8a0: 695b ldr r3, [r3, #20]
801a8a2: 2b00 cmp r3, #0
801a8a4: d004 beq.n 801a8b0 <ipfrag_free_pbuf_custom+0x48>
pbuf_free(pcr->original);
801a8a6: 68fb ldr r3, [r7, #12]
801a8a8: 695b ldr r3, [r3, #20]
801a8aa: 4618 mov r0, r3
801a8ac: f7f5 fe7e bl 80105ac <pbuf_free>
}
ip_frag_free_pbuf_custom_ref(pcr);
801a8b0: 68f8 ldr r0, [r7, #12]
801a8b2: f7ff ffbd bl 801a830 <ip_frag_free_pbuf_custom_ref>
}
801a8b6: bf00 nop
801a8b8: 3710 adds r7, #16
801a8ba: 46bd mov sp, r7
801a8bc: bd80 pop {r7, pc}
801a8be: bf00 nop
801a8c0: 0801ed14 .word 0x0801ed14
801a8c4: 0801eed8 .word 0x0801eed8
801a8c8: 0801ed5c .word 0x0801ed5c
801a8cc: 0801eee4 .word 0x0801eee4
0801a8d0 <ip4_frag>:
*
* @return ERR_OK if sent successfully, err_t otherwise
*/
err_t
ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest)
{
801a8d0: b580 push {r7, lr}
801a8d2: b094 sub sp, #80 ; 0x50
801a8d4: af02 add r7, sp, #8
801a8d6: 60f8 str r0, [r7, #12]
801a8d8: 60b9 str r1, [r7, #8]
801a8da: 607a str r2, [r7, #4]
struct pbuf *rambuf;
#if !LWIP_NETIF_TX_SINGLE_PBUF
struct pbuf *newpbuf;
u16_t newpbuflen = 0;
801a8dc: 2300 movs r3, #0
801a8de: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
u16_t left_to_copy;
#endif
struct ip_hdr *original_iphdr;
struct ip_hdr *iphdr;
const u16_t nfb = (u16_t)((netif->mtu - IP_HLEN) / 8);
801a8e2: 68bb ldr r3, [r7, #8]
801a8e4: 8d1b ldrh r3, [r3, #40] ; 0x28
801a8e6: 3b14 subs r3, #20
801a8e8: 2b00 cmp r3, #0
801a8ea: da00 bge.n 801a8ee <ip4_frag+0x1e>
801a8ec: 3307 adds r3, #7
801a8ee: 10db asrs r3, r3, #3
801a8f0: 877b strh r3, [r7, #58] ; 0x3a
u16_t left, fragsize;
u16_t ofo;
int last;
u16_t poff = IP_HLEN;
801a8f2: 2314 movs r3, #20
801a8f4: 87fb strh r3, [r7, #62] ; 0x3e
u16_t tmp;
int mf_set;
original_iphdr = (struct ip_hdr *)p->payload;
801a8f6: 68fb ldr r3, [r7, #12]
801a8f8: 685b ldr r3, [r3, #4]
801a8fa: 637b str r3, [r7, #52] ; 0x34
iphdr = original_iphdr;
801a8fc: 6b7b ldr r3, [r7, #52] ; 0x34
801a8fe: 633b str r3, [r7, #48] ; 0x30
if (IPH_HL_BYTES(iphdr) != IP_HLEN) {
801a900: 6b3b ldr r3, [r7, #48] ; 0x30
801a902: 781b ldrb r3, [r3, #0]
801a904: f003 030f and.w r3, r3, #15
801a908: b2db uxtb r3, r3
801a90a: 009b lsls r3, r3, #2
801a90c: b2db uxtb r3, r3
801a90e: 2b14 cmp r3, #20
801a910: d002 beq.n 801a918 <ip4_frag+0x48>
/* ip4_frag() does not support IP options */
return ERR_VAL;
801a912: f06f 0305 mvn.w r3, #5
801a916: e110 b.n 801ab3a <ip4_frag+0x26a>
}
LWIP_ERROR("ip4_frag(): pbuf too short", p->len >= IP_HLEN, return ERR_VAL);
801a918: 68fb ldr r3, [r7, #12]
801a91a: 895b ldrh r3, [r3, #10]
801a91c: 2b13 cmp r3, #19
801a91e: d809 bhi.n 801a934 <ip4_frag+0x64>
801a920: 4b88 ldr r3, [pc, #544] ; (801ab44 <ip4_frag+0x274>)
801a922: f44f 723f mov.w r2, #764 ; 0x2fc
801a926: 4988 ldr r1, [pc, #544] ; (801ab48 <ip4_frag+0x278>)
801a928: 4888 ldr r0, [pc, #544] ; (801ab4c <ip4_frag+0x27c>)
801a92a: f000 fb4b bl 801afc4 <iprintf>
801a92e: f06f 0305 mvn.w r3, #5
801a932: e102 b.n 801ab3a <ip4_frag+0x26a>
/* Save original offset */
tmp = lwip_ntohs(IPH_OFFSET(iphdr));
801a934: 6b3b ldr r3, [r7, #48] ; 0x30
801a936: 88db ldrh r3, [r3, #6]
801a938: b29b uxth r3, r3
801a93a: 4618 mov r0, r3
801a93c: f7f4 fa7e bl 800ee3c <lwip_htons>
801a940: 4603 mov r3, r0
801a942: 87bb strh r3, [r7, #60] ; 0x3c
ofo = tmp & IP_OFFMASK;
801a944: 8fbb ldrh r3, [r7, #60] ; 0x3c
801a946: f3c3 030c ubfx r3, r3, #0, #13
801a94a: f8a7 3040 strh.w r3, [r7, #64] ; 0x40
/* already fragmented? if so, the last fragment we create must have MF, too */
mf_set = tmp & IP_MF;
801a94e: 8fbb ldrh r3, [r7, #60] ; 0x3c
801a950: f403 5300 and.w r3, r3, #8192 ; 0x2000
801a954: 62fb str r3, [r7, #44] ; 0x2c
left = (u16_t)(p->tot_len - IP_HLEN);
801a956: 68fb ldr r3, [r7, #12]
801a958: 891b ldrh r3, [r3, #8]
801a95a: 3b14 subs r3, #20
801a95c: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
while (left) {
801a960: e0e1 b.n 801ab26 <ip4_frag+0x256>
/* Fill this fragment */
fragsize = LWIP_MIN(left, (u16_t)(nfb * 8));
801a962: 8f7b ldrh r3, [r7, #58] ; 0x3a
801a964: 00db lsls r3, r3, #3
801a966: b29b uxth r3, r3
801a968: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
801a96c: 4293 cmp r3, r2
801a96e: bf28 it cs
801a970: 4613 movcs r3, r2
801a972: 857b strh r3, [r7, #42] ; 0x2a
/* When not using a static buffer, create a chain of pbufs.
* The first will be a PBUF_RAM holding the link and IP header.
* The rest will be PBUF_REFs mirroring the pbuf chain to be fragged,
* but limited to the size of an mtu.
*/
rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM);
801a974: f44f 7220 mov.w r2, #640 ; 0x280
801a978: 2114 movs r1, #20
801a97a: 200e movs r0, #14
801a97c: f7f5 fb32 bl 800ffe4 <pbuf_alloc>
801a980: 6278 str r0, [r7, #36] ; 0x24
if (rambuf == NULL) {
801a982: 6a7b ldr r3, [r7, #36] ; 0x24
801a984: 2b00 cmp r3, #0
801a986: f000 80d5 beq.w 801ab34 <ip4_frag+0x264>
goto memerr;
}
LWIP_ASSERT("this needs a pbuf in one piece!",
801a98a: 6a7b ldr r3, [r7, #36] ; 0x24
801a98c: 895b ldrh r3, [r3, #10]
801a98e: 2b13 cmp r3, #19
801a990: d806 bhi.n 801a9a0 <ip4_frag+0xd0>
801a992: 4b6c ldr r3, [pc, #432] ; (801ab44 <ip4_frag+0x274>)
801a994: f44f 7249 mov.w r2, #804 ; 0x324
801a998: 496d ldr r1, [pc, #436] ; (801ab50 <ip4_frag+0x280>)
801a99a: 486c ldr r0, [pc, #432] ; (801ab4c <ip4_frag+0x27c>)
801a99c: f000 fb12 bl 801afc4 <iprintf>
(rambuf->len >= (IP_HLEN)));
SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN);
801a9a0: 6a7b ldr r3, [r7, #36] ; 0x24
801a9a2: 685b ldr r3, [r3, #4]
801a9a4: 2214 movs r2, #20
801a9a6: 6b79 ldr r1, [r7, #52] ; 0x34
801a9a8: 4618 mov r0, r3
801a9aa: f000 faf5 bl 801af98 <memcpy>
iphdr = (struct ip_hdr *)rambuf->payload;
801a9ae: 6a7b ldr r3, [r7, #36] ; 0x24
801a9b0: 685b ldr r3, [r3, #4]
801a9b2: 633b str r3, [r7, #48] ; 0x30
left_to_copy = fragsize;
801a9b4: 8d7b ldrh r3, [r7, #42] ; 0x2a
801a9b6: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
while (left_to_copy) {
801a9ba: e064 b.n 801aa86 <ip4_frag+0x1b6>
struct pbuf_custom_ref *pcr;
u16_t plen = (u16_t)(p->len - poff);
801a9bc: 68fb ldr r3, [r7, #12]
801a9be: 895a ldrh r2, [r3, #10]
801a9c0: 8ffb ldrh r3, [r7, #62] ; 0x3e
801a9c2: 1ad3 subs r3, r2, r3
801a9c4: 83fb strh r3, [r7, #30]
LWIP_ASSERT("p->len >= poff", p->len >= poff);
801a9c6: 68fb ldr r3, [r7, #12]
801a9c8: 895b ldrh r3, [r3, #10]
801a9ca: 8ffa ldrh r2, [r7, #62] ; 0x3e
801a9cc: 429a cmp r2, r3
801a9ce: d906 bls.n 801a9de <ip4_frag+0x10e>
801a9d0: 4b5c ldr r3, [pc, #368] ; (801ab44 <ip4_frag+0x274>)
801a9d2: f240 322d movw r2, #813 ; 0x32d
801a9d6: 495f ldr r1, [pc, #380] ; (801ab54 <ip4_frag+0x284>)
801a9d8: 485c ldr r0, [pc, #368] ; (801ab4c <ip4_frag+0x27c>)
801a9da: f000 faf3 bl 801afc4 <iprintf>
newpbuflen = LWIP_MIN(left_to_copy, plen);
801a9de: 8bfa ldrh r2, [r7, #30]
801a9e0: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
801a9e4: 4293 cmp r3, r2
801a9e6: bf28 it cs
801a9e8: 4613 movcs r3, r2
801a9ea: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
/* Is this pbuf already empty? */
if (!newpbuflen) {
801a9ee: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46
801a9f2: 2b00 cmp r3, #0
801a9f4: d105 bne.n 801aa02 <ip4_frag+0x132>
poff = 0;
801a9f6: 2300 movs r3, #0
801a9f8: 87fb strh r3, [r7, #62] ; 0x3e
p = p->next;
801a9fa: 68fb ldr r3, [r7, #12]
801a9fc: 681b ldr r3, [r3, #0]
801a9fe: 60fb str r3, [r7, #12]
continue;
801aa00: e041 b.n 801aa86 <ip4_frag+0x1b6>
}
pcr = ip_frag_alloc_pbuf_custom_ref();
801aa02: f7ff ff0d bl 801a820 <ip_frag_alloc_pbuf_custom_ref>
801aa06: 61b8 str r0, [r7, #24]
if (pcr == NULL) {
801aa08: 69bb ldr r3, [r7, #24]
801aa0a: 2b00 cmp r3, #0
801aa0c: d103 bne.n 801aa16 <ip4_frag+0x146>
pbuf_free(rambuf);
801aa0e: 6a78 ldr r0, [r7, #36] ; 0x24
801aa10: f7f5 fdcc bl 80105ac <pbuf_free>
goto memerr;
801aa14: e08f b.n 801ab36 <ip4_frag+0x266>
}
/* Mirror this pbuf, although we might not need all of it. */
newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
801aa16: 69b8 ldr r0, [r7, #24]
(u8_t *)p->payload + poff, newpbuflen);
801aa18: 68fb ldr r3, [r7, #12]
801aa1a: 685a ldr r2, [r3, #4]
newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
801aa1c: 8ffb ldrh r3, [r7, #62] ; 0x3e
801aa1e: 4413 add r3, r2
801aa20: f8b7 1046 ldrh.w r1, [r7, #70] ; 0x46
801aa24: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46
801aa28: 9201 str r2, [sp, #4]
801aa2a: 9300 str r3, [sp, #0]
801aa2c: 4603 mov r3, r0
801aa2e: 2241 movs r2, #65 ; 0x41
801aa30: 2000 movs r0, #0
801aa32: f7f5 fc01 bl 8010238 <pbuf_alloced_custom>
801aa36: 6178 str r0, [r7, #20]
if (newpbuf == NULL) {
801aa38: 697b ldr r3, [r7, #20]
801aa3a: 2b00 cmp r3, #0
801aa3c: d106 bne.n 801aa4c <ip4_frag+0x17c>
ip_frag_free_pbuf_custom_ref(pcr);
801aa3e: 69b8 ldr r0, [r7, #24]
801aa40: f7ff fef6 bl 801a830 <ip_frag_free_pbuf_custom_ref>
pbuf_free(rambuf);
801aa44: 6a78 ldr r0, [r7, #36] ; 0x24
801aa46: f7f5 fdb1 bl 80105ac <pbuf_free>
goto memerr;
801aa4a: e074 b.n 801ab36 <ip4_frag+0x266>
}
pbuf_ref(p);
801aa4c: 68f8 ldr r0, [r7, #12]
801aa4e: f7f5 fe53 bl 80106f8 <pbuf_ref>
pcr->original = p;
801aa52: 69bb ldr r3, [r7, #24]
801aa54: 68fa ldr r2, [r7, #12]
801aa56: 615a str r2, [r3, #20]
pcr->pc.custom_free_function = ipfrag_free_pbuf_custom;
801aa58: 69bb ldr r3, [r7, #24]
801aa5a: 4a3f ldr r2, [pc, #252] ; (801ab58 <ip4_frag+0x288>)
801aa5c: 611a str r2, [r3, #16]
/* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain
* so that it is removed when pbuf_dechain is later called on rambuf.
*/
pbuf_cat(rambuf, newpbuf);
801aa5e: 6979 ldr r1, [r7, #20]
801aa60: 6a78 ldr r0, [r7, #36] ; 0x24
801aa62: f7f5 fe71 bl 8010748 <pbuf_cat>
left_to_copy = (u16_t)(left_to_copy - newpbuflen);
801aa66: f8b7 2044 ldrh.w r2, [r7, #68] ; 0x44
801aa6a: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46
801aa6e: 1ad3 subs r3, r2, r3
801aa70: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
if (left_to_copy) {
801aa74: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
801aa78: 2b00 cmp r3, #0
801aa7a: d004 beq.n 801aa86 <ip4_frag+0x1b6>
poff = 0;
801aa7c: 2300 movs r3, #0
801aa7e: 87fb strh r3, [r7, #62] ; 0x3e
p = p->next;
801aa80: 68fb ldr r3, [r7, #12]
801aa82: 681b ldr r3, [r3, #0]
801aa84: 60fb str r3, [r7, #12]
while (left_to_copy) {
801aa86: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
801aa8a: 2b00 cmp r3, #0
801aa8c: d196 bne.n 801a9bc <ip4_frag+0xec>
}
}
poff = (u16_t)(poff + newpbuflen);
801aa8e: 8ffa ldrh r2, [r7, #62] ; 0x3e
801aa90: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46
801aa94: 4413 add r3, r2
801aa96: 87fb strh r3, [r7, #62] ; 0x3e
#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
/* Correct header */
last = (left <= netif->mtu - IP_HLEN);
801aa98: 68bb ldr r3, [r7, #8]
801aa9a: 8d1b ldrh r3, [r3, #40] ; 0x28
801aa9c: f1a3 0213 sub.w r2, r3, #19
801aaa0: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
801aaa4: 429a cmp r2, r3
801aaa6: bfcc ite gt
801aaa8: 2301 movgt r3, #1
801aaaa: 2300 movle r3, #0
801aaac: b2db uxtb r3, r3
801aaae: 623b str r3, [r7, #32]
/* Set new offset and MF flag */
tmp = (IP_OFFMASK & (ofo));
801aab0: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40
801aab4: f3c3 030c ubfx r3, r3, #0, #13
801aab8: 87bb strh r3, [r7, #60] ; 0x3c
if (!last || mf_set) {
801aaba: 6a3b ldr r3, [r7, #32]
801aabc: 2b00 cmp r3, #0
801aabe: d002 beq.n 801aac6 <ip4_frag+0x1f6>
801aac0: 6afb ldr r3, [r7, #44] ; 0x2c
801aac2: 2b00 cmp r3, #0
801aac4: d003 beq.n 801aace <ip4_frag+0x1fe>
/* the last fragment has MF set if the input frame had it */
tmp = tmp | IP_MF;
801aac6: 8fbb ldrh r3, [r7, #60] ; 0x3c
801aac8: f443 5300 orr.w r3, r3, #8192 ; 0x2000
801aacc: 87bb strh r3, [r7, #60] ; 0x3c
}
IPH_OFFSET_SET(iphdr, lwip_htons(tmp));
801aace: 8fbb ldrh r3, [r7, #60] ; 0x3c
801aad0: 4618 mov r0, r3
801aad2: f7f4 f9b3 bl 800ee3c <lwip_htons>
801aad6: 4603 mov r3, r0
801aad8: 461a mov r2, r3
801aada: 6b3b ldr r3, [r7, #48] ; 0x30
801aadc: 80da strh r2, [r3, #6]
IPH_LEN_SET(iphdr, lwip_htons((u16_t)(fragsize + IP_HLEN)));
801aade: 8d7b ldrh r3, [r7, #42] ; 0x2a
801aae0: 3314 adds r3, #20
801aae2: b29b uxth r3, r3
801aae4: 4618 mov r0, r3
801aae6: f7f4 f9a9 bl 800ee3c <lwip_htons>
801aaea: 4603 mov r3, r0
801aaec: 461a mov r2, r3
801aaee: 6b3b ldr r3, [r7, #48] ; 0x30
801aaf0: 805a strh r2, [r3, #2]
IPH_CHKSUM_SET(iphdr, 0);
801aaf2: 6b3b ldr r3, [r7, #48] ; 0x30
801aaf4: 2200 movs r2, #0
801aaf6: 729a strb r2, [r3, #10]
801aaf8: 2200 movs r2, #0
801aafa: 72da strb r2, [r3, #11]
#endif /* CHECKSUM_GEN_IP */
/* No need for separate header pbuf - we allowed room for it in rambuf
* when allocated.
*/
netif->output(netif, rambuf, dest);
801aafc: 68bb ldr r3, [r7, #8]
801aafe: 695b ldr r3, [r3, #20]
801ab00: 687a ldr r2, [r7, #4]
801ab02: 6a79 ldr r1, [r7, #36] ; 0x24
801ab04: 68b8 ldr r0, [r7, #8]
801ab06: 4798 blx r3
* recreate it next time round the loop. If we're lucky the hardware
* will have already sent the packet, the free will really free, and
* there will be zero memory penalty.
*/
pbuf_free(rambuf);
801ab08: 6a78 ldr r0, [r7, #36] ; 0x24
801ab0a: f7f5 fd4f bl 80105ac <pbuf_free>
left = (u16_t)(left - fragsize);
801ab0e: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
801ab12: 8d7b ldrh r3, [r7, #42] ; 0x2a
801ab14: 1ad3 subs r3, r2, r3
801ab16: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
ofo = (u16_t)(ofo + nfb);
801ab1a: f8b7 2040 ldrh.w r2, [r7, #64] ; 0x40
801ab1e: 8f7b ldrh r3, [r7, #58] ; 0x3a
801ab20: 4413 add r3, r2
801ab22: f8a7 3040 strh.w r3, [r7, #64] ; 0x40
while (left) {
801ab26: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
801ab2a: 2b00 cmp r3, #0
801ab2c: f47f af19 bne.w 801a962 <ip4_frag+0x92>
}
MIB2_STATS_INC(mib2.ipfragoks);
return ERR_OK;
801ab30: 2300 movs r3, #0
801ab32: e002 b.n 801ab3a <ip4_frag+0x26a>
goto memerr;
801ab34: bf00 nop
memerr:
MIB2_STATS_INC(mib2.ipfragfails);
return ERR_MEM;
801ab36: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
}
801ab3a: 4618 mov r0, r3
801ab3c: 3748 adds r7, #72 ; 0x48
801ab3e: 46bd mov sp, r7
801ab40: bd80 pop {r7, pc}
801ab42: bf00 nop
801ab44: 0801ed14 .word 0x0801ed14
801ab48: 0801eef0 .word 0x0801eef0
801ab4c: 0801ed5c .word 0x0801ed5c
801ab50: 0801ef0c .word 0x0801ef0c
801ab54: 0801ef2c .word 0x0801ef2c
801ab58: 0801a869 .word 0x0801a869
0801ab5c <ethernet_input>:
* @see ETHARP_SUPPORT_VLAN
* @see LWIP_HOOK_VLAN_CHECK
*/
err_t
ethernet_input(struct pbuf *p, struct netif *netif)
{
801ab5c: b580 push {r7, lr}
801ab5e: b086 sub sp, #24
801ab60: af00 add r7, sp, #0
801ab62: 6078 str r0, [r7, #4]
801ab64: 6039 str r1, [r7, #0]
struct eth_hdr *ethhdr;
u16_t type;
#if LWIP_ARP || ETHARP_SUPPORT_VLAN || LWIP_IPV6
u16_t next_hdr_offset = SIZEOF_ETH_HDR;
801ab66: 230e movs r3, #14
801ab68: 82fb strh r3, [r7, #22]
#endif /* LWIP_ARP || ETHARP_SUPPORT_VLAN */
LWIP_ASSERT_CORE_LOCKED();
if (p->len <= SIZEOF_ETH_HDR) {
801ab6a: 687b ldr r3, [r7, #4]
801ab6c: 895b ldrh r3, [r3, #10]
801ab6e: 2b0e cmp r3, #14
801ab70: d96e bls.n 801ac50 <ethernet_input+0xf4>
ETHARP_STATS_INC(etharp.drop);
MIB2_STATS_NETIF_INC(netif, ifinerrors);
goto free_and_return;
}
if (p->if_idx == NETIF_NO_INDEX) {
801ab72: 687b ldr r3, [r7, #4]
801ab74: 7bdb ldrb r3, [r3, #15]
801ab76: 2b00 cmp r3, #0
801ab78: d106 bne.n 801ab88 <ethernet_input+0x2c>
p->if_idx = netif_get_index(netif);
801ab7a: 683b ldr r3, [r7, #0]
801ab7c: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
801ab80: 3301 adds r3, #1
801ab82: b2da uxtb r2, r3
801ab84: 687b ldr r3, [r7, #4]
801ab86: 73da strb r2, [r3, #15]
}
/* points to packet payload, which starts with an Ethernet header */
ethhdr = (struct eth_hdr *)p->payload;
801ab88: 687b ldr r3, [r7, #4]
801ab8a: 685b ldr r3, [r3, #4]
801ab8c: 613b str r3, [r7, #16]
(unsigned char)ethhdr->dest.addr[3], (unsigned char)ethhdr->dest.addr[4], (unsigned char)ethhdr->dest.addr[5],
(unsigned char)ethhdr->src.addr[0], (unsigned char)ethhdr->src.addr[1], (unsigned char)ethhdr->src.addr[2],
(unsigned char)ethhdr->src.addr[3], (unsigned char)ethhdr->src.addr[4], (unsigned char)ethhdr->src.addr[5],
lwip_htons(ethhdr->type)));
type = ethhdr->type;
801ab8e: 693b ldr r3, [r7, #16]
801ab90: 7b1a ldrb r2, [r3, #12]
801ab92: 7b5b ldrb r3, [r3, #13]
801ab94: 021b lsls r3, r3, #8
801ab96: 4313 orrs r3, r2
801ab98: 81fb strh r3, [r7, #14]
#if LWIP_ARP_FILTER_NETIF
netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, lwip_htons(type));
#endif /* LWIP_ARP_FILTER_NETIF*/
if (ethhdr->dest.addr[0] & 1) {
801ab9a: 693b ldr r3, [r7, #16]
801ab9c: 781b ldrb r3, [r3, #0]
801ab9e: f003 0301 and.w r3, r3, #1
801aba2: 2b00 cmp r3, #0
801aba4: d023 beq.n 801abee <ethernet_input+0x92>
/* this might be a multicast or broadcast packet */
if (ethhdr->dest.addr[0] == LL_IP4_MULTICAST_ADDR_0) {
801aba6: 693b ldr r3, [r7, #16]
801aba8: 781b ldrb r3, [r3, #0]
801abaa: 2b01 cmp r3, #1
801abac: d10f bne.n 801abce <ethernet_input+0x72>
#if LWIP_IPV4
if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
801abae: 693b ldr r3, [r7, #16]
801abb0: 785b ldrb r3, [r3, #1]
801abb2: 2b00 cmp r3, #0
801abb4: d11b bne.n 801abee <ethernet_input+0x92>
(ethhdr->dest.addr[2] == LL_IP4_MULTICAST_ADDR_2)) {
801abb6: 693b ldr r3, [r7, #16]
801abb8: 789b ldrb r3, [r3, #2]
if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
801abba: 2b5e cmp r3, #94 ; 0x5e
801abbc: d117 bne.n 801abee <ethernet_input+0x92>
/* mark the pbuf as link-layer multicast */
p->flags |= PBUF_FLAG_LLMCAST;
801abbe: 687b ldr r3, [r7, #4]
801abc0: 7b5b ldrb r3, [r3, #13]
801abc2: f043 0310 orr.w r3, r3, #16
801abc6: b2da uxtb r2, r3
801abc8: 687b ldr r3, [r7, #4]
801abca: 735a strb r2, [r3, #13]
801abcc: e00f b.n 801abee <ethernet_input+0x92>
(ethhdr->dest.addr[1] == LL_IP6_MULTICAST_ADDR_1)) {
/* mark the pbuf as link-layer multicast */
p->flags |= PBUF_FLAG_LLMCAST;
}
#endif /* LWIP_IPV6 */
else if (eth_addr_cmp(&ethhdr->dest, &ethbroadcast)) {
801abce: 693b ldr r3, [r7, #16]
801abd0: 2206 movs r2, #6
801abd2: 4928 ldr r1, [pc, #160] ; (801ac74 <ethernet_input+0x118>)
801abd4: 4618 mov r0, r3
801abd6: f000 f9d1 bl 801af7c <memcmp>
801abda: 4603 mov r3, r0
801abdc: 2b00 cmp r3, #0
801abde: d106 bne.n 801abee <ethernet_input+0x92>
/* mark the pbuf as link-layer broadcast */
p->flags |= PBUF_FLAG_LLBCAST;
801abe0: 687b ldr r3, [r7, #4]
801abe2: 7b5b ldrb r3, [r3, #13]
801abe4: f043 0308 orr.w r3, r3, #8
801abe8: b2da uxtb r2, r3
801abea: 687b ldr r3, [r7, #4]
801abec: 735a strb r2, [r3, #13]
}
}
switch (type) {
801abee: 89fb ldrh r3, [r7, #14]
801abf0: 2b08 cmp r3, #8
801abf2: d003 beq.n 801abfc <ethernet_input+0xa0>
801abf4: f5b3 6fc1 cmp.w r3, #1544 ; 0x608
801abf8: d014 beq.n 801ac24 <ethernet_input+0xc8>
}
#endif
ETHARP_STATS_INC(etharp.proterr);
ETHARP_STATS_INC(etharp.drop);
MIB2_STATS_NETIF_INC(netif, ifinunknownprotos);
goto free_and_return;
801abfa: e032 b.n 801ac62 <ethernet_input+0x106>
if (!(netif->flags & NETIF_FLAG_ETHARP)) {
801abfc: 683b ldr r3, [r7, #0]
801abfe: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
801ac02: f003 0308 and.w r3, r3, #8
801ac06: 2b00 cmp r3, #0
801ac08: d024 beq.n 801ac54 <ethernet_input+0xf8>
if (pbuf_remove_header(p, next_hdr_offset)) {
801ac0a: 8afb ldrh r3, [r7, #22]
801ac0c: 4619 mov r1, r3
801ac0e: 6878 ldr r0, [r7, #4]
801ac10: f7f5 fc46 bl 80104a0 <pbuf_remove_header>
801ac14: 4603 mov r3, r0
801ac16: 2b00 cmp r3, #0
801ac18: d11e bne.n 801ac58 <ethernet_input+0xfc>
ip4_input(p, netif);
801ac1a: 6839 ldr r1, [r7, #0]
801ac1c: 6878 ldr r0, [r7, #4]
801ac1e: f7fe ff09 bl 8019a34 <ip4_input>
break;
801ac22: e013 b.n 801ac4c <ethernet_input+0xf0>
if (!(netif->flags & NETIF_FLAG_ETHARP)) {
801ac24: 683b ldr r3, [r7, #0]
801ac26: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
801ac2a: f003 0308 and.w r3, r3, #8
801ac2e: 2b00 cmp r3, #0
801ac30: d014 beq.n 801ac5c <ethernet_input+0x100>
if (pbuf_remove_header(p, next_hdr_offset)) {
801ac32: 8afb ldrh r3, [r7, #22]
801ac34: 4619 mov r1, r3
801ac36: 6878 ldr r0, [r7, #4]
801ac38: f7f5 fc32 bl 80104a0 <pbuf_remove_header>
801ac3c: 4603 mov r3, r0
801ac3e: 2b00 cmp r3, #0
801ac40: d10e bne.n 801ac60 <ethernet_input+0x104>
etharp_input(p, netif);
801ac42: 6839 ldr r1, [r7, #0]
801ac44: 6878 ldr r0, [r7, #4]
801ac46: f7fe f8a5 bl 8018d94 <etharp_input>
break;
801ac4a: bf00 nop
}
/* This means the pbuf is freed or consumed,
so the caller doesn't have to free it again */
return ERR_OK;
801ac4c: 2300 movs r3, #0
801ac4e: e00c b.n 801ac6a <ethernet_input+0x10e>
goto free_and_return;
801ac50: bf00 nop
801ac52: e006 b.n 801ac62 <ethernet_input+0x106>
goto free_and_return;
801ac54: bf00 nop
801ac56: e004 b.n 801ac62 <ethernet_input+0x106>
goto free_and_return;
801ac58: bf00 nop
801ac5a: e002 b.n 801ac62 <ethernet_input+0x106>
goto free_and_return;
801ac5c: bf00 nop
801ac5e: e000 b.n 801ac62 <ethernet_input+0x106>
goto free_and_return;
801ac60: bf00 nop
free_and_return:
pbuf_free(p);
801ac62: 6878 ldr r0, [r7, #4]
801ac64: f7f5 fca2 bl 80105ac <pbuf_free>
return ERR_OK;
801ac68: 2300 movs r3, #0
}
801ac6a: 4618 mov r0, r3
801ac6c: 3718 adds r7, #24
801ac6e: 46bd mov sp, r7
801ac70: bd80 pop {r7, pc}
801ac72: bf00 nop
801ac74: 08021044 .word 0x08021044
0801ac78 <ethernet_output>:
* @return ERR_OK if the packet was sent, any other err_t on failure
*/
err_t
ethernet_output(struct netif * netif, struct pbuf * p,
const struct eth_addr * src, const struct eth_addr * dst,
u16_t eth_type) {
801ac78: b580 push {r7, lr}
801ac7a: b086 sub sp, #24
801ac7c: af00 add r7, sp, #0
801ac7e: 60f8 str r0, [r7, #12]
801ac80: 60b9 str r1, [r7, #8]
801ac82: 607a str r2, [r7, #4]
801ac84: 603b str r3, [r7, #0]
struct eth_hdr *ethhdr;
u16_t eth_type_be = lwip_htons(eth_type);
801ac86: 8c3b ldrh r3, [r7, #32]
801ac88: 4618 mov r0, r3
801ac8a: f7f4 f8d7 bl 800ee3c <lwip_htons>
801ac8e: 4603 mov r3, r0
801ac90: 82fb strh r3, [r7, #22]
eth_type_be = PP_HTONS(ETHTYPE_VLAN);
} else
#endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */
{
if (pbuf_add_header(p, SIZEOF_ETH_HDR) != 0) {
801ac92: 210e movs r1, #14
801ac94: 68b8 ldr r0, [r7, #8]
801ac96: f7f5 fbf3 bl 8010480 <pbuf_add_header>
801ac9a: 4603 mov r3, r0
801ac9c: 2b00 cmp r3, #0
801ac9e: d125 bne.n 801acec <ethernet_output+0x74>
}
}
LWIP_ASSERT_CORE_LOCKED();
ethhdr = (struct eth_hdr *)p->payload;
801aca0: 68bb ldr r3, [r7, #8]
801aca2: 685b ldr r3, [r3, #4]
801aca4: 613b str r3, [r7, #16]
ethhdr->type = eth_type_be;
801aca6: 693b ldr r3, [r7, #16]
801aca8: 8afa ldrh r2, [r7, #22]
801acaa: 819a strh r2, [r3, #12]
SMEMCPY(&ethhdr->dest, dst, ETH_HWADDR_LEN);
801acac: 693b ldr r3, [r7, #16]
801acae: 2206 movs r2, #6
801acb0: 6839 ldr r1, [r7, #0]
801acb2: 4618 mov r0, r3
801acb4: f000 f970 bl 801af98 <memcpy>
SMEMCPY(&ethhdr->src, src, ETH_HWADDR_LEN);
801acb8: 693b ldr r3, [r7, #16]
801acba: 3306 adds r3, #6
801acbc: 2206 movs r2, #6
801acbe: 6879 ldr r1, [r7, #4]
801acc0: 4618 mov r0, r3
801acc2: f000 f969 bl 801af98 <memcpy>
LWIP_ASSERT("netif->hwaddr_len must be 6 for ethernet_output!",
801acc6: 68fb ldr r3, [r7, #12]
801acc8: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
801accc: 2b06 cmp r3, #6
801acce: d006 beq.n 801acde <ethernet_output+0x66>
801acd0: 4b0a ldr r3, [pc, #40] ; (801acfc <ethernet_output+0x84>)
801acd2: f44f 7299 mov.w r2, #306 ; 0x132
801acd6: 490a ldr r1, [pc, #40] ; (801ad00 <ethernet_output+0x88>)
801acd8: 480a ldr r0, [pc, #40] ; (801ad04 <ethernet_output+0x8c>)
801acda: f000 f973 bl 801afc4 <iprintf>
(netif->hwaddr_len == ETH_HWADDR_LEN));
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE,
("ethernet_output: sending packet %p\n", (void *)p));
/* send the packet */
return netif->linkoutput(netif, p);
801acde: 68fb ldr r3, [r7, #12]
801ace0: 699b ldr r3, [r3, #24]
801ace2: 68b9 ldr r1, [r7, #8]
801ace4: 68f8 ldr r0, [r7, #12]
801ace6: 4798 blx r3
801ace8: 4603 mov r3, r0
801acea: e002 b.n 801acf2 <ethernet_output+0x7a>
goto pbuf_header_failed;
801acec: bf00 nop
pbuf_header_failed:
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("ethernet_output: could not allocate room for header.\n"));
LINK_STATS_INC(link.lenerr);
return ERR_BUF;
801acee: f06f 0301 mvn.w r3, #1
}
801acf2: 4618 mov r0, r3
801acf4: 3718 adds r7, #24
801acf6: 46bd mov sp, r7
801acf8: bd80 pop {r7, pc}
801acfa: bf00 nop
801acfc: 0801ef3c .word 0x0801ef3c
801ad00: 0801ef74 .word 0x0801ef74
801ad04: 0801efa8 .word 0x0801efa8
0801ad08 <sys_mbox_new>:
#endif
/*-----------------------------------------------------------------------------------*/
// Creates an empty mailbox.
err_t sys_mbox_new(sys_mbox_t *mbox, int size)
{
801ad08: b580 push {r7, lr}
801ad0a: b086 sub sp, #24
801ad0c: af00 add r7, sp, #0
801ad0e: 6078 str r0, [r7, #4]
801ad10: 6039 str r1, [r7, #0]
#if (osCMSIS < 0x20000U)
osMessageQDef(QUEUE, size, void *);
801ad12: 683b ldr r3, [r7, #0]
801ad14: 60bb str r3, [r7, #8]
801ad16: 2304 movs r3, #4
801ad18: 60fb str r3, [r7, #12]
801ad1a: 2300 movs r3, #0
801ad1c: 613b str r3, [r7, #16]
801ad1e: 2300 movs r3, #0
801ad20: 617b str r3, [r7, #20]
*mbox = osMessageCreate(osMessageQ(QUEUE), NULL);
801ad22: f107 0308 add.w r3, r7, #8
801ad26: 2100 movs r1, #0
801ad28: 4618 mov r0, r3
801ad2a: f7f0 ffb5 bl 800bc98 <osMessageCreate>
801ad2e: 4602 mov r2, r0
801ad30: 687b ldr r3, [r7, #4]
801ad32: 601a str r2, [r3, #0]
if(lwip_stats.sys.mbox.max < lwip_stats.sys.mbox.used)
{
lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used;
}
#endif /* SYS_STATS */
if(*mbox == NULL)
801ad34: 687b ldr r3, [r7, #4]
801ad36: 681b ldr r3, [r3, #0]
801ad38: 2b00 cmp r3, #0
801ad3a: d102 bne.n 801ad42 <sys_mbox_new+0x3a>
return ERR_MEM;
801ad3c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
801ad40: e000 b.n 801ad44 <sys_mbox_new+0x3c>
return ERR_OK;
801ad42: 2300 movs r3, #0
}
801ad44: 4618 mov r0, r3
801ad46: 3718 adds r7, #24
801ad48: 46bd mov sp, r7
801ad4a: bd80 pop {r7, pc}
0801ad4c <sys_mbox_trypost>:
/*-----------------------------------------------------------------------------------*/
// Try to post the "msg" to the mailbox.
err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg)
{
801ad4c: b580 push {r7, lr}
801ad4e: b084 sub sp, #16
801ad50: af00 add r7, sp, #0
801ad52: 6078 str r0, [r7, #4]
801ad54: 6039 str r1, [r7, #0]
err_t result;
#if (osCMSIS < 0x20000U)
if(osMessagePut(*mbox, (uint32_t)msg, 0) == osOK)
801ad56: 687b ldr r3, [r7, #4]
801ad58: 681b ldr r3, [r3, #0]
801ad5a: 6839 ldr r1, [r7, #0]
801ad5c: 2200 movs r2, #0
801ad5e: 4618 mov r0, r3
801ad60: f7f0 ffc2 bl 800bce8 <osMessagePut>
801ad64: 4603 mov r3, r0
801ad66: 2b00 cmp r3, #0
801ad68: d102 bne.n 801ad70 <sys_mbox_trypost+0x24>
#else
if(osMessageQueuePut(*mbox, &msg, 0, 0) == osOK)
#endif
{
result = ERR_OK;
801ad6a: 2300 movs r3, #0
801ad6c: 73fb strb r3, [r7, #15]
801ad6e: e001 b.n 801ad74 <sys_mbox_trypost+0x28>
}
else
{
// could not post, queue must be full
result = ERR_MEM;
801ad70: 23ff movs r3, #255 ; 0xff
801ad72: 73fb strb r3, [r7, #15]
#if SYS_STATS
lwip_stats.sys.mbox.err++;
#endif /* SYS_STATS */
}
return result;
801ad74: f997 300f ldrsb.w r3, [r7, #15]
}
801ad78: 4618 mov r0, r3
801ad7a: 3710 adds r7, #16
801ad7c: 46bd mov sp, r7
801ad7e: bd80 pop {r7, pc}
0801ad80 <sys_arch_mbox_fetch>:
Note that a function with a similar name, sys_mbox_fetch(), is
implemented by lwIP.
*/
u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout)
{
801ad80: b580 push {r7, lr}
801ad82: b08c sub sp, #48 ; 0x30
801ad84: af00 add r7, sp, #0
801ad86: 61f8 str r0, [r7, #28]
801ad88: 61b9 str r1, [r7, #24]
801ad8a: 617a str r2, [r7, #20]
#if (osCMSIS < 0x20000U)
osEvent event;
uint32_t starttime = osKernelSysTick();
801ad8c: f7f0 fdb3 bl 800b8f6 <osKernelSysTick>
801ad90: 62f8 str r0, [r7, #44] ; 0x2c
#else
osStatus_t status;
uint32_t starttime = osKernelGetTickCount();
#endif
if(timeout != 0)
801ad92: 697b ldr r3, [r7, #20]
801ad94: 2b00 cmp r3, #0
801ad96: d017 beq.n 801adc8 <sys_arch_mbox_fetch+0x48>
{
#if (osCMSIS < 0x20000U)
event = osMessageGet (*mbox, timeout);
801ad98: 69fb ldr r3, [r7, #28]
801ad9a: 6819 ldr r1, [r3, #0]
801ad9c: f107 0320 add.w r3, r7, #32
801ada0: 697a ldr r2, [r7, #20]
801ada2: 4618 mov r0, r3
801ada4: f7f0 ffe0 bl 800bd68 <osMessageGet>
if(event.status == osEventMessage)
801ada8: 6a3b ldr r3, [r7, #32]
801adaa: 2b10 cmp r3, #16
801adac: d109 bne.n 801adc2 <sys_arch_mbox_fetch+0x42>
{
*msg = (void *)event.value.v;
801adae: 6a7b ldr r3, [r7, #36] ; 0x24
801adb0: 461a mov r2, r3
801adb2: 69bb ldr r3, [r7, #24]
801adb4: 601a str r2, [r3, #0]
return (osKernelSysTick() - starttime);
801adb6: f7f0 fd9e bl 800b8f6 <osKernelSysTick>
801adba: 4602 mov r2, r0
801adbc: 6afb ldr r3, [r7, #44] ; 0x2c
801adbe: 1ad3 subs r3, r2, r3
801adc0: e019 b.n 801adf6 <sys_arch_mbox_fetch+0x76>
return (osKernelGetTickCount() - starttime);
}
#endif
else
{
return SYS_ARCH_TIMEOUT;
801adc2: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
801adc6: e016 b.n 801adf6 <sys_arch_mbox_fetch+0x76>
}
}
else
{
#if (osCMSIS < 0x20000U)
event = osMessageGet (*mbox, osWaitForever);
801adc8: 69fb ldr r3, [r7, #28]
801adca: 6819 ldr r1, [r3, #0]
801adcc: 463b mov r3, r7
801adce: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
801add2: 4618 mov r0, r3
801add4: f7f0 ffc8 bl 800bd68 <osMessageGet>
801add8: f107 0320 add.w r3, r7, #32
801addc: 463a mov r2, r7
801adde: ca07 ldmia r2, {r0, r1, r2}
801ade0: e883 0007 stmia.w r3, {r0, r1, r2}
*msg = (void *)event.value.v;
801ade4: 6a7b ldr r3, [r7, #36] ; 0x24
801ade6: 461a mov r2, r3
801ade8: 69bb ldr r3, [r7, #24]
801adea: 601a str r2, [r3, #0]
return (osKernelSysTick() - starttime);
801adec: f7f0 fd83 bl 800b8f6 <osKernelSysTick>
801adf0: 4602 mov r2, r0
801adf2: 6afb ldr r3, [r7, #44] ; 0x2c
801adf4: 1ad3 subs r3, r2, r3
#else
osMessageQueueGet(*mbox, msg, 0, osWaitForever );
return (osKernelGetTickCount() - starttime);
#endif
}
}
801adf6: 4618 mov r0, r3
801adf8: 3730 adds r7, #48 ; 0x30
801adfa: 46bd mov sp, r7
801adfc: bd80 pop {r7, pc}
0801adfe <sys_mbox_valid>:
return SYS_MBOX_EMPTY;
}
}
/*----------------------------------------------------------------------------------*/
int sys_mbox_valid(sys_mbox_t *mbox)
{
801adfe: b480 push {r7}
801ae00: b083 sub sp, #12
801ae02: af00 add r7, sp, #0
801ae04: 6078 str r0, [r7, #4]
if (*mbox == SYS_MBOX_NULL)
801ae06: 687b ldr r3, [r7, #4]
801ae08: 681b ldr r3, [r3, #0]
801ae0a: 2b00 cmp r3, #0
801ae0c: d101 bne.n 801ae12 <sys_mbox_valid+0x14>
return 0;
801ae0e: 2300 movs r3, #0
801ae10: e000 b.n 801ae14 <sys_mbox_valid+0x16>
else
return 1;
801ae12: 2301 movs r3, #1
}
801ae14: 4618 mov r0, r3
801ae16: 370c adds r7, #12
801ae18: 46bd mov sp, r7
801ae1a: f85d 7b04 ldr.w r7, [sp], #4
801ae1e: 4770 bx lr
0801ae20 <sys_init>:
#else
osMutexId_t lwip_sys_mutex;
#endif
// Initialize sys arch
void sys_init(void)
{
801ae20: b580 push {r7, lr}
801ae22: af00 add r7, sp, #0
#if (osCMSIS < 0x20000U)
lwip_sys_mutex = osMutexCreate(osMutex(lwip_sys_mutex));
801ae24: 4803 ldr r0, [pc, #12] ; (801ae34 <sys_init+0x14>)
801ae26: f7f0 fdd6 bl 800b9d6 <osMutexCreate>
801ae2a: 4603 mov r3, r0
801ae2c: 4a02 ldr r2, [pc, #8] ; (801ae38 <sys_init+0x18>)
801ae2e: 6013 str r3, [r2, #0]
#else
lwip_sys_mutex = osMutexNew(NULL);
#endif
}
801ae30: bf00 nop
801ae32: bd80 pop {r7, pc}
801ae34: 08021054 .word 0x08021054
801ae38: 2000f884 .word 0x2000f884
0801ae3c <sys_mutex_new>:
/* Mutexes*/
/*-----------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------*/
#if LWIP_COMPAT_MUTEX == 0
/* Create a new mutex*/
err_t sys_mutex_new(sys_mutex_t *mutex) {
801ae3c: b580 push {r7, lr}
801ae3e: b084 sub sp, #16
801ae40: af00 add r7, sp, #0
801ae42: 6078 str r0, [r7, #4]
#if (osCMSIS < 0x20000U)
osMutexDef(MUTEX);
801ae44: 2300 movs r3, #0
801ae46: 60bb str r3, [r7, #8]
801ae48: 2300 movs r3, #0
801ae4a: 60fb str r3, [r7, #12]
*mutex = osMutexCreate(osMutex(MUTEX));
801ae4c: f107 0308 add.w r3, r7, #8
801ae50: 4618 mov r0, r3
801ae52: f7f0 fdc0 bl 800b9d6 <osMutexCreate>
801ae56: 4602 mov r2, r0
801ae58: 687b ldr r3, [r7, #4]
801ae5a: 601a str r2, [r3, #0]
#else
*mutex = osMutexNew(NULL);
#endif
if(*mutex == NULL)
801ae5c: 687b ldr r3, [r7, #4]
801ae5e: 681b ldr r3, [r3, #0]
801ae60: 2b00 cmp r3, #0
801ae62: d102 bne.n 801ae6a <sys_mutex_new+0x2e>
{
#if SYS_STATS
++lwip_stats.sys.mutex.err;
#endif /* SYS_STATS */
return ERR_MEM;
801ae64: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
801ae68: e000 b.n 801ae6c <sys_mutex_new+0x30>
++lwip_stats.sys.mutex.used;
if (lwip_stats.sys.mutex.max < lwip_stats.sys.mutex.used) {
lwip_stats.sys.mutex.max = lwip_stats.sys.mutex.used;
}
#endif /* SYS_STATS */
return ERR_OK;
801ae6a: 2300 movs r3, #0
}
801ae6c: 4618 mov r0, r3
801ae6e: 3710 adds r7, #16
801ae70: 46bd mov sp, r7
801ae72: bd80 pop {r7, pc}
0801ae74 <sys_mutex_lock>:
osMutexDelete(*mutex);
}
/*-----------------------------------------------------------------------------------*/
/* Lock a mutex*/
void sys_mutex_lock(sys_mutex_t *mutex)
{
801ae74: b580 push {r7, lr}
801ae76: b082 sub sp, #8
801ae78: af00 add r7, sp, #0
801ae7a: 6078 str r0, [r7, #4]
#if (osCMSIS < 0x20000U)
osMutexWait(*mutex, osWaitForever);
801ae7c: 687b ldr r3, [r7, #4]
801ae7e: 681b ldr r3, [r3, #0]
801ae80: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
801ae84: 4618 mov r0, r3
801ae86: f7f0 fdbf bl 800ba08 <osMutexWait>
#else
osMutexAcquire(*mutex, osWaitForever);
#endif
}
801ae8a: bf00 nop
801ae8c: 3708 adds r7, #8
801ae8e: 46bd mov sp, r7
801ae90: bd80 pop {r7, pc}
0801ae92 <sys_mutex_unlock>:
/*-----------------------------------------------------------------------------------*/
/* Unlock a mutex*/
void sys_mutex_unlock(sys_mutex_t *mutex)
{
801ae92: b580 push {r7, lr}
801ae94: b082 sub sp, #8
801ae96: af00 add r7, sp, #0
801ae98: 6078 str r0, [r7, #4]
osMutexRelease(*mutex);
801ae9a: 687b ldr r3, [r7, #4]
801ae9c: 681b ldr r3, [r3, #0]
801ae9e: 4618 mov r0, r3
801aea0: f7f0 fe00 bl 800baa4 <osMutexRelease>
}
801aea4: bf00 nop
801aea6: 3708 adds r7, #8
801aea8: 46bd mov sp, r7
801aeaa: bd80 pop {r7, pc}
0801aeac <sys_thread_new>:
function "thread()". The "arg" argument will be passed as an argument to the
thread() function. The id of the new thread is returned. Both the id and
the priority are system dependent.
*/
sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread , void *arg, int stacksize, int prio)
{
801aeac: b580 push {r7, lr}
801aeae: b08c sub sp, #48 ; 0x30
801aeb0: af00 add r7, sp, #0
801aeb2: 60f8 str r0, [r7, #12]
801aeb4: 60b9 str r1, [r7, #8]
801aeb6: 607a str r2, [r7, #4]
801aeb8: 603b str r3, [r7, #0]
#if (osCMSIS < 0x20000U)
const osThreadDef_t os_thread_def = { (char *)name, (os_pthread)thread, (osPriority)prio, 0, stacksize};
801aeba: f107 0314 add.w r3, r7, #20
801aebe: 2200 movs r2, #0
801aec0: 601a str r2, [r3, #0]
801aec2: 605a str r2, [r3, #4]
801aec4: 609a str r2, [r3, #8]
801aec6: 60da str r2, [r3, #12]
801aec8: 611a str r2, [r3, #16]
801aeca: 615a str r2, [r3, #20]
801aecc: 619a str r2, [r3, #24]
801aece: 68fb ldr r3, [r7, #12]
801aed0: 617b str r3, [r7, #20]
801aed2: 68bb ldr r3, [r7, #8]
801aed4: 61bb str r3, [r7, #24]
801aed6: 6bbb ldr r3, [r7, #56] ; 0x38
801aed8: b21b sxth r3, r3
801aeda: 83bb strh r3, [r7, #28]
801aedc: 683b ldr r3, [r7, #0]
801aede: 627b str r3, [r7, #36] ; 0x24
return osThreadCreate(&os_thread_def, arg);
801aee0: f107 0314 add.w r3, r7, #20
801aee4: 6879 ldr r1, [r7, #4]
801aee6: 4618 mov r0, r3
801aee8: f7f0 fd15 bl 800b916 <osThreadCreate>
801aeec: 4603 mov r3, r0
.stack_size = stacksize,
.priority = (osPriority_t)prio,
};
return osThreadNew(thread, arg, &attributes);
#endif
}
801aeee: 4618 mov r0, r3
801aef0: 3730 adds r7, #48 ; 0x30
801aef2: 46bd mov sp, r7
801aef4: bd80 pop {r7, pc}
...
0801aef8 <sys_arch_protect>:
Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS
API is available
*/
sys_prot_t sys_arch_protect(void)
{
801aef8: b580 push {r7, lr}
801aefa: af00 add r7, sp, #0
#if (osCMSIS < 0x20000U)
osMutexWait(lwip_sys_mutex, osWaitForever);
801aefc: 4b04 ldr r3, [pc, #16] ; (801af10 <sys_arch_protect+0x18>)
801aefe: 681b ldr r3, [r3, #0]
801af00: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
801af04: 4618 mov r0, r3
801af06: f7f0 fd7f bl 800ba08 <osMutexWait>
#else
osMutexAcquire(lwip_sys_mutex, osWaitForever);
#endif
return (sys_prot_t)1;
801af0a: 2301 movs r3, #1
}
801af0c: 4618 mov r0, r3
801af0e: bd80 pop {r7, pc}
801af10: 2000f884 .word 0x2000f884
0801af14 <sys_arch_unprotect>:
Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS
API is available
*/
void sys_arch_unprotect(sys_prot_t pval)
{
801af14: b580 push {r7, lr}
801af16: b082 sub sp, #8
801af18: af00 add r7, sp, #0
801af1a: 6078 str r0, [r7, #4]
( void ) pval;
osMutexRelease(lwip_sys_mutex);
801af1c: 4b04 ldr r3, [pc, #16] ; (801af30 <sys_arch_unprotect+0x1c>)
801af1e: 681b ldr r3, [r3, #0]
801af20: 4618 mov r0, r3
801af22: f7f0 fdbf bl 800baa4 <osMutexRelease>
}
801af26: bf00 nop
801af28: 3708 adds r7, #8
801af2a: 46bd mov sp, r7
801af2c: bd80 pop {r7, pc}
801af2e: bf00 nop
801af30: 2000f884 .word 0x2000f884
0801af34 <__libc_init_array>:
801af34: b570 push {r4, r5, r6, lr}
801af36: 4d0d ldr r5, [pc, #52] ; (801af6c <__libc_init_array+0x38>)
801af38: 4c0d ldr r4, [pc, #52] ; (801af70 <__libc_init_array+0x3c>)
801af3a: 1b64 subs r4, r4, r5
801af3c: 10a4 asrs r4, r4, #2
801af3e: 2600 movs r6, #0
801af40: 42a6 cmp r6, r4
801af42: d109 bne.n 801af58 <__libc_init_array+0x24>
801af44: 4d0b ldr r5, [pc, #44] ; (801af74 <__libc_init_array+0x40>)
801af46: 4c0c ldr r4, [pc, #48] ; (801af78 <__libc_init_array+0x44>)
801af48: f001 f856 bl 801bff8 <_init>
801af4c: 1b64 subs r4, r4, r5
801af4e: 10a4 asrs r4, r4, #2
801af50: 2600 movs r6, #0
801af52: 42a6 cmp r6, r4
801af54: d105 bne.n 801af62 <__libc_init_array+0x2e>
801af56: bd70 pop {r4, r5, r6, pc}
801af58: f855 3b04 ldr.w r3, [r5], #4
801af5c: 4798 blx r3
801af5e: 3601 adds r6, #1
801af60: e7ee b.n 801af40 <__libc_init_array+0xc>
801af62: f855 3b04 ldr.w r3, [r5], #4
801af66: 4798 blx r3
801af68: 3601 adds r6, #1
801af6a: e7f2 b.n 801af52 <__libc_init_array+0x1e>
801af6c: 080211b0 .word 0x080211b0
801af70: 080211b0 .word 0x080211b0
801af74: 080211b0 .word 0x080211b0
801af78: 080211b4 .word 0x080211b4
0801af7c <memcmp>:
801af7c: b530 push {r4, r5, lr}
801af7e: 3901 subs r1, #1
801af80: 2400 movs r4, #0
801af82: 42a2 cmp r2, r4
801af84: d101 bne.n 801af8a <memcmp+0xe>
801af86: 2000 movs r0, #0
801af88: e005 b.n 801af96 <memcmp+0x1a>
801af8a: 5d03 ldrb r3, [r0, r4]
801af8c: 3401 adds r4, #1
801af8e: 5d0d ldrb r5, [r1, r4]
801af90: 42ab cmp r3, r5
801af92: d0f6 beq.n 801af82 <memcmp+0x6>
801af94: 1b58 subs r0, r3, r5
801af96: bd30 pop {r4, r5, pc}
0801af98 <memcpy>:
801af98: 440a add r2, r1
801af9a: 4291 cmp r1, r2
801af9c: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
801afa0: d100 bne.n 801afa4 <memcpy+0xc>
801afa2: 4770 bx lr
801afa4: b510 push {r4, lr}
801afa6: f811 4b01 ldrb.w r4, [r1], #1
801afaa: f803 4f01 strb.w r4, [r3, #1]!
801afae: 4291 cmp r1, r2
801afb0: d1f9 bne.n 801afa6 <memcpy+0xe>
801afb2: bd10 pop {r4, pc}
0801afb4 <memset>:
801afb4: 4402 add r2, r0
801afb6: 4603 mov r3, r0
801afb8: 4293 cmp r3, r2
801afba: d100 bne.n 801afbe <memset+0xa>
801afbc: 4770 bx lr
801afbe: f803 1b01 strb.w r1, [r3], #1
801afc2: e7f9 b.n 801afb8 <memset+0x4>
0801afc4 <iprintf>:
801afc4: b40f push {r0, r1, r2, r3}
801afc6: 4b0a ldr r3, [pc, #40] ; (801aff0 <iprintf+0x2c>)
801afc8: b513 push {r0, r1, r4, lr}
801afca: 681c ldr r4, [r3, #0]
801afcc: b124 cbz r4, 801afd8 <iprintf+0x14>
801afce: 69a3 ldr r3, [r4, #24]
801afd0: b913 cbnz r3, 801afd8 <iprintf+0x14>
801afd2: 4620 mov r0, r4
801afd4: f000 f8c4 bl 801b160 <__sinit>
801afd8: ab05 add r3, sp, #20
801afda: 9a04 ldr r2, [sp, #16]
801afdc: 68a1 ldr r1, [r4, #8]
801afde: 9301 str r3, [sp, #4]
801afe0: 4620 mov r0, r4
801afe2: f000 fa4b bl 801b47c <_vfiprintf_r>
801afe6: b002 add sp, #8
801afe8: e8bd 4010 ldmia.w sp!, {r4, lr}
801afec: b004 add sp, #16
801afee: 4770 bx lr
801aff0: 20000078 .word 0x20000078
0801aff4 <rand>:
801aff4: 4b17 ldr r3, [pc, #92] ; (801b054 <rand+0x60>)
801aff6: b510 push {r4, lr}
801aff8: 681c ldr r4, [r3, #0]
801affa: 6ba3 ldr r3, [r4, #56] ; 0x38
801affc: b9b3 cbnz r3, 801b02c <rand+0x38>
801affe: 2018 movs r0, #24
801b000: f000 f960 bl 801b2c4 <malloc>
801b004: 63a0 str r0, [r4, #56] ; 0x38
801b006: b928 cbnz r0, 801b014 <rand+0x20>
801b008: 4602 mov r2, r0
801b00a: 4b13 ldr r3, [pc, #76] ; (801b058 <rand+0x64>)
801b00c: 4813 ldr r0, [pc, #76] ; (801b05c <rand+0x68>)
801b00e: 214e movs r1, #78 ; 0x4e
801b010: f000 f830 bl 801b074 <__assert_func>
801b014: 4a12 ldr r2, [pc, #72] ; (801b060 <rand+0x6c>)
801b016: 4b13 ldr r3, [pc, #76] ; (801b064 <rand+0x70>)
801b018: e9c0 2300 strd r2, r3, [r0]
801b01c: 4b12 ldr r3, [pc, #72] ; (801b068 <rand+0x74>)
801b01e: 6083 str r3, [r0, #8]
801b020: 230b movs r3, #11
801b022: 8183 strh r3, [r0, #12]
801b024: 2201 movs r2, #1
801b026: 2300 movs r3, #0
801b028: e9c0 2304 strd r2, r3, [r0, #16]
801b02c: 6ba1 ldr r1, [r4, #56] ; 0x38
801b02e: 480f ldr r0, [pc, #60] ; (801b06c <rand+0x78>)
801b030: 690a ldr r2, [r1, #16]
801b032: 694b ldr r3, [r1, #20]
801b034: 4c0e ldr r4, [pc, #56] ; (801b070 <rand+0x7c>)
801b036: 4350 muls r0, r2
801b038: fb04 0003 mla r0, r4, r3, r0
801b03c: fba2 3404 umull r3, r4, r2, r4
801b040: 1c5a adds r2, r3, #1
801b042: 4404 add r4, r0
801b044: f144 0000 adc.w r0, r4, #0
801b048: e9c1 2004 strd r2, r0, [r1, #16]
801b04c: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000
801b050: bd10 pop {r4, pc}
801b052: bf00 nop
801b054: 20000078 .word 0x20000078
801b058: 08021060 .word 0x08021060
801b05c: 08021077 .word 0x08021077
801b060: abcd330e .word 0xabcd330e
801b064: e66d1234 .word 0xe66d1234
801b068: 0005deec .word 0x0005deec
801b06c: 5851f42d .word 0x5851f42d
801b070: 4c957f2d .word 0x4c957f2d
0801b074 <__assert_func>:
801b074: b51f push {r0, r1, r2, r3, r4, lr}
801b076: 4614 mov r4, r2
801b078: 461a mov r2, r3
801b07a: 4b09 ldr r3, [pc, #36] ; (801b0a0 <__assert_func+0x2c>)
801b07c: 681b ldr r3, [r3, #0]
801b07e: 4605 mov r5, r0
801b080: 68d8 ldr r0, [r3, #12]
801b082: b14c cbz r4, 801b098 <__assert_func+0x24>
801b084: 4b07 ldr r3, [pc, #28] ; (801b0a4 <__assert_func+0x30>)
801b086: 9100 str r1, [sp, #0]
801b088: e9cd 3401 strd r3, r4, [sp, #4]
801b08c: 4906 ldr r1, [pc, #24] ; (801b0a8 <__assert_func+0x34>)
801b08e: 462b mov r3, r5
801b090: f000 f8e4 bl 801b25c <fiprintf>
801b094: f000 fddc bl 801bc50 <abort>
801b098: 4b04 ldr r3, [pc, #16] ; (801b0ac <__assert_func+0x38>)
801b09a: 461c mov r4, r3
801b09c: e7f3 b.n 801b086 <__assert_func+0x12>
801b09e: bf00 nop
801b0a0: 20000078 .word 0x20000078
801b0a4: 080210d6 .word 0x080210d6
801b0a8: 080210e3 .word 0x080210e3
801b0ac: 08021111 .word 0x08021111
0801b0b0 <std>:
801b0b0: 2300 movs r3, #0
801b0b2: b510 push {r4, lr}
801b0b4: 4604 mov r4, r0
801b0b6: e9c0 3300 strd r3, r3, [r0]
801b0ba: e9c0 3304 strd r3, r3, [r0, #16]
801b0be: 6083 str r3, [r0, #8]
801b0c0: 8181 strh r1, [r0, #12]
801b0c2: 6643 str r3, [r0, #100] ; 0x64
801b0c4: 81c2 strh r2, [r0, #14]
801b0c6: 6183 str r3, [r0, #24]
801b0c8: 4619 mov r1, r3
801b0ca: 2208 movs r2, #8
801b0cc: 305c adds r0, #92 ; 0x5c
801b0ce: f7ff ff71 bl 801afb4 <memset>
801b0d2: 4b05 ldr r3, [pc, #20] ; (801b0e8 <std+0x38>)
801b0d4: 6263 str r3, [r4, #36] ; 0x24
801b0d6: 4b05 ldr r3, [pc, #20] ; (801b0ec <std+0x3c>)
801b0d8: 62a3 str r3, [r4, #40] ; 0x28
801b0da: 4b05 ldr r3, [pc, #20] ; (801b0f0 <std+0x40>)
801b0dc: 62e3 str r3, [r4, #44] ; 0x2c
801b0de: 4b05 ldr r3, [pc, #20] ; (801b0f4 <std+0x44>)
801b0e0: 6224 str r4, [r4, #32]
801b0e2: 6323 str r3, [r4, #48] ; 0x30
801b0e4: bd10 pop {r4, pc}
801b0e6: bf00 nop
801b0e8: 0801ba25 .word 0x0801ba25
801b0ec: 0801ba47 .word 0x0801ba47
801b0f0: 0801ba7f .word 0x0801ba7f
801b0f4: 0801baa3 .word 0x0801baa3
0801b0f8 <_cleanup_r>:
801b0f8: 4901 ldr r1, [pc, #4] ; (801b100 <_cleanup_r+0x8>)
801b0fa: f000 b8c1 b.w 801b280 <_fwalk_reent>
801b0fe: bf00 nop
801b100: 0801bd8d .word 0x0801bd8d
0801b104 <__sfmoreglue>:
801b104: b570 push {r4, r5, r6, lr}
801b106: 1e4a subs r2, r1, #1
801b108: 2568 movs r5, #104 ; 0x68
801b10a: 4355 muls r5, r2
801b10c: 460e mov r6, r1
801b10e: f105 0174 add.w r1, r5, #116 ; 0x74
801b112: f000 f92f bl 801b374 <_malloc_r>
801b116: 4604 mov r4, r0
801b118: b140 cbz r0, 801b12c <__sfmoreglue+0x28>
801b11a: 2100 movs r1, #0
801b11c: e9c0 1600 strd r1, r6, [r0]
801b120: 300c adds r0, #12
801b122: 60a0 str r0, [r4, #8]
801b124: f105 0268 add.w r2, r5, #104 ; 0x68
801b128: f7ff ff44 bl 801afb4 <memset>
801b12c: 4620 mov r0, r4
801b12e: bd70 pop {r4, r5, r6, pc}
0801b130 <__sfp_lock_acquire>:
801b130: 4801 ldr r0, [pc, #4] ; (801b138 <__sfp_lock_acquire+0x8>)
801b132: f000 b8c5 b.w 801b2c0 <__retarget_lock_acquire_recursive>
801b136: bf00 nop
801b138: 2000f890 .word 0x2000f890
0801b13c <__sfp_lock_release>:
801b13c: 4801 ldr r0, [pc, #4] ; (801b144 <__sfp_lock_release+0x8>)
801b13e: f000 b8c0 b.w 801b2c2 <__retarget_lock_release_recursive>
801b142: bf00 nop
801b144: 2000f890 .word 0x2000f890
0801b148 <__sinit_lock_acquire>:
801b148: 4801 ldr r0, [pc, #4] ; (801b150 <__sinit_lock_acquire+0x8>)
801b14a: f000 b8b9 b.w 801b2c0 <__retarget_lock_acquire_recursive>
801b14e: bf00 nop
801b150: 2000f88b .word 0x2000f88b
0801b154 <__sinit_lock_release>:
801b154: 4801 ldr r0, [pc, #4] ; (801b15c <__sinit_lock_release+0x8>)
801b156: f000 b8b4 b.w 801b2c2 <__retarget_lock_release_recursive>
801b15a: bf00 nop
801b15c: 2000f88b .word 0x2000f88b
0801b160 <__sinit>:
801b160: b510 push {r4, lr}
801b162: 4604 mov r4, r0
801b164: f7ff fff0 bl 801b148 <__sinit_lock_acquire>
801b168: 69a3 ldr r3, [r4, #24]
801b16a: b11b cbz r3, 801b174 <__sinit+0x14>
801b16c: e8bd 4010 ldmia.w sp!, {r4, lr}
801b170: f7ff bff0 b.w 801b154 <__sinit_lock_release>
801b174: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48
801b178: 6523 str r3, [r4, #80] ; 0x50
801b17a: 4b13 ldr r3, [pc, #76] ; (801b1c8 <__sinit+0x68>)
801b17c: 4a13 ldr r2, [pc, #76] ; (801b1cc <__sinit+0x6c>)
801b17e: 681b ldr r3, [r3, #0]
801b180: 62a2 str r2, [r4, #40] ; 0x28
801b182: 42a3 cmp r3, r4
801b184: bf04 itt eq
801b186: 2301 moveq r3, #1
801b188: 61a3 streq r3, [r4, #24]
801b18a: 4620 mov r0, r4
801b18c: f000 f820 bl 801b1d0 <__sfp>
801b190: 6060 str r0, [r4, #4]
801b192: 4620 mov r0, r4
801b194: f000 f81c bl 801b1d0 <__sfp>
801b198: 60a0 str r0, [r4, #8]
801b19a: 4620 mov r0, r4
801b19c: f000 f818 bl 801b1d0 <__sfp>
801b1a0: 2200 movs r2, #0
801b1a2: 60e0 str r0, [r4, #12]
801b1a4: 2104 movs r1, #4
801b1a6: 6860 ldr r0, [r4, #4]
801b1a8: f7ff ff82 bl 801b0b0 <std>
801b1ac: 68a0 ldr r0, [r4, #8]
801b1ae: 2201 movs r2, #1
801b1b0: 2109 movs r1, #9
801b1b2: f7ff ff7d bl 801b0b0 <std>
801b1b6: 68e0 ldr r0, [r4, #12]
801b1b8: 2202 movs r2, #2
801b1ba: 2112 movs r1, #18
801b1bc: f7ff ff78 bl 801b0b0 <std>
801b1c0: 2301 movs r3, #1
801b1c2: 61a3 str r3, [r4, #24]
801b1c4: e7d2 b.n 801b16c <__sinit+0xc>
801b1c6: bf00 nop
801b1c8: 0802105c .word 0x0802105c
801b1cc: 0801b0f9 .word 0x0801b0f9
0801b1d0 <__sfp>:
801b1d0: b5f8 push {r3, r4, r5, r6, r7, lr}
801b1d2: 4607 mov r7, r0
801b1d4: f7ff ffac bl 801b130 <__sfp_lock_acquire>
801b1d8: 4b1e ldr r3, [pc, #120] ; (801b254 <__sfp+0x84>)
801b1da: 681e ldr r6, [r3, #0]
801b1dc: 69b3 ldr r3, [r6, #24]
801b1de: b913 cbnz r3, 801b1e6 <__sfp+0x16>
801b1e0: 4630 mov r0, r6
801b1e2: f7ff ffbd bl 801b160 <__sinit>
801b1e6: 3648 adds r6, #72 ; 0x48
801b1e8: e9d6 3401 ldrd r3, r4, [r6, #4]
801b1ec: 3b01 subs r3, #1
801b1ee: d503 bpl.n 801b1f8 <__sfp+0x28>
801b1f0: 6833 ldr r3, [r6, #0]
801b1f2: b30b cbz r3, 801b238 <__sfp+0x68>
801b1f4: 6836 ldr r6, [r6, #0]
801b1f6: e7f7 b.n 801b1e8 <__sfp+0x18>
801b1f8: f9b4 500c ldrsh.w r5, [r4, #12]
801b1fc: b9d5 cbnz r5, 801b234 <__sfp+0x64>
801b1fe: 4b16 ldr r3, [pc, #88] ; (801b258 <__sfp+0x88>)
801b200: 60e3 str r3, [r4, #12]
801b202: f104 0058 add.w r0, r4, #88 ; 0x58
801b206: 6665 str r5, [r4, #100] ; 0x64
801b208: f000 f859 bl 801b2be <__retarget_lock_init_recursive>
801b20c: f7ff ff96 bl 801b13c <__sfp_lock_release>
801b210: e9c4 5501 strd r5, r5, [r4, #4]
801b214: e9c4 5504 strd r5, r5, [r4, #16]
801b218: 6025 str r5, [r4, #0]
801b21a: 61a5 str r5, [r4, #24]
801b21c: 2208 movs r2, #8
801b21e: 4629 mov r1, r5
801b220: f104 005c add.w r0, r4, #92 ; 0x5c
801b224: f7ff fec6 bl 801afb4 <memset>
801b228: e9c4 550d strd r5, r5, [r4, #52] ; 0x34
801b22c: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48
801b230: 4620 mov r0, r4
801b232: bdf8 pop {r3, r4, r5, r6, r7, pc}
801b234: 3468 adds r4, #104 ; 0x68
801b236: e7d9 b.n 801b1ec <__sfp+0x1c>
801b238: 2104 movs r1, #4
801b23a: 4638 mov r0, r7
801b23c: f7ff ff62 bl 801b104 <__sfmoreglue>
801b240: 4604 mov r4, r0
801b242: 6030 str r0, [r6, #0]
801b244: 2800 cmp r0, #0
801b246: d1d5 bne.n 801b1f4 <__sfp+0x24>
801b248: f7ff ff78 bl 801b13c <__sfp_lock_release>
801b24c: 230c movs r3, #12
801b24e: 603b str r3, [r7, #0]
801b250: e7ee b.n 801b230 <__sfp+0x60>
801b252: bf00 nop
801b254: 0802105c .word 0x0802105c
801b258: ffff0001 .word 0xffff0001
0801b25c <fiprintf>:
801b25c: b40e push {r1, r2, r3}
801b25e: b503 push {r0, r1, lr}
801b260: 4601 mov r1, r0
801b262: ab03 add r3, sp, #12
801b264: 4805 ldr r0, [pc, #20] ; (801b27c <fiprintf+0x20>)
801b266: f853 2b04 ldr.w r2, [r3], #4
801b26a: 6800 ldr r0, [r0, #0]
801b26c: 9301 str r3, [sp, #4]
801b26e: f000 f905 bl 801b47c <_vfiprintf_r>
801b272: b002 add sp, #8
801b274: f85d eb04 ldr.w lr, [sp], #4
801b278: b003 add sp, #12
801b27a: 4770 bx lr
801b27c: 20000078 .word 0x20000078
0801b280 <_fwalk_reent>:
801b280: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
801b284: 4606 mov r6, r0
801b286: 4688 mov r8, r1
801b288: f100 0448 add.w r4, r0, #72 ; 0x48
801b28c: 2700 movs r7, #0
801b28e: e9d4 9501 ldrd r9, r5, [r4, #4]
801b292: f1b9 0901 subs.w r9, r9, #1
801b296: d505 bpl.n 801b2a4 <_fwalk_reent+0x24>
801b298: 6824 ldr r4, [r4, #0]
801b29a: 2c00 cmp r4, #0
801b29c: d1f7 bne.n 801b28e <_fwalk_reent+0xe>
801b29e: 4638 mov r0, r7
801b2a0: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
801b2a4: 89ab ldrh r3, [r5, #12]
801b2a6: 2b01 cmp r3, #1
801b2a8: d907 bls.n 801b2ba <_fwalk_reent+0x3a>
801b2aa: f9b5 300e ldrsh.w r3, [r5, #14]
801b2ae: 3301 adds r3, #1
801b2b0: d003 beq.n 801b2ba <_fwalk_reent+0x3a>
801b2b2: 4629 mov r1, r5
801b2b4: 4630 mov r0, r6
801b2b6: 47c0 blx r8
801b2b8: 4307 orrs r7, r0
801b2ba: 3568 adds r5, #104 ; 0x68
801b2bc: e7e9 b.n 801b292 <_fwalk_reent+0x12>
0801b2be <__retarget_lock_init_recursive>:
801b2be: 4770 bx lr
0801b2c0 <__retarget_lock_acquire_recursive>:
801b2c0: 4770 bx lr
0801b2c2 <__retarget_lock_release_recursive>:
801b2c2: 4770 bx lr
0801b2c4 <malloc>:
801b2c4: 4b02 ldr r3, [pc, #8] ; (801b2d0 <malloc+0xc>)
801b2c6: 4601 mov r1, r0
801b2c8: 6818 ldr r0, [r3, #0]
801b2ca: f000 b853 b.w 801b374 <_malloc_r>
801b2ce: bf00 nop
801b2d0: 20000078 .word 0x20000078
0801b2d4 <_free_r>:
801b2d4: b537 push {r0, r1, r2, r4, r5, lr}
801b2d6: 2900 cmp r1, #0
801b2d8: d048 beq.n 801b36c <_free_r+0x98>
801b2da: f851 3c04 ldr.w r3, [r1, #-4]
801b2de: 9001 str r0, [sp, #4]
801b2e0: 2b00 cmp r3, #0
801b2e2: f1a1 0404 sub.w r4, r1, #4
801b2e6: bfb8 it lt
801b2e8: 18e4 addlt r4, r4, r3
801b2ea: f000 fe01 bl 801bef0 <__malloc_lock>
801b2ee: 4a20 ldr r2, [pc, #128] ; (801b370 <_free_r+0x9c>)
801b2f0: 9801 ldr r0, [sp, #4]
801b2f2: 6813 ldr r3, [r2, #0]
801b2f4: 4615 mov r5, r2
801b2f6: b933 cbnz r3, 801b306 <_free_r+0x32>
801b2f8: 6063 str r3, [r4, #4]
801b2fa: 6014 str r4, [r2, #0]
801b2fc: b003 add sp, #12
801b2fe: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
801b302: f000 bdfb b.w 801befc <__malloc_unlock>
801b306: 42a3 cmp r3, r4
801b308: d90b bls.n 801b322 <_free_r+0x4e>
801b30a: 6821 ldr r1, [r4, #0]
801b30c: 1862 adds r2, r4, r1
801b30e: 4293 cmp r3, r2
801b310: bf04 itt eq
801b312: 681a ldreq r2, [r3, #0]
801b314: 685b ldreq r3, [r3, #4]
801b316: 6063 str r3, [r4, #4]
801b318: bf04 itt eq
801b31a: 1852 addeq r2, r2, r1
801b31c: 6022 streq r2, [r4, #0]
801b31e: 602c str r4, [r5, #0]
801b320: e7ec b.n 801b2fc <_free_r+0x28>
801b322: 461a mov r2, r3
801b324: 685b ldr r3, [r3, #4]
801b326: b10b cbz r3, 801b32c <_free_r+0x58>
801b328: 42a3 cmp r3, r4
801b32a: d9fa bls.n 801b322 <_free_r+0x4e>
801b32c: 6811 ldr r1, [r2, #0]
801b32e: 1855 adds r5, r2, r1
801b330: 42a5 cmp r5, r4
801b332: d10b bne.n 801b34c <_free_r+0x78>
801b334: 6824 ldr r4, [r4, #0]
801b336: 4421 add r1, r4
801b338: 1854 adds r4, r2, r1
801b33a: 42a3 cmp r3, r4
801b33c: 6011 str r1, [r2, #0]
801b33e: d1dd bne.n 801b2fc <_free_r+0x28>
801b340: 681c ldr r4, [r3, #0]
801b342: 685b ldr r3, [r3, #4]
801b344: 6053 str r3, [r2, #4]
801b346: 4421 add r1, r4
801b348: 6011 str r1, [r2, #0]
801b34a: e7d7 b.n 801b2fc <_free_r+0x28>
801b34c: d902 bls.n 801b354 <_free_r+0x80>
801b34e: 230c movs r3, #12
801b350: 6003 str r3, [r0, #0]
801b352: e7d3 b.n 801b2fc <_free_r+0x28>
801b354: 6825 ldr r5, [r4, #0]
801b356: 1961 adds r1, r4, r5
801b358: 428b cmp r3, r1
801b35a: bf04 itt eq
801b35c: 6819 ldreq r1, [r3, #0]
801b35e: 685b ldreq r3, [r3, #4]
801b360: 6063 str r3, [r4, #4]
801b362: bf04 itt eq
801b364: 1949 addeq r1, r1, r5
801b366: 6021 streq r1, [r4, #0]
801b368: 6054 str r4, [r2, #4]
801b36a: e7c7 b.n 801b2fc <_free_r+0x28>
801b36c: b003 add sp, #12
801b36e: bd30 pop {r4, r5, pc}
801b370: 20008868 .word 0x20008868
0801b374 <_malloc_r>:
801b374: b5f8 push {r3, r4, r5, r6, r7, lr}
801b376: 1ccd adds r5, r1, #3
801b378: f025 0503 bic.w r5, r5, #3
801b37c: 3508 adds r5, #8
801b37e: 2d0c cmp r5, #12
801b380: bf38 it cc
801b382: 250c movcc r5, #12
801b384: 2d00 cmp r5, #0
801b386: 4606 mov r6, r0
801b388: db01 blt.n 801b38e <_malloc_r+0x1a>
801b38a: 42a9 cmp r1, r5
801b38c: d903 bls.n 801b396 <_malloc_r+0x22>
801b38e: 230c movs r3, #12
801b390: 6033 str r3, [r6, #0]
801b392: 2000 movs r0, #0
801b394: bdf8 pop {r3, r4, r5, r6, r7, pc}
801b396: f000 fdab bl 801bef0 <__malloc_lock>
801b39a: 4921 ldr r1, [pc, #132] ; (801b420 <_malloc_r+0xac>)
801b39c: 680a ldr r2, [r1, #0]
801b39e: 4614 mov r4, r2
801b3a0: b99c cbnz r4, 801b3ca <_malloc_r+0x56>
801b3a2: 4f20 ldr r7, [pc, #128] ; (801b424 <_malloc_r+0xb0>)
801b3a4: 683b ldr r3, [r7, #0]
801b3a6: b923 cbnz r3, 801b3b2 <_malloc_r+0x3e>
801b3a8: 4621 mov r1, r4
801b3aa: 4630 mov r0, r6
801b3ac: f000 fb2a bl 801ba04 <_sbrk_r>
801b3b0: 6038 str r0, [r7, #0]
801b3b2: 4629 mov r1, r5
801b3b4: 4630 mov r0, r6
801b3b6: f000 fb25 bl 801ba04 <_sbrk_r>
801b3ba: 1c43 adds r3, r0, #1
801b3bc: d123 bne.n 801b406 <_malloc_r+0x92>
801b3be: 230c movs r3, #12
801b3c0: 6033 str r3, [r6, #0]
801b3c2: 4630 mov r0, r6
801b3c4: f000 fd9a bl 801befc <__malloc_unlock>
801b3c8: e7e3 b.n 801b392 <_malloc_r+0x1e>
801b3ca: 6823 ldr r3, [r4, #0]
801b3cc: 1b5b subs r3, r3, r5
801b3ce: d417 bmi.n 801b400 <_malloc_r+0x8c>
801b3d0: 2b0b cmp r3, #11
801b3d2: d903 bls.n 801b3dc <_malloc_r+0x68>
801b3d4: 6023 str r3, [r4, #0]
801b3d6: 441c add r4, r3
801b3d8: 6025 str r5, [r4, #0]
801b3da: e004 b.n 801b3e6 <_malloc_r+0x72>
801b3dc: 6863 ldr r3, [r4, #4]
801b3de: 42a2 cmp r2, r4
801b3e0: bf0c ite eq
801b3e2: 600b streq r3, [r1, #0]
801b3e4: 6053 strne r3, [r2, #4]
801b3e6: 4630 mov r0, r6
801b3e8: f000 fd88 bl 801befc <__malloc_unlock>
801b3ec: f104 000b add.w r0, r4, #11
801b3f0: 1d23 adds r3, r4, #4
801b3f2: f020 0007 bic.w r0, r0, #7
801b3f6: 1ac2 subs r2, r0, r3
801b3f8: d0cc beq.n 801b394 <_malloc_r+0x20>
801b3fa: 1a1b subs r3, r3, r0
801b3fc: 50a3 str r3, [r4, r2]
801b3fe: e7c9 b.n 801b394 <_malloc_r+0x20>
801b400: 4622 mov r2, r4
801b402: 6864 ldr r4, [r4, #4]
801b404: e7cc b.n 801b3a0 <_malloc_r+0x2c>
801b406: 1cc4 adds r4, r0, #3
801b408: f024 0403 bic.w r4, r4, #3
801b40c: 42a0 cmp r0, r4
801b40e: d0e3 beq.n 801b3d8 <_malloc_r+0x64>
801b410: 1a21 subs r1, r4, r0
801b412: 4630 mov r0, r6
801b414: f000 faf6 bl 801ba04 <_sbrk_r>
801b418: 3001 adds r0, #1
801b41a: d1dd bne.n 801b3d8 <_malloc_r+0x64>
801b41c: e7cf b.n 801b3be <_malloc_r+0x4a>
801b41e: bf00 nop
801b420: 20008868 .word 0x20008868
801b424: 2000886c .word 0x2000886c
0801b428 <__sfputc_r>:
801b428: 6893 ldr r3, [r2, #8]
801b42a: 3b01 subs r3, #1
801b42c: 2b00 cmp r3, #0
801b42e: b410 push {r4}
801b430: 6093 str r3, [r2, #8]
801b432: da08 bge.n 801b446 <__sfputc_r+0x1e>
801b434: 6994 ldr r4, [r2, #24]
801b436: 42a3 cmp r3, r4
801b438: db01 blt.n 801b43e <__sfputc_r+0x16>
801b43a: 290a cmp r1, #10
801b43c: d103 bne.n 801b446 <__sfputc_r+0x1e>
801b43e: f85d 4b04 ldr.w r4, [sp], #4
801b442: f000 bb33 b.w 801baac <__swbuf_r>
801b446: 6813 ldr r3, [r2, #0]
801b448: 1c58 adds r0, r3, #1
801b44a: 6010 str r0, [r2, #0]
801b44c: 7019 strb r1, [r3, #0]
801b44e: 4608 mov r0, r1
801b450: f85d 4b04 ldr.w r4, [sp], #4
801b454: 4770 bx lr
0801b456 <__sfputs_r>:
801b456: b5f8 push {r3, r4, r5, r6, r7, lr}
801b458: 4606 mov r6, r0
801b45a: 460f mov r7, r1
801b45c: 4614 mov r4, r2
801b45e: 18d5 adds r5, r2, r3
801b460: 42ac cmp r4, r5
801b462: d101 bne.n 801b468 <__sfputs_r+0x12>
801b464: 2000 movs r0, #0
801b466: e007 b.n 801b478 <__sfputs_r+0x22>
801b468: f814 1b01 ldrb.w r1, [r4], #1
801b46c: 463a mov r2, r7
801b46e: 4630 mov r0, r6
801b470: f7ff ffda bl 801b428 <__sfputc_r>
801b474: 1c43 adds r3, r0, #1
801b476: d1f3 bne.n 801b460 <__sfputs_r+0xa>
801b478: bdf8 pop {r3, r4, r5, r6, r7, pc}
...
0801b47c <_vfiprintf_r>:
801b47c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
801b480: 460d mov r5, r1
801b482: b09d sub sp, #116 ; 0x74
801b484: 4614 mov r4, r2
801b486: 4698 mov r8, r3
801b488: 4606 mov r6, r0
801b48a: b118 cbz r0, 801b494 <_vfiprintf_r+0x18>
801b48c: 6983 ldr r3, [r0, #24]
801b48e: b90b cbnz r3, 801b494 <_vfiprintf_r+0x18>
801b490: f7ff fe66 bl 801b160 <__sinit>
801b494: 4b89 ldr r3, [pc, #548] ; (801b6bc <_vfiprintf_r+0x240>)
801b496: 429d cmp r5, r3
801b498: d11b bne.n 801b4d2 <_vfiprintf_r+0x56>
801b49a: 6875 ldr r5, [r6, #4]
801b49c: 6e6b ldr r3, [r5, #100] ; 0x64
801b49e: 07d9 lsls r1, r3, #31
801b4a0: d405 bmi.n 801b4ae <_vfiprintf_r+0x32>
801b4a2: 89ab ldrh r3, [r5, #12]
801b4a4: 059a lsls r2, r3, #22
801b4a6: d402 bmi.n 801b4ae <_vfiprintf_r+0x32>
801b4a8: 6da8 ldr r0, [r5, #88] ; 0x58
801b4aa: f7ff ff09 bl 801b2c0 <__retarget_lock_acquire_recursive>
801b4ae: 89ab ldrh r3, [r5, #12]
801b4b0: 071b lsls r3, r3, #28
801b4b2: d501 bpl.n 801b4b8 <_vfiprintf_r+0x3c>
801b4b4: 692b ldr r3, [r5, #16]
801b4b6: b9eb cbnz r3, 801b4f4 <_vfiprintf_r+0x78>
801b4b8: 4629 mov r1, r5
801b4ba: 4630 mov r0, r6
801b4bc: f000 fb5a bl 801bb74 <__swsetup_r>
801b4c0: b1c0 cbz r0, 801b4f4 <_vfiprintf_r+0x78>
801b4c2: 6e6b ldr r3, [r5, #100] ; 0x64
801b4c4: 07dc lsls r4, r3, #31
801b4c6: d50e bpl.n 801b4e6 <_vfiprintf_r+0x6a>
801b4c8: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
801b4cc: b01d add sp, #116 ; 0x74
801b4ce: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
801b4d2: 4b7b ldr r3, [pc, #492] ; (801b6c0 <_vfiprintf_r+0x244>)
801b4d4: 429d cmp r5, r3
801b4d6: d101 bne.n 801b4dc <_vfiprintf_r+0x60>
801b4d8: 68b5 ldr r5, [r6, #8]
801b4da: e7df b.n 801b49c <_vfiprintf_r+0x20>
801b4dc: 4b79 ldr r3, [pc, #484] ; (801b6c4 <_vfiprintf_r+0x248>)
801b4de: 429d cmp r5, r3
801b4e0: bf08 it eq
801b4e2: 68f5 ldreq r5, [r6, #12]
801b4e4: e7da b.n 801b49c <_vfiprintf_r+0x20>
801b4e6: 89ab ldrh r3, [r5, #12]
801b4e8: 0598 lsls r0, r3, #22
801b4ea: d4ed bmi.n 801b4c8 <_vfiprintf_r+0x4c>
801b4ec: 6da8 ldr r0, [r5, #88] ; 0x58
801b4ee: f7ff fee8 bl 801b2c2 <__retarget_lock_release_recursive>
801b4f2: e7e9 b.n 801b4c8 <_vfiprintf_r+0x4c>
801b4f4: 2300 movs r3, #0
801b4f6: 9309 str r3, [sp, #36] ; 0x24
801b4f8: 2320 movs r3, #32
801b4fa: f88d 3029 strb.w r3, [sp, #41] ; 0x29
801b4fe: f8cd 800c str.w r8, [sp, #12]
801b502: 2330 movs r3, #48 ; 0x30
801b504: f8df 81c0 ldr.w r8, [pc, #448] ; 801b6c8 <_vfiprintf_r+0x24c>
801b508: f88d 302a strb.w r3, [sp, #42] ; 0x2a
801b50c: f04f 0901 mov.w r9, #1
801b510: 4623 mov r3, r4
801b512: 469a mov sl, r3
801b514: f813 2b01 ldrb.w r2, [r3], #1
801b518: b10a cbz r2, 801b51e <_vfiprintf_r+0xa2>
801b51a: 2a25 cmp r2, #37 ; 0x25
801b51c: d1f9 bne.n 801b512 <_vfiprintf_r+0x96>
801b51e: ebba 0b04 subs.w fp, sl, r4
801b522: d00b beq.n 801b53c <_vfiprintf_r+0xc0>
801b524: 465b mov r3, fp
801b526: 4622 mov r2, r4
801b528: 4629 mov r1, r5
801b52a: 4630 mov r0, r6
801b52c: f7ff ff93 bl 801b456 <__sfputs_r>
801b530: 3001 adds r0, #1
801b532: f000 80aa beq.w 801b68a <_vfiprintf_r+0x20e>
801b536: 9a09 ldr r2, [sp, #36] ; 0x24
801b538: 445a add r2, fp
801b53a: 9209 str r2, [sp, #36] ; 0x24
801b53c: f89a 3000 ldrb.w r3, [sl]
801b540: 2b00 cmp r3, #0
801b542: f000 80a2 beq.w 801b68a <_vfiprintf_r+0x20e>
801b546: 2300 movs r3, #0
801b548: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
801b54c: e9cd 2305 strd r2, r3, [sp, #20]
801b550: f10a 0a01 add.w sl, sl, #1
801b554: 9304 str r3, [sp, #16]
801b556: 9307 str r3, [sp, #28]
801b558: f88d 3053 strb.w r3, [sp, #83] ; 0x53
801b55c: 931a str r3, [sp, #104] ; 0x68
801b55e: 4654 mov r4, sl
801b560: 2205 movs r2, #5
801b562: f814 1b01 ldrb.w r1, [r4], #1
801b566: 4858 ldr r0, [pc, #352] ; (801b6c8 <_vfiprintf_r+0x24c>)
801b568: f7e4 fe52 bl 8000210 <memchr>
801b56c: 9a04 ldr r2, [sp, #16]
801b56e: b9d8 cbnz r0, 801b5a8 <_vfiprintf_r+0x12c>
801b570: 06d1 lsls r1, r2, #27
801b572: bf44 itt mi
801b574: 2320 movmi r3, #32
801b576: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
801b57a: 0713 lsls r3, r2, #28
801b57c: bf44 itt mi
801b57e: 232b movmi r3, #43 ; 0x2b
801b580: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
801b584: f89a 3000 ldrb.w r3, [sl]
801b588: 2b2a cmp r3, #42 ; 0x2a
801b58a: d015 beq.n 801b5b8 <_vfiprintf_r+0x13c>
801b58c: 9a07 ldr r2, [sp, #28]
801b58e: 4654 mov r4, sl
801b590: 2000 movs r0, #0
801b592: f04f 0c0a mov.w ip, #10
801b596: 4621 mov r1, r4
801b598: f811 3b01 ldrb.w r3, [r1], #1
801b59c: 3b30 subs r3, #48 ; 0x30
801b59e: 2b09 cmp r3, #9
801b5a0: d94e bls.n 801b640 <_vfiprintf_r+0x1c4>
801b5a2: b1b0 cbz r0, 801b5d2 <_vfiprintf_r+0x156>
801b5a4: 9207 str r2, [sp, #28]
801b5a6: e014 b.n 801b5d2 <_vfiprintf_r+0x156>
801b5a8: eba0 0308 sub.w r3, r0, r8
801b5ac: fa09 f303 lsl.w r3, r9, r3
801b5b0: 4313 orrs r3, r2
801b5b2: 9304 str r3, [sp, #16]
801b5b4: 46a2 mov sl, r4
801b5b6: e7d2 b.n 801b55e <_vfiprintf_r+0xe2>
801b5b8: 9b03 ldr r3, [sp, #12]
801b5ba: 1d19 adds r1, r3, #4
801b5bc: 681b ldr r3, [r3, #0]
801b5be: 9103 str r1, [sp, #12]
801b5c0: 2b00 cmp r3, #0
801b5c2: bfbb ittet lt
801b5c4: 425b neglt r3, r3
801b5c6: f042 0202 orrlt.w r2, r2, #2
801b5ca: 9307 strge r3, [sp, #28]
801b5cc: 9307 strlt r3, [sp, #28]
801b5ce: bfb8 it lt
801b5d0: 9204 strlt r2, [sp, #16]
801b5d2: 7823 ldrb r3, [r4, #0]
801b5d4: 2b2e cmp r3, #46 ; 0x2e
801b5d6: d10c bne.n 801b5f2 <_vfiprintf_r+0x176>
801b5d8: 7863 ldrb r3, [r4, #1]
801b5da: 2b2a cmp r3, #42 ; 0x2a
801b5dc: d135 bne.n 801b64a <_vfiprintf_r+0x1ce>
801b5de: 9b03 ldr r3, [sp, #12]
801b5e0: 1d1a adds r2, r3, #4
801b5e2: 681b ldr r3, [r3, #0]
801b5e4: 9203 str r2, [sp, #12]
801b5e6: 2b00 cmp r3, #0
801b5e8: bfb8 it lt
801b5ea: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff
801b5ee: 3402 adds r4, #2
801b5f0: 9305 str r3, [sp, #20]
801b5f2: f8df a0e4 ldr.w sl, [pc, #228] ; 801b6d8 <_vfiprintf_r+0x25c>
801b5f6: 7821 ldrb r1, [r4, #0]
801b5f8: 2203 movs r2, #3
801b5fa: 4650 mov r0, sl
801b5fc: f7e4 fe08 bl 8000210 <memchr>
801b600: b140 cbz r0, 801b614 <_vfiprintf_r+0x198>
801b602: 2340 movs r3, #64 ; 0x40
801b604: eba0 000a sub.w r0, r0, sl
801b608: fa03 f000 lsl.w r0, r3, r0
801b60c: 9b04 ldr r3, [sp, #16]
801b60e: 4303 orrs r3, r0
801b610: 3401 adds r4, #1
801b612: 9304 str r3, [sp, #16]
801b614: f814 1b01 ldrb.w r1, [r4], #1
801b618: 482c ldr r0, [pc, #176] ; (801b6cc <_vfiprintf_r+0x250>)
801b61a: f88d 1028 strb.w r1, [sp, #40] ; 0x28
801b61e: 2206 movs r2, #6
801b620: f7e4 fdf6 bl 8000210 <memchr>
801b624: 2800 cmp r0, #0
801b626: d03f beq.n 801b6a8 <_vfiprintf_r+0x22c>
801b628: 4b29 ldr r3, [pc, #164] ; (801b6d0 <_vfiprintf_r+0x254>)
801b62a: bb1b cbnz r3, 801b674 <_vfiprintf_r+0x1f8>
801b62c: 9b03 ldr r3, [sp, #12]
801b62e: 3307 adds r3, #7
801b630: f023 0307 bic.w r3, r3, #7
801b634: 3308 adds r3, #8
801b636: 9303 str r3, [sp, #12]
801b638: 9b09 ldr r3, [sp, #36] ; 0x24
801b63a: 443b add r3, r7
801b63c: 9309 str r3, [sp, #36] ; 0x24
801b63e: e767 b.n 801b510 <_vfiprintf_r+0x94>
801b640: fb0c 3202 mla r2, ip, r2, r3
801b644: 460c mov r4, r1
801b646: 2001 movs r0, #1
801b648: e7a5 b.n 801b596 <_vfiprintf_r+0x11a>
801b64a: 2300 movs r3, #0
801b64c: 3401 adds r4, #1
801b64e: 9305 str r3, [sp, #20]
801b650: 4619 mov r1, r3
801b652: f04f 0c0a mov.w ip, #10
801b656: 4620 mov r0, r4
801b658: f810 2b01 ldrb.w r2, [r0], #1
801b65c: 3a30 subs r2, #48 ; 0x30
801b65e: 2a09 cmp r2, #9
801b660: d903 bls.n 801b66a <_vfiprintf_r+0x1ee>
801b662: 2b00 cmp r3, #0
801b664: d0c5 beq.n 801b5f2 <_vfiprintf_r+0x176>
801b666: 9105 str r1, [sp, #20]
801b668: e7c3 b.n 801b5f2 <_vfiprintf_r+0x176>
801b66a: fb0c 2101 mla r1, ip, r1, r2
801b66e: 4604 mov r4, r0
801b670: 2301 movs r3, #1
801b672: e7f0 b.n 801b656 <_vfiprintf_r+0x1da>
801b674: ab03 add r3, sp, #12
801b676: 9300 str r3, [sp, #0]
801b678: 462a mov r2, r5
801b67a: 4b16 ldr r3, [pc, #88] ; (801b6d4 <_vfiprintf_r+0x258>)
801b67c: a904 add r1, sp, #16
801b67e: 4630 mov r0, r6
801b680: f3af 8000 nop.w
801b684: 4607 mov r7, r0
801b686: 1c78 adds r0, r7, #1
801b688: d1d6 bne.n 801b638 <_vfiprintf_r+0x1bc>
801b68a: 6e6b ldr r3, [r5, #100] ; 0x64
801b68c: 07d9 lsls r1, r3, #31
801b68e: d405 bmi.n 801b69c <_vfiprintf_r+0x220>
801b690: 89ab ldrh r3, [r5, #12]
801b692: 059a lsls r2, r3, #22
801b694: d402 bmi.n 801b69c <_vfiprintf_r+0x220>
801b696: 6da8 ldr r0, [r5, #88] ; 0x58
801b698: f7ff fe13 bl 801b2c2 <__retarget_lock_release_recursive>
801b69c: 89ab ldrh r3, [r5, #12]
801b69e: 065b lsls r3, r3, #25
801b6a0: f53f af12 bmi.w 801b4c8 <_vfiprintf_r+0x4c>
801b6a4: 9809 ldr r0, [sp, #36] ; 0x24
801b6a6: e711 b.n 801b4cc <_vfiprintf_r+0x50>
801b6a8: ab03 add r3, sp, #12
801b6aa: 9300 str r3, [sp, #0]
801b6ac: 462a mov r2, r5
801b6ae: 4b09 ldr r3, [pc, #36] ; (801b6d4 <_vfiprintf_r+0x258>)
801b6b0: a904 add r1, sp, #16
801b6b2: 4630 mov r0, r6
801b6b4: f000 f880 bl 801b7b8 <_printf_i>
801b6b8: e7e4 b.n 801b684 <_vfiprintf_r+0x208>
801b6ba: bf00 nop
801b6bc: 08021134 .word 0x08021134
801b6c0: 08021154 .word 0x08021154
801b6c4: 08021114 .word 0x08021114
801b6c8: 08021174 .word 0x08021174
801b6cc: 0802117e .word 0x0802117e
801b6d0: 00000000 .word 0x00000000
801b6d4: 0801b457 .word 0x0801b457
801b6d8: 0802117a .word 0x0802117a
0801b6dc <_printf_common>:
801b6dc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
801b6e0: 4616 mov r6, r2
801b6e2: 4699 mov r9, r3
801b6e4: 688a ldr r2, [r1, #8]
801b6e6: 690b ldr r3, [r1, #16]
801b6e8: f8dd 8020 ldr.w r8, [sp, #32]
801b6ec: 4293 cmp r3, r2
801b6ee: bfb8 it lt
801b6f0: 4613 movlt r3, r2
801b6f2: 6033 str r3, [r6, #0]
801b6f4: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
801b6f8: 4607 mov r7, r0
801b6fa: 460c mov r4, r1
801b6fc: b10a cbz r2, 801b702 <_printf_common+0x26>
801b6fe: 3301 adds r3, #1
801b700: 6033 str r3, [r6, #0]
801b702: 6823 ldr r3, [r4, #0]
801b704: 0699 lsls r1, r3, #26
801b706: bf42 ittt mi
801b708: 6833 ldrmi r3, [r6, #0]
801b70a: 3302 addmi r3, #2
801b70c: 6033 strmi r3, [r6, #0]
801b70e: 6825 ldr r5, [r4, #0]
801b710: f015 0506 ands.w r5, r5, #6
801b714: d106 bne.n 801b724 <_printf_common+0x48>
801b716: f104 0a19 add.w sl, r4, #25
801b71a: 68e3 ldr r3, [r4, #12]
801b71c: 6832 ldr r2, [r6, #0]
801b71e: 1a9b subs r3, r3, r2
801b720: 42ab cmp r3, r5
801b722: dc26 bgt.n 801b772 <_printf_common+0x96>
801b724: f894 2043 ldrb.w r2, [r4, #67] ; 0x43
801b728: 1e13 subs r3, r2, #0
801b72a: 6822 ldr r2, [r4, #0]
801b72c: bf18 it ne
801b72e: 2301 movne r3, #1
801b730: 0692 lsls r2, r2, #26
801b732: d42b bmi.n 801b78c <_printf_common+0xb0>
801b734: f104 0243 add.w r2, r4, #67 ; 0x43
801b738: 4649 mov r1, r9
801b73a: 4638 mov r0, r7
801b73c: 47c0 blx r8
801b73e: 3001 adds r0, #1
801b740: d01e beq.n 801b780 <_printf_common+0xa4>
801b742: 6823 ldr r3, [r4, #0]
801b744: 68e5 ldr r5, [r4, #12]
801b746: 6832 ldr r2, [r6, #0]
801b748: f003 0306 and.w r3, r3, #6
801b74c: 2b04 cmp r3, #4
801b74e: bf08 it eq
801b750: 1aad subeq r5, r5, r2
801b752: 68a3 ldr r3, [r4, #8]
801b754: 6922 ldr r2, [r4, #16]
801b756: bf0c ite eq
801b758: ea25 75e5 biceq.w r5, r5, r5, asr #31
801b75c: 2500 movne r5, #0
801b75e: 4293 cmp r3, r2
801b760: bfc4 itt gt
801b762: 1a9b subgt r3, r3, r2
801b764: 18ed addgt r5, r5, r3
801b766: 2600 movs r6, #0
801b768: 341a adds r4, #26
801b76a: 42b5 cmp r5, r6
801b76c: d11a bne.n 801b7a4 <_printf_common+0xc8>
801b76e: 2000 movs r0, #0
801b770: e008 b.n 801b784 <_printf_common+0xa8>
801b772: 2301 movs r3, #1
801b774: 4652 mov r2, sl
801b776: 4649 mov r1, r9
801b778: 4638 mov r0, r7
801b77a: 47c0 blx r8
801b77c: 3001 adds r0, #1
801b77e: d103 bne.n 801b788 <_printf_common+0xac>
801b780: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
801b784: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
801b788: 3501 adds r5, #1
801b78a: e7c6 b.n 801b71a <_printf_common+0x3e>
801b78c: 18e1 adds r1, r4, r3
801b78e: 1c5a adds r2, r3, #1
801b790: 2030 movs r0, #48 ; 0x30
801b792: f881 0043 strb.w r0, [r1, #67] ; 0x43
801b796: 4422 add r2, r4
801b798: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
801b79c: f882 1043 strb.w r1, [r2, #67] ; 0x43
801b7a0: 3302 adds r3, #2
801b7a2: e7c7 b.n 801b734 <_printf_common+0x58>
801b7a4: 2301 movs r3, #1
801b7a6: 4622 mov r2, r4
801b7a8: 4649 mov r1, r9
801b7aa: 4638 mov r0, r7
801b7ac: 47c0 blx r8
801b7ae: 3001 adds r0, #1
801b7b0: d0e6 beq.n 801b780 <_printf_common+0xa4>
801b7b2: 3601 adds r6, #1
801b7b4: e7d9 b.n 801b76a <_printf_common+0x8e>
...
0801b7b8 <_printf_i>:
801b7b8: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
801b7bc: 460c mov r4, r1
801b7be: 4691 mov r9, r2
801b7c0: 7e27 ldrb r7, [r4, #24]
801b7c2: 990c ldr r1, [sp, #48] ; 0x30
801b7c4: 2f78 cmp r7, #120 ; 0x78
801b7c6: 4680 mov r8, r0
801b7c8: 469a mov sl, r3
801b7ca: f104 0243 add.w r2, r4, #67 ; 0x43
801b7ce: d807 bhi.n 801b7e0 <_printf_i+0x28>
801b7d0: 2f62 cmp r7, #98 ; 0x62
801b7d2: d80a bhi.n 801b7ea <_printf_i+0x32>
801b7d4: 2f00 cmp r7, #0
801b7d6: f000 80d8 beq.w 801b98a <_printf_i+0x1d2>
801b7da: 2f58 cmp r7, #88 ; 0x58
801b7dc: f000 80a3 beq.w 801b926 <_printf_i+0x16e>
801b7e0: f104 0642 add.w r6, r4, #66 ; 0x42
801b7e4: f884 7042 strb.w r7, [r4, #66] ; 0x42
801b7e8: e03a b.n 801b860 <_printf_i+0xa8>
801b7ea: f1a7 0363 sub.w r3, r7, #99 ; 0x63
801b7ee: 2b15 cmp r3, #21
801b7f0: d8f6 bhi.n 801b7e0 <_printf_i+0x28>
801b7f2: a001 add r0, pc, #4 ; (adr r0, 801b7f8 <_printf_i+0x40>)
801b7f4: f850 f023 ldr.w pc, [r0, r3, lsl #2]
801b7f8: 0801b851 .word 0x0801b851
801b7fc: 0801b865 .word 0x0801b865
801b800: 0801b7e1 .word 0x0801b7e1
801b804: 0801b7e1 .word 0x0801b7e1
801b808: 0801b7e1 .word 0x0801b7e1
801b80c: 0801b7e1 .word 0x0801b7e1
801b810: 0801b865 .word 0x0801b865
801b814: 0801b7e1 .word 0x0801b7e1
801b818: 0801b7e1 .word 0x0801b7e1
801b81c: 0801b7e1 .word 0x0801b7e1
801b820: 0801b7e1 .word 0x0801b7e1
801b824: 0801b971 .word 0x0801b971
801b828: 0801b895 .word 0x0801b895
801b82c: 0801b953 .word 0x0801b953
801b830: 0801b7e1 .word 0x0801b7e1
801b834: 0801b7e1 .word 0x0801b7e1
801b838: 0801b993 .word 0x0801b993
801b83c: 0801b7e1 .word 0x0801b7e1
801b840: 0801b895 .word 0x0801b895
801b844: 0801b7e1 .word 0x0801b7e1
801b848: 0801b7e1 .word 0x0801b7e1
801b84c: 0801b95b .word 0x0801b95b
801b850: 680b ldr r3, [r1, #0]
801b852: 1d1a adds r2, r3, #4
801b854: 681b ldr r3, [r3, #0]
801b856: 600a str r2, [r1, #0]
801b858: f104 0642 add.w r6, r4, #66 ; 0x42
801b85c: f884 3042 strb.w r3, [r4, #66] ; 0x42
801b860: 2301 movs r3, #1
801b862: e0a3 b.n 801b9ac <_printf_i+0x1f4>
801b864: 6825 ldr r5, [r4, #0]
801b866: 6808 ldr r0, [r1, #0]
801b868: 062e lsls r6, r5, #24
801b86a: f100 0304 add.w r3, r0, #4
801b86e: d50a bpl.n 801b886 <_printf_i+0xce>
801b870: 6805 ldr r5, [r0, #0]
801b872: 600b str r3, [r1, #0]
801b874: 2d00 cmp r5, #0
801b876: da03 bge.n 801b880 <_printf_i+0xc8>
801b878: 232d movs r3, #45 ; 0x2d
801b87a: 426d negs r5, r5
801b87c: f884 3043 strb.w r3, [r4, #67] ; 0x43
801b880: 485e ldr r0, [pc, #376] ; (801b9fc <_printf_i+0x244>)
801b882: 230a movs r3, #10
801b884: e019 b.n 801b8ba <_printf_i+0x102>
801b886: f015 0f40 tst.w r5, #64 ; 0x40
801b88a: 6805 ldr r5, [r0, #0]
801b88c: 600b str r3, [r1, #0]
801b88e: bf18 it ne
801b890: b22d sxthne r5, r5
801b892: e7ef b.n 801b874 <_printf_i+0xbc>
801b894: 680b ldr r3, [r1, #0]
801b896: 6825 ldr r5, [r4, #0]
801b898: 1d18 adds r0, r3, #4
801b89a: 6008 str r0, [r1, #0]
801b89c: 0628 lsls r0, r5, #24
801b89e: d501 bpl.n 801b8a4 <_printf_i+0xec>
801b8a0: 681d ldr r5, [r3, #0]
801b8a2: e002 b.n 801b8aa <_printf_i+0xf2>
801b8a4: 0669 lsls r1, r5, #25
801b8a6: d5fb bpl.n 801b8a0 <_printf_i+0xe8>
801b8a8: 881d ldrh r5, [r3, #0]
801b8aa: 4854 ldr r0, [pc, #336] ; (801b9fc <_printf_i+0x244>)
801b8ac: 2f6f cmp r7, #111 ; 0x6f
801b8ae: bf0c ite eq
801b8b0: 2308 moveq r3, #8
801b8b2: 230a movne r3, #10
801b8b4: 2100 movs r1, #0
801b8b6: f884 1043 strb.w r1, [r4, #67] ; 0x43
801b8ba: 6866 ldr r6, [r4, #4]
801b8bc: 60a6 str r6, [r4, #8]
801b8be: 2e00 cmp r6, #0
801b8c0: bfa2 ittt ge
801b8c2: 6821 ldrge r1, [r4, #0]
801b8c4: f021 0104 bicge.w r1, r1, #4
801b8c8: 6021 strge r1, [r4, #0]
801b8ca: b90d cbnz r5, 801b8d0 <_printf_i+0x118>
801b8cc: 2e00 cmp r6, #0
801b8ce: d04d beq.n 801b96c <_printf_i+0x1b4>
801b8d0: 4616 mov r6, r2
801b8d2: fbb5 f1f3 udiv r1, r5, r3
801b8d6: fb03 5711 mls r7, r3, r1, r5
801b8da: 5dc7 ldrb r7, [r0, r7]
801b8dc: f806 7d01 strb.w r7, [r6, #-1]!
801b8e0: 462f mov r7, r5
801b8e2: 42bb cmp r3, r7
801b8e4: 460d mov r5, r1
801b8e6: d9f4 bls.n 801b8d2 <_printf_i+0x11a>
801b8e8: 2b08 cmp r3, #8
801b8ea: d10b bne.n 801b904 <_printf_i+0x14c>
801b8ec: 6823 ldr r3, [r4, #0]
801b8ee: 07df lsls r7, r3, #31
801b8f0: d508 bpl.n 801b904 <_printf_i+0x14c>
801b8f2: 6923 ldr r3, [r4, #16]
801b8f4: 6861 ldr r1, [r4, #4]
801b8f6: 4299 cmp r1, r3
801b8f8: bfde ittt le
801b8fa: 2330 movle r3, #48 ; 0x30
801b8fc: f806 3c01 strble.w r3, [r6, #-1]
801b900: f106 36ff addle.w r6, r6, #4294967295 ; 0xffffffff
801b904: 1b92 subs r2, r2, r6
801b906: 6122 str r2, [r4, #16]
801b908: f8cd a000 str.w sl, [sp]
801b90c: 464b mov r3, r9
801b90e: aa03 add r2, sp, #12
801b910: 4621 mov r1, r4
801b912: 4640 mov r0, r8
801b914: f7ff fee2 bl 801b6dc <_printf_common>
801b918: 3001 adds r0, #1
801b91a: d14c bne.n 801b9b6 <_printf_i+0x1fe>
801b91c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
801b920: b004 add sp, #16
801b922: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
801b926: 4835 ldr r0, [pc, #212] ; (801b9fc <_printf_i+0x244>)
801b928: f884 7045 strb.w r7, [r4, #69] ; 0x45
801b92c: 6823 ldr r3, [r4, #0]
801b92e: 680e ldr r6, [r1, #0]
801b930: 061f lsls r7, r3, #24
801b932: f856 5b04 ldr.w r5, [r6], #4
801b936: 600e str r6, [r1, #0]
801b938: d514 bpl.n 801b964 <_printf_i+0x1ac>
801b93a: 07d9 lsls r1, r3, #31
801b93c: bf44 itt mi
801b93e: f043 0320 orrmi.w r3, r3, #32
801b942: 6023 strmi r3, [r4, #0]
801b944: b91d cbnz r5, 801b94e <_printf_i+0x196>
801b946: 6823 ldr r3, [r4, #0]
801b948: f023 0320 bic.w r3, r3, #32
801b94c: 6023 str r3, [r4, #0]
801b94e: 2310 movs r3, #16
801b950: e7b0 b.n 801b8b4 <_printf_i+0xfc>
801b952: 6823 ldr r3, [r4, #0]
801b954: f043 0320 orr.w r3, r3, #32
801b958: 6023 str r3, [r4, #0]
801b95a: 2378 movs r3, #120 ; 0x78
801b95c: 4828 ldr r0, [pc, #160] ; (801ba00 <_printf_i+0x248>)
801b95e: f884 3045 strb.w r3, [r4, #69] ; 0x45
801b962: e7e3 b.n 801b92c <_printf_i+0x174>
801b964: 065e lsls r6, r3, #25
801b966: bf48 it mi
801b968: b2ad uxthmi r5, r5
801b96a: e7e6 b.n 801b93a <_printf_i+0x182>
801b96c: 4616 mov r6, r2
801b96e: e7bb b.n 801b8e8 <_printf_i+0x130>
801b970: 680b ldr r3, [r1, #0]
801b972: 6826 ldr r6, [r4, #0]
801b974: 6960 ldr r0, [r4, #20]
801b976: 1d1d adds r5, r3, #4
801b978: 600d str r5, [r1, #0]
801b97a: 0635 lsls r5, r6, #24
801b97c: 681b ldr r3, [r3, #0]
801b97e: d501 bpl.n 801b984 <_printf_i+0x1cc>
801b980: 6018 str r0, [r3, #0]
801b982: e002 b.n 801b98a <_printf_i+0x1d2>
801b984: 0671 lsls r1, r6, #25
801b986: d5fb bpl.n 801b980 <_printf_i+0x1c8>
801b988: 8018 strh r0, [r3, #0]
801b98a: 2300 movs r3, #0
801b98c: 6123 str r3, [r4, #16]
801b98e: 4616 mov r6, r2
801b990: e7ba b.n 801b908 <_printf_i+0x150>
801b992: 680b ldr r3, [r1, #0]
801b994: 1d1a adds r2, r3, #4
801b996: 600a str r2, [r1, #0]
801b998: 681e ldr r6, [r3, #0]
801b99a: 6862 ldr r2, [r4, #4]
801b99c: 2100 movs r1, #0
801b99e: 4630 mov r0, r6
801b9a0: f7e4 fc36 bl 8000210 <memchr>
801b9a4: b108 cbz r0, 801b9aa <_printf_i+0x1f2>
801b9a6: 1b80 subs r0, r0, r6
801b9a8: 6060 str r0, [r4, #4]
801b9aa: 6863 ldr r3, [r4, #4]
801b9ac: 6123 str r3, [r4, #16]
801b9ae: 2300 movs r3, #0
801b9b0: f884 3043 strb.w r3, [r4, #67] ; 0x43
801b9b4: e7a8 b.n 801b908 <_printf_i+0x150>
801b9b6: 6923 ldr r3, [r4, #16]
801b9b8: 4632 mov r2, r6
801b9ba: 4649 mov r1, r9
801b9bc: 4640 mov r0, r8
801b9be: 47d0 blx sl
801b9c0: 3001 adds r0, #1
801b9c2: d0ab beq.n 801b91c <_printf_i+0x164>
801b9c4: 6823 ldr r3, [r4, #0]
801b9c6: 079b lsls r3, r3, #30
801b9c8: d413 bmi.n 801b9f2 <_printf_i+0x23a>
801b9ca: 68e0 ldr r0, [r4, #12]
801b9cc: 9b03 ldr r3, [sp, #12]
801b9ce: 4298 cmp r0, r3
801b9d0: bfb8 it lt
801b9d2: 4618 movlt r0, r3
801b9d4: e7a4 b.n 801b920 <_printf_i+0x168>
801b9d6: 2301 movs r3, #1
801b9d8: 4632 mov r2, r6
801b9da: 4649 mov r1, r9
801b9dc: 4640 mov r0, r8
801b9de: 47d0 blx sl
801b9e0: 3001 adds r0, #1
801b9e2: d09b beq.n 801b91c <_printf_i+0x164>
801b9e4: 3501 adds r5, #1
801b9e6: 68e3 ldr r3, [r4, #12]
801b9e8: 9903 ldr r1, [sp, #12]
801b9ea: 1a5b subs r3, r3, r1
801b9ec: 42ab cmp r3, r5
801b9ee: dcf2 bgt.n 801b9d6 <_printf_i+0x21e>
801b9f0: e7eb b.n 801b9ca <_printf_i+0x212>
801b9f2: 2500 movs r5, #0
801b9f4: f104 0619 add.w r6, r4, #25
801b9f8: e7f5 b.n 801b9e6 <_printf_i+0x22e>
801b9fa: bf00 nop
801b9fc: 08021185 .word 0x08021185
801ba00: 08021196 .word 0x08021196
0801ba04 <_sbrk_r>:
801ba04: b538 push {r3, r4, r5, lr}
801ba06: 4d06 ldr r5, [pc, #24] ; (801ba20 <_sbrk_r+0x1c>)
801ba08: 2300 movs r3, #0
801ba0a: 4604 mov r4, r0
801ba0c: 4608 mov r0, r1
801ba0e: 602b str r3, [r5, #0]
801ba10: f7e8 fe46 bl 80046a0 <_sbrk>
801ba14: 1c43 adds r3, r0, #1
801ba16: d102 bne.n 801ba1e <_sbrk_r+0x1a>
801ba18: 682b ldr r3, [r5, #0]
801ba1a: b103 cbz r3, 801ba1e <_sbrk_r+0x1a>
801ba1c: 6023 str r3, [r4, #0]
801ba1e: bd38 pop {r3, r4, r5, pc}
801ba20: 2000f880 .word 0x2000f880
0801ba24 <__sread>:
801ba24: b510 push {r4, lr}
801ba26: 460c mov r4, r1
801ba28: f9b1 100e ldrsh.w r1, [r1, #14]
801ba2c: f000 fa6c bl 801bf08 <_read_r>
801ba30: 2800 cmp r0, #0
801ba32: bfab itete ge
801ba34: 6d63 ldrge r3, [r4, #84] ; 0x54
801ba36: 89a3 ldrhlt r3, [r4, #12]
801ba38: 181b addge r3, r3, r0
801ba3a: f423 5380 biclt.w r3, r3, #4096 ; 0x1000
801ba3e: bfac ite ge
801ba40: 6563 strge r3, [r4, #84] ; 0x54
801ba42: 81a3 strhlt r3, [r4, #12]
801ba44: bd10 pop {r4, pc}
0801ba46 <__swrite>:
801ba46: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
801ba4a: 461f mov r7, r3
801ba4c: 898b ldrh r3, [r1, #12]
801ba4e: 05db lsls r3, r3, #23
801ba50: 4605 mov r5, r0
801ba52: 460c mov r4, r1
801ba54: 4616 mov r6, r2
801ba56: d505 bpl.n 801ba64 <__swrite+0x1e>
801ba58: f9b1 100e ldrsh.w r1, [r1, #14]
801ba5c: 2302 movs r3, #2
801ba5e: 2200 movs r2, #0
801ba60: f000 f9d0 bl 801be04 <_lseek_r>
801ba64: 89a3 ldrh r3, [r4, #12]
801ba66: f9b4 100e ldrsh.w r1, [r4, #14]
801ba6a: f423 5380 bic.w r3, r3, #4096 ; 0x1000
801ba6e: 81a3 strh r3, [r4, #12]
801ba70: 4632 mov r2, r6
801ba72: 463b mov r3, r7
801ba74: 4628 mov r0, r5
801ba76: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
801ba7a: f000 b869 b.w 801bb50 <_write_r>
0801ba7e <__sseek>:
801ba7e: b510 push {r4, lr}
801ba80: 460c mov r4, r1
801ba82: f9b1 100e ldrsh.w r1, [r1, #14]
801ba86: f000 f9bd bl 801be04 <_lseek_r>
801ba8a: 1c43 adds r3, r0, #1
801ba8c: 89a3 ldrh r3, [r4, #12]
801ba8e: bf15 itete ne
801ba90: 6560 strne r0, [r4, #84] ; 0x54
801ba92: f423 5380 biceq.w r3, r3, #4096 ; 0x1000
801ba96: f443 5380 orrne.w r3, r3, #4096 ; 0x1000
801ba9a: 81a3 strheq r3, [r4, #12]
801ba9c: bf18 it ne
801ba9e: 81a3 strhne r3, [r4, #12]
801baa0: bd10 pop {r4, pc}
0801baa2 <__sclose>:
801baa2: f9b1 100e ldrsh.w r1, [r1, #14]
801baa6: f000 b8db b.w 801bc60 <_close_r>
...
0801baac <__swbuf_r>:
801baac: b5f8 push {r3, r4, r5, r6, r7, lr}
801baae: 460e mov r6, r1
801bab0: 4614 mov r4, r2
801bab2: 4605 mov r5, r0
801bab4: b118 cbz r0, 801babe <__swbuf_r+0x12>
801bab6: 6983 ldr r3, [r0, #24]
801bab8: b90b cbnz r3, 801babe <__swbuf_r+0x12>
801baba: f7ff fb51 bl 801b160 <__sinit>
801babe: 4b21 ldr r3, [pc, #132] ; (801bb44 <__swbuf_r+0x98>)
801bac0: 429c cmp r4, r3
801bac2: d12b bne.n 801bb1c <__swbuf_r+0x70>
801bac4: 686c ldr r4, [r5, #4]
801bac6: 69a3 ldr r3, [r4, #24]
801bac8: 60a3 str r3, [r4, #8]
801baca: 89a3 ldrh r3, [r4, #12]
801bacc: 071a lsls r2, r3, #28
801bace: d52f bpl.n 801bb30 <__swbuf_r+0x84>
801bad0: 6923 ldr r3, [r4, #16]
801bad2: b36b cbz r3, 801bb30 <__swbuf_r+0x84>
801bad4: 6923 ldr r3, [r4, #16]
801bad6: 6820 ldr r0, [r4, #0]
801bad8: 1ac0 subs r0, r0, r3
801bada: 6963 ldr r3, [r4, #20]
801badc: b2f6 uxtb r6, r6
801bade: 4283 cmp r3, r0
801bae0: 4637 mov r7, r6
801bae2: dc04 bgt.n 801baee <__swbuf_r+0x42>
801bae4: 4621 mov r1, r4
801bae6: 4628 mov r0, r5
801bae8: f000 f950 bl 801bd8c <_fflush_r>
801baec: bb30 cbnz r0, 801bb3c <__swbuf_r+0x90>
801baee: 68a3 ldr r3, [r4, #8]
801baf0: 3b01 subs r3, #1
801baf2: 60a3 str r3, [r4, #8]
801baf4: 6823 ldr r3, [r4, #0]
801baf6: 1c5a adds r2, r3, #1
801baf8: 6022 str r2, [r4, #0]
801bafa: 701e strb r6, [r3, #0]
801bafc: 6963 ldr r3, [r4, #20]
801bafe: 3001 adds r0, #1
801bb00: 4283 cmp r3, r0
801bb02: d004 beq.n 801bb0e <__swbuf_r+0x62>
801bb04: 89a3 ldrh r3, [r4, #12]
801bb06: 07db lsls r3, r3, #31
801bb08: d506 bpl.n 801bb18 <__swbuf_r+0x6c>
801bb0a: 2e0a cmp r6, #10
801bb0c: d104 bne.n 801bb18 <__swbuf_r+0x6c>
801bb0e: 4621 mov r1, r4
801bb10: 4628 mov r0, r5
801bb12: f000 f93b bl 801bd8c <_fflush_r>
801bb16: b988 cbnz r0, 801bb3c <__swbuf_r+0x90>
801bb18: 4638 mov r0, r7
801bb1a: bdf8 pop {r3, r4, r5, r6, r7, pc}
801bb1c: 4b0a ldr r3, [pc, #40] ; (801bb48 <__swbuf_r+0x9c>)
801bb1e: 429c cmp r4, r3
801bb20: d101 bne.n 801bb26 <__swbuf_r+0x7a>
801bb22: 68ac ldr r4, [r5, #8]
801bb24: e7cf b.n 801bac6 <__swbuf_r+0x1a>
801bb26: 4b09 ldr r3, [pc, #36] ; (801bb4c <__swbuf_r+0xa0>)
801bb28: 429c cmp r4, r3
801bb2a: bf08 it eq
801bb2c: 68ec ldreq r4, [r5, #12]
801bb2e: e7ca b.n 801bac6 <__swbuf_r+0x1a>
801bb30: 4621 mov r1, r4
801bb32: 4628 mov r0, r5
801bb34: f000 f81e bl 801bb74 <__swsetup_r>
801bb38: 2800 cmp r0, #0
801bb3a: d0cb beq.n 801bad4 <__swbuf_r+0x28>
801bb3c: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff
801bb40: e7ea b.n 801bb18 <__swbuf_r+0x6c>
801bb42: bf00 nop
801bb44: 08021134 .word 0x08021134
801bb48: 08021154 .word 0x08021154
801bb4c: 08021114 .word 0x08021114
0801bb50 <_write_r>:
801bb50: b538 push {r3, r4, r5, lr}
801bb52: 4d07 ldr r5, [pc, #28] ; (801bb70 <_write_r+0x20>)
801bb54: 4604 mov r4, r0
801bb56: 4608 mov r0, r1
801bb58: 4611 mov r1, r2
801bb5a: 2200 movs r2, #0
801bb5c: 602a str r2, [r5, #0]
801bb5e: 461a mov r2, r3
801bb60: f7e8 fd4d bl 80045fe <_write>
801bb64: 1c43 adds r3, r0, #1
801bb66: d102 bne.n 801bb6e <_write_r+0x1e>
801bb68: 682b ldr r3, [r5, #0]
801bb6a: b103 cbz r3, 801bb6e <_write_r+0x1e>
801bb6c: 6023 str r3, [r4, #0]
801bb6e: bd38 pop {r3, r4, r5, pc}
801bb70: 2000f880 .word 0x2000f880
0801bb74 <__swsetup_r>:
801bb74: 4b32 ldr r3, [pc, #200] ; (801bc40 <__swsetup_r+0xcc>)
801bb76: b570 push {r4, r5, r6, lr}
801bb78: 681d ldr r5, [r3, #0]
801bb7a: 4606 mov r6, r0
801bb7c: 460c mov r4, r1
801bb7e: b125 cbz r5, 801bb8a <__swsetup_r+0x16>
801bb80: 69ab ldr r3, [r5, #24]
801bb82: b913 cbnz r3, 801bb8a <__swsetup_r+0x16>
801bb84: 4628 mov r0, r5
801bb86: f7ff faeb bl 801b160 <__sinit>
801bb8a: 4b2e ldr r3, [pc, #184] ; (801bc44 <__swsetup_r+0xd0>)
801bb8c: 429c cmp r4, r3
801bb8e: d10f bne.n 801bbb0 <__swsetup_r+0x3c>
801bb90: 686c ldr r4, [r5, #4]
801bb92: 89a3 ldrh r3, [r4, #12]
801bb94: f9b4 200c ldrsh.w r2, [r4, #12]
801bb98: 0719 lsls r1, r3, #28
801bb9a: d42c bmi.n 801bbf6 <__swsetup_r+0x82>
801bb9c: 06dd lsls r5, r3, #27
801bb9e: d411 bmi.n 801bbc4 <__swsetup_r+0x50>
801bba0: 2309 movs r3, #9
801bba2: 6033 str r3, [r6, #0]
801bba4: f042 0340 orr.w r3, r2, #64 ; 0x40
801bba8: 81a3 strh r3, [r4, #12]
801bbaa: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
801bbae: e03e b.n 801bc2e <__swsetup_r+0xba>
801bbb0: 4b25 ldr r3, [pc, #148] ; (801bc48 <__swsetup_r+0xd4>)
801bbb2: 429c cmp r4, r3
801bbb4: d101 bne.n 801bbba <__swsetup_r+0x46>
801bbb6: 68ac ldr r4, [r5, #8]
801bbb8: e7eb b.n 801bb92 <__swsetup_r+0x1e>
801bbba: 4b24 ldr r3, [pc, #144] ; (801bc4c <__swsetup_r+0xd8>)
801bbbc: 429c cmp r4, r3
801bbbe: bf08 it eq
801bbc0: 68ec ldreq r4, [r5, #12]
801bbc2: e7e6 b.n 801bb92 <__swsetup_r+0x1e>
801bbc4: 0758 lsls r0, r3, #29
801bbc6: d512 bpl.n 801bbee <__swsetup_r+0x7a>
801bbc8: 6b61 ldr r1, [r4, #52] ; 0x34
801bbca: b141 cbz r1, 801bbde <__swsetup_r+0x6a>
801bbcc: f104 0344 add.w r3, r4, #68 ; 0x44
801bbd0: 4299 cmp r1, r3
801bbd2: d002 beq.n 801bbda <__swsetup_r+0x66>
801bbd4: 4630 mov r0, r6
801bbd6: f7ff fb7d bl 801b2d4 <_free_r>
801bbda: 2300 movs r3, #0
801bbdc: 6363 str r3, [r4, #52] ; 0x34
801bbde: 89a3 ldrh r3, [r4, #12]
801bbe0: f023 0324 bic.w r3, r3, #36 ; 0x24
801bbe4: 81a3 strh r3, [r4, #12]
801bbe6: 2300 movs r3, #0
801bbe8: 6063 str r3, [r4, #4]
801bbea: 6923 ldr r3, [r4, #16]
801bbec: 6023 str r3, [r4, #0]
801bbee: 89a3 ldrh r3, [r4, #12]
801bbf0: f043 0308 orr.w r3, r3, #8
801bbf4: 81a3 strh r3, [r4, #12]
801bbf6: 6923 ldr r3, [r4, #16]
801bbf8: b94b cbnz r3, 801bc0e <__swsetup_r+0x9a>
801bbfa: 89a3 ldrh r3, [r4, #12]
801bbfc: f403 7320 and.w r3, r3, #640 ; 0x280
801bc00: f5b3 7f00 cmp.w r3, #512 ; 0x200
801bc04: d003 beq.n 801bc0e <__swsetup_r+0x9a>
801bc06: 4621 mov r1, r4
801bc08: 4630 mov r0, r6
801bc0a: f000 f931 bl 801be70 <__smakebuf_r>
801bc0e: 89a0 ldrh r0, [r4, #12]
801bc10: f9b4 200c ldrsh.w r2, [r4, #12]
801bc14: f010 0301 ands.w r3, r0, #1
801bc18: d00a beq.n 801bc30 <__swsetup_r+0xbc>
801bc1a: 2300 movs r3, #0
801bc1c: 60a3 str r3, [r4, #8]
801bc1e: 6963 ldr r3, [r4, #20]
801bc20: 425b negs r3, r3
801bc22: 61a3 str r3, [r4, #24]
801bc24: 6923 ldr r3, [r4, #16]
801bc26: b943 cbnz r3, 801bc3a <__swsetup_r+0xc6>
801bc28: f010 0080 ands.w r0, r0, #128 ; 0x80
801bc2c: d1ba bne.n 801bba4 <__swsetup_r+0x30>
801bc2e: bd70 pop {r4, r5, r6, pc}
801bc30: 0781 lsls r1, r0, #30
801bc32: bf58 it pl
801bc34: 6963 ldrpl r3, [r4, #20]
801bc36: 60a3 str r3, [r4, #8]
801bc38: e7f4 b.n 801bc24 <__swsetup_r+0xb0>
801bc3a: 2000 movs r0, #0
801bc3c: e7f7 b.n 801bc2e <__swsetup_r+0xba>
801bc3e: bf00 nop
801bc40: 20000078 .word 0x20000078
801bc44: 08021134 .word 0x08021134
801bc48: 08021154 .word 0x08021154
801bc4c: 08021114 .word 0x08021114
0801bc50 <abort>:
801bc50: b508 push {r3, lr}
801bc52: 2006 movs r0, #6
801bc54: f000 f992 bl 801bf7c <raise>
801bc58: 2001 movs r0, #1
801bc5a: f7e8 fca9 bl 80045b0 <_exit>
...
0801bc60 <_close_r>:
801bc60: b538 push {r3, r4, r5, lr}
801bc62: 4d06 ldr r5, [pc, #24] ; (801bc7c <_close_r+0x1c>)
801bc64: 2300 movs r3, #0
801bc66: 4604 mov r4, r0
801bc68: 4608 mov r0, r1
801bc6a: 602b str r3, [r5, #0]
801bc6c: f7e8 fce3 bl 8004636 <_close>
801bc70: 1c43 adds r3, r0, #1
801bc72: d102 bne.n 801bc7a <_close_r+0x1a>
801bc74: 682b ldr r3, [r5, #0]
801bc76: b103 cbz r3, 801bc7a <_close_r+0x1a>
801bc78: 6023 str r3, [r4, #0]
801bc7a: bd38 pop {r3, r4, r5, pc}
801bc7c: 2000f880 .word 0x2000f880
0801bc80 <__sflush_r>:
801bc80: 898a ldrh r2, [r1, #12]
801bc82: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
801bc86: 4605 mov r5, r0
801bc88: 0710 lsls r0, r2, #28
801bc8a: 460c mov r4, r1
801bc8c: d458 bmi.n 801bd40 <__sflush_r+0xc0>
801bc8e: 684b ldr r3, [r1, #4]
801bc90: 2b00 cmp r3, #0
801bc92: dc05 bgt.n 801bca0 <__sflush_r+0x20>
801bc94: 6c0b ldr r3, [r1, #64] ; 0x40
801bc96: 2b00 cmp r3, #0
801bc98: dc02 bgt.n 801bca0 <__sflush_r+0x20>
801bc9a: 2000 movs r0, #0
801bc9c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
801bca0: 6ae6 ldr r6, [r4, #44] ; 0x2c
801bca2: 2e00 cmp r6, #0
801bca4: d0f9 beq.n 801bc9a <__sflush_r+0x1a>
801bca6: 2300 movs r3, #0
801bca8: f412 5280 ands.w r2, r2, #4096 ; 0x1000
801bcac: 682f ldr r7, [r5, #0]
801bcae: 602b str r3, [r5, #0]
801bcb0: d032 beq.n 801bd18 <__sflush_r+0x98>
801bcb2: 6d60 ldr r0, [r4, #84] ; 0x54
801bcb4: 89a3 ldrh r3, [r4, #12]
801bcb6: 075a lsls r2, r3, #29
801bcb8: d505 bpl.n 801bcc6 <__sflush_r+0x46>
801bcba: 6863 ldr r3, [r4, #4]
801bcbc: 1ac0 subs r0, r0, r3
801bcbe: 6b63 ldr r3, [r4, #52] ; 0x34
801bcc0: b10b cbz r3, 801bcc6 <__sflush_r+0x46>
801bcc2: 6c23 ldr r3, [r4, #64] ; 0x40
801bcc4: 1ac0 subs r0, r0, r3
801bcc6: 2300 movs r3, #0
801bcc8: 4602 mov r2, r0
801bcca: 6ae6 ldr r6, [r4, #44] ; 0x2c
801bccc: 6a21 ldr r1, [r4, #32]
801bcce: 4628 mov r0, r5
801bcd0: 47b0 blx r6
801bcd2: 1c43 adds r3, r0, #1
801bcd4: 89a3 ldrh r3, [r4, #12]
801bcd6: d106 bne.n 801bce6 <__sflush_r+0x66>
801bcd8: 6829 ldr r1, [r5, #0]
801bcda: 291d cmp r1, #29
801bcdc: d82c bhi.n 801bd38 <__sflush_r+0xb8>
801bcde: 4a2a ldr r2, [pc, #168] ; (801bd88 <__sflush_r+0x108>)
801bce0: 40ca lsrs r2, r1
801bce2: 07d6 lsls r6, r2, #31
801bce4: d528 bpl.n 801bd38 <__sflush_r+0xb8>
801bce6: 2200 movs r2, #0
801bce8: 6062 str r2, [r4, #4]
801bcea: 04d9 lsls r1, r3, #19
801bcec: 6922 ldr r2, [r4, #16]
801bcee: 6022 str r2, [r4, #0]
801bcf0: d504 bpl.n 801bcfc <__sflush_r+0x7c>
801bcf2: 1c42 adds r2, r0, #1
801bcf4: d101 bne.n 801bcfa <__sflush_r+0x7a>
801bcf6: 682b ldr r3, [r5, #0]
801bcf8: b903 cbnz r3, 801bcfc <__sflush_r+0x7c>
801bcfa: 6560 str r0, [r4, #84] ; 0x54
801bcfc: 6b61 ldr r1, [r4, #52] ; 0x34
801bcfe: 602f str r7, [r5, #0]
801bd00: 2900 cmp r1, #0
801bd02: d0ca beq.n 801bc9a <__sflush_r+0x1a>
801bd04: f104 0344 add.w r3, r4, #68 ; 0x44
801bd08: 4299 cmp r1, r3
801bd0a: d002 beq.n 801bd12 <__sflush_r+0x92>
801bd0c: 4628 mov r0, r5
801bd0e: f7ff fae1 bl 801b2d4 <_free_r>
801bd12: 2000 movs r0, #0
801bd14: 6360 str r0, [r4, #52] ; 0x34
801bd16: e7c1 b.n 801bc9c <__sflush_r+0x1c>
801bd18: 6a21 ldr r1, [r4, #32]
801bd1a: 2301 movs r3, #1
801bd1c: 4628 mov r0, r5
801bd1e: 47b0 blx r6
801bd20: 1c41 adds r1, r0, #1
801bd22: d1c7 bne.n 801bcb4 <__sflush_r+0x34>
801bd24: 682b ldr r3, [r5, #0]
801bd26: 2b00 cmp r3, #0
801bd28: d0c4 beq.n 801bcb4 <__sflush_r+0x34>
801bd2a: 2b1d cmp r3, #29
801bd2c: d001 beq.n 801bd32 <__sflush_r+0xb2>
801bd2e: 2b16 cmp r3, #22
801bd30: d101 bne.n 801bd36 <__sflush_r+0xb6>
801bd32: 602f str r7, [r5, #0]
801bd34: e7b1 b.n 801bc9a <__sflush_r+0x1a>
801bd36: 89a3 ldrh r3, [r4, #12]
801bd38: f043 0340 orr.w r3, r3, #64 ; 0x40
801bd3c: 81a3 strh r3, [r4, #12]
801bd3e: e7ad b.n 801bc9c <__sflush_r+0x1c>
801bd40: 690f ldr r7, [r1, #16]
801bd42: 2f00 cmp r7, #0
801bd44: d0a9 beq.n 801bc9a <__sflush_r+0x1a>
801bd46: 0793 lsls r3, r2, #30
801bd48: 680e ldr r6, [r1, #0]
801bd4a: bf08 it eq
801bd4c: 694b ldreq r3, [r1, #20]
801bd4e: 600f str r7, [r1, #0]
801bd50: bf18 it ne
801bd52: 2300 movne r3, #0
801bd54: eba6 0807 sub.w r8, r6, r7
801bd58: 608b str r3, [r1, #8]
801bd5a: f1b8 0f00 cmp.w r8, #0
801bd5e: dd9c ble.n 801bc9a <__sflush_r+0x1a>
801bd60: 6a21 ldr r1, [r4, #32]
801bd62: 6aa6 ldr r6, [r4, #40] ; 0x28
801bd64: 4643 mov r3, r8
801bd66: 463a mov r2, r7
801bd68: 4628 mov r0, r5
801bd6a: 47b0 blx r6
801bd6c: 2800 cmp r0, #0
801bd6e: dc06 bgt.n 801bd7e <__sflush_r+0xfe>
801bd70: 89a3 ldrh r3, [r4, #12]
801bd72: f043 0340 orr.w r3, r3, #64 ; 0x40
801bd76: 81a3 strh r3, [r4, #12]
801bd78: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
801bd7c: e78e b.n 801bc9c <__sflush_r+0x1c>
801bd7e: 4407 add r7, r0
801bd80: eba8 0800 sub.w r8, r8, r0
801bd84: e7e9 b.n 801bd5a <__sflush_r+0xda>
801bd86: bf00 nop
801bd88: 20400001 .word 0x20400001
0801bd8c <_fflush_r>:
801bd8c: b538 push {r3, r4, r5, lr}
801bd8e: 690b ldr r3, [r1, #16]
801bd90: 4605 mov r5, r0
801bd92: 460c mov r4, r1
801bd94: b913 cbnz r3, 801bd9c <_fflush_r+0x10>
801bd96: 2500 movs r5, #0
801bd98: 4628 mov r0, r5
801bd9a: bd38 pop {r3, r4, r5, pc}
801bd9c: b118 cbz r0, 801bda6 <_fflush_r+0x1a>
801bd9e: 6983 ldr r3, [r0, #24]
801bda0: b90b cbnz r3, 801bda6 <_fflush_r+0x1a>
801bda2: f7ff f9dd bl 801b160 <__sinit>
801bda6: 4b14 ldr r3, [pc, #80] ; (801bdf8 <_fflush_r+0x6c>)
801bda8: 429c cmp r4, r3
801bdaa: d11b bne.n 801bde4 <_fflush_r+0x58>
801bdac: 686c ldr r4, [r5, #4]
801bdae: f9b4 300c ldrsh.w r3, [r4, #12]
801bdb2: 2b00 cmp r3, #0
801bdb4: d0ef beq.n 801bd96 <_fflush_r+0xa>
801bdb6: 6e62 ldr r2, [r4, #100] ; 0x64
801bdb8: 07d0 lsls r0, r2, #31
801bdba: d404 bmi.n 801bdc6 <_fflush_r+0x3a>
801bdbc: 0599 lsls r1, r3, #22
801bdbe: d402 bmi.n 801bdc6 <_fflush_r+0x3a>
801bdc0: 6da0 ldr r0, [r4, #88] ; 0x58
801bdc2: f7ff fa7d bl 801b2c0 <__retarget_lock_acquire_recursive>
801bdc6: 4628 mov r0, r5
801bdc8: 4621 mov r1, r4
801bdca: f7ff ff59 bl 801bc80 <__sflush_r>
801bdce: 6e63 ldr r3, [r4, #100] ; 0x64
801bdd0: 07da lsls r2, r3, #31
801bdd2: 4605 mov r5, r0
801bdd4: d4e0 bmi.n 801bd98 <_fflush_r+0xc>
801bdd6: 89a3 ldrh r3, [r4, #12]
801bdd8: 059b lsls r3, r3, #22
801bdda: d4dd bmi.n 801bd98 <_fflush_r+0xc>
801bddc: 6da0 ldr r0, [r4, #88] ; 0x58
801bdde: f7ff fa70 bl 801b2c2 <__retarget_lock_release_recursive>
801bde2: e7d9 b.n 801bd98 <_fflush_r+0xc>
801bde4: 4b05 ldr r3, [pc, #20] ; (801bdfc <_fflush_r+0x70>)
801bde6: 429c cmp r4, r3
801bde8: d101 bne.n 801bdee <_fflush_r+0x62>
801bdea: 68ac ldr r4, [r5, #8]
801bdec: e7df b.n 801bdae <_fflush_r+0x22>
801bdee: 4b04 ldr r3, [pc, #16] ; (801be00 <_fflush_r+0x74>)
801bdf0: 429c cmp r4, r3
801bdf2: bf08 it eq
801bdf4: 68ec ldreq r4, [r5, #12]
801bdf6: e7da b.n 801bdae <_fflush_r+0x22>
801bdf8: 08021134 .word 0x08021134
801bdfc: 08021154 .word 0x08021154
801be00: 08021114 .word 0x08021114
0801be04 <_lseek_r>:
801be04: b538 push {r3, r4, r5, lr}
801be06: 4d07 ldr r5, [pc, #28] ; (801be24 <_lseek_r+0x20>)
801be08: 4604 mov r4, r0
801be0a: 4608 mov r0, r1
801be0c: 4611 mov r1, r2
801be0e: 2200 movs r2, #0
801be10: 602a str r2, [r5, #0]
801be12: 461a mov r2, r3
801be14: f7e8 fc36 bl 8004684 <_lseek>
801be18: 1c43 adds r3, r0, #1
801be1a: d102 bne.n 801be22 <_lseek_r+0x1e>
801be1c: 682b ldr r3, [r5, #0]
801be1e: b103 cbz r3, 801be22 <_lseek_r+0x1e>
801be20: 6023 str r3, [r4, #0]
801be22: bd38 pop {r3, r4, r5, pc}
801be24: 2000f880 .word 0x2000f880
0801be28 <__swhatbuf_r>:
801be28: b570 push {r4, r5, r6, lr}
801be2a: 460e mov r6, r1
801be2c: f9b1 100e ldrsh.w r1, [r1, #14]
801be30: 2900 cmp r1, #0
801be32: b096 sub sp, #88 ; 0x58
801be34: 4614 mov r4, r2
801be36: 461d mov r5, r3
801be38: da07 bge.n 801be4a <__swhatbuf_r+0x22>
801be3a: 2300 movs r3, #0
801be3c: 602b str r3, [r5, #0]
801be3e: 89b3 ldrh r3, [r6, #12]
801be40: 061a lsls r2, r3, #24
801be42: d410 bmi.n 801be66 <__swhatbuf_r+0x3e>
801be44: f44f 6380 mov.w r3, #1024 ; 0x400
801be48: e00e b.n 801be68 <__swhatbuf_r+0x40>
801be4a: 466a mov r2, sp
801be4c: f000 f8b2 bl 801bfb4 <_fstat_r>
801be50: 2800 cmp r0, #0
801be52: dbf2 blt.n 801be3a <__swhatbuf_r+0x12>
801be54: 9a01 ldr r2, [sp, #4]
801be56: f402 4270 and.w r2, r2, #61440 ; 0xf000
801be5a: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000
801be5e: 425a negs r2, r3
801be60: 415a adcs r2, r3
801be62: 602a str r2, [r5, #0]
801be64: e7ee b.n 801be44 <__swhatbuf_r+0x1c>
801be66: 2340 movs r3, #64 ; 0x40
801be68: 2000 movs r0, #0
801be6a: 6023 str r3, [r4, #0]
801be6c: b016 add sp, #88 ; 0x58
801be6e: bd70 pop {r4, r5, r6, pc}
0801be70 <__smakebuf_r>:
801be70: 898b ldrh r3, [r1, #12]
801be72: b573 push {r0, r1, r4, r5, r6, lr}
801be74: 079d lsls r5, r3, #30
801be76: 4606 mov r6, r0
801be78: 460c mov r4, r1
801be7a: d507 bpl.n 801be8c <__smakebuf_r+0x1c>
801be7c: f104 0347 add.w r3, r4, #71 ; 0x47
801be80: 6023 str r3, [r4, #0]
801be82: 6123 str r3, [r4, #16]
801be84: 2301 movs r3, #1
801be86: 6163 str r3, [r4, #20]
801be88: b002 add sp, #8
801be8a: bd70 pop {r4, r5, r6, pc}
801be8c: ab01 add r3, sp, #4
801be8e: 466a mov r2, sp
801be90: f7ff ffca bl 801be28 <__swhatbuf_r>
801be94: 9900 ldr r1, [sp, #0]
801be96: 4605 mov r5, r0
801be98: 4630 mov r0, r6
801be9a: f7ff fa6b bl 801b374 <_malloc_r>
801be9e: b948 cbnz r0, 801beb4 <__smakebuf_r+0x44>
801bea0: f9b4 300c ldrsh.w r3, [r4, #12]
801bea4: 059a lsls r2, r3, #22
801bea6: d4ef bmi.n 801be88 <__smakebuf_r+0x18>
801bea8: f023 0303 bic.w r3, r3, #3
801beac: f043 0302 orr.w r3, r3, #2
801beb0: 81a3 strh r3, [r4, #12]
801beb2: e7e3 b.n 801be7c <__smakebuf_r+0xc>
801beb4: 4b0d ldr r3, [pc, #52] ; (801beec <__smakebuf_r+0x7c>)
801beb6: 62b3 str r3, [r6, #40] ; 0x28
801beb8: 89a3 ldrh r3, [r4, #12]
801beba: 6020 str r0, [r4, #0]
801bebc: f043 0380 orr.w r3, r3, #128 ; 0x80
801bec0: 81a3 strh r3, [r4, #12]
801bec2: 9b00 ldr r3, [sp, #0]
801bec4: 6163 str r3, [r4, #20]
801bec6: 9b01 ldr r3, [sp, #4]
801bec8: 6120 str r0, [r4, #16]
801beca: b15b cbz r3, 801bee4 <__smakebuf_r+0x74>
801becc: f9b4 100e ldrsh.w r1, [r4, #14]
801bed0: 4630 mov r0, r6
801bed2: f000 f881 bl 801bfd8 <_isatty_r>
801bed6: b128 cbz r0, 801bee4 <__smakebuf_r+0x74>
801bed8: 89a3 ldrh r3, [r4, #12]
801beda: f023 0303 bic.w r3, r3, #3
801bede: f043 0301 orr.w r3, r3, #1
801bee2: 81a3 strh r3, [r4, #12]
801bee4: 89a0 ldrh r0, [r4, #12]
801bee6: 4305 orrs r5, r0
801bee8: 81a5 strh r5, [r4, #12]
801beea: e7cd b.n 801be88 <__smakebuf_r+0x18>
801beec: 0801b0f9 .word 0x0801b0f9
0801bef0 <__malloc_lock>:
801bef0: 4801 ldr r0, [pc, #4] ; (801bef8 <__malloc_lock+0x8>)
801bef2: f7ff b9e5 b.w 801b2c0 <__retarget_lock_acquire_recursive>
801bef6: bf00 nop
801bef8: 2000f88c .word 0x2000f88c
0801befc <__malloc_unlock>:
801befc: 4801 ldr r0, [pc, #4] ; (801bf04 <__malloc_unlock+0x8>)
801befe: f7ff b9e0 b.w 801b2c2 <__retarget_lock_release_recursive>
801bf02: bf00 nop
801bf04: 2000f88c .word 0x2000f88c
0801bf08 <_read_r>:
801bf08: b538 push {r3, r4, r5, lr}
801bf0a: 4d07 ldr r5, [pc, #28] ; (801bf28 <_read_r+0x20>)
801bf0c: 4604 mov r4, r0
801bf0e: 4608 mov r0, r1
801bf10: 4611 mov r1, r2
801bf12: 2200 movs r2, #0
801bf14: 602a str r2, [r5, #0]
801bf16: 461a mov r2, r3
801bf18: f7e8 fb54 bl 80045c4 <_read>
801bf1c: 1c43 adds r3, r0, #1
801bf1e: d102 bne.n 801bf26 <_read_r+0x1e>
801bf20: 682b ldr r3, [r5, #0]
801bf22: b103 cbz r3, 801bf26 <_read_r+0x1e>
801bf24: 6023 str r3, [r4, #0]
801bf26: bd38 pop {r3, r4, r5, pc}
801bf28: 2000f880 .word 0x2000f880
0801bf2c <_raise_r>:
801bf2c: 291f cmp r1, #31
801bf2e: b538 push {r3, r4, r5, lr}
801bf30: 4604 mov r4, r0
801bf32: 460d mov r5, r1
801bf34: d904 bls.n 801bf40 <_raise_r+0x14>
801bf36: 2316 movs r3, #22
801bf38: 6003 str r3, [r0, #0]
801bf3a: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
801bf3e: bd38 pop {r3, r4, r5, pc}
801bf40: 6c42 ldr r2, [r0, #68] ; 0x44
801bf42: b112 cbz r2, 801bf4a <_raise_r+0x1e>
801bf44: f852 3021 ldr.w r3, [r2, r1, lsl #2]
801bf48: b94b cbnz r3, 801bf5e <_raise_r+0x32>
801bf4a: 4620 mov r0, r4
801bf4c: f000 f830 bl 801bfb0 <_getpid_r>
801bf50: 462a mov r2, r5
801bf52: 4601 mov r1, r0
801bf54: 4620 mov r0, r4
801bf56: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
801bf5a: f000 b817 b.w 801bf8c <_kill_r>
801bf5e: 2b01 cmp r3, #1
801bf60: d00a beq.n 801bf78 <_raise_r+0x4c>
801bf62: 1c59 adds r1, r3, #1
801bf64: d103 bne.n 801bf6e <_raise_r+0x42>
801bf66: 2316 movs r3, #22
801bf68: 6003 str r3, [r0, #0]
801bf6a: 2001 movs r0, #1
801bf6c: e7e7 b.n 801bf3e <_raise_r+0x12>
801bf6e: 2400 movs r4, #0
801bf70: f842 4025 str.w r4, [r2, r5, lsl #2]
801bf74: 4628 mov r0, r5
801bf76: 4798 blx r3
801bf78: 2000 movs r0, #0
801bf7a: e7e0 b.n 801bf3e <_raise_r+0x12>
0801bf7c <raise>:
801bf7c: 4b02 ldr r3, [pc, #8] ; (801bf88 <raise+0xc>)
801bf7e: 4601 mov r1, r0
801bf80: 6818 ldr r0, [r3, #0]
801bf82: f7ff bfd3 b.w 801bf2c <_raise_r>
801bf86: bf00 nop
801bf88: 20000078 .word 0x20000078
0801bf8c <_kill_r>:
801bf8c: b538 push {r3, r4, r5, lr}
801bf8e: 4d07 ldr r5, [pc, #28] ; (801bfac <_kill_r+0x20>)
801bf90: 2300 movs r3, #0
801bf92: 4604 mov r4, r0
801bf94: 4608 mov r0, r1
801bf96: 4611 mov r1, r2
801bf98: 602b str r3, [r5, #0]
801bf9a: f7e8 faf7 bl 800458c <_kill>
801bf9e: 1c43 adds r3, r0, #1
801bfa0: d102 bne.n 801bfa8 <_kill_r+0x1c>
801bfa2: 682b ldr r3, [r5, #0]
801bfa4: b103 cbz r3, 801bfa8 <_kill_r+0x1c>
801bfa6: 6023 str r3, [r4, #0]
801bfa8: bd38 pop {r3, r4, r5, pc}
801bfaa: bf00 nop
801bfac: 2000f880 .word 0x2000f880
0801bfb0 <_getpid_r>:
801bfb0: f7e8 bae4 b.w 800457c <_getpid>
0801bfb4 <_fstat_r>:
801bfb4: b538 push {r3, r4, r5, lr}
801bfb6: 4d07 ldr r5, [pc, #28] ; (801bfd4 <_fstat_r+0x20>)
801bfb8: 2300 movs r3, #0
801bfba: 4604 mov r4, r0
801bfbc: 4608 mov r0, r1
801bfbe: 4611 mov r1, r2
801bfc0: 602b str r3, [r5, #0]
801bfc2: f7e8 fb44 bl 800464e <_fstat>
801bfc6: 1c43 adds r3, r0, #1
801bfc8: d102 bne.n 801bfd0 <_fstat_r+0x1c>
801bfca: 682b ldr r3, [r5, #0]
801bfcc: b103 cbz r3, 801bfd0 <_fstat_r+0x1c>
801bfce: 6023 str r3, [r4, #0]
801bfd0: bd38 pop {r3, r4, r5, pc}
801bfd2: bf00 nop
801bfd4: 2000f880 .word 0x2000f880
0801bfd8 <_isatty_r>:
801bfd8: b538 push {r3, r4, r5, lr}
801bfda: 4d06 ldr r5, [pc, #24] ; (801bff4 <_isatty_r+0x1c>)
801bfdc: 2300 movs r3, #0
801bfde: 4604 mov r4, r0
801bfe0: 4608 mov r0, r1
801bfe2: 602b str r3, [r5, #0]
801bfe4: f7e8 fb43 bl 800466e <_isatty>
801bfe8: 1c43 adds r3, r0, #1
801bfea: d102 bne.n 801bff2 <_isatty_r+0x1a>
801bfec: 682b ldr r3, [r5, #0]
801bfee: b103 cbz r3, 801bff2 <_isatty_r+0x1a>
801bff0: 6023 str r3, [r4, #0]
801bff2: bd38 pop {r3, r4, r5, pc}
801bff4: 2000f880 .word 0x2000f880
0801bff8 <_init>:
801bff8: b5f8 push {r3, r4, r5, r6, r7, lr}
801bffa: bf00 nop
801bffc: bcf8 pop {r3, r4, r5, r6, r7}
801bffe: bc08 pop {r3}
801c000: 469e mov lr, r3
801c002: 4770 bx lr
0801c004 <_fini>:
801c004: b5f8 push {r3, r4, r5, r6, r7, lr}
801c006: bf00 nop
801c008: bcf8 pop {r3, r4, r5, r6, r7}
801c00a: bc08 pop {r3}
801c00c: 469e mov lr, r3
801c00e: 4770 bx lr
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